WO1989012320A1

WO1989012320A1 - Wafer scale integrated circuits

Info

Publication number: WO1989012320A1
Application number: PCT/GB1989/000594
Authority: WO
Inventors: Michael Brent; Neal Macdonald; Anthony Marsh
Original assignee: Anamartic Limited
Priority date: 1988-06-01
Filing date: 1989-05-31
Publication date: 1989-12-14
Also published as: KR900702569A; EP0378613A1

Abstract

Like integrated circuits or "chips" (10) on a wafer (22) supported on a printed circuit board (24) are supplied with power by VCC and VSS bondwires (20) stitch bonded to pads on all chips (10). The bondwires are interrupted at the equator so that a supply line fault in the top or bottom half of the wafer will not affect any chips in the lower half of the wafer, and vice versa. Global signal lines (18) WCK (wafer clock) and CMND (command) are similarly treated, being formed in metal which is interrupted in an equatorial band (26). Every chip (10) has input and output bond pads for data input and output to a chain of chips grown using inter-module connections in a manner known per se. The chips may thus be masked using like reticles while always having available edge chips (10') whose input and output bond pads can be used to make external connections, via bondwires (38).

Description

WAFER SCALE INTEGRATED CIRCUITS This invention relates to wafer scale integrated (WSI ) circuits comprising an array of integrated circuit modules on the wafer. The modules correspond more or less to the "chips" which would result were the wafer to be diced and each module may be a memory module or a processing module of some kind. The modules are interconnected by local connections and global lines. The local connections are module to module connections between neighbouring modules whereas the global lines extend to all modules and comprise both power supply lines and one or more lines for carrying global clock or command signals. The present invention is concerned with certain problems arising in connection with global lines but the nature of the global command signals is of no importance to the invention. Nevertheless background information as to kind of signals which may be involved will be found in GB-A-2 177 825.

The present invention may be applied to WSI circuits of the kind described in GB-A-1 377 859 and GB-A-2 177 825 in which a chain, chains or a branching chain or chains or modules may be set up by software commands, by selectively enabling the local connections referred to above. The invention is not however restricted to such circuits. The modules are preferably, but not necessarily, arranged in rows and columns so that each module (apart that is from modules at the edge of the array) has four immediate neighbours, the local connections being provided between each pair of immediate neighbours.

An advantage of these known WSI circuits is that a chain of good modules can be grown, thereby avoiding modules which are defective because of wafer faults - which are unavoidable at the wafer scale level. The technique will also deal with the problem of isolated defective local connections. However there can be more troublesome problems with defective global lines, as explained below.

Although the invention is not concerned with the particular technology used to process the wafer this will typically follow conventional integrated circuit practice and involve polysilicon connections and connections etched in at least one, and usually two, metal layers (metal 1 and metal 2). The whole trend of current technology continues to be towards higher resolution which increases the risk of connection faults and also requires the use of stepper technology instead of whole wafer projection during the various masking steps used in manufacture. In whole wafer projection each mask defines structure over the whole wafer and can therefore be configured to create not merely the fine detail required in the creation of each module but also relatively coarse structures on the scale of the wafer, such as bonding pads round the edge of the wafer and networks of global lines. In stepper technology each mask or reticle defines the structure of a single module or of a small cluster (e.g. two) of modules, the reticle being stepped about the wafer to expose the totality of modules. There is a high premium on using the same reticle over the whole wafer to avoid the reduction in throughput caused by changing reticles but stepping an invariant reticle cannot create wafer scale structure other than periodic structure repeating a structure having the scale of a cluster of modules.

When the chain growing technique is used it is necessary to provide at least one bondsite module whereat data signals may be input and output, this module desirably being at the edge of the wafer. In the prior art, bondsite modules are different from nonbonds ite modules and the use of stepper technology is therefore problematic.

In GB-A-2 177 825 the modules are arranged in rows and columns (the choice of which is which is arbitrary) and all global lines extend in the column direction. A specific problem which has to be addressed is that a faulty column conductor may erect a barrier partitioning the wafer into usable and unusable portions. Even using the chain growing technique referred to above it may not be possible to get past this barrier into a substantial portion of the wafer containing many good modules. For this reason it has already been proposed (GB-A-2 178 204) to use Christmas tree-like global power lines with a central spine in the row direction, from which column conductors branch on both sides. If one such conductor is faulty it is unlikely that its counterpart will also be faulty and so the barrier only affects the top or bottom half of the wafer and can be got round in the other half. This technique was satisfactory using whole wafer projection but cannot be implemented economically using stepper technology.

Finally, as the line widths are reduced, it becomes increasingly difficult to provide adequate global power lines and calculations show that a module remote from a bondsite can readily suffer a power supply voltage drop in excess of 1.5v if power lines are formed in second metal. Such a voltage drop is totally unacceptable.

It is thus apparent that there is a complex pattern of related problems affecting the wafer scale structures in general and the global lines in particular, especially the global power lines. The object of the present invention is to provide a solution to these problems and the invention resides in the following features which can be used singly or in various combinations.

(1) Each module or each module cluster extends a plurality of signal lines to corresponding bond pads, whereby bondwire connections may be made anywhere desired, in particular at any desired location at the edge of the wafer. The signal lines treated thus can include at least an input line and an output line for data.

(2) Each module or each module cluster has power supply bond pads and power is supplied to the modules by bondwires stitch bonded to these pads.

(3) At least some global lines extend into the wafer from two opposite sides thereof, without meeting, so that a fault in a line extending in from one side will not affect the counterpart line extending in from the other side. In the case of power supply global lines, the stitch bonding can be interrupted. Preferably the other global lines for signals are formed in a metal layer which is interrupted by an equatorial band containing no metal. This may be achieved in various ways:

(a) define the pattern of the metal layer using a single stepper reticle and separately define the equatorial band using a whole wafer projection mask.

(b) define the pattern of the metal layer using a single stepper reticle but blade the reticle in such a way that the equatorial band is left free of metal whereas the lines are continuous across other inter-row bands. Blading is a known technique whereby blades or shutters are adjusted to define the margins of a reticle.

(c) define the pattern of the metal layer using one stepper reticle for modules flanking the equatorial band and another stepper reticle for the other modules.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 is a diagram of a pair of chips showing some of the connections thereof,

Fig. 2 is a similar diagram of the chips showing other connections,

Fig. 3 is a simplified block diagram of one chip,

Fig. 4 shows a wafer on a printed circuit board and the bondwire connections,

Fig. 5 illustrates a detail V of Fig. 4, and

Fig.6 illustrates a modified form of chip.

It must be emphasized that there are many possible chip configurations within the scope of the invention and the embodiment of Figs. 1 to 5 is purely byway of example. Fig. 6 is added to illustrate a rather different example.

Each module or chip 10 shown in Fig.1 is composed largely of a 1 Mbit DRAM 12 of conventional design. The DRAM is accessed via logic 14. The chip may be constructed in accordance with GB-A 2177825 to which reference should be made for full details. The present application uses the same symbols as GB-A 2177825 to denote signals. In the simplified block diagram of Fig.3, the logic 14 can receive data on commonly connected inputs XINN, XINE, XINS and XINW (all connected to XIN), pass data on to a neighbouring chip-via a selected one of four switched outputs XOUTN, XOUTE, XOUTS and XOUTW, write received data into the DRAM 12, receive data on a return path from a neighbouring chip via a selected one of four switched inputs RINN, RINE, RINS, RINW, pass such data on to commonly connected outputs ROUTN, ROUTE, ROUTS and ROUTW (all connected to ROUT) and read data from the DRAM 12 to these outputs. The chips are formed on a wafer by stepper technology and, because of the aspect ratio of one chip, it is convenient to step a cluster of two chips, shown in Fig.1. The chips are framed by a "flash" 16 in which there is overlap between successive stepper reticle placements. All of the input and output connections are so disposed along the N, E, S, W edges of the chip that N and S connections will connect up, as will E and W connections. As is apparent, XINN of the lower chip connects to XOUTS of the lower chip while RINS of the upper chip connects to ROUTN of the lower chip. Connections are thereby established over the whole wafer which will enable a chain of chips to be grown, as described in GB-A 2177825. The connections thus far described may be made in metal 1 and polysilicon and they are unaffected by the treatment of metal 2, described below.

In accordance with one feature of the present invention, every chip, or at least one chip of every cluster, has a bondpad XMIT connected to the input line XIN and a bondpad RECV connected to the output line ROUT. Accordingly, any chip can be used as a bondsite chip from which a chain of chips may be grown. In practice four chips are used as bondsite chips, as will be explained with reference to Fig.4.

All chips have to receive supply voltages V_SS and V_CC such as Ov and 5v and to this end every chip has a corresponding pad so labelled. All chips also have to receive the global commands WCK (wafer clock) and CMND (command) and every chip has a corresponding bondpad. The bondpads V_SS and V_CC are not connected in the integrated circuit structure but WCK and CMND are connected by tracks 18 in metal 2, shown in Fig.2, which omits the data input and output lines of Fig.1 for simplicity. As shown in Figs. 1 and 2 the power supply bondpads V _CC and V_SS are connected by bondwires 20 stitch-bonded to the columns of pads.

The complete layout is indicated in Fig.4 which, for simplicity shows far fewer chips in a wafer than would actually be present and only representative connections are shown.

The array of chips 10 is formed on a wafer 22 which is mounted on a printed circuit board (PCB) 24. Along the top of this board there run tracks for V_SS, V_CC, CMND and WCK. Along the bottom these tracks are dupl icated. In each col umn of ch ips 10, al l V_CC bondpads in the top half of the wafer are connected by one bondwire 20 to the V _CC track at the top of the board 24 and al l V_SS bondpads are connected by the other bondwire 20 to the V_SS track at the top of the board. The V«p and Vgg pads of the chips in the lower half of the waf er are s imilarly connected to the V«p and Vgg tracks at the bottom of the board. Moreover, within each column, the WCK and CMND pads are connected by the metal 2 tracks 18 within the integra ted circui t s tructure itself. However, there is an equatorial band indicated by a thick, dark l ine 26 where there is no metal 2, so that each track 18 is separated into top and bottom halves. For this reason the WCK and CMND bondpads of the top chip of each column are connected to the top WCK and CMND PCB tracks by bondwires 32 and the WCK and CMND bondpads of the bottom chip of each column are connected to the bottom WCK and CMND PCB tracks by bondwires 34.

The equatorial band 26 may be formed by us ing a sl ightly modif ied reticle for the row 28 of chips above this band when masking metal 2, the bottom f lash, shown shaded in F ig.2, be ing omitted. This is il l us trated in F ig.5, showing the ends of the ha lf tracks 18, separated by a gap in the band 26 formed because the f lash 30 is not present, even though the top f lash 36 of the next chip bel ow remains.

Four chips 10' a long the bottom of the waf er are used as bonds ite chips and their XMIT and RECV pads are connected to correspond ing pairs of pads on the PCB 24 by bondwires 38.

F ig. 6 shows an al ternative arrangement us ing a clus ter of two s ide-by-s ide chips 40 bounded lateral ly by al ternate V_SS and V_CC tracks. Al though these are continuous, wires may be s titch-bonded along them to ensure adequate current carrying capacity to the chips. CMND and WCK have tracks 42 with bondpads top and bottom, so that connections may be made at the top and bottom chips of each col umn, as in F ig.4. XMIT and RECV are dupl icated at each s ide as XMITW and XMITE and RECVW and RECVE so that any chip at the lef t or right hand side of the array may be used as a bonds ite chip. No attempt is made to show the IN and OUT connections corresponding to F ig.1. In the complete wafer an equatorial band interrupting the tracks 42 is provided, as in F ig.4. The equatorial band 26 in Fig. 4 may alternatively be formed by initially laying down continuous tracks 18, i.e. using a normal reticle for all modules for metal 2, and thereafter etching gaps in the metal 2 tracks using a more crudely aligned (e.g. 2-3u) whole wafer mask.

Claims

CLAIMS:

1. A wafer scale integrated circuit comprising an array of integrated circuits formed on the one wafer, local connections between the modules and global lines including power supply lines and signal lines extending to all modules, wherein each module or cluster of modules has power supply bond pads and the power supply lines are formed by bondwires stitch bonded to these bond pads.

2. A wafer scale integrated circuit according to claim 1, wherein the bondwires all run parallel and extend into the wafer from two opposite edges thereof and are each interrupted at an intermediate point.

3. A wafer scale integrated circuit comprising an array of integrated circuits formed on the one wafer, local connections between the modules and global lines including power supply lines and signal lines extending to all modules, wherein at least some global lines extend into the wafer from two opposite sides thereof, without meeting, so that a fault in a line extending in from one side will not affect the counterpart line extending in from the other side.

4. A wafer scale integrated circuit according to claim 3, wherein at least same global lines are formed in a metal layer which is interrupted by an equatorial band containing no metal.

5. A method of making a wafer scale integrated circuit according to claim 4, wherein the pattern of the metal layer is defined using a single stepper reticle pertaining to one module or cluster of modules and the equatorial band is separately defined using a whole wafer projection mask.

6. A method of making a wafer scale integrated circuit according to claim 4, wherein the pattern of the metal layer is defined using a single stepper reticle pertaining to one module or cluster of modules and the equatorial band is defined by blading the reticle in such a way that the equatorial band is left free of metal whereas the lines are continuous across other inter-row bands.

7. A method of making a wafer scale integrated circuit according to claim 4, wherein the pattern of the metal layer is defined using a first stepper reticle for modules flanking the equatorial band and another stepper reticle for the other modules.

8. A wafer scale integrated circuit comprising an array of integrated circuits formed on the one wafer, local connections between the modules and global lines including power supply lines and signal lines extending to all modules, wherein each module or each module cluster extends a plurality of signal lines to corresponding bond pads, whereby bondwire connections can be made anywhere desired, in particular at any desired location at the edge of the wafer.

9. A wafer scale integrated circuit according to claim 8, wherein the signal lines extended to bond pads include at least an input line for data and an output line for data.

10. A wafer scale integrated circuit substantially as hereinbefore described with reference to and as illustrated in Figures 1 to 5 or Figure 6 of the accompanying drawings.