WO1989003096A1

WO1989003096A1 - Interface card configurable by optical input

Info

Publication number: WO1989003096A1
Application number: PCT/US1988/003326
Authority: WO
Inventors: John H Long, Jr.; John B. Hamilton; Jane F. Thorne; Noel E. Singh; Keith R. Hogan; Patrice Bourgeois
Original assignee: Case Communications Inc.
Priority date: 1987-09-28
Filing date: 1988-09-28
Publication date: 1989-04-06

Abstract

A communications system interface card (302), wherein optical input (e.g. from a bar code reader) can be used to reconfigure the card by selecting among the various programmable interface protocol settings available on the card.

Description

TITLE OF THE INVENTION

INTERFACE CARD CONFIGURABLE BY OPTICAL INPUT

PARTIAL WAIVER OF COPYRIGHT

All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.

However,- the copyright owner has- no- objection to the facsimile reproduction by anyone- of the patent document or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND AND SUMMARY OF THE INVENTION The present invention relates to communication systems.

A common problem in complex communications system is reconfiguring the system to take advan¬ tage of the available options. That is, as communication systems and their protocols become more sophisticated, the number of options which users desire to take advantage of increases. For example, the number of available choices in baud rates, parity protocols, handshaking protocols, automatic detection options, error correction options, etc., is still increasing. Taking advantage of this capability may be a problem in smaller stand-alone stations.

It is possible, in a multiplexer system, to use the back plane as a command bus to interrogate and reconfigure individual cards in the multiplexer system. However, at present this requires some relatively sophisticated additional hardware and software, which substantially increases the cost of the system. Therefore, this may not be economical for many systems. In particular, as multiplexer stations of broader capability become more common, the economics of reconfiguring the stations with the required flexibility become more critical. The present invention provides a very compact and economical way to exploit the full flexibility of a densely packed programmable interface system. The present _* invention accomplishes this in^" a fashion which permits the programmable capabilities of the programmable interface to be accessed and tested and/or modified, without requiring a terminal or keypad for the interface.

The present invention provides an optical interface for inputting configuration data to a complex programmable interface card. In the presently preferred embodiment, this is done by using a bar code reader which is scanned over a printed bar code to input the desired commands, but a variety of other optical data input schemes could be used instead.

U.S. Patent No. 4,608,487 to Awane et al. does contain some teaching related to use of a bar code printer (or other automatic rapid optically-scanned data input) for rapid input of programmable option selections. However, Awane et al. contains no suggestion of use of such input for interface protocol selection. It also contains no suggestion of application to systems as complex as a tele¬ communications interface.

U.S. Patent No. 4,323,773 to Carpenter (on a microwave oven which is programmed by bar code reader input) is merely an example of use of a bar code to input processing parameters. Another more recent example is shown in U.S. Patent No. 4,329,684 to Monteath et al.. which teaches a system whereby VCRs can be programmed by running a wand over bar codes printed in a TV Guide.

One advantage of the present invention is that configuration for unusual interface specifications can be accomplished fairly easily. For example, the^•presently preferred embodiment permits configu¬ ration for HP3000 interfaces or Wang interfaces rapidly.

Alternatively, it would be possible to use a network management system to take control of the system bus to send the commands to the various cards, and therefore speed up the types of recon¬ figuration described here. However, this involves significant added expense, which is not justified in many applications. One particular advantage of the present invention is reconfiguration of multiplexer stations located at remote sites. This is parti¬ cularly advantageous because a bar code reader is very portable. This is particularly an advantage when field service personnel are being sent out to customer sites, since reconfiguration and testing can be done in the field without uncertainty as to availability of interface equipment.

The foregoing section has included some discussion of various known teachings which are believed to be related to various ones of the innovations disclosed in the present application, interspersed with discussion of generally applic¬ able innovative teachings and/or specific discus¬ sion of the best mode as presently contemplated. However, applicants specifically note that not every such idea discussed in this section is necessarily prior art. For example, the charac¬ terizations of the particular patents and publica¬ tions discussed may relate them to inventive concepts in a way which is itself based on knowl¬ edge of some of the inventive concepts. Moreover, this discussion attempts to fairly present various suggested technical alternatives (to the best of applicants' knowledge), even though the teachings of some of those technical alternatives may not be "prior art" under the patent laws of the United States or of other countries. Applicants also

__* specifically note that statements made herein regarding innovative features do_^ not necessarily delimit the various inventions claimed, for at least the following reasons: 1) various parts of the discussion may relate to some (but not all) classes of novel embodiments disclosed; 2) various parts of the discussion may relate to innovative teachings disclosed but not claimed in this specific application as filed; 3) various parts of the discussion may relate specifically to the "best mode contemplated by the inventor of carrying out his invention" (as expressly required by the patent laws of the United States) , and will therefore discuss features which are particularly related to this subclass of embodiments, and are not necessary parts of the claimed invention; and 4) the discus¬ sion is generally quite heuristic, and therefore focusses on particular points without explicitly distinguishing between the features and advantages of particular subclasses of embodiments and those inherent in the invention generally.

BRIEF DESCRIPTION OF THE DRAWING The present invention will be described with reference to the accompanying drawings, wherein:

Figure 1 schematically shows a sample large network using multiplexers.

Figure 2 shows an example of a node containing multiple frames, each of which may include multiple multiplexer cards.

Figure 3 shows an example of a multiplexer frame containing multiple cards, and Figure 7 schematically shows the cooperation of the differ- ent components of such a multiplexer frame.

Figure 4 schematically shows the data flows in the programmable interface card.

Figure 5 shows the software organization used in the programmable interface card of the presently preferred embodiment.

Figure 6 indicates schematically the logical organization used to decode the various possible sequential activation of the two buttons on the front panel of the programmable interface card into command states.

Figure 8 shows the front panel of the program¬ mable interface card, in the presently preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

System Context

Figure 1 shows a sample network configuration.

As this figure very schematically indicates, multiplexing and connection options can be used to configure a very large number of options for signal routing across a total network space which may be very complex indeed. However, a key piece of the system shown is provided by the multiplexers 102 which are connected to the network 101. Each of these multiplexers connects devices or hosts 104 (such as printers, terminals, modems, or CPUs) into the network 101. Note that the lines 106 which connect the peripherals to the multiplexer will typically be operating at lower speed than the lines 108 which connect multiplexers within the network 101. Optionally, the multiplexers 102 may be organized into nodes 110.

In the presently preferred embodiment, the innovative teachings herein are used to realize a readily reconfigurable multiplexer 102 as one or more interface cards 302 (shown, for example, in Figure 3) .

The interface card 302 can be thought of as the

- ^• outermost card in the multiplex^'er, .i.e. as the

"fringe" around the network which^' is the complete multiplexer system. This card permits an interface from terminals, CPUs, printers, modems, etc., into the local bus in the multiplexer, and thence to other stations elsewhere in the network 101.

Components of a Multiplexer

The presently preferred embodiment uses an advantageous board/frame/node architecture. This architecture will therefore be described in the course of describing the best mode as presently contemplated. However, it should be recognized that this architecture is not at all necessary for use of the innovative concepts disclosed and claimed herein.

In this embodiment, one node 110 (like that shown in Figure 2) can contain multiple frames 202, and each frame 202 can contain multiple program- mable interface cards 302, in addition to other required or optional cards.

Figure 7 schematically shows the architecture used to organize cards in a frame 202, in the presently preferred embodiment. Several types of cards are used.

First, a master card 304 (controlled at least partly through a local interface to a mapping and test panel 308) controls the backplane 320. Second, there will be one or more high-speed interface cards 306. In the presently preferred embodiment, these cards interface to high-speed lines 108, using an X25-like protocol, at a data rate of up to 64K bits per second. Third, there will be one or more buffer cards 312. The buffer cards basically hold memory: one card can write information into a buffer location, and another card can read it out over the AMD bus 320. Fourth, there will be one or more programmable low-speed interface cards 302, which interface to low-speed lines 106 (which may operate, for example, at 9600 bps) .

Figure 3 shows a sample frame 202, including power supply 316, data entry panel 318, and chassis 322.

Master Cards

The master cards 304 define the channel mappings for the memory blocks in the buffer. When these mappings have been defined or redefined, the interfaces of the various cards through memory have been defined. Local Bus

The AMD bus 320, as used in the presently preferred embodiment, is physically 90 lines wide

(45 on each side of each card) . It uses 16 of these lines for data, and operates at a clock rate of about 1.01 MegaHertz.

The. AMD bus 320 has one dedicated line which indicates, whether it is carrying control signals or data... T . also contains two more dedicated lines which: indicate which of the four possible channels the:- bus- is talking to. It also includes several lines;which are dedicated to card addressing.

Buffer Cards The buffer cards 312 are used to provide temporary storage for data in transit.

Programmable Interface Cards The interface^*card 302 can be thought of as the outermost interface card in the multiplexer system, i.e. as.the "fringe" around the network 101 (which is the complete multiplexer system. This card permits an interface from individual devices (terminals, CPUs, printers, plotters, controllers, modems, etc., connected by lines 106) into the local bus 320 in the multiplexer 202, and thence to other stations elsewhere in the network.

The interface card 302 in the sample embodi¬ ment disclosed can be hardware-configured to interface to any of three electrical standards (RS232, current loop, or RS422) . It can also implement many other data transfer options, including baud rates, parity protocols, handshaking protocols, automatic baud rate detection options, error correction options, etc.. Thus, the soft interface card 302 permits terminals, hosts, etc. , to interface into the AMD bus in the frame 202. In the presently preferred embodiment, each soft interface card 302 can interface from the bus 320 network to up to four individual devices.

Hiσh-Speed Line Driver Cards The high-speed interface cards 306 provide a high-speed modem interface to carry composite framed data to and from the multiplexer station 110. In the presently preferred embodiment, these cards 306 are usually connected to a twisted-pair channel of up to 64K bits/sec.

Extension Units Each frame 202 which includes a master card 304 -may be regarded as a "master frame". . In addition, each master frame 202 can- also control up to four extension frames 202*. The master frame and extension frames will be linked by a bus extension module (card) 314 in the master frame, and a bus transmission module (card) in each extension frame. The extension frames 202' can include soft interface cards 302, but not high¬ speed interface cards 306 or master cards 304. Thus, the number of peripheral interfaces 106 per high speed interface 108 can be expanded, for the high-speed interface capacity of a single master frame. Qptional Cards

The frame 202 may also optionally contain additional cards, such as USO cards. USO cards are user switching option cards, which permit the asynchronous ports to use a short form addressing, e.g., use the logical names to address destina¬ tions.

Another common option is gateway cards, which provide a high-speed interface to a host.

Implementation of Programmable Interface As noted above, the presently preferred embodiment provides a programmable interface card 302, within a multi-card multiplexer station, exploiting some of the novel configuration command capabilities provided herein. (Of course, this is not by any means the only way to take advantage of these novel teachings.)^' The structure of^*this card, in the presently preferred embodiment, will now be described in detail.

General Hardware Figure 4 shows a simple view of the key data flow paths in the card 302, in the presently preferred embodiment. A Motorola 68000 is used for CPU 404. Two DUART (dual asynchronous receiver/- transmitter) chips 402 are used to interface to lines 106. (Line driver chips are also used, to convert the TTL outputs of the DUART chips 402 to ±12 Volt levels.) Preferably a local buffer 406 is also used. The interface 408 to the backplane 320 is simple, and preferably only includes TTL latches. Software Structure In the presently preferred embodiment, the programmable interface boards 302 include resident firmware for processor 404 which will now be described with reference to Figure 5. (Those of ordinary skill will readily recognize that a tremendous variety of methods can be used to implement the functionality described below.)

This software includes a foreground task 502 running all non-time-critical functions, and three background interrupt tasks 504, 506, and 508 performing the time-critical functions.

The foreground task 502 runs continually, and is responsible for managing the supervisor func- tions, polling the front panel switches 802, writing to the LED display 804, processing the bar code reader commands, and polling the front panel connector 801 to identify which devices (if any) are attached. The foreground task is also respons- ible for driving LED warning indicators 806, except that the t/d (transmit data) and r/d (receive data) lights are driven by signals from the driver chips 402, subject to multiplexing logic controlled by the processor 404. One time-critical task is an interrupt driven task 504 which is responsible for data transmission and status update for the channels within the card. The interrupt is driven by a 1.01 millisecond clock from the backplane, and when executed, will do the following: input a character or control code from the backplane 320; output a character or control code to the backplane 320; poll each channel 106 for input charac¬ ters; and output characters to the channels 106.

The control codes which are inputted from and outputted to the AMD bus 320 are used to transfer 5 flow control status, pass RS232 control signal and timing information, and communicate with other cards 304 or 306 in the system. For example, these control codes can be used to propagate the DTR signal from a terminal, through the network, to the

10 host it is connected to.

The next two interrupt tasks 506 and 508 are initiated by timed interrupts from the DUARTs 402. A timer value is entered into the DUART's internal register, and an enabling signal starts a regularly

15 timed interrupt.

The ABR (auto baud rate detect) interrupt task 506 is timed as described above, and runs at 500 microsecond intervals when ABR is enabled and active for at least one channel. It samples the

20. transmit data line for the channel and determines the speed of the attached device.

The control code and control signal propaga¬ tion interrupt task 508 is timed as described above, and runs at 4 millisecond intervals. It

25 monitors the incoming data for control codes, and actions the appropriate response. This task also monitors the control signals from the channels, and injects control codes into the data for delivery to the AMD bus.

30, In the presently preferred embodiment, the soft interface card 302 is set up with password protection, so that changing the programmable options using terminal access requires entry of the appropriate password. However, in the presently

35 preferred embodiment, access via the light pen (or other bar code reader or optical input link) causes the password protection to be bypassed. This is done because, in systems applications such as those to which the preferred embodiment is primarily directed, the primary use of password protection is 5 not so much for data security as to prevent ignorant users from inadvertently disrupting the system configuration. Since it is unlikely that anyone would plug in a light pen (and start reading bar code data) inadvertently, password protection

10. is considered to be not as necessary for input on this channel. However, alternatively, of course, password protection could also be used on the bar code reader channel, by requiring a user ID, printed in the form of a bar code, to be scanned at

15 the outset of each bar code reader session before the card would accept configuration commands from the bar code reader port. Alternatively, the two

.„-- buttons 802^' provided on the front panel could also be₄used for inputting a password in binary form, 0 after the bar code reader had been connected. (That is, the connection of the bar code reader would provide a branch in the logic tree shown in Figure 6.)

The foreground program also polls the front 5 panel switches, and changes the display on the front panel LED accordingly. (Figure 6 shows the various LED display states used in the presently preferred embodiment.) This foreground program also polls the front connector, to detect what has been 0 hooked up to it.

Another function performed in the foreground programing is interpretation of the light pen data, and translation of it to supervisor commands. Command Input Options In the presently preferred embodiment, the front edge of each soft interface card 302 is exposed at the front of frame 202, and includes a 9 pin connector 801, as shown in Figure 8. This connector can be used in any of three ways. First, it can be used as a data output port. There are two push buttons 802 and an LED one-character display 804 on the front, and by pushing the button the available channels for scope monitoring can be scanned through, and the LED display 804 will indicate which channel is currently being scanned. (A sample of the logic implemented for use of the buttons 802 shown in Figure 6.) This is useful in diagnostics.

Secondly, a terminal can be hooked up to this connector 801. The system will detect the presence of the terminal, and permit the terminal to"be used, to control the card 302 in supervisor mode. Thus, the various options available can be addressed through the terminal. A third option is connecting a light pen to this connector, so that the card 302 can receive data which is generated by running the light pen over a bar code. The various connection options use connectors which tie together various pin subsets of the 9 pen connector for the various connection options, so that the card will sense from resistances which option is connected.

Optical Input

The light pen used in the presently preferred embodiment is a standard Hewlett Packard pen (HP model number HBCS2300) . The pen includes digital circuitry to convert the analog optical signals and decode the bar-code, so that what comes into the card through the interface port is digital data. Testinσ the System

Testing the soft interface cards 302 is usually done by configuring them to talk to each other in a daisy chain fashion. Thus, a tester inputs a signal at one end of the daisy chain and tests the return signal for errors. The daisy chain configuration will be implemented by a combination of the AMD bus 320 and cabling. All of the soft interface cards 302 tested in a single run will typically be in one frame 202 (plus optional extension frames 202'). The tester can be any of a variety of testers well known to those skilled in the telecommunications art. In a sample preferred embodiment, the tester used is a Tektronix 834.

In the presently preferred embodiment, the master card 304 also has the capability to put the frame into a self test mode. Thus, the system testing steps described comes after a burn in and self test has been performed.

Since the buffer cards 312 are required in order to use the AMD bus, the daisy chain test procedures described can be used to test the buffer cards 312 as well as the soft interface cards 302. In addition, by including cabling to link two high¬ speed interface cards 306 together, high-speed interface cards 306 can also be tested. Thus, a full system test can be performed very simply: since so many of the system interconnections are programmably reconfigurable, one full set of daisy chain tests (wherein each card has had its inter¬ face tested in each mode) is all that is needed for a complete system test.

The system is tested with hardware configured essentially as the customer has ordered it. That is, the presently preferred embodiment uses the soft reconfiguration capability to test a system full of cards at once, rather than independently testing a large number of individual cards.

After a multiplexer frame 202 is filled with the correct cards in the correct order for the customer specification, test cable is set up to implement the desired daisy chain configuration. The master card 304 is programmed, via the panel 318, to enable the desired daisy chain configura- tion. A light pen is then plugged into each of the soft interface cards 302, and is run over a chosen bar code to set up the soft interface cards 302 appropriately. The tester is cabled into two soft interface cards 302 (configured to be at the ends of the daisy chain) , and is then turn on the for 24 hours. After the 24 hour test has been completed (with zero 1 bit errors) the bar code reader is used again to reconfigure all of the soft interface cards ^'302 to the default settings. That is, the special setups fo"r testing configuration must be removed before the card is shipped.

As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly their scope is not limited except by the allowed claims.

Claims

CLAIMSWhat is Claimed is:

1. A programmable interface system, compris¬ ing: first and second interface ports; a processor connected to implement data transfer between said first and second interface ports in accordance with a programmably alterable interface protocol; and an optical command input, said processor being connected to said input to permit said programmable interface protocols to be altered by said processor selectably in accordance with commands (corresponding to optically stored information) received on said input.

2. A programmable interface system, compris¬ ing: first and second interface ports; a processor connected to implement data transfer between said first and second interface ports in accordance with a programmably alterable interface protocol; and an optical data input, comprising an optical reader and interpretation logic connected to said optical reader; wherein said processor is connected to said input so that said processor can receive commands through said input to alter said program¬ mably alterable interface protocol.

3. A communications system, comprising: a plurality of programmable interface subsystems; wherein plural ones of said interface subsystems are respectively connected with at least one external interface port; and said respective interface subsystems are interconnected to permit data transfer between respective ones of said interface ports in accordance with respective programmably alterable interface protocols; and wherein at least some ones of said interface subsystems comprise optical command inputs connected so that respective one of said programmable interface protocols can be altered by inputting optically stored commands over said optical command input.

4. The system of Claim 1, wherein said optical command input comprises a bar code reader.

5. The system 'of Claim 1, wherein "said optical command input comprises an optical character recognition unit.

6. The system of Claim 1, wherein said optical command input comprises a hand-held sensor unit.

7. The system of Claim 1, wherein said respective interface ports comprise asynchronous receiver/transmitter chips.

8. The system of Claim 1, wherein said processor is located on a common circuit board with physical connections to both of said respective interface ports.

9. The system of Claim 1, wherein said processor is not located on a common circuit board with all physical elements composing both of said interface ports.

10. The system of Claim 1, wherein said processor is connected to control more than one pair of said interface ports.

11. The system of Claim 1, wherein said processor is connected to control more than one pair of said interface ports, and not all of said pairs of interface ports are located on a common circuit board with said processor.

12. The system of Claim 1, wherein said processor comprises at least one microprocessor.

• * *

13. The system of Claim 1, wherein said first and second interface ports, each comprise respective separate -physical connections.

14. The system of Claim 1, wherein said processor is also connected to a second command input, whereby said processor can be accessed by a terminal.

15. The system of Claim 1, wherein said processor comprises a connector at said command input such that a terminal can be connected to said connector to access said processor.

16. The system of Claim 1, wherein said processor comprises a connector at said command input such that a terminal can be connected to said connector to access said processor; and wherein said processor is password protected against at least some commands coming from a terminal at said connector, but not against said commands corresponding to optically stored information.

17. The system of Claim 1, wherein said processor is also connected to a second command input link, whereby said processor can be accessed by a terminal; and wherein said processor is password protected against at least some commands coming out on said second command input link, but not against commands coming in on said optical command input link.

18. The system of Claim 1, wherein no full keyboard is permanently attached to said processor.

^» 19. The system of Claim -l, wherein no data entry pad is permanently attached to said proces¬ sor.

20. The system of Claim 1, wherein said processor is also permanently attached to at least two data entry switches, such that a user can enter a plurality of operational environments of said processor by activating respective ones of said switches in an appropriate sequence.

21. The system of Claim 1, wherein said first interface port has a higher maximum data rate•than said second interface port, and wherein said processor is connected to a plurality of said second interface ports, and multiplexes said plural second interface ports to implement data transfer between said first port and each of said second interface ports.

22. The system of Claim 1, wherein said processor is part of a subsystem, and wherein said subsystem is connected to said first port through a backplane bus, and wherein said subsystem is connected to said second port through cabling which is connected directly to said subsystem.

23. The system of Claim 1, wherein said optical command input comprises a hand-held sensor unit incorporating logic therein.

24. The system of Claim 2, wherein said optical data input comprises a bar code reader.

25. The^' system of Claim 2, wherein said optical data input comprises an optical character recognition unit.

26. The system of Claim 2, wherein said optical data input comprises a hand-held sensor _, unit.

27. The system of Claim 2, wherein said processor is not located on a common circuit board with all physical elements composing both of said interface ports.

28. The system of Claim 2, wherein said processor is connected to control more than two of said interface ports.

29. The system of Claim 2, wherein said first and second interface ports each comprise respective separate physical connections.

30. The system of Claim 2, wherein said processor is also connectable such that a terminal can be connected to access said processor; and wherein said processor is password protected against at least some commands coming from a terminal, but not against said commands corresponding to optically stored information.

31. The system of Claim 2, wherein said processor is also permanently attached to at least two data entry switches, such that a user"can enter a plurality - of operational environments of said processor by activating respective ones of said switches in an appropriate sequence.

32. The system of Claim 2, wherein said first interface port has a higher maximum data rate than said second interface port, and wherein said processor is connected to a plurality of said second interface ports, and multiplexes said plural second interface ports to implement data transfer between said first port and each of said second interface ports.

33. The system of Claim 3, wherein some ones of said interface ports have much higher maximum data rates than other ones of said external interface ports.

34. The system of Claim 3, wherein at least some ones of said subsystems each comprise multiple ones of said external interface ports, and are connected to multiplex said multiple respective interface ports to other said interface ports in said system.

35. The system of Claim 3, wherein at least one of said optical command inputs comprises a bar code reader.

36. The system of Claim 3, wherein at least one said optical command input comprises an optical character recognition unit.

37. The system of Claim 3, wherein at least one said optical command input comprises a hand- held sensor unit incorporating logic therein.