WO1988008616A1

WO1988008616A1 - A method of fabricating a high density masked programmable read-only memory

Info

Publication number: WO1988008616A1
Application number: PCT/US1988/001320
Authority: WO
Inventors: Bruce B. Roesner
Original assignee: Instant Circuit Corporation
Priority date: 1987-04-27
Filing date: 1988-04-21
Publication date: 1988-11-03
Also published as: AU1705588A; US4796074A

Abstract

A read-only memory is fabricated by a methodology wherein a two-dimensional semiconductor diode layer (161) is laid down on a plurality of word lines which have previously been disposed upon an insulator supporting substrate (10). The semiconductor diode layer (161) is disposed on the plurality of word lines (12) without regard to any alignment criteria. A plurality of Schottky diodes is then defined in the semiconductor diode layer. Each Schottky diode is aligned with one of the underlying word lines in a one-to-one mapping. A programmable material (22) is inlaid on the Schottky diodes and the plurality of bit lines (24) laid upon the programmable material. The bit lines (24) are aligned with the underlying Schottky diodes so that the Schottky diodes are again electrically coupled through the programmable material to one bit line in a one-to-one mapping.

Description

A METHOD OF FABRICATING A HIGH DENSITY MASKED

PROGRAMMABLE READ-ONLY MEMORY

__ Background of the Invention

1. Field of the Invention

The invention relates to the field of semiconductor memories as fabricated in integrated circuits and more particularly to a read-only memory and a method for fabricating the same at a high number of devices per unit area of semiconductor chip, i.e. high device density.

2. Description of the Prior Art

Ever since the invention of a first integrated circuit the micro-miniaturization of semiconductor circuits, particularly digital memories, has progressed by decreasing the size of the semiconductor chip allocated to each "memory cell and/or increasing the size of the chip.

The ability to increase the size of the chip is typically limited by substantial loss in yield as the chip area increases. Attempts to decrease the sources of defect in the chips, which cause yields to suffer, have been very complex and uneconomically expensive.

^•Similarly, substantial efforts in the integrated circuit industry in reducing the size of ndividual circuit components within a given area have reached and pushed the inherent limitations of electron beam lithography or X-ray lithography in the attempt to reliably fabricate components with geometries of less than two microns in any one dimension. Further micro-miniaturization beyond a two- micron rule or step has thus far been exceedingly expensive and generally limited by the inherent effects of electron scattering and proximity effects within the semiconductor devices thus fabricated.

As a result, substantial efforts have been undertaken to derive suitable designs for a memory cell within a read¬ only memory which can be reliably fabricated in high densities within the inherent limitations of current manufacturing techniques. Examples of such designs are shown in Roesner, "Method of Forming a Metal Semiconductor Field Effect Transistor", U.S. Patent 4,358,891 (1982);

Roesner, "Mask Programmable Read-Only Memory Stacked above Semiconductor Substrate", U.S. Patent 4,424,579 (1984); Roesner et al., "Reduced-Area, Read-Only Memory", U.S. Patent 4,598,386 (1986); and Roesner, "Electrically Programmable Read-Only Memory Stacked above a Semiconductor Substrate", U.S. Patent 4,442,507 (1984), each of which references are herein expressly incorporated by reference for the enablement purpose of the present disclosure.

The relevance of the prior art is best understood in the context of the art as shown by Roesner '507. Refer particularly to Figure 11 of that patent, a version of whic is recreated here as Figure 1 , and which shows two adjacen cells. The cells are disposed in an insulating substrate 1 on which a heavily N doped word line 12 has been disposed within an etched cavity defined in an overlying insulating layer 14. A lightly N doped diode layer 16 is disposed on and in contact with word line 12. The width, as seen through the cross-sectional view of Figure 1 , of each cell, as defined by its word line width, is approximately 4 microns. A space of 2 microns separates the two adjacent cells, since the 2-micron rule dictates that the minimum spacing which can be reliably defined by present commercial production techniques is 2 microns.

A suicide of a noble metal is disposed within the aperture 18 of each cell in contact with diode layer 16. A Schottky diode is thus formed within the boundaries defined by layers 12 and 16.

Therefore, the total distance which is required betwee Schottky diodes is the amount of space determined by the misalignment of metallic layer 20 with respect to layers ^' 12 and 16, which for a 2-micron process must never be less tha at least 1 micron.

Lightly N-doped programmable material 22- selected from the group of silicon, ^• germanium, carbon and alpha-tin is then disposed over metallic layer 20. Material 22 exhibits a relatively high resistance so long as the voltage across it does not exceed the threshold level. However, once the 1 threshold voltage is exceeded, the resistance of material 22 irreversibly switches from a high resistance state to a relatively low resistance state._

^"~"⁼* ' A^' metallic address line 24 is then disposed upon and

5 connects with programmable material 22 to complete the memory structure as more completely described in Roesner '507.

Very clearly, based upon fabrication methodologies and circuit structures which have heretofore existed, a memory

10 comprised of devices such as shown in Figure 1 cannot be fabricated with a greater density than that which allowed approximately 6 microns between the center of one cell and the next adjacent cell.

Therefore, what is needed is a design for a

15 semiconductor memory and a structure for a memory cell whereby the defects of the prior art are overcome and wherein more particularly a higher density read-only memory can be fabricated using a conventional 2-micron process.

20 Brief Summary of the Invention

The invention is a method of fabricated a read¬ only memory comprises the steps of selectively disposing a plurality of word lines on a semiconductor substrate. - A 25 two-dimensional diode layer is disposed on the word lines and substrate. An insulating layer is selectively disposed_ on the diode layer. The insulating layer has a plurality apertures defined therein. Each aperture is approximately aligned with one of the underlyed word lines. A two- dimensional metallic layer is selectively disposed within each of the apertures defined in the insulating layer in contact with the underlying diode layer to form a Schottky diode therebetween. A programmable layer is disposed in contact with at least the metallic two-dimensional layers disposed within the apertures defined in the insulating layer. A plurality of conductive bit lines are disposed on the programmable layer.. Each bit line is approximately aligned with at least one of the underlying Schottky diodes formed between the two-dimensional metallic layer and the underlying portion of the two-dimensional diode layer. As result, the read-only memory is fabricated w-ith only two alignment steps so that bit line pitch. and word line pitch are each substantially decreased.

In the step of disposing the programmable layer in a first embodiment, the programmable layer is disposed as a integral two-dimensional layer in contact with the insulating layer and the metallic layer formed part of the Schottky diode.

In a second embodiment in the step of disposing the programmable layer, the .programmable layer is selectively disposed to form a corresponded plurality of two-dimensiona contact pads. Each contact pad of the programmable layer i in electrical contact with only one of the two-dimensional metallic layers disposed in the apertures and forms part of the Schottky diode.

In the step of disposing the two-dimensional diode layer, what is disposed is a doped semiconductive material with a vertical resistivity of at least 109 ohms per squar

In the step of disposing the programmable layer, a layer of material selected from a group comprised of silicon, germanium, carbon and alpha-tin with a doped ^• concentration of less than 1017 dopant atoms per cubic centimeter is. disposed and the programmable layer is never subjected to a temperature above 600 degrees C.

The invention is. also an electrical programmable read only memory having memory cells in an insulating layer whi overlies a semiconductor substrate. The invention compris a semiconductor substrate, a plurality of conductive word lines disposed on the substrate, and a first semiconductor material having a polycrystalline grain structure formed a a two-dimensional layer on the plurality of word lines and the substrate. An insulating layer is disposed upon the first semiconductor material. The insulating layer has a plurality of apertures defined therethrough to expose portions of the first semiconductor material. Each of the apertures defined in the insulating layer is approximately aligned with one of the word lines disposed beneath the aperture and the first semiconductor material. A metallic compound is disposed into contact with the first semiconductor material and forms a plurality of Schottky diodes therewith. The metallic compound is disposed in the form of a two-dimensional layer within each of the aperture in the insulating layer. A Schottky diode is formed in eac of the plurality of apertures. A second semiconductor laye is disposed at least within the apertures in electrical contact with the metallic compound. The second semiconductor layer is composed of semiconductor material having a first and second electrical state. The semiconductor material is electrically and permanently configured to the second electrical state from the first electrical state upon application of a threshold signal to the second semiconductor material. A plurality of conductive bit lines is disposed on the second semiconducto material and 'aligned at least with the metallic compound underlying the second semiconductor material. As a result, cell densities in the memory is increased and the bit line and word line pitch decreased without any increase in fabrication and alignment tolerances by which the memory is constructed.

In one embodiment the second semiconductor layer is disposed on the insulating layer and the metallic compound as a two-dimensional layer having an area substantially larger than at least one memory cell and is disposed thereo without regard to alignment to underlying structure. In another embodiment the second semiconductor layer disposed on the underlying metallic compound in the form a plurality of two-dimensional pads. Each _ρad is dispose at least in part in the aperture defined within the insulating layer and is in contact at least in part with metallic compound.

The first electrical state of the second semiconduct layer is a state characterized by high vertical electrica resistivity and the second electrical state is a state characterized by low vertical electrical resistivity. Th signal, which irreversibly configures the second semiconductor" material from the first electrical state to the second electrical state, is a voltage which exceeds a predetermined threshold voltage and which is applied acro at least a portion of the second semiconductor material. Only that portion subjected to the threshold voltage^"is configured from the first electrical state to ^'the second electrical state. The remaining portion of the second semiconductor material, which is not exposed to the threshold voltage, remains in the first electrical state high vertical resistivity.

The second semiconductor material is selected from t group comprised of silicon, germanium, carbon and alpha-t having a crystalline grain size which is smaller than tha of the first semiconductor material and having a concentration of dopant atoms of less than 1017th per cub centimeter.

The first semiconductor material is subjected to temperatures of over 600 degrees C. whereas the second semiconductor material is subjected to temperatures of onl less than 600 degrees C. to achieve its relatively large a small grain sizes as compared to the first semiconductor material.

The invention can also be characterized as an improvement in a method of fabricated a read-only memory i an integrated circuit having a plurality of conductive wor lines and a plurality of conductive bit lines. The plurality of word lines is generally orthogonally oriented with respect to the plurality of bit lines. The read-only memory has a plurality of memory cells. The memory cells are vertically disposed within the integrated circuit between the plurality of word lines and the plurality of b lines. The improvement comprises the steps of disposing a two-dimensional semiconductor diode layer of material on a selected one of either the plurality of word lines or plurality of bit lines, whichever is first disposed on an underlying supported semiconductor substrate. The diode material is disposed as a two-dimensional layer without regard to alignment of the selected one of the plurality o bit lines or word lines. A plurality of Schottky diodes i selectively formed in the diode material. The formation i executed so as to approximately align each one of the

Schottky diodes with at least one of the plurality of word lines or bit lines upon which the diode material is disposed. A programmable material is disposed in electrical communication with at least each one of the plurality of

Schottky diodes. The programmable material is characterized by a high resistivity state reconfigurable to a low resistivity state. The programmable material is irreversibly configured between the two resistivity states by application of a threshold voltage. The threshold voltage alters the electrical state of the programmable material only in the proximity of that portion of the programmable material to which the threshold voltage has been applied. The other one of the plurality of bit lines or word lines is selectively disposed on the programmable material. The other one of the plurality of bit lines or word lines is aligned, when disposed, with at least one of the underlying Schottky diodes. As a result, a read-only memory is fabricated wi -h the necessity for only two alignments between overlying and underlying related elements within the memory so that bit line pitch and word line pitch may be decreased and memory cell density increased.

Refer now to the following drawings wherein like elements are referenced by like numerals. Brief Description of the Drawings

Figure 1 is a cross-sectional diagrammatic partial vi of a prior art memory showing two adjacent memory cells su as the type shown and described in connection with U.S. Patent 4,442,507.

»

Figure 2 is a cross-sectional view of a memory fabricated according to the invention having a structure according to the invention wherein memory density is increased by 30% or more while still using a 2-micron process.

Figure 3 is a cross-sectional view of the memory of Figure 2 taken through an orthogonal direction to the sectional view of Figure 2. Figure 2 illustrates a cross section across the word lines, whereas Figure 3 illustrates a cross section across the bit lines.

The invention and its various embodiments may be bette understood by now turning to the following detailed description.

Detailed Description of the Preferred Embodiment

The word line pitch within a read-only memory may be decreased, thereby increasing the cell density within the memory, without imposing any additional or stricter spacing rules or fabrication techniques utilized in the manufacture of the read-only memory integrated circuit chip. The read¬ only memory is comprised of a plurality of memory cells, each cell of which includes a Schottky diode serially coupled to an electrically programmable resistive element. The resistive elements in a Schottky diode are serially coupled between a corresponding bit line and word line. Application of a voltage exceeding a predetermined threshold of voltage to the resistive element causes the resistive element to irreversibly convert from a high resistive state to a lower resistive state. A read-only memory is fabricated by a methodology wherein a two-dimensional semiconductor diode layer is laid down on a plurality of word lines which have previously been disposed upon a semiconductor supporting substrate. The semiconductor diode layer is disposed on the plurality of word lines without regard to any alignment criteria. A plurality of Schottky diodes is then defined in the semiconductor diode layer. Each Schottky diode is aligned with one of the underlying word lines in a one-to-one mapping. A programmable material is inlaid on the Schottky diodes and the plurality of bit lines laid upon the programmable material. The bit lines are aligned with the underlying Schottky diodes so that the Schottky diodes are again electrically coupled through the programmable material to one bit line in a one-to-one mapping. The bit lines and word lines are orthogonally disposed with respect to the Schottky diodes so that each diode is uniquely addressed by one word line and one bit line. The programmable material may be laid upon the Schottky diode as a two-dimensional layer or as a plurality.^' of strips or paths without regard to any alignment criteria. Because a single alignment is required in each of two orthogonal dimensions between the word line and the Schottky diode in one dimension, or the bit line and Schottky diode in another dimension, the center-to-center word line or bit line pitch may be reduced to four microns and utilizing a fabrication methodology based a two-micron rule. As a result, at least a thirty percent reduction in the amount of space required for each dimension of the cell is realized. Figure 2 illustrates in cross-sectional view a device fabricated according to the invention within a 2-m^'icron rule. Word lines 12 are. disposed in a conventional manner on insulating substrate 10 using the same process by which the same word lines 12 were created in connection with the prior art device illustrated in Figure 1. However, word lines 12 are defined by a single masking step and, when the lightly N doped diode layer 16' is disposed upon the device, the entire diode layer 16' is left in contact and intact rather than being subsequently etched to form diode pads 16 as in the case of the prior art device of Figure 1. The vertical resistivity of the lightly N doped layer 16' is high enough, i.e., more than 109 ohms per square, that word lines 12 which are mutually connected to the two- dimensional layer 16 ' nevertheless remain electrically isolated.

As before, an insulating layer 14 is then disposed on top of diode layer 16 ' followed by the opening of contact apertures 18 through a conventional photolithographic process. However, the Schottky diode programmable layers 2 are disposed on the substrate so as to be coincident or nearly coincident with underlying word lines 12. The device is completed by then disposing and defining programmable layers 22 within apertures 18 on Schottky metallic layers 20 followed by selective deposition of a metallic bit line 24.

The semiconductor layer is fabricated by depositing either silicon or germanium which is doped in situ on the deposited surface. The diode layer is then annealed at temperatures above 600 degrees C. to activate the dopant atoms. On the other hand, the programmable layer is a semiconductor material which is maintained at all points during the fabrication at temperatures at or below 600 degrees C.

It may be readily appreciated by examination of Figure 2 that by being able to align the Schottky contact layer 20 with underlying word line 12 , the word line pitch within th semiconductor memory becomes 4 microns from the center of one cell to the next under a 2-micron rule, rather than the 6-micron word ^"line pitch which was the best that could be achieved under the prior art design of Figure 1.

However, according to the invention,_ not only the wor line pitch but also the bit line pitch is decreased. Turn for example to the cross-sectional view of Figure 3 which a section taken through the device of Figure 2, which is orthogonal to the view illustrated in Figure 2, and is perpendicular across the bit lines and parallel to the wor lines as seen through lines 3--3 of Figure 2. It can be readily appreciated by examining Figure 3 that under a 2- micron rule, bit lines 24 may be spaced one from each othe as close as 2 microns and in turn may have a width of 2 microns. No spacing limitation or restriction arises due any feature of the underlying structure. For example, programmable layer 22 has a high enough resistivity such that it may be left in place such as is shown between devices 26 and 28 or may be etched away as depicted between devices 28 and 30. As long as the interconnecting material of programmable layer 22 remains i its high resistance state, no interfering 'crosstalk betwee the adjacent cells occurs.

In any case, the bit line pitch from the center of one bit line to the next adjacent bit line, as illustrated in Figure 3, is approximately 4 microns since again the only alignment which must be undertaken is a single alignment of the overlying bit line 24 with the underlying Schottky diod layer 20. Neither programmable layer 22 nor underlying diode layer 16 ' nor word line 12 require any additional alignments during the fabrication process.

Figure 4 is a perspective of the embodiment of Figures 2 and 3 which provides a graphic two-dimensional image of the fact: that the alignments which need to be made in a read-only memory according to the invention is the alignment of the Schottky diode layer 20 with underlying word line 12; that the alignment which is made is only in the X -direction as depicted in Figure 4; and that an alignment of the overlying bit line 24 and the underlying Schottky diode 20 is the only alignment made in the Y dimension of Figure 4. No alignment occurs with respect to diode layer 16 ' nor programmable layer 22 inasmuch as either one or both of these layers may be a two-di ensionally integral and contiguous layer within the entire memory.

The illustrated embodiments have been shown only for the purposes of example and should not be taken as limiting the invention which is defined by the following claims. It must be understood that many modifications may be made by those having ordinary skill in the art without departing from the spirit and scope of the invention.

Claims

1. A method of fabricating a read-only memory comprising the steps of: selectively disposing a plurality of word lines on a semiconductor substrate; disposing a two-dimensional diode layer on said word lines and substrate; selectively disposing an insulating layer on said diode layer, said insulating layer having a plurality of apertures defined therein, each aperture being approximately aligned with one of said underlying word lines; selectively disposing a two-dimensional metallic layer within each of said apertures defined in said insulating layer in contact with the underlying diode layer to form a Schottky diode therebetween; disposing a programmable layer in contact with at least said metallic two-dimensional layers disposed within said apertures defined in said insulating layer; disposing a plurality of conductive bit lines on said programmable layer, each bit line being approximately aligned with at least one of said underlying Schottky diodes formed between said two-dimensional metallic layer and said . underlying portion of said two-dimensional diode layer, whereby said read-only memory is fabricated wit only two alignment steps so that bit line pitch and word line pitch are each substantially decreased.

2. The method of Claim 1 where in said step of disposing said programmable layer, said programmable layer is disposed as a integral two-dimensional layer in contact with said insulating layer and said metallic layer forming part of said Schottky diode.

3. The method of Claim 1 where in said step of disposing said programmable layer, said programmable layer is selectively disposed to form a corresponding plurality o two-dimensional contact pads, each contact pad of said programmable layer being in electrical contact with only on of said two-dimensional metallic layers disposed in said apertures and forming part of said Schottky diode.

4. The method of Claim 1 where in said step of disposing said two-dimensional diode layer, what is dispose is a doped semiconductive material with a vertical resistivity of at least 109 ohms per square.

5. The method of Claim 2 where in said step of disposing said two-dimensional diode layer, what is dispose is a doped semiconductive material with a vertical resistivity of at least 109 ohms per square. ^~

6. The method of Claim 3 where in said step of disposing said two-dimensional diode layer, what is dispose is a doped semiconductive material with a vertical resistivity of at least 109 ohms per square.

7. The method of Claim 1 where in said step of disposing said programmable layer, a layer of material selected from a group comprised of silicon, germanium, carbon and alpha-tin with a doping concentration of less than 1017 dopant atoms per cubic centimeter is disposed and where in said method said programmable layer is never subjected to a temperature above' 600 degrees C.

8. An electrical programmable read-only memory having memory cells in an insulating layer which overlies a semiconductor substrate comprising: a semiconductor substrate; a plurality of conductive word lines disposed on said substrate; a first semiconductor material having a polycrystalline grain structure formed as a two-dimensional layer o said plurality of word lines and said substrate; an insulating layer disposed upon said first semiconductor material, said insulating layer having a plurality of apertures defined therethrough exposing portions of said first semiconductor material, each of said apertures defined in said insulating layer being approximately aligned with one of said word lines disposed beneath said aperture and said first semiconductor material; a metallic compound in contact with said first semiconductor material forming a plurality of Schottky diodes therewith, said metallic compound being disposed in the form of a two-dimensional layer within each of said apertures in said insulating layer, a Schottky diode being formed in each of said plurality of apertures; a second semiconductor layer disposed at least within said apertures in electrical contact with said metallic compound, said second semiconductor layer composed of semiconductor material having a first and second electrical state, said semiconductor material being electrically and permanently configured to said second electrical state from said first electrical state upon application of a threshold signal to said second semiconductor material; and a plurality of conductive bit lines disposed on said second semiconductor material and aligned at least v/ith said metallic compound underlying said second semiconductor material, whereby cell densities in said memory is increase and said bit line and word line pitch decreased without any increase in fabrication and alignment tolerances by which said memory is constructed.

9. The memory of Claim 8 wherein said second semiconductor layer is disposed on said insulating layer an said metallic compound as a two-dimensional layer having an area substantially larger than at least one memory cell and disposed thereon without regard to alignment to underlying structure.

10. The memory of Claim 8 wherein said second semiconductor layer is disposed on said underlying metallic compound in the form of a plurality of two-dimensional pads each pad being disposed at least in part in said aperture defined within said insulating layer and in contact at least in part with said metallic compound.

11. The memory of Claim 8 wherein said first electrical state of said second semiconductor layer is a state characterized by high vertical electrical resistivity and wherein said second electrical state is a state characterized by low vertical electrical resistivity, said signal, which irreversibly configures said second semiconductor material from said first electrical state to said second electrical state, being a voltage exceeding a predetermined threshold voltage applied across at least a portion of said second semiconductor material, only that

._» portion being subjected to said threshold voltage being configured from said first electrical state to said second electrical state, the remaining portion of said second semiconductor material, which is not exposed to said threshold voltage, remaining in said first electrical state of high vertical resistivity.

12, The memory of Claim 9 wherein said first electrical state of said second semiconductor layer is a state characterized by high vertical electrical resistivity and wherein said second electrical state is a state characterized by low vertical electrical resistivity, said signal, which irreversibly configures said second semiconductor material from said first electrical state to said second electrical state, being a voltage exceeding a predetermined threshold voltage applied across at least a portion of said- second semiconductor material, only that portion being subjected to said threshold voltage being- configured from said first electrical state to said second electrical state, the remaining portion of said second semiconductor material, which is not exposed to said threshold voltage, remaining in said first electrical state of high vertical resistivity. ^' 13. The memory of Claim 12 wherein said second semiconductor material consists essentially of a single element semiconductor selected from a group of -silicon, germanium, carbon and alpha-tin having a crystalline grain size which is smaller than that of said first semiconducto material and having a concentration of dopant atoms of les than 1017 per cubic centimeter.

14. The memory of Claim 13 wherein said first semiconductor material is subjected to temperatures of ove 600 degrees C. whereas said second semiconductor material subjected to temperatures of only less than 600 degrees C. to achieve its relatively large and small grain sizes as compared to said first semiconductor material.^'

15. An improvement in a method of fabricating a read-only memory in an integrated circuit having a plurali of conductive word lines and a plurality of conductive bit lines, said plurality of word lines being generally orthogonally oriented v/ith respect to said plurality of bi lines, said read-only memory having a plurality of memory cells, said memory cells being vertically disposed within said integrated circuit between said plurality of v/ord lin and said plurality of bit lines, said improvement comprisin : disposing a two-dimensional semiconductor diode layer of material on a selected one of either said plurality of word lines or plurality of bit lines whichever is first disposed on an underlying supporting semiconductor substrate, said diode material being disposed as a two- dimensional layer without regard to alignment of said selected one of said plurality of bit lines or word lines; selectively forming a plurality of Schottky diodes in said diode material, said formation being executed so as to approximately align each one of said Schottky diodes with at least one of said plurality of word lines or bit lines upon which said diode material is disposed; disposing a programmable material in electrical communication with at least each one of said plurality of Schottky diodes, .said programmable material being characterized by a high resistivity state reconfigurable to a low resistivity state,- said programmable material being irreversibly configured between said two resistivity states by application of a threshold voltage, said threshold voltage altering the electrical state of said programmable material only in the proximity of that portion of said programmable material to which said threshold voltage has been applied; and selectively disposing said other one of said plurality of bit lines or word lines on said programmable material, said other one of said plurality of bit lines or word lines being aligned, when disposed, with at least one of said underlying Schottky diodes,

Whereby a read-only memory is fabricated with the necessity for only two alignments between overlying and underlying related elements within said memory so that bit line pitch and' word line pitch may be decreased and memory

» cell density increased.

16. The improvement of Claim 15 where said step of disposing said programmable material comprises the step of disposing a two-dimensional layer of said programmable material over said plurality of Schottky diodes without regard to alignment with respect to aid Schottky diodes or any other element within said memory,

17. The method of Claim 15 where in said step of disposing said programmable material, said^' programmable material is disposed in the form of a plurality of two- dimensional pads, each two-dimensional pad being approximately aligned v/ith at least a subplurality of underlying Schottky diodes formed within said memory.

^' 18. The improvement of Claim 15 further comprising the steps of selectively applying a predetermine pattern of voltages to said plurality of bit lines and to said plurality of word lines in a predetermined sequence convert selected portions of said programmable material irreversibly between said two electrical states.

19. The improvement of Claim 16 further comprising the steps of selectively applying a predetermine pattern of voltages to said plurality of bit lines and to said plurality of word lines in a predetermined sequence to convert selected portions of said programmable material irreversibly between said two electrical states.