WO1988002553A3 - Integrated circuit packaging configuration for rapid customized design and unique test capability - Google Patents

Integrated circuit packaging configuration for rapid customized design and unique test capability Download PDF

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Publication number
WO1988002553A3
WO1988002553A3 PCT/US1987/002497 US8702497W WO8802553A3 WO 1988002553 A3 WO1988002553 A3 WO 1988002553A3 US 8702497 W US8702497 W US 8702497W WO 8802553 A3 WO8802553 A3 WO 8802553A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
high density
customization
advantage
circuit packaging
Prior art date
Application number
PCT/US1987/002497
Other languages
French (fr)
Other versions
WO1988002553A2 (en
Inventor
Charles William Eichelberger
Kenneth Brakeley Ii Welles
Robert John Wojnarowski
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of WO1988002553A2 publication Critical patent/WO1988002553A2/en
Publication of WO1988002553A3 publication Critical patent/WO1988002553A3/en
Priority to KR1019880700594A priority Critical patent/KR880701972A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

High density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips (10) are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns (30). All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.
PCT/US1987/002497 1986-09-26 1987-09-28 Integrated circuit packaging configuration for rapid customized design and unique test capability WO1988002553A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880700594A KR880701972A (en) 1986-09-26 1988-05-26 Integrated circuit packaging configuration for high-speed custom design and test

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US912,457 1986-09-26
US06/912,457 US4866508A (en) 1986-09-26 1986-09-26 Integrated circuit packaging configuration for rapid customized design and unique test capability

Publications (2)

Publication Number Publication Date
WO1988002553A2 WO1988002553A2 (en) 1988-04-07
WO1988002553A3 true WO1988002553A3 (en) 1988-05-05

Family

ID=25431958

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1987/002497 WO1988002553A2 (en) 1986-09-26 1987-09-28 Integrated circuit packaging configuration for rapid customized design and unique test capability

Country Status (5)

Country Link
US (1) US4866508A (en)
EP (1) EP0283515A1 (en)
JP (1) JPH01501033A (en)
KR (1) KR880701972A (en)
WO (1) WO1988002553A2 (en)

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US5424589A (en) * 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
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US5731223A (en) * 1996-09-24 1998-03-24 Lsi Logic Corporation Array of solder pads on an integrated circuit
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US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
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US6225821B1 (en) * 1998-05-18 2001-05-01 Lattice Semiconductor Corporation Package migration for related programmable logic devices
US6111756A (en) * 1998-09-11 2000-08-29 Fujitsu Limited Universal multichip interconnect systems
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EP0178227A2 (en) * 1984-10-05 1986-04-16 Fujitsu Limited Integrated circuit semiconductor device formed on a wafer

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Also Published As

Publication number Publication date
WO1988002553A2 (en) 1988-04-07
EP0283515A1 (en) 1988-09-28
US4866508A (en) 1989-09-12
KR880701972A (en) 1988-11-07
JPH01501033A (en) 1989-04-06

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