WO1985000694A1 - Shallow-junction semiconductor devices - Google Patents

Shallow-junction semiconductor devices Download PDF

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Publication number
WO1985000694A1
WO1985000694A1 PCT/US1984/000851 US8400851W WO8500694A1 WO 1985000694 A1 WO1985000694 A1 WO 1985000694A1 US 8400851 W US8400851 W US 8400851W WO 8500694 A1 WO8500694 A1 WO 8500694A1
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WO
WIPO (PCT)
Prior art keywords
species
neutral
depth
junction
approximately
Prior art date
Application number
PCT/US1984/000851
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French (fr)
Inventor
Michael James Kelly
Hyman Joseph Levinstein
Shyam Prasad Murarka
David Stanley Yaney
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American Telephone & Telegraph Company
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Publication date
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Publication of WO1985000694A1 publication Critical patent/WO1985000694A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2252Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material

Definitions

  • This invention relates to shallow-junction semiconductor devices.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a neutral species is initially implanted into a surface region of a semiconductor body.
  • the neutral species is implanted to form a layer whose maximum concentration occurs at a depth greater than that of a p-n junction to be subsequently formed.
  • the junction is subsequently established at a depth that is greater than the depth of the peak concentration of the neutral-species layer.
  • a dopant species is then implanted into the surface region at a depth less than the depth of the maximum-concentration of the previously implanted neutral species. Annealing to activate the dopant species is then carried out.
  • the neutral-species layer serves to getter point defects in the body of the device. Additionally, this layer serves as a physical barrier to diffusion of dopant species. As a result, the diffusivity of the dopant species in the body is significantly lowered relative to the case in which no neutral-species layer is provided. In any event, the result is that a p-n junction is formed in the body of the device at an extremely shallow depth.
  • FIGS. 1 through 4 are schematic representations of a portion of a MOSFET device at successive stages of a fabrication sequence that embodies the principles of the present invention. Detailed Description
  • shallow p-n junctions can be formed in a variety of semiconductor devices. These devices include, for example, p-n diodes, bipolar transistors and MOSFET devices. By way of example, the invention is described in connection with the provision of shallow p-n junctions in a MOSFET device.
  • FIG. 1 A portion of such a MOSFET device at an intermediate stage of its fabrication cycle is shown in FIG. 1, such portion comprising a known gate-and-source-and -drain (GASAD) structure.
  • the structure comprises a silicon body 10 having field-oxide (silicon dioxide) portions 12, 14 thereon.
  • the structure further includes a gate-oxide (silicon dioxide) layer 16, a doped polysilicon layer 18, and a metallic suicide (e.g. tantalum disilicide) layer 20. Also, the structure includes additional silicon dioxide layers 22,24. Openings 25, 26 are defined by the oxide layers 12, 22 and 14, 24. Source and drain regions are later formed in the body 10 in approximate alignment with these openings.
  • a so-called neutral species is implanted into regions of body 10 defined by the openings 25, 26.
  • Known ion implantation techniques can be used.
  • neutral species means ion species that do not produce active carriers in the semiconductor body and that are effective to limit the diffusivity of active species in the body.
  • neutral species include carbon, oxygen, argon or any other inert gas.
  • Group IV elements such as silicon, germanium and tin, and nitrogen (minor activity) .
  • the peak or maximum concentration of the approximately Gaussian-shaped distribution of the neutral-species implant in the body 10 is schematically depicted by lines 30, 32 formed with x's.
  • the dosage of the neutral-species implant represented in FIG. 2 is selected to provide approximately one or two monolayers of the neutral species at the peak-concentration depth.
  • the energy of the incident ions is selected such that the peak concentration of the implanted neutral species occurs approximately 2000 A below the surface of the body 10.
  • the peak concentration of the neutral-species implant is selected to occur at a depth greater than that of the p-n junction(s) to be subsequently formed in the body 10.
  • the depth of the subsequently formed p-n junction(s) is, for example, approximately one-tenth to three-quarters that of the depth of the peak concentration of the neutral species. (In other devices, described below, the depth of the p-n junction(s) is greater than the depth of the peak concentration of the neutral-species implant.)
  • dosages and energies can be used.
  • One set of dosage and energy values for the aforelisted neutral species is as follows: carbon, 5 x 10 15 ions per square centimeter (i/cm 2 ), 80 kilo-electron-volts (keV); oxygen, 5 x 10 15 i/cm9 46 , 80 keV; silicon, 5 x
  • the respective peak-concentration depth of each of the neutral species is approximately 2000 A below the surface of the body 10 shown in FIG. 2.
  • the device structure represented in FIG. 2 is next subjected to an annealing step.
  • active species such as arsenic
  • the annealing is done, for example, at a temperature in the range 700-to-900 degrees Celsius in an inert ambient for about one-half hour. During annealing, no substantial vertical or lateral movement of the implanted neutral species occurs. Nor does any substantial movement occur later during the so-called activation annealing step described below.
  • an active species is introduced into the structure by any of various known means, e.g., by ion implantation, as indicated by the arrows 34 in FIG. 3.
  • the implanted active species comprises, for example, a pentavalent n-type impurity such as arsenic, phosphorus or antimony, or a trivalent p-type impurity such as boron or gallium.
  • the depth of the peak or maximum concentration of the approximately Gaussian-shaped distribution of the active-species implant in the body 10 is schematically represented in FIG. 3 by " lines 36, 38 formed with dots.
  • the peak concentration of the implanted active species is selected to occur relatively close to the top surface of the body 10, e.g., at a depth of approximately 200-to-1000 A.
  • an arsenic implant having a peak- concentration depth 36, 38 of approximately 200 A is achieved by implanting 4 x 10 i/c ⁇ r at 30 keV.
  • a carbon or nitrogen implant having a peak-concentration depth 30 , 32 ( FIG . 3 ) of about 2000 A a boron implant
  • OMPI ⁇ ⁇ ⁇ Wl? ⁇ having a peak-concentration depth 36, 38 of approximately 1000 A is achieved by implanting 4 x 10 1 5 i/cm 2 at 30 keV.
  • Extremely shallow p-n junctions are thereby formed.
  • activation annealing is carried out at, for example, about 1000 degrees Celsius for approximately three hours in a standard mildly dry oxidizing atmosphere.
  • the resulting p-n junction is at a depth of approximately 1400 A.
  • the p-n junction is at a depth of about 3700 A.
  • activation annealing is carried out at, for example, about 900 degrees Celsius for approximately five hours in a standard mildly dry oxidizing atmosphere.
  • the p-n junction occurs at approximately 3300 A. without the presence of the neutral-species implant, but with all other processing conditions approximately the same, the p-n junction occurs at a depth of about 6700 A.
  • the p-n junction is at a depth less than the depth of the peak concentration of an implanted neutral species layer.
  • the p-n junction is at a depth greater than the depth of the peak concentration of the implanted neutral-species layer.
  • the active impurity species can be initially introduced into the device structure at a shallower depth than specified above for boron and/or by activation annealing the structure at a lower temperature than specified above.
  • the peak concentration of the neutral- species layer can be initially formed sufficiently deep that, after annealing, the junction is established at a depth less than the depth of the peak concentration of the neutral-species layer.

Abstract

A shallow-junction semiconductor device is fabricated by initially implanting a neutral species (non-doping impurity) into a surface region (30, 32) of a semiconductor body (10) prior to the introduction of a dopant therein. This implant serves as a getter for defects and also as a physical barrier. The thermal diffusivity of subsequently introduced dopant species is thereby significantly reduced. As a result, extremely shallow junctions (36, 38) are realized.

Description

SHALLOW-JUNCTION SEMICONDUCTOR DEVICES
Background of the Invention
This invention relates to shallow-junction semiconductor devices.
In various semiconductor devices, such as the metal-oxide-semiconductor field-effect transistor (MOSFET), it is desirable that a p-n junction of the device be as close to a substrate surface as possible. The present invention provides a means for obtaining p-n junctions which are significantly closer to a semiconductor body surface than was heretofore obtainable. Summary of the Invention
A neutral species is initially implanted into a surface region of a semiconductor body. In one example, the neutral species is implanted to form a layer whose maximum concentration occurs at a depth greater than that of a p-n junction to be subsequently formed. (In another example, the junction is subsequently established at a depth that is greater than the depth of the peak concentration of the neutral-species layer.) A dopant species is then implanted into the surface region at a depth less than the depth of the maximum-concentration of the previously implanted neutral species. Annealing to activate the dopant species is then carried out.
It is theorized that during this annealing step, the neutral-species layer serves to getter point defects in the body of the device. Additionally, this layer serves as a physical barrier to diffusion of dopant species. As a result, the diffusivity of the dopant species in the body is significantly lowered relative to the case in which no neutral-species layer is provided. In any event, the result is that a p-n junction is formed in the body of the device at an extremely shallow depth. Brief Description of the Drawing
FIGS. 1 through 4 are schematic representations of a portion of a MOSFET device at successive stages of a fabrication sequence that embodies the principles of the present invention. Detailed Description
In accordance with this invention, shallow p-n junctions can be formed in a variety of semiconductor devices. These devices include, for example, p-n diodes, bipolar transistors and MOSFET devices. By way of example, the invention is described in connection with the provision of shallow p-n junctions in a MOSFET device. A portion of such a MOSFET device at an intermediate stage of its fabrication cycle is shown in FIG. 1, such portion comprising a known gate-and-source-and -drain (GASAD) structure. The structure comprises a silicon body 10 having field-oxide (silicon dioxide) portions 12, 14 thereon.
The structure further includes a gate-oxide (silicon dioxide) layer 16, a doped polysilicon layer 18, and a metallic suicide (e.g. tantalum disilicide) layer 20. Also, the structure includes additional silicon dioxide layers 22,24. Openings 25, 26 are defined by the oxide layers 12, 22 and 14, 24. Source and drain regions are later formed in the body 10 in approximate alignment with these openings.
In accordance with the invention, a so-called neutral species is implanted into regions of body 10 defined by the openings 25, 26. Known ion implantation techniques can be used.
The term "neutral species" means ion species that do not produce active carriers in the semiconductor body and that are effective to limit the diffusivity of active species in the body. Such neutral species include carbon, oxygen, argon or any other inert gas. Group IV elements such as silicon, germanium and tin, and nitrogen (minor activity) . ions directed at the FIG. 2 structure are represented by arrows 28, the ions reaching the body 10 only through the openings 25, 26. In FIG. 2, the depth of
O the peak or maximum concentration of the approximately Gaussian-shaped distribution of the neutral-species implant in the body 10 is schematically depicted by lines 30, 32 formed with x's. Illustratively, the dosage of the neutral-species implant represented in FIG. 2 is selected to provide approximately one or two monolayers of the neutral species at the peak-concentration depth. Additionally, for the illustrative MOSFET device shown, the energy of the incident ions is selected such that the peak concentration of the implanted neutral species occurs approximately 2000 A below the surface of the body 10. In some devices, the peak concentration of the neutral-species implant is selected to occur at a depth greater than that of the p-n junction(s) to be subsequently formed in the body 10. In such devices, the depth of the subsequently formed p-n junction(s) is, for example, approximately one-tenth to three-quarters that of the depth of the peak concentration of the neutral species. (In other devices, described below, the depth of the p-n junction(s) is greater than the depth of the peak concentration of the neutral-species implant.) Various dosages and energies can be used. One set of dosage and energy values for the aforelisted neutral species is as follows: carbon, 5 x 10 15 ions per square centimeter (i/cm2), 80 kilo-electron-volts (keV); oxygen, 5 x 10 15 i/cm946, 80 keV; silicon, 5 x
1015 i/cm2, 150 keV; germanium, 5 x 1015 i/cm2, 300 keV; tin, 5 x 1015 i/cm2, 400 keV; argon, 5 x 10 15 i/cm946, 180 keV; and nitrogen, 5 x 10 15 i/cm*6, 80 keV. For these values, the respective peak-concentration depth of each of the neutral species is approximately 2000 A below the surface of the body 10 shown in FIG. 2.
In some, but not necessarily all cases, the device structure represented in FIG. 2 is next subjected to an annealing step. (For a subsequently introduced active species such as arsenic, it may actually be advantageous
_ O
• - wip
^ .N' not to anneal the implanted neutral species at this point in the fabrication procedure.) In this annealing step, - damage to the crystalline structure of the body 10 caused by the neutral-species implant is reduced. Further, the implanted species is stabilized and in effect locked in place in the body 10. Also, some gettering of defects and impurities in the body 10 typically occurs during this annealing step.
The annealing is done, for example, at a temperature in the range 700-to-900 degrees Celsius in an inert ambient for about one-half hour. During annealing, no substantial vertical or lateral movement of the implanted neutral species occurs. Nor does any substantial movement occur later during the so-called activation annealing step described below.
Next, an active species is introduced into the structure by any of various known means, e.g., by ion implantation, as indicated by the arrows 34 in FIG. 3. The implanted active species comprises, for example, a pentavalent n-type impurity such as arsenic, phosphorus or antimony, or a trivalent p-type impurity such as boron or gallium.
The depth of the peak or maximum concentration of the approximately Gaussian-shaped distribution of the active-species implant in the body 10 is schematically represented in FIG. 3 by "lines 36, 38 formed with dots.
The peak concentration of the implanted active species is selected to occur relatively close to the top surface of the body 10, e.g., at a depth of approximately 200-to-1000 A.
More specifically, for a carbon neutral species implant having a peak-concentration depth 30, 32 (FIG. 3) of about 2000 A, an arsenic implant having a peak- concentration depth 36, 38 of approximately 200 A is achieved by implanting 4 x 10 i/cπr at 30 keV. For a carbon or nitrogen implant having a peak-concentration depth 30 , 32 ( FIG . 3 ) of about 2000 A , a boron impl ant
OMPI Λ ~ Wl?θ having a peak-concentration depth 36, 38 of approximately 1000 A is achieved by implanting 4 x 1015 i/cm2 at 30 keV.
Subsequently, standard activation annealing of the second-implanted or active dopant species is carried out. During this step, it is believed that gettering of point defects and metallic impurities occurs in the body 10. It appears also that, because of this gettering action, the thermal diffusivity of the active species is substantially reduced relative to what it would have been in the absence of the neutral-species implant. Additionally, it appears that the priorly formed neutral-species implant serves as a physical barrier against diffusion of the active species. However, regardless of the physical phenomena involved, the result of the described process is that the p-n junction formed by the active-species implant occurs at a depth far less than it would have been if the neutral-species implant had not been present. Extremely shallow p-n junctions are thereby formed. For an active-species implant of arsenic, activation annealing is carried out at, for example, about 1000 degrees Celsius for approximately three hours in a standard mildly dry oxidizing atmosphere. The resulting p-n junction is at a depth of approximately 1400 A. without the priorly implanted neutral-species, but with all other processing conditions approximately the same, the p-n junction is at a depth of about 3700 A.
For an active-species implant of boron, activation annealing is carried out at, for example, about 900 degrees Celsius for approximately five hours in a standard mildly dry oxidizing atmosphere. The p-n junction occurs at approximately 3300 A. without the presence of the neutral-species implant, but with all other processing conditions approximately the same, the p-n junction occurs at a depth of about 6700 A.
In the example above in which the active species comprises arsenic, the p-n junction is at a depth less than the depth of the peak concentration of an implanted neutral species layer. Conversely, in the example above in which the active species comprises boron, the p-n junction is at a depth greater than the depth of the peak concentration of the implanted neutral-species layer. In general, it is feasible to form p-n junctions at a depth in the range of approximately one-tenth to two times the depth of the peak concentration of the implanted neutral-species layer.
It is possible to form the p-n junction at a depth less than the depth of the peak concentration of the implanted neutral-species layer or in a number of ways. For example, the active impurity species can be initially introduced into the device structure at a shallower depth than specified above for boron and/or by activation annealing the structure at a lower temperature than specified above. Or the peak concentration of the neutral- species layer can be initially formed sufficiently deep that, after annealing, the junction is established at a depth less than the depth of the peak concentration of the neutral-species layer.

Claims

Claims
1. A device comprising: a semiconductor body (10) CHARACTERIZED BY a neutral-species layer (30, 32) in said body having a profile whose peak concentration is at a predetermined depth below a surface of said body, and a p-n junction (36,38) in said body at a depth below said surface that is approximately one-tenth to two times that of said predetermined depth.
2. A device as in claim 1 wherein said neutral species is selected from the group consisting of carbon, oxygen, silicon, germanium, tin, an inert gas and nitrogen.
3. A device as in claim 2 wherein said p-n junction is established in said body at a depth that is approximately one-tenth to three quarters that of the depth of the peak concentration of said neutral species.
4. A device as in claim 1 wherein the peak concentration of said neutral-species layer is approximately 2000 A below said surface and said junction is approximately 1400 A below said surface.
5. A method of fabricating a semiconductor device, CHARACTERIZED BY the steps of implanting a neutral species through a surface of a semiconductor body (10) to form a neutral-species layer (30,32) having a peak concentration at a predetermined depth below said surface, introducing an active species through said surface, and annealing said body to activate said active species and to establish a p-n junction (36, 38) in said body.
6. A method as in claim 5 wherein the peak concentration of the active species introduced through said surface is established, before annealing, at a depth that is less than the depth of the peak concentration of said neutral-species layer.
7. A method as in claim 6 wherein said junction is established after annealing at a depth in the range of approximately one-tenth to two times said predetermined depth.
8. A method as in claim 7 wherein said neutral species is selected from the group consisting of carbon, oxygen, silicon, germanium, tin, an inert gas and nitrogen.
PCT/US1984/000851 1983-07-25 1984-06-04 Shallow-junction semiconductor devices WO1985000694A1 (en)

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US516,755 1995-08-18

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2578096A1 (en) * 1985-02-28 1986-08-29 Bull Sa Method of manufacturing an MOS transistor and resulting integrated circuit device
EP0209939A1 (en) * 1985-07-11 1987-01-28 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
EP0350845A2 (en) * 1988-07-12 1990-01-17 Seiko Epson Corporation Semiconductor device with doped regions and method for manufacturing it
EP0417955A1 (en) * 1989-09-08 1991-03-20 Fujitsu Limited Shallow junction formation by ion-implantation
US5654209A (en) * 1988-07-12 1997-08-05 Seiko Epson Corporation Method of making N-type semiconductor region by implantation
EP0806794A2 (en) * 1996-04-29 1997-11-12 Texas Instruments Incorporated Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation
WO1997042652A1 (en) * 1996-05-08 1997-11-13 Advanced Micro Devices, Inc. Control of junction depth and channel length using generated interstitial gradients to oppose dopant diffusion
WO1999025021A1 (en) * 1997-11-12 1999-05-20 Advanced Micro Devices, Inc. Preventing boron penetration through thin gate oxide of p-channel devices in advanced cmos technology
WO1999033103A1 (en) * 1997-12-19 1999-07-01 Advanced Micro Devices, Inc. Semiconductor device having a pmos device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
US6087209A (en) * 1998-07-31 2000-07-11 Advanced Micro Devices, Inc. Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant
US6146934A (en) * 1997-12-19 2000-11-14 Advanced Micro Devices, Inc. Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
EP1282158A1 (en) * 2001-07-31 2003-02-05 STMicroelectronics S.A. Method of manufacturing a bipolar transistor in an integrated CMOS circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190849A (en) * 1992-01-14 1993-07-30 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3796929A (en) * 1970-12-09 1974-03-12 Philips Nv Junction isolated integrated circuit resistor with crystal damage near isolation junction
US4069068A (en) * 1976-07-02 1978-01-17 International Business Machines Corporation Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions
JPS53120263A (en) * 1977-03-29 1978-10-20 Nec Corp Manufacture of semiconductor device
JPS553828B2 (en) * 1972-11-30 1980-01-26
JPS5583263A (en) * 1978-12-19 1980-06-23 Fujitsu Ltd Mos semiconductor device
JPS55121680A (en) * 1979-03-13 1980-09-18 Nec Corp Manufacture of semiconductor device
JPS5627924A (en) * 1979-08-14 1981-03-18 Toshiba Corp Semiconductor device and its manufacture
JPS5632742A (en) * 1979-08-24 1981-04-02 Toshiba Corp Manufacture of semiconductor device
JPS5693367A (en) * 1979-12-20 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
EP0042552A2 (en) * 1980-06-16 1981-12-30 Kabushiki Kaisha Toshiba MOS type semiconductor device
JPS57106123A (en) * 1980-12-24 1982-07-01 Toshiba Corp Manufacture of semiconductor device
JPS5856417A (en) * 1981-09-30 1983-04-04 Toshiba Corp Low-temperature activating method for boron ion implanted layer in silicon

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492786B1 (en) * 1969-03-28 1974-01-22

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3796929A (en) * 1970-12-09 1974-03-12 Philips Nv Junction isolated integrated circuit resistor with crystal damage near isolation junction
JPS553828B2 (en) * 1972-11-30 1980-01-26
US4069068A (en) * 1976-07-02 1978-01-17 International Business Machines Corporation Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions
JPS53120263A (en) * 1977-03-29 1978-10-20 Nec Corp Manufacture of semiconductor device
JPS5583263A (en) * 1978-12-19 1980-06-23 Fujitsu Ltd Mos semiconductor device
JPS55121680A (en) * 1979-03-13 1980-09-18 Nec Corp Manufacture of semiconductor device
JPS5627924A (en) * 1979-08-14 1981-03-18 Toshiba Corp Semiconductor device and its manufacture
JPS5632742A (en) * 1979-08-24 1981-04-02 Toshiba Corp Manufacture of semiconductor device
JPS5693367A (en) * 1979-12-20 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
EP0035598A2 (en) * 1979-12-20 1981-09-16 Fujitsu Limited A method of manufacturing a semiconductor device having reduced leakage currents
EP0042552A2 (en) * 1980-06-16 1981-12-30 Kabushiki Kaisha Toshiba MOS type semiconductor device
JPS57106123A (en) * 1980-12-24 1982-07-01 Toshiba Corp Manufacture of semiconductor device
JPS5856417A (en) * 1981-09-30 1983-04-04 Toshiba Corp Low-temperature activating method for boron ion implanted layer in silicon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0151585A4 *

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2578096A1 (en) * 1985-02-28 1986-08-29 Bull Sa Method of manufacturing an MOS transistor and resulting integrated circuit device
EP0209939A1 (en) * 1985-07-11 1987-01-28 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
WO1987004860A1 (en) * 1986-02-07 1987-08-13 Motorola, Inc. Partially dielectrically isolated semiconductor devices
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
EP0350845A2 (en) * 1988-07-12 1990-01-17 Seiko Epson Corporation Semiconductor device with doped regions and method for manufacturing it
EP0350845A3 (en) * 1988-07-12 1991-05-29 Seiko Epson Corporation Semiconductor device with doped regions and method for manufacturing it
US5654209A (en) * 1988-07-12 1997-08-05 Seiko Epson Corporation Method of making N-type semiconductor region by implantation
EP0417955A1 (en) * 1989-09-08 1991-03-20 Fujitsu Limited Shallow junction formation by ion-implantation
US5145794A (en) * 1989-09-08 1992-09-08 Fujitsu Limited Formation of shallow junction by implantation of dopant into partially crystalline disordered region
EP0806794A2 (en) * 1996-04-29 1997-11-12 Texas Instruments Incorporated Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation
EP0806794A3 (en) * 1996-04-29 1998-09-02 Texas Instruments Incorporated Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation
WO1997042652A1 (en) * 1996-05-08 1997-11-13 Advanced Micro Devices, Inc. Control of junction depth and channel length using generated interstitial gradients to oppose dopant diffusion
US5825066A (en) * 1996-05-08 1998-10-20 Advanced Micro Devices, Inc. Control of juction depth and channel length using generated interstitial gradients to oppose dopant diffusion
WO1999025021A1 (en) * 1997-11-12 1999-05-20 Advanced Micro Devices, Inc. Preventing boron penetration through thin gate oxide of p-channel devices in advanced cmos technology
US5973370A (en) * 1997-11-12 1999-10-26 Advanced Micro Devices, Inc. Preventing boron penetration through thin gate oxide of P-channel devices in advanced CMOS technology
WO1999033103A1 (en) * 1997-12-19 1999-07-01 Advanced Micro Devices, Inc. Semiconductor device having a pmos device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
US6013546A (en) * 1997-12-19 2000-01-11 Advanced Micro Devices, Inc. Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
US6146934A (en) * 1997-12-19 2000-11-14 Advanced Micro Devices, Inc. Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
US6087209A (en) * 1998-07-31 2000-07-11 Advanced Micro Devices, Inc. Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant
EP1282158A1 (en) * 2001-07-31 2003-02-05 STMicroelectronics S.A. Method of manufacturing a bipolar transistor in an integrated CMOS circuit
FR2828331A1 (en) * 2001-07-31 2003-02-07 St Microelectronics Sa METHOD FOR MANUFACTURING BIPOLAR TRANSISTOR IN A CMOS INTEGRATED CIRCUIT
US6756279B2 (en) 2001-07-31 2004-06-29 Stmicroelectronics S.A. Method for manufacturing a bipolar transistor in a CMOS integrated circuit

Also Published As

Publication number Publication date
EP0151585A4 (en) 1986-02-20
CA1222835A (en) 1987-06-09
JPS60501927A (en) 1985-11-07
EP0151585A1 (en) 1985-08-21

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