WO1984001482A1

WO1984001482A1 - Cash flow monitoring system

Info

Publication number: WO1984001482A1
Application number: PCT/US1982/001334
Authority: WO
Inventors: Kenneth L Clements
Original assignee: Cybex Int
Priority date: 1982-09-27
Filing date: 1982-09-27
Publication date: 1984-04-12
Also published as: AU9050482A; GB2140659B; AU555336B2; GB8412482D0; JPS59501808A; EP0119999A1; GB2140659A

Abstract

A computerized monitoring system which incorporates the power lines (60) that provide electrical power to the remote devices (12) as the physical communications medium of a serial data bus for the computer system. The system comprises a central computer (10) and a plurality of computerized sensor modules (80) within the individual remote devices. The central computer and each of the sensor modules (80) has associated with it a respective data link (70, 87) for coupling respective signal generating and receiving means (65, 67, 82, 85) to the power distribution lines (60) and for manipulating the signals to and from a form suitable for transmission on the power distribution lines. Phase shift keying is used wherein binary bits of data are represented as 180o phase shifts of the pulses in a carrier pulse train. A data transmission rate of approximately 15,000 baud with a carrier frequency of 120 KHz is typical. A polling signal includes a preamble of pure carrier frequency, followed by the serial number of the device being polled, by the data (or instructions) defining the message content. Each data link has its own clock for generating a pulse train at a frequency very close to the common carrier frequency, and includes means for bringing its own carrier frequency pulse train approximately into a predetermined phase relationship with the carrier train that is appearing on the power lines.

Description

CASH FLOW MONITORING SYSTEM

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to comput¬ erized data communications systems, and more specifically to a computer system for monitoring a plurality of remote elec¬ trically operated devices such as slot machines wherein the data bus incorporates the electrical power lines supplying the remote devices.

Background of the Invention

A generation ago many computer experts were of the opinion that a handful of general purpose digital computers would satisfy all the computing needs of the United States (and presumably the world). Today we have hand-held program¬ mable calculators and home computers, and the commercial and industrial use of a central computer to monitor and control a plurality of remote electrical devices has become common¬ place. The remote devices may be geographically dispersed (e.g. computer terminals in various cities), or may be rela¬ tively proximate one another in a single building (e.g. heating and ventilation controls) . The common denominator is information transfer, regardless of whether the information is to be used for accounting, security, energy conservation, or some other purpose.

One known and commonly used way of transferring data is to encode the data bits as a series of phase shifts that are superimposed on a carrier signal. This technique, known as phase shift keying, is most often carried out by having the transmitter constantly sending the carrier signal so that the receiver can remain in constant synchronization. Needless to say, this cannot be done if two-way communication is to be carried out over the same telemetry lines. In such a case, separate clocks at the transmitter and receiver are maintained in constant synchronization during data transmis-

C PI sion by means of a phase locked loop which derives its timing from the bit changes themselves. The use of a phase locked loop is less than optimal since it requires a considerable amount of critically designed circuitry and involves a signi- ficant amount of lockup time in order to synchronize the clocks. Moreover, when the environment is noisy, a spurious signal has the effect of throwing the phase locked loop out of lock so as to destroy the data, even if the spurious signal itself didn't represent a threat to data integrity. Slot machines are but one example of devices whose operation is characterized by substantial cash flow and thus present accounting and security problems. In the context of a gambling casino, a large number of machines are located in a room which is accessible to the public at all times. Each machine is characterized by a payout ratio that is slightly less than one hundred percent so that on the average the casino retains a small share of the total money passing through the machines. Overall profitability depends on having a large number of slot machines operating twenty-four hours a day, seven days a week, so that the effects of statistical anomalies are eliminated and the small percentage retained by the casino is applied to a large base to provide a large positive cash flow increment.

Slot machines are, for the most part, relatively complex electromechanical devices. Even minor malfunctions can result in substantial changes in the payout ratio, thus rendering the machines non-profitable, or even worse, cash drains. In addition to malfunctions of an accidental sort, there are those malfunctions caused by intentional tampering with the machine mechanism. Such tampering methods and their manifestations are well known to those in the slot machine art, and all too well by those engaged in the larcenous activities. Given the large amounts of cash involved, small systematic cash diversion, typically too small to be detected by casino management, is nevertheless attractive to the would be wrongdoers.

O PI Mindful of the desirability of remotely monitoring the cash flow characteristics of a plurality of slot ma¬ chines, there have been proposed security and monitoring systems including a central computer in communication with individual sensor units within the slot machines. Data transfer occurs along dedicated telemetry lines, thus pro¬ viding reasonably high data integrity.

Unfortunately, the use of dedicated telemetry line has the significant disadvantage that providing such dedi- cated lines represents a significant expense. Moreover, if it is desired to retrofit a roomful of slot machines with such a security system, the installation of the data lines i intolerably disruptive. Aside from the fact that each machine is required to be inoperative for the installation o its sensor unit, the operation of large groups of machines must be suspended for considerable intervals while the telemetry lines are being installed. As mentioned above, slot machine profitability depends on the operation of the machines on a substantially continuous basis. Therefore, th cost of suspending operation of large numbers of machines fo even several hours represents a substantial disincentive to retrofit the machines in the first place.

Consequently, in spite of the demonstrable need for remote slot machine .monitoring systems, the costs involved i retrofitting a roomful of slot machines with such a system has tended to hinder the development and implementation of remote slot machine monitoring systems.

SUMMARY OF THE INVENTION The present invention provides a computerized monitoring system which eliminates all down time for retro¬ fitting except for the modest time required to provide each individual remote device with its own internal sensor unit. This is accomplished by incorporating the power lines that provide electrical power to the remote devices as the physi- cal communications medium of a serial data bus for the com¬ puter system. A particular installation for slot machines is disclosed. The computerized communications system comprises a central computer and a plurality of computerized sensor modules within the individual slot machines. The central computer and the individual sensor modules are capable of and include means for sending and receiving signals to and from one another, the significance of the signals to be described more fully below. The central computer and each of the sensor modules has associated with it a respective data link for coupling the respective signal generating and receiving means to the power distribution lines and for manipulating the signals to and from a form suitable for transmission on the power distribution lines. Phase shift keying is used wherein binary bits of data are represented as 180° phase shifts of the pulses in a carrier pulse train.' A data trans- mission rate of approximately 15,000 baud with a carrier frequency of 120 kHz is typical.

Communication may occur between any two devices, but in the preferred embodiment, communication is initiated by the central computer which sequentially polls individual sensor modules within the slot machines on a regular cyclical basis. Each slot machine sensor module is assigned a serial number for identification purposes. The polling signal includes a preamble of pure carrier frequency, followed by the serial number of the device being polled, followed by the data (or instructions) defining the message content. Each data link has its own clock for generating a pulse train at a frequency very close to the common carrier frequency, and includes means for bringing its own carrier frequency pulse train approximately into a predetermined phase relationship with the carrier train that is appearing on the power lines. This is typically done by stepping the phase by 90° incre¬ ments until the local clock is in proper phase. Thus, when the serial number portion of the message begins, all data links are synchronized with the carrier in order to be able to interpret the serial number. When the serial number is determined, each device ascertains whether the message is destined for it, and if so, receives and acts on the message.

O PI WliO Typically, the message from the main computer requests the transmission from the remote sensor of some data. If the transmission from the remote sensor occurs substantially immediately, the central computer is already synchronized with the sensor.

It is important to recognize the fact that the electrical power distribution lines represent an extremely noisy environment and thus an unlikely medium for messages where error free data transmission is a prerequisite. The noise on the electrical lines arises from the various device drawing electrical power such as motors with arcing brushes and solid state control units characterized by extremely sharp changes in current conduction. While some potential sources of electrical interference may be filtered, sharp pulses contain power at virtually all frequencies, and canno be filtered.

Despite this seemingly grim situation, the time distribution of noise on the power lines is not random, but rather correlates with the phase of the 60 Hz line voltage. Consequently, there are significant periods during which electrical lines are relatively free of noise, the time interval after zero crossing typically being the cleanest.

In recognition of the noisy environment, the mes¬ sage formats are designed to achieve substantially error fre data transfer. In particular, messages are kept short, and suitable parity checks and other error detection techniques are employed. If a reasonable probability of error is detected, the message is ignored completely rather than any attempt being made to reconstruct it. Thus, if the message was from the computer, the remote sensor does not answer, signifying to the central computer that an error occurred. If the error occurred in a message from a remote sensor, the central computer disregards the message and retransmits. It should be noted that synchronization of the receiving data link clock with the transmitting data link clock occurs once only at the beginning of the message. Therefore, only spurious signals that represent a data error will be troublesome, the system being immune to noise whose only effect would be to destroy the synchronization. More¬ over, the nature of the synchronization process, involving only a decision as to whether or not to step the phase by 90°, allows synchronization to take place quickly. Thus, a high effective bit rate is achieved despite the short message format.

According to a further aspect of the present inven¬ tion, each data link has means for changing (for example, halving) the carrier frequency if it is determined that messages at the original frequency are not getting through without error. This capability lowers the probability that data transmission is totally interfered with.

Each sensor module has a sensor/interface which provides signals to monitor the significant events in the slot machine operation, such as the receipt of coins, the turning of the reels, the payout of coins, and the opening o the slot machine door. A typical machine generates 50 volt AC signals for energizing the payout motor and for incremen- ting electromechanical counters that keep track of coin destinations and the like. The sensor/interface provides signals corresponding to the AC signals in the machine, signals indicative of the coin path followed by a coin, signals representative of the movement and timing of the reels, and a signal representative of the position of the door. In order to ensure slot machine integrity, no mech¬ anical connection is made to the working mechanical compo¬ nents of the machine and electrical connections are kept to minimum. The electromechanical signals regarding the state of the slot machine are monitored by a plurality of opto/isolators assemblies. While an electrical connection i made to sense the electrical signals originating in the machine, the connection is one-way; while the sensor module can respond to the AC signals, it cannot influence them. Th passage of a coin through the machine is monitored by a plur

OMPI ality of optical interruption detector assemblies placed at locations to detect a coin coming into the machine, a coin being paid out, a coin entering the safe, and a coin enterin the hopper. These optical interruption detector assemblies also serve to verify the proper functioning of the slot machines own electromechanical counters. The motion of the reels is monitored by a plurality of reflected light senors which change their respective states as alternating dark and light portions on the reels pass by. An additional reflecte light sensor is mounted proximate the door of the slot machine and cooperates with a reflective target mounted on the door to provide a signal that is representative of the distance between the sensor and the reflective target. This signal, in the form of a voltage, is communicated through a voltage controlled oscillator, so that by monitoring the frequency of the signal from the voltage controlled oscilla¬ tor, it is possible to verify that the door is indeed closed or that the door is opened under proper authorization. For a further understanding of the nature and advantages of the present invention, reference should be mad to the remaining portions of this application and the at¬ tached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified electrical schematic for th power distribution system in a hypothetical casino;

Fig. 2 is a block diagram of the communication system utilizing the electrical power distribution lines;

Fig. 3 is a block diagram of the data link associ¬ ated with one of the slot machines; Figs. 4A and 4B, taken together, form a circuit schematic of the microprocessor and data link;

Figs. 5A and 5B, taken together, form a circuit schematic of the slot machine sensor and interface;

Fig. 6 is a schematic of alternate reel monitoring circuitry;

Figs. 7A and 7B, taken together, form a circuit schematic of the communications processor; and Fig. 8 is a diagram illustrating the system message format. DETAILED DESCRIPTION OF THE INVENTION Overview Broadly, the present invention provides a computer¬ ized monitoring system which uses the power lines that pro¬ vide electrical power to the monitored devices as the physi¬ cal data communications medium of the computer data bus. For definiteness, the description that follows will be with reference to monitoring a plurality of slot machines in a casino. In order to implement the system of the present invention, it is often necessary to make minor modifications to the power distribution wiring within the casino in order to provide a continuous signal path. Fig. 1 is a schematic block diagram showing a typical power distribution system for a hypothetical casino. As will be described below, the data is transmitted at fre¬ quencies greatly in excess of the 60 Hz at which AC power is supplied. For example, a data rate of 10 kHz (10,000 baud) superimposed on a carrier frequency in the range of 50-200 kHz is typical. The important elements of the system include a central computer system 10 and a plurality of specially outfitted slot machines 12. For definiteness, assume that a first group 15 of slot machines, all of which operate on 110 volts, is located on the ground floor of the casino; and that a second group 17, a first subgroup 18 of which operates on 220 volts and a second subgroup 19 of which operates on 110 volts, is located on the mezzanine floor of the casino. Further, assume that computer system 10, ground floor slot machines 15, and mezzanine slot machines 17 are powered from respective isolated secondary windings 20, 22, and 25 of a main transformer 27. Power from the transformer secondaries is communicated to respective electrical panels 30, 32, and 35 which typically provide circuit breakers for individual circuits served by that panel. A stepdown transformer 36 is provided between panel 25 and slot machine subgroup 19. It is immediately apparent that the power lines do not provide a suitable communication medium.when isolated transformer secondaries are used. To overcome this, couplin capacitors are installed to provide a continuous current pat for high frequency signals. In particular, coupling capaci¬ tors 37 are installed between corresponding terminals of primaries 20 and 22, and coupling capacitors 40 are installe between corresponding terminals of secondaries 22 and 25. Additionally, coupling capacitors 42 are installed across th circuit breakers in computer room breaker panel 30 and acros any other breakers where it is desired to keep the communica tion lines open in the event of a breaker opening. Also, since power to slot machine subgroup 19 is stepped down from 220 volts to 110 volts, capacitors 45 are connected between corresponding primary and secondary terminals of transformer 20. The value of the capacitors is not critical; 0.1 micro¬ farad bidirectional capacitors rated at 1200 volts are suitable.

With the electrical power distribution system for the casino thus modified by the addition of coupling capaci¬ tors, the entire power distribution system may be treated as electrically continuous for the purposes of the discussion that follows. Fig. 2 is a block diagram showing central computer system 10 and several specially outfitted slot machines 12 connected to a common power line 60, which for purposes of electrical signals at high frequencies, may be considered a continuous two-conductor line. Central compute system 10 includes a mini-computer 65 which receives its electrical power from line 60, a communications processor 67, and a central computer data link 70 that is coupled to power line 60 by suitable capacitors 72. Communications processor 67 transfers data between mini-computer 65 and central com¬ puter data link 70. Each slot machine 12 includes the slot machine proper, designated by reference numeral 75, and a sensor subassembly 80 which includes a sensor/interface 82, a microcomputer 85, and a slot machine data link 87. Slot machine data link 87 is coupled to power distribution line 60

V/ r by capacitors 90. Each slot machine data link 87 is sub¬ stantially the same as central computer data link 70. Data Link

Fig. 3 is a block diagram illustrating the basic elements of data link 87 and its interaction with micropro¬ cessor 85. It should be understood that electronic compo¬ nents in data link 87, microcomputer 85, and sensor/interface 82 derive their electrical power from power supply circuitry 91 coupled to power distribution line 60. Broadly, phase shift keying is used to superimpose binary bits on a carrier (clock) frequency in the range 50-200 (60 or 120 kHz being preferred) kHz with bit changes being signified by a 180° phase shift from the basic carrier. Data link 87 includes clock circuitry 92, transmitting circuitry 93, receiving circuitry 94, and phase comparison circuitry 95. The clock frequency is supplied to transmitting circuitry 93 on a line 96 and to phase comparison circuitry 95 on a line 97 by clock circuitry 92 which receives a 240 kHz square wave from an ALE output 100 of microprocessor 85. Microprocessor 85 is driven by a local crystal oscillator 101 which ultimately defines the ALE output. A data output 102 of microprocessor 85, designated PHASE, controls the phase of clock 92.

Consider first transmitting data circuitry 93. The clock pulses on line 96 are transmitted to gate circuitry 104 which is controlled by a further data output 105 of micropro¬ cessor 85, designated XMIT . The gate output is passed to driving circuitry 111 and a low pass filter 112.to produce a sine wave on a data output line 113 at the carrier frequency and in constant phase relationship with the clock phase on line 96. This signal is capacitively coupled to power line 60 by capacitors 90 as described above.

With reference to the circuit schematic of Fig. 4A, the operation of data link 87 during data transmission may be understood. Clock circuitry 92 includes flip-flops 120 and 122, each of which provides a frequency division by a factor of 2. A 2-to-l multiplexer 123 is controlled by a line 124, designated X2, so that flip-flop 120 may be selectively by-

CVPI f ^+> passed to avoid one of the frequency divisions. As can be seen, line 96 is in fact a pair of complementary output line from the and outputs of flip-flop 122 while line 97 is coupled to the output only. An Exclusive OR (XOR) gate 12 is interposed between the flip-flops, and has one of its inputs controlled by PHASE output 102. Flip-flop 122 is triggered by a rising edge with the result that each transi¬ tion at PHASE output 102 causes a 90° phase shift on lines 9 and 97. XMIT output 105 is also coupled to PHASE output 102 through a 10K resistor 127. Microprocessor 85 has an internal 50K pullup resistor on PHASE output 102, so that a low level at XMIT output 105 actually holds PHASE output 102 low. When microprocessor 85 specifies a high level at output 102, it sends a short high pulse which it expects would keep output 102 high. The result is that PHASE output 102 goes high and is quickly pulled low by XMIT output 105. Thus, with XMIT output 105 low, an instruction to set PHASE output 102 high results in an upward and a downward transi¬ tion at that output which causes a 180° phase change at the outputs of flip-flop 122.

The output lines of flip-flop 122 that define line 96 are coupled to first inputs of respective AND gates 130 and 132 within gate circuitry 104. The second inputs are controlled by XMIT output 105 so that the output ultimately is controlled by the level on XMIT output 105. Driving circuitry 111 includes driving transistors in a push/pull configuration to produce a square wave that replicates the Q output from flip-flop 122. Unless XMIT output 105 is low, no pulses are produced by driver 111. Low pass filter 112 is typically a 200 kHz low pass filter. The square wave from driver 111 is then filtered to suppress radiofrequency sig¬ nals and capacitively coupled to line 60, with the resulting sine wave being communicated to all the other data links in the system. Before discussing receiving circuitry 94, it is important to recognize that data reception depends on the receiving data link clock's being initially generally in _

phase, or 180^β out of phase, with the transmitting data link clock so that 180° phase shifts can be recognized. Since the individual ALE outputs of the microprocessors are controlled ultimately by individual local crystal oscillators, there is no guarantee that any two data link clocks will be in any particular phase relationship at a given time. However, the crystals are sufficiently uniform that once a given phase relationship between two of the clocks is established, the relationship persists for a sufficiently long time to permit data transmission. Accordingly, there is also provided means for synchronizing the receiving data link clock to the trans¬ mitting data link clock, as will now be described.

Incoming signals on power line 60 are passed by coupling capacitor 90 to a data input line 138 and trans- mitted to receiving circuitry 94 which includes a high pass filter 140, limiting circuitry 142, and suitable amplifica¬ tion circuitry 145 to provide a square wave at the carrier frequency and in constant phase relationship with the incom¬ ing signal. The square wave is fed to the first input of an XOR gate 150, the other input of which receives the clock signal from locally controlled clock 92 on line 97. The output of XOR gate 150 depends on the relative phase between the two signals. The nature of an XOR gate is such that the output is a pulse train at twice the carrier frequency with the duty cycle (fraction of time high) varying linearly from 0 to 1 as the phase difference varies from 0 to + 180°. In particular, if the two signals are precisely in phase, a uniform low level is output; if out of phase, a uniform high level is output. If the signals are 90° out of phase, a square wave at twice the carrier frequency is at the output. The output is passed through a low pass filter 152 in order to produce a level that is directly representative of the duty cycle and hence the phase difference.

Notice that a phase difference of + 90° is unsuit- able for data recognition, since a 180° phase shift of the incoming data results in a phase difference of ;_j;90^o, which produces the same level at the output of low pass filter 152

VIr and is ^'thus indistinguishable. Accordingly, to determine whether the level from low pass filter 152 is sufficiently high or low to make phase shifts of 180° recognizable, the level is passed to discriminator circuitry 160 that applies level test and a so-called strict test and provides two output signals that are communicated to respective test inputs 162 and 165 of microprocessor 85. The level at input 162 is high or low depending on the output from low pass filter 152 while the level at input 165 indicates whether th level from low pass filter 152 is sufficiently far removed from the halfway level that 180° phase shifts are reliably recognizable. If it is determined that the phase difference between the incoming signal and the receiving data link cloc is generally near + 90°, microprocessor 85 steps the phase b 90°.

With additional reference to the circuit schematic of Figs. 4A and 4B, the operation of data link 87 during reception may now be understood. In particular, during reception, XMIT output 105 is held high, so that when microprocessor 85 commands a high level at PHASE output 102, the level stays high. Thus, with XMIT output 105 high, PHASE output 102 may be set high or low to induce single transitions causing 90° phase shifts in the output from cloc 92. Low pass filter 152 is preferably a second order active low pass filter with the component parameters chosen to define a corner frequency 2/3 the baud rate with 6 db/octave attenuation above the corner. This suitably eliminates vestiges of signals at or above the carrier frequency which, as discussed above, is typically 8 to 10 times the baud rate. Discriminator circuitry 160 includes a center thresholder 167 with 10% hysteresis to feed test input 162 for the level test, and a window comparator 170 with comparison points at one-third and two-thirds the voltage to feed test input 165 for the strict test. The status of test inputs 162 and 165 may be rapidly checked by microprocessor 85.

It should be noted that the output from low pass filter 152 will also be at the halfway level when there is no

c ri incoming signal at the carrier frequency, that is when there is random noise on power line 60, and will remain at that level despite 90° steps in the clock output. Thus, each data link can, when desired, "listen" for signals at the carrier frequency by periodically stepping the clock phase by 90° to see if the output from low pass filter 152 passes the strict test. Once a signal at the carrier frequency is found, shifts in the level from low pass filter 152 denote shifts i the binary bits. Slot Machine Sensor/Interface

As should be apparent from the above description o the data link, the operation does not depend on the particu¬ lar nature of the data that microcomputer 85 receives from its remote device (slot machine). However, for definiteness, a preferred embodiment of sensor/interface 82 for a slot machine will be disclosed.

Before describing the sensor/interface, it is helpful t consider some basic principles of operation of a typical electromechanical slot machine. As is well known, a slot machine has a plurality of coaxial adjacent reels, each having a plurality of pictorial symbols on its cylindrical surface. An operator places one or more coins in a slot, an pulls a handle. This causes the reels to turn independently of one another, and depending on the configuration of aligne symbols when the reels stop, coins may be paid out in varyin amounts. The significant events in the slot machine opera¬ tion are the receipt of coins, the turning of the reels, the payout of coins, and the opening of the slot machine door which allows casino personnel to gain access to the machine' interior. From an accounting and security point of view, useful information can be gained by suitable monitoring of the machine with respect to any and all of these events.

Upon insertion of a coin into the slot machine, a mechanical sorter makes an initial determination that the coin is an acceptable coin of a particular denomination. Th downward passage of the coin then actuates a icroswitch to initiate the machine cycle. The coin then falls into a

OΪ.-H hopper where it is available for payout, or, if the hopper i full, into a safe at the bottom of the machine where it is n longer available for payout. A typical machine generates 50 volt AC signals for energizing the payout motor and for incrementing electromechanical counters that keep track of information such as the number of coins accepted, the number of coins entering the hopper, and the like.

Figs. 5A and 5B, taken together, form a circuit schematic of sensor/interface 82. Broadly, the sensor/inter face provides signals corresponding to the AC signals in the machine, signals indicative of the coin path followed by a coin, signals representative of the movement and timing of the reels, and a signal representative of the position of th door. The general requirement to ensure slot machine integ- rity is that no mechanical connection be made to the working mechanical components of the machine and that electrical connections be kept to a minimum.

The electromechanical signals regarding the state of the slot machine are monitored by a plurality of opto/isolator assemblies 180. Each opto/isolator assembly includes an opto/isolator 182, itself comprising a light emitting diode (LED) 182a and a phototransistor 182b, and a thresholder 185. LED 182a is energized by the presence of 50 volt, 60 cycle signals within the machine and turns photo- transistor 182b on to provide an electrical signal which is passed through thresholder 185 to an appropriate data input of microcomputer 85. It should be noted that while an elec¬ trical connection is made to sense the electrical signals for the payout motor and the electromechanical counters, there is no direct electrical connection between the source of the AC signals and the computer electronics. Moreover, the connec¬ tion is one-way; while microcomputer 85 can respond to the AC signals, it cannot influence them. In a particular embodi¬ ment, there are four opto/isolator assemblies 180 that are coupled to respective sources of signals representing a coin coming into the machine, a coin being paid out of the

OMFI

* /λ. machine, a coin going into the safe, and the payout motor's being energized.

The passage of a coin through the machine is moni¬ tored by a plurality of optical interruption detector assem- blies 190. Each optical interruption detector assembly 190 includes a an LED 192 on a first side of the expected coin path, a cooperating phototransistor 195 on the opposite side, and a thresholder 197. The passage of a coin between LED 192 and phototransistor 195 causes an electrical pulse which is communicated through thresholder 197 to an appropriate data input of microcomputer 85. According to a particular embodi¬ ment, there are four such optical interruption detector assemblies, placed at locations to detect a coin coming into the machine, a coin being paid out, a coin entering the safe, and a coin entering the hopper. It will be appreciated that optical interruption detector assemblies 190 serve to also verify the proper functioning of the electromechanical count¬ ers. With respect to the coin entering the machine, it is preferable to have the particular optical interruption detector assembly 190 proximate the microswitch which ini¬ tiates the machine cycle so that microcomputer 85 can detect an attempt to repeatedly actuate the microswitch with a coin on a string.

The motion of the reels, fragmentary portions being designated 199, is monitored by a plurality of individual reel motion detectors 200, each of which comprises a re¬ flected light sensor 202 and a thresholder 205. Sensor 202 changes its state as alternating dark and light portions on the reels pass by, and the change in state is electrically communicated through thresholder 205 to an appropriate date input of microcomputer 85. In the particular embodiment, for a slot machine having three reels, there are three such reel motion detectors. An additional reflected light sensor 210 is mounted proximate the door of the slot machine and co- operates with a reflective target 212 mounted on the door to provide a signal that is representative of the distance between sensor 210 and reflective target 212. Sensor 210 provides a precise reading of door position over the last centimeter or so of door travel prior to the door's closing. This signal, in the form of a voltage, is communicated through a voltage controlled oscillator 215 to microcomputer 85. Microcomputer 85 can monitor the frequency of the signa from voltage controlled oscillator 215 in order to verify that the door is indeed closed, or that the door is opened under proper authorization.

In order for microcomputer 85 to properly respond to system messages being communicated over power line 60, an in order for the microcomputer to properly monitor the slot machine functioning, it is necessary to have access to infor mation unique to its own particular slot machine. In addi¬ tion to an identification number for the slot machine, there are timing parameters and other quantities that are charac¬ teristic of that machine and vary from one machine to an¬ other. This information is preferably stored in a separate memory chip 220, designated a slot machine memory. Slot machine memory 220 must be non-volatile so that the appro- priate parameters are not lost during a power interruption. If it is desired to also maintain long term registers (such as total number of cycles that the slot machine has under¬ gone), it is necessary that memory locations within slot machine memory 220 be capable of being updated. These re- quirements are met by using a CMOS RAM for slot machine memory 220, and providing a battery 221 for backup when normal power is absent. The address information is latched at memory address latches 222 on the falling edge of the ALE signal. Address and data are transmitted on microcomputer data bus 223 in a time multiplexed fashion.

In the circuitry described with reference to Figs. 5A and 5B, alternating changes in state of reflected light sensors 202 signify the movement of reels 199, and thus give information on reel velocity. However, many slot machines have the property that the reel may move backwards by one position before finally stopping, thus rendering it difficult to reliably monitor the precise position of the reel. Fig. 6 is a circuit schematic of alternate reel monitoring circuitry capable of monitoring the reel's position as well as its velocity, being suitable for use where the reels are charac¬ terized by unidirectional rotation. While only one reel's associated circuitry is shown, the identical circuitry is provided for each of reels 199. Each of reels 199 is pro¬ vided with marker such as a contrasting dot 225 at a prede¬ termined position, preferably near an edge of the cylindrical surface of reel 199. The basic purpose of the circuitry is to use dot 225 as a reference and to count the number of symbols passing after the dot in order to gain a precise indication of the reel position.

Associated with reel 199 is a first reflected light sensor 227 (comprising an LED 227a and a phototransistor 227b) directed toward the symbols on the reel, and a second reflected light sensor 230 (comprising an LED 230a and a phototransistor 230b) directed at the axial portion of the reel where dot 225 is located. An oscillator circuit 232, which may comprise a timer and appropriate passive compo- nents, energizes LEDs 227a and 228a at a predetermined fre¬ quency, preferably 700 Hz. Thus, as the alternating dark and light portions corresponding to pictorial symbols on reel 199 pass reflected sight sensor 227, a 700 Hz signal is inter¬ mittently generated at phototransistor 227b during the per- iods that light is being reflected. The signals from photo¬ transistor 227b are passed through 700 Hz band pass circuitry 235, and thence to 700 Hz detection circuitry 240. Circuitry 235 is characterized by a gain of 5 and value of 3 to amplify and filter the signals in order to provide a clean 700 Hz signal during those intervals when light is being reflected. Detection circuitry 240, tuned to the same 700 Hz frequency provides an output signal pulse for each picture that goes by sensor 227. These pulses are passed to a 5-bit counter 245 which provides a numeric representation of the position of reel 199.

Phototransistor 228b provides a 700 Hz signal during those portions of the rotation of the reel that light

GMFI srΛ- . V/I ϋ is being reflected. Therefore, assuming that the reel is light colored with a dark dot, the signal is present except when dot 25 passes. The signal from phototransistor 228b is passed through corresponding band pass and gain circuitry 24 and then through a 700 Hz detector 250, the output of which is communicated to the reset input of counter 245. There¬ fore, during the rotation of reel 199, counter 245 is reset the first time that dot 225 passes under reflected sensor 22 and upon every subsequent passage thereafter. Since the motion of reel 199 is unidirectional, the output of counter 245 gives a true representation of the reel position. The output of counter 245 is communicated to appropriate lines o data bus 221. The corresponding counters for the other reel are similarly coupled to the data bus, and microcomputer 85 can select which reel's counter contents are to be strobed onto the data bus at a particular moment. Communications Processor

Just as each slot machine data link 87 communicate to its respective slot machine 75 through a slot machine microcomputer 85 and a sensor/interface 82, similarly centra computer data link 70 communicates to central minicomputer 6 through communications processor 67. Fig. 7 is a simplified circuit schematic of communications processor 67.

Broadly, communications processor fulfills two mai functions. The first is reconfiguring the data between the format for transmission onto or reception from the power lines and the format for central minicomputer 65. The secon function is bidirectional voltage isolation.

Communication processor 67 comprises a microproces- sor 260 which is coupled to central computer data link 70 in the same manner that microcomputer 85 is coupled to slot machine data link 87. Microprocessor 260 communicates to a universal synchronous/asynchronous receiver and transmitter (hereinafter USART) 262. USART 262 transmits signals on lines 265 and 267 to the LED (input) side of an opto/isolator 270, and receives signals on lines 272 and 273 from the phototransistor (output) side of an opto/isolator 274. Data

O PI WIPO link 70, microprocessor 260, and USART 262 receive their electrical power from a common power supply.and the signals are TTL compatible. Signals^" at the phototransistor side of opto/isolator 270 and at the LED side of opto/isolator 274 are communicated to minicomputer 65 at 19,200 baud. A sepa¬ rate power supply 275 provides +12 volt, +5 volt, 0 volt, an -12 volt levels so that the signals are EIA spec RS-232 compatible. System Message Format A standard communication between central minicom¬ puter 65 and one of slot machines 12 occurs between communi¬ cations processor microprocessor 260 and microcomputer 85 with the transmitted data being applied to and extracted fro power line 60 by central computer data link 70 and slot machine data link 87. For the system described above, such standard message includes an initial message from the central computer and a response from the slot machine. During syste operation, microcomputer 85 is essentially doing two things. First, it is monitoring the various signals from sensor/inte face 82 and updating various of its own counters and status registers (to be described below). Second, and simultaneous ly, it is carrying out a communications protocol with the rest of the system. The slot machine monitoring is carried out at a standard program level while the system communica- tions is carried out an interrupt level of the microprocessor.

Turning to Fig. 8, the standard message format is graphically depicted. The polling message from central mini computer 65 (actually microprocessor 260 via data link 70) begins with a preamble of pure carrier frequency to enable each microcomputer 85 to get synchronized with the carrier frequency in order that the subsequently transmitted message can be successfully demodulated. The preamble has a dura¬ tion, designated Tl, that is typically 4-12 standard bit times, depending on transfer characteristics. The standard bit time, designated T2, is determined by the baud rate and may be approximately 1/30,000th to 1/10,000th of a second.

O P The message content is included in two frames, eac having 11 bits, namely a start bit, 8 bits of data, an odd parity bit, and a stop bit. ^' The start bit is defined by a 180° phase shift relative to the preamble and is defined to be a data '0' . Subsequent bit changes are signified by further 180° phase shifts. The stop bit is defined to be a data '1' . The first frame includes data bits 0-7 while the second frame includes data bits 8-15. Data bits 0-11 form a 12-bit address while data bits 12-15 define a 4-bit command code, thus providing for 16 possible commands.

The response begins with a preamble of pure carrie frequency having a duration, designated T3, that is approxi¬ mately 2 standard bit times. This preamble is not required for synchronization (since the response occurs substantially immediately after the polling message), but rather serves to define the start of the first response frame. Depending on the nature of the polling message, the total response may be 1-4 frames in length, each frame of which has 11 bits as in the polling message. In order to allow microcomputer 85 the maximum length of uninterrupted time for monitoring the slot machine operation, communications from the central computer are caused to occur in a predictable time slot at a constant repetition rate. In particular, the time slot is suffici- ently long to accommodate the preamble, the two frames of message, and up to four frames of response. The interval between the start of the preamble on subsequent polls is a system constant. An internal timer in microcomputer 85 generates an interrupt that signifies that it is time to receive a message from communications processor 67, at which time, data link 87 hunts for the preamble at the carrier frequency and synchronizes as described above so that the message may be received. This occurs in each sensor module. On start up of a particular sensor module, in order that the time slots may be established, microcomputer 85 and data link 87 must constantly search for carrier frequency by periodically stepping the clock phase by 90° as described

OMPI W1PO above. Once the preamble at the carrier frequency is de¬ tected, the microcomputer uses its very accurate internal timer and sets it to a quantity such that it will be inter¬ rupted by its own timer at exactly the time of the start of the next preamble. As long as microcomputer 85 remains powered, it will stay in basic synchronization by starting its timer again from when it receives the stop bit at the end of frame 2 of the message from the communications processor. The communications processor must do an analogous timing so that it sends out preamble at this specified rate to be followed by commands that it is ordered to send by central minicomputer 65.

Thus it can be seen that synchronization takes place at two levels. First, on powering up of any particular one of remote microcomputers 85, that microcomputer's inter¬ nal timer is synchronized with the polling messages that are being transmitted at fixed intervals from communications processor 67. Second, on each polling, a signal at the carrier frequency must be found and the clock synchronized in order to receive data.

At the non-interrupt level, microcomputer 85 is constantly monitoring the signals from sensor/interface 82 in order to ascertain the status of slot machine 75. Most of the time is spent awaiting a signal from the "coin in" sensor to indicate that a coin has been dropped into the machine. When this happens, microcomputer 85 updates the appropriate counters and waits for another coin to be inserted or for the slot machine handle to be pulled and the reels to start spinning. Once this has occurred, microcomputer 85 goes into the next phase of the cycle and waits for the reels to stop, checks their timing, and checks for payout, if there any. Turning next to the particular commands and re¬ sponses, it should be understood that the following is an illustrative format. For security reasons, the particular significance of the bits is likely to be different from one casino to the next, and furthermore is likely to be changed

O PI Vy at periodic intervals to discourage any attempt for unauthor ized personnel to gain meaningful access to the data.

The 16 command codes and the length of the expecte response for each are shown in Table 1. It should be re¬ called that up to four frames (32 bits) may be accommodated.

TABLE 1

BITS RESPONSE

TYPE 15 14 13 12 COMMAND (BITS)

Group Poll 1 (2 bit times) for each of 16 machines

1 0 0 0 1 Report Status 8 2 0 0 1 0 Report Cycle Phase Code 8 3 0 0 1 1 Report Error Code 8 4 0 1 0 0 Return Cycle No. 24 5 0 1 0 1 Return No. of Coins In 24 6 0 1 1 0 Return No. of Coins Out 24 7 0 1 1 1 Return No. of Coins in Hopper 24 8 1 0 0 0 Return No. of Coins in Safe 24 9 1 0 .0 1 Return No. of Coins on Last 16 Payout

10 1 0 1 0 Return Last Payout Code 16 11 1 0 1 1 Return Data Check Code 24 12 1 1 0 0 Switch to Alternate Frequency 8 & Return Status

13 1 Clear Error Code & 8 Return Status

14 0 Return Cycle No. of 24. Last Error

15 1 1 1 Return Check Code for 8 Last Message

Elaborating on the above, the individual commands will now be considered.

OMΓI Command type 0 is a group poll wherein groups of machines are polled to quickly see if any machines have data to transmit. The expected response is one bit for each member of a polled group of 16 slot machines, although the response for a given slot machine actually extends over two bit times. In particular, carrier frequency in phase with the signal during the stop bit is sent for the first bit time and then a 180° phase shift is introduced if there is a message to transmit. After polling in this fashion, the central computer can individually poll those machines with data to report.

Command type 1 requests the return of an 8-bit status register. The particular significance of the status register bits is shown in Table 2 wherein a designated occur- rence is signified by that bit's being a '1'.

TABLE 2 Status Bit

0

1

2

3 Jack Pot

4 Cycle in Progress

5 Error Condition

6 Door Open

7 Event to Report

Command type 2 request the return of an 8 bit cycle phase code register. Various slot machines are set up so they can take some number of coins on a particular cycle prior to the handle's being pulled. Bits 0-3 are coded to indicate the number of coins that have been accepted while bits 4-7 are coded to indicate what part of the cycle the slot machine is currently in. The particular bit allocation and cycle phase codes are shown in Table 3.

OM?I TABLE 3

Cycle Phase Code Bit

No. of Coins Input This Cycle

se

Waiting for Coin

Coin(s) Accepted

0 0 1 0 Reels Spinning

0 0 1 1 Payout Cycle

0 1 0 0 Halt on Jackpot

0 1 0 1 Halt on Hopper Empty

0 1 1 0 Disabled by Operator

0 1 1 1 Hopper Fill in Progress

Command type 3 requests the return of an 8-bit error code. The type of error codes can be representative of states arising out of equipment failure, normally occurring events, or intentional attempts to defraud the machine. Typical situations for the latter are if the machine timing is changed due to someone's having drilled a small hole in the machine and inserted a wire to affect the governor or other movement of the wheel, or if the machine has been subjected to a large magnetic field to affect the operation.

TABLE 4

Error Code

Bit

0 Sensor Failure 1 Hopper Empty 2 Coin Path Error 3 Incorrect Payout 4 Payout Turn-on Out of Sequence 5 Magnetic Tamper 6 Timing Tamper 7 Coin Input Tamper Command type 4 requests the return of a 24-bit counter representative of the number of cycles the machine has undergone.

Command type 5 requests the return of a 24-bit counter representative of the number of coins that have been put into the machine.

Command type 6 requests the return of a 24-bit counter representative of the number of coins that have been paid out in the past. Command type 7 requests the return of a 24-bit counter representative of the number of coins that have gone into the hopper.

Command type 8 is requests the return of a 24-bit counter representative of the number of coins that have gone into the safe.

Command type 9 requests the return of a 16-bit counter representative of the number of coins that were paid out on the last cycle.

Command type 10 requests the return of the last payout code which is a 16-bit number that contains coded information regarding what combination came up on the reels and is used to verify that a particular machine has come up with a winning combination when it starts to pay.

Command type 11 requests the return of a 24-bit data check code which is the sum of the number of coins in, the number of coins out, the number of coins in the hopper, and the number of coins in the safe. It is used to detect that one of these quantities changed since the last time the machine was interrogated. Command type 12 instructs microcomputer 85 to select the alternate carrier frequency from whenever it may be at the time, and, when it gets to that other carrier fre¬ quency, to return the status register.

Command type 13 instructs microcomputer 85 to clea the error code and return the status, but this will only occur if the previous command to the particular microcompute

OMPI VT O was a type 3 command to return the error code. Otherwise th response to the command is merely to return the status register but not to clear the error code.

Command type 14 requests return of the 24-bit cycl number of the last cycle on which an error occurred.

Command type 15 requests that the return of an 8-bit check code for the last message. This is a checksum which is used to verify the accuracy of certain types of information that have been transferred. Microcomputer 85 takes the 8-bit data frames that were in the last message, sums up the individual frames, and comes up with an 8-bit two's complement number that is sent out as a response.

In summary it can be seen that the present inven¬ tion provides a computerized monitoring and communications system that is characterized by simplicity and reliability while providing high data transfer rates under highly inhos¬ pitable conditions. While the above provides a full and complete disclosure of the preferred embodiments of the invention, various modifications, alternate constructions, and equivalents may be employed without departing from the true spirit and scope of the invention. For example, the system is clearly applicable to remote devices other than slot machines. Therefore, the above description and illus¬ trations should not be construed as limiting the scope of th invention which is defined by the appended claims.

C PI

Claims

1. A system for monitoring the operation of a plurality of remote electrically operated devices, each of said devices receiving power from a common set of power distribution lines, comprising: a central computer including signal generating means and signal receiving means; central computer data link means coupling said central computer signal generating means and said central computer signal receiving means to said power distribution lines to permit said central computer to send signals over said power distribution lines and to receive signals over said power distribution lines; said signals from said central computer having a time structure including a portion representative of a par¬ ticular one of said remote devices with which communication is desired; ► a corresponding plurality of subassemblies asso¬ ciated with said remote devices, each of said subassemblies comprising: a sensor having signal receiving means responsive to said signals from said central computer and having signal generating means for generating signals represen tative of desired operation information; sensor data link means coupling said sensor signal generating means and said sensor signal receiving means to said power distribution lines to permit said sensor to receive said signals from said central computer over said power distribution lines, and to permit said senso to send said signals representative of operation inform tion to said central computer over said power distribu¬ tion lines to said central computer; said sensor having means for transmitting said signals representative of operation information only in response to a signal from said central computer designa

O H_ ing the particular device associated with that particu¬ lar sensor.

2. The invention of claim 1 wherein said electrically operated devices are slot machines, and wherein said sensor includes means for detecting coin drop, coin payout, and wheel rotation.

3. The invention of claim 1 wherein said sensor data link means includes means for generating a cyclical waveform at a carrier frequency and means for superimposing binary data on said cyclical waveform with changes in the binary bits of said data being represented by phase shifts.

4. The invention of claim 3 wherein said sensor data link means includes means for varying the phase of said first-mentioned cyclical waveform to bring said first-men- tioned cyclical waveform generally into a predetermined phas relationship with a second cyclical waveform at approximatel the same frequency appearing on said power distribution lines, whereupon subsequent phase shifts in said second cyclical waveform representative of binary data may be detected.

5. The invention of claim 4 wherein said means for varying the phase comprises means for stepping the phase by 90° increments.

6. The invention of claim 1 wherein a) said sensor data link comprises: a clock for generating a first cyclical pulse train, said clock having a phase control input and means for varying the phase of said first cyclical pulse train in response to signals at said phase control input; transmitting means responsive to said first cyclical pulse train for applying a first sinu- soidal signal to said power distribution lines, said first sinusoidal signal having said carrier frequency and being in a constant phase relation¬ ship with said first cyclical pulse train; receiving means responsive to a second sinu¬ soidal signal generally at said carrier frequency appearing on said power distribution lines, said receiving means having means for generating a second cyclical pulse train at the frequency of said second sinusoidal signal and in a predeter¬ mined phase relationship with respect to said second sinusoidal signal; and phase comparison means responsive to said first cyclical pulse train from said clock and said second cyclical pulse train from said receiving means, said phase comparison means having means for producing a signal representative of the phase relationship between said first and second cyclical pulse trains; b) said sensor signal receiving means and signal generating means together comprise: first means for applying signals to said phase control input on said clock to shift the phase of said first cyclical pulse train by 180° to repre- sent binary data bits to be transmitted; and second means for applying signals to said phase control input of said clock to step said phase by 90° to synchronize said first cyclical pulse train with said second cyclical pulse train during data reception in order to permit said phase comparison means to be sensitive to 180° phase shifts in said second sinusoidal signal.

7. In a communications system for interchanging data among members of a plurality of remote electrically operated devices, each of said devices receiving power from a common set of power distribution lines, an improved data lin assembly comprising: clock means for generating a first cyclical wave¬ form at. a carrier frequency; transmitter means for applying said first cyclical waveform to said power distribution lines; phase shifting means for shifting the phase of sai first cyclical waveform in response to signals at a control input; transmission control means for providing signals a said control input to cause phase shifts representative of binary data to be impressed on said first cyclical waveform; means for receiving a second cyclical waveform at approximately the same frequency appearing on said power distribution lines; phase comparison means responsive to the phase relationship between said first and second cyclical wave¬ forms; and ♦ synchronization control means for providing signals at said control input to bring said first cyclical waveform generally into a predetermined phase relationship with said second cyclical waveform, whereupon subsequent phase shifts in said second cyclical waveform representative of binary data may be detected.

8. The invention of claim 7 wherein said phase shifting means comprises means for stepping the phase by 90° increments.

9. The invention of claim 7 wherein said trans¬ mission control means and said synchronization control means together comprise a programmed microprocessor having first output means operatively coupled to said clock means for generating a cyclical pulse train at a harmonic of said carrier frequency to define said carrier frequency and second output means operatively coupled to said control input.

10. The invention of claim 7 wherein said syn¬ chronization control means is operative to provide signals at said control input only until said predetermined phase relationship is achieved.

11. The invention of claim 7 wherein said trans¬ mission control means and said phase shifting means are operative to effect 180° phase shifts of said first cyclical waveform to correspond to bit changes in said data.

12. The invention of claim 7 wherein said phase comparison means comprises: means for generating a voltage level representative of the duty cycle of the logical exclusive OR between said first and second cyclical waveforms; threshold means for generating a logic level cor- responding to said voltage level; and window means for generating a logic level indica¬ tive of whether or not said voltage level is representative of a duty cycle generally near 50% corresponding to a phase difference generally near ±90°.

13. In a communications system for interchanging data among members of a plurality of remote electrically operated devices, each of said devices receiving power from a common set of power distribution lines, an improved data link assembly comprising: a) a data link including: a clock for generating a first cyclical pulse train, said clock having a phase control input and means for varying the phase of said first cyclical pulse train in response to signals at said phase control input; transmitting means responsive to said first cyclical pulse train for applying a first carrier signal to said power distribution lines, said firs carrier signal having a carrier frequency and bein in a constant phase relationship with said first cyclical pulse train; receiving means responsive to a second carrie signal generally at said carrier frequency appear- ing on said power distribution lines, said receiv¬ ing means having means for generating a second cyclical pulse train at the frequency of said second carrier signal and in a predetermined phase relationship with respect to said second carrier signal; and phase comparison means responsive to said first cyclical pulse train from said clock and sai second cyclical pulse train from said receiving means, said phase comparison means having means fo producing a signal representative of the phase relationship between said first and second cyclica pulse trains; b) signal receiving means and signal generating means together including: first means for applying signals to said phas control input on said clock to shift the phase of said first cyclical pulse train by 180° to repre¬ sent binary data bits to be transmitted; and second means for applying signals to said phase control input of said clock to step said phase by 90° to synchronize said first cyclical pulse train with said second cyclical pulse train during data reception in order to permit said phase comparison means to be rendered sensitive to 180° phase shifts in said second carrier signal.

14. A system for communication between a central computer and at least one remote electrically operated device, said device receiving power from a set of power distribution lines, comprising: means associated with said central computer for sending a polling message on said power distribution line,

O PI s -, WIPO said polling message having a time structure including a preamble at a carrier frequency followed by binary data represented by phase shifts ^"relative to said preamble; a data link associated with said remote electrical ly operated device comprising: clock means for generating a first cyclical waveform at a frequency close to said carrier frequency; transmitter means for applying said first cyclical waveform to said power distribution lines; phase shifting means for shifting the phase o said first cyclical waveform in response to signals at control input, transmission control means for providing signals at said control input to cause phase shifts representative of binary data to be impressed on said first cyclical waveform, means for receiving a second cyclical wavefor at approximately the same frequency appearing on said power distribution lines, phase comparison means responsive to the phas relationship between said first and second cyclical waveforms, and synchronization control means for providing signals at said control input to bring said first cycli cal waveform generally into a predetermined phase rela¬ tionship with said second cyclical waveform, whereupon subsequent phase shifts in said second cyclical wavefor representative of binary data may be detected; said data link thus being operable to initially synchronize with said preamble, to then demodulate said data portion of said polling message, and to finally transmit a response on said power distribution lines.

15. The invention of claim 14 wherein said phase shifting means comprises means for stepping the phase by 90° increments.

16. The invention of claim 14 wherein said trans¬ mission control means and said synchronization control means together comprise a programmed microprocessor having first output means operatively coupled to said clock means for generating a cyclical pulse train at a harmonic of said carrier frequency to define said carrier frequency and secon output means operatively coupled to said control input.

17. The invention of claim 14 wherein said syn¬ chronization control means is operative to provide signals at said control input only until said predetermined phase relationship is achieved.

18. The invention of claim 14 wherein said trans¬ mission control means and said phase shifting means are operative to effect 180° phase shifts of said first cyclical waveform to correspond to bit changes in said data.

19. The invention of claim 14 wherein said phase comparison means comprises: means for generating a voltage level representativ of the duty cycle of the logical exclusive OR between said first and second cyclical waveforms; threshold means for generating a logic level cor¬ responding to said voltage level; and window means for generating a logic level indica¬ tive of whether or not said voltage level is representative of a duty cycle generally near 50% corresponding to a phase difference generally near ±90 .'o

20. The invention of claim 14 wherein said means associated with said central computer comprises a second data link having the claimed elements of said first-mentioned data link of claim 14.

21. A system for monitoring the operation of a plurality of remote electrically operated devices, each of

OMPI said devices receiving power from a common set of power distribution lines, comprising: a central computer including signal generating means and signal receiving means; central computer data link means coupling said central computer signal generating means and said central computer signal receiving means to said power distribution lines to permit said central computer to send signals over said power distribution lines and to receive signals over said power distribution lines; said signals from said central computer having a time structure including a portion representative of a particular one of said remote devices with which communica¬ tion is desired; and a corresponding plurality of subassemblies associ¬ ated with said remote devices, each of said subassemblies comprising: a sensor having signal receiving means responsive to said signals from said central computer and having signal generating means for generating signals repre¬ sentative of desired operation information, said sensor having means for transmitting said signals representa¬ tive of operation information only in response to a signal from said central computer designating the particular device associated with that particular sensor; sensor data link means coupling said sensor signal generating means and said sensor signal receiving means to said power distribution lines to permit said sensor to receive said signals from said central computer over said power distribution lines', and to permit said sensor to send said signals representative of operation information to said central computer over said power distribution lines to said central computer, said sensor data link means including a locally controlled clock for generating a first cyclical pulse train at a carrier frequency, said clock having a phase control input and means for stepping the phase of said first cyclical pulse train by predetermined increments in re¬ sponse to signals at said phase control input, transmitting means responsive to said first cyclical pulse train for applying a first sinu¬ soidal signal to said power distribution lines, said first sinusoidal signal having said carrier frequency and being in a constant phase relation- ship with said first cyclical pulse train, receiving means responsive to a second sinusoidal signal generally at said carrier frequency appearing on said power distribution lines, said receiving means having means for generating a second cyclical pulse train at the frequency of said second sinusoidal signal and in a predetermined phase relationship with respect to said second sinusoidal signal, and phase comparison means responsive to said first cyclical pulse train from said clock and said second cyclical pulse train from said re¬ ceiving means, said phase comparison means having means for producing a signal representative of the phase relationship between said first and second cyclical pulse trains; said sensor signal receiving means and signal generating means together including first means for applying signals to said phase control input on said clock to step the phase of said first cyclical pulse train by predetermined intervals to represent binary data bits to be transmitted, and second means for applying signals to said phase control input of said clock to step the phase of said first cyclical waveform by said predetermined increments to bring said first cyclical pulse train generally into a pre-

Q--.-T1 Wli'G determined phase relationship with said second cyclical pulse train during an initial period of data reception in order to permit said phase comparison means to be sensitive to subsequent phase shifts of said predetermined intervals in said second sinusoidal signal, said second means for applying signals operating during data recep¬ tion only until said first cyclical waveform has been brought into said predetermined phase re- lationship with said second cyclical waveform; said sensor having means for transmitting said signals representative of operation information only in response to a signal from said central computer desig¬ nating the particular device associated with that particular sensor.

22. The invention of claim 21 wherein said electrically operated devices are slot machines, and wherein said sensor includes means for detecting coin drop, coin payout, and wheel rotation.

23. In a communications system for interchanging data among members of a plurality of remote electrically operated devices, each of said devices receiving power from a common set of power distribution lines, an improved data link assembly comprising: locally controlled clock means for generating a first cyclical waveform at a carrier frequency; transmitter means for applying said first cyclical waveform to said power distribution lines; phase shifting means for stepping the phase of said first cyclical waveform by predetermined increments in response to signals at a control input; transmission control means for providing signals at said control input to cause phase shifts of predetermined intervals representative of binary data to be impressed on said first cyclical waveform; means for receiving a second cyclical waveform at a frequency approximately the same as said carrier frequency appearing on said power distribution lines; phase comparison means responsive to the phase relationship between said first and second cyclical wave¬ forms; and synchronization control means for providing signals at said control input to step the phase of said first cyclical waveform by said predetermined increments in order to bring said first cyclical waveform generally into a predetermined phase relationship with said second cyclical waveform during an initial period of data reception, where¬ upon subsequent phase shifts of said predetermined intervals in said second cyclical waveform representative of binary data may be detected, said synchronization control means operating during data reception only until said first cyclical waveform has been brought into said predetermined phase relationship with said second cyclical waveform.

24. The invention of claim 23 wherein said pre- determined increments are 90° increments.

25. The invention of claim 23 wherein said trans¬ mission control means and said synchronization control means together comprise a programmed microprocessor having first output means operatively coupled to said clock means for generating a cyclical pulse train at a harmonic of said carrier frequency to define said carrier frequency and second output means operatively coupled to said control input.

26. The invention of claim 23 wherein said trans¬ mission control means and said phase shifting means are operative to effect 180° phase shifts of said first cyclical waveform to correspond to bit changes in said data.

27. The invention of claim 23 wherein said phase comparison means comprises: means for generating a voltage level representative of the duty cycle of the logical exclusive OR between said first and second cyclical waveforms; threshold means for generating a logic level cor- responding to said voltage level; and window means for generating a logic level indica¬ tive of whether or not said voltage level is representative of a duty cycle generally near 50% corresponding to a phase difference generally near ±90°.

28. In a communications system for interchanging data among members of a plurality of remote electrically operated devices, each of said devices receiving power from a common set of power distribution lines, an improved data link assembly comprising: a) a data link including: a clock for generating a first cyclical pulse train, said clock having a phase control input and means for varying the phase of said first cyclical pulse train in response to signals at said phase control input; transmitting means responsive to said first cyclical pulse train for applying a first carrier signal to said power distribution lines, said first carrier signal having a carrier frequency and being in a constant phase relationship with said first cyclical pulse train; receiving means responsive to a second carrier signal generally at said carrier frequency appearing on said power distribution lines, said receiving means having means for generating a second cyclical pulse train at the frequency of said second carrier signal and in a constant phase relationship with said second carrier signal; and phase comparison means responsive to said first cyclical pulse train from said clock and said second cyclical pulse train from said re- ceiving means, said phase comparison means having means for producing a signal representative of the phase relationship-between said first and second cyclical pulse trains; b) signal receiving means and signal generating means together including: first means for applying signals to said phase control input on said clock to shift the phase of said first cyclical pulse train by 180° to represent binary data bits to be transmitted; and second means for applying signals to said phase control input of said clock to step said phase by 90° increments to bring said first cyclical pulse train into a predetermined phase relationship with said second cyclical pulse train during an initial period of data reception in order to permit said phase comparison means to be rendered sensitive to subsequent 180° phase shifts in said second carrier signal, said second means for applying signals operating during data recep¬ tion only until said first cyclical waveform has been brought into said predetermined phase re¬ lationship with said second cyclical waveform.

29. A system for communication between a central computer and at least one remote electrically operated device, said device receiving power from a set of power distribution lines, comprising: means associated with said central computer for sending a polling message on said power distribution line, said polling message having a time structure including a preamble at a carrier frequency followed by binary date represented by phase shifts relative to said preamble; a data link associated with said remote elec- trically operated device comprising: locally controlled clock means for generating a first cyclical waveform at a frequency close to said carrier frequency; transmitter means for applying said first cyclical waveform to said power distribution lines; phase shifting means for stepping the phase of said first cyclical waveform by predetermined increments in response to signals at a control input, transmission control means for providing signals at said control input to cause phase shifts of predetermined intervals representative of binary data to be impressed on said first cyclical waveform, means for receiving a second cyclical wave¬ form at approximately said carrier frequency appearing on said power distribution lines, phase comparison means responsive to the phase relationship between said first and second cyclical waveforms, and synchronization control means for providing signals at said control input to step the phase of said first cyclical waveform in order to bring said first cyclical waveform generally into a predetermined phase relationship with said second cyclical waveform during an initial period of data reception, whereupon subse- quent phase shifts of said predetermined intervals in said second cyclical waveform representative of binary data may be detected, said synchronization control means operating during data reception only until said first cyclical waveform has been brought into said predetermined phase relationship with said second cyclical waveform; said data link thus being operable initially to synchronize with said preamble, then to demodulate said data portion of said polling message, and finally to transmit a response on said power distribution lines.

30. The invention of claim 29 wherein said phase shifting means comprises means for stepping_.the phase by 90° increments.

31. The invention of claim 29 wherein said trans- mission control means and said synchronization control means together comprise a programmed microprocessor having first output means operatively coupled to said clock means for generating a cyclical pulse train at a harmonic of said carrier frequency to define said carrier frequency and secon output means operatively coupled to said control input.

32. The invention of claim 29 wherein said trans¬ mission control means and said phase shifting means are operative to effect 180° phase shifts of said first cyclical waveform to correspond to bit changes in said data.

33. The invention of claim 29 wherein said phase comparison means comprises: means for generating a voltage level representativ of the duty cycle of the logical exclusive OR between said first and second cyclical waveforms; threshold means for generating a logic level cor¬ responding to said voltage level; and window means for generating a logic level indica¬ tive of whether or not said voltage level is representative of a duty cycle generally near 50% corresponding to a phase difference generally near ±90°,

34. The invention of claim 29 wherein said means associated with said central computer comprises a second data link having the claimed elements of said first-mentioned data link of claim 29.

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