WO1982002965A1

WO1982002965A1 - Multi-processor office system complex

Info

Publication number: WO1982002965A1
Application number: PCT/US1982/000231
Authority: WO
Inventors: Mize Johnson Jr
Original assignee: Mize Johnson Jr
Priority date: 1981-02-25
Filing date: 1982-02-24
Publication date: 1982-09-02
Also published as: EP0073239A1; GB8423510D0; GB2144892A; ES509892A0; ES8303741A1; CA1184310A; IT8219853A0; GB2107906B; GB2107906A; IT1149773B

Abstract

A multi-processor system formed by a plurality of intelligent Processing nodes (100, 101, 102, 103) interconnected by one or more transmission lines (15) to form a shared resource cluster provides two levels of modularity which facilitate system design and growth requirements. Within each node a synchronous exchange bus (25) interconnects processors (30) in any combination up to a maximum total number of units, all microprocessor controlled except for global memory and the like. Each microprocessor controlled unit (350) connected to the synchronous exchange bus includes random access memory (302) which is functionally divided into a first portion (302) for storing instructions and data for the on-board processor and a second portion acting as a global memory (43) accessible by other processor controlled units on the bus. Memory address assignment for the global memory portion of each unit memory is stored in the unit in a register (106) which is accessible by other units, so that the system can reconfigure memory address assignments by re-writing the memory address assignment in the on-board register via the bus or directly from the on-board processor. An I/O or slot address (R1) is assigned to each board as it is plugged into the bus identification lines and this I/O or slot address is used to access the board for memory address assignment.

Description

Multi-Processor Office System Complex

The present invention relates to data and word processing systems in general, and more particularly, to a multi-terminal document preparation and data processing system of the shared-resource or clustered configuration type which combines the similar, yet divergent, technologies of word and data processing to perform a full range of business tasks both within the office and from remote locations . Systems capable of performing data and word processing fall within the basic categories of ( 1) full-featured stand-alone units, (2) shared logic systems containing a number of display-based work stations sharing the logic of a central computer, and (3) sharedresource or clustered configurations in which intelligent terminals or work stations are interconnected to provide common access to central computer, controller and/or disc storage. The advantages of standalone units reside in their ability to function independently of other units, and therefore, are not subjected to operating malfunctions as a result of breakdown of other units ; however, such stand-alone units have the disadvantage of providing a higher-per-station cost and limited capability insofar as data storage and available features is concerned. On the other hand, shared logic systems in which work stations share the logic of a central computer for storage, retrieval, text manipulation and printing reduce the cost per work station and provide a greater capability insofar as features and storage capability is concerned , but when the central computer malfunctions , the entire system is affected.

The most recent development in data and word processing office systems is directed to the shared-resource or clustered configuration approach in which work stations are provided in a selected number on a modular basis and interconnected to provide a full sharing of capabilities throughout the system while maintaining a certain independence and isolation within each work station insofar as effects of malfunctions in other work stations are concerned . This modular approach also permits the adaptation of such systems to offices of large and small size alike, permitting growth of the system in steo with the need for increased services within the office . Many systems have been proposed to handle word or data processing applications, but very few systems have been integrated to handle both applications. Those systems which have accomplished such integration have done so by interconnecting systems originally developed independently of each other as opposed to a design that integrates both word and data processing from the outset. Thus, these semi-integrated systems fail to provide the degree of efficiency in either the data processing or the word processing area which is required at the level of present-day technology. The advantages of modularity have been applied to various areas of system design in the past years in an effort to accommodate the economic and functional requirements of business customers and avoid the obsolescence which is built into non-expandable systems of a predetermined size. In both the shared-logic systems and the sharedresource or clustered configuration systems proposed to date, the basic requirement of modularity has been implemented by providing for expansion on a single level of modularity generally through the ability to add work stations to the system as the need for greater capability arises . In clustered configuration systems in which intelligent work stations or terminals are interconnected in a system providing for sharedresource, as opposed to the shared-logic system in which non-intelligent terminals or semi-intelligent terminals are connected to a central computer, the work stations are relatively costly so that the addition of a work station each time increased capability is required places a heavy burden on the owner of the system. Thus, there is a present need for a system of the clustered configuration type in which modularity is provided on two levels so that system design and expansion can occur not only with the addition of work stations but with the expansion of existing work stations, providing greater control over the size, capability and flexibility of the system.

It is therefore a principal object of the present invention to provide an integrated word processing and data processing system of the shared-resource or clustered configuration type providing two levels of modularity, the highest level being in the cluster which is built up using nodes configured around a basic set of functional hardware modules. It is another object of the present invention to provide a system of the type described in which all elements are highly programmable so that different requirements can be accommodated with software/firmware changes instead of hardware changes . It is another object of the present invention to provide a system of the type described which minimizes product life cycle costs .

It is a further object of the present invention to provide a system of the type described which is capable of accommodating both low cost and high performance applications. It is a further object of the present invnetion to provide a system of the type described in which modularity of functions provide for future hardware /software growth with minimal system impact.

It is a further object of the present invention to provide a system of the type described which eliminates the need for dedicated processors for certain functions, specific numbers of processors in a system, specific processor types , particular memory mapping or protection hardware, and other architectural dependencies .

The basic unit of the system in accordance with the present invention is an intelligent processing node provided in the form of a stand-alone intelligent unit providing the capability for document text entry, modification, storage, and hard-copy output. A major feature of this system is the ability to connect up to sixteen nodes , with a highspeed cluster communication link to form a cluster, which represents the first level of modularity in the system . Nodes within a cluster can share each other's peripheral resources including floppy disc storage and output devices . This allows greater flexibility in the design and growth of the system and provides a basis for various advanced features such as electronic mail distribution and other data communication and processing features . The work station is based on an intelligent terminal that is cable-connected to a node that contains one or more processing units, floppy discs and device control electronics . The intelligent terminal incorporates a keyboard, a raster-scan CRT display, and a read-write memory, and is driven by a microprocessor. The node can support a plurality of terminals, depending on desired work station response, but is also capable of supporting several types of peripherals, including a floppy disc, rigid disc, daisy-wheel printer, draft printer, twin-wheel printer, high-speed dedicated cluster link communications, commercial carrier data communications and a typesetter. The number and combination of peripherals per node is limited only by the device controller slots and controller channel availability in the node and by desired response times .

The memory which forms part of each general purpose processor in each node can be dual ported so that other processors in the node can access it. This feature tends to further reduce bus contention by allowing I/O controllers and other processors to deposit data directly into the local memory of the processor responsible for handling it. This also makes it possible to provide for auto-configuration of the memory address space available on the boards connected in common to the bus, which combined address space provides the appearance of a shared global memory. In this regard, each card is provided with a physical I/O address corresponding to the slot it occupies on the bus, and by use of this I/O address, the memory address block assignments for each card can be automatically established, as desired, by the system, simply changing the assigned address data stored in a register on its and/or another card or cards on the bus . This eliminates the manual assignment of addresses via switches, which leads to possible operator error and malfunction of the system .

Thus, a system is provided in accordance with the present invention in which a first level of modularity is built into the cluster through the interconnection of a desired number of nodes via the cluster communications link, while a second level of modularity is provided within the node itself by permitting the varied connection of different numbers of intelligent terminals and other peripheral devices to the control pedestal. These and other objects, features and advantages of the present invention will become more apparent from the detailed description of a preferred embodiment presented herein in conjunction with the accompanying drawings. Brief Description of Drawings

Figure 1 is a schematic diagram of one embodiment of the present invention forming a system cluster;

Figure 2 is a schematic diagram of the configuration of an intelligent processor node;

Figure 3 is a schematic diagram of the architectural arrangement of elements forming the intelligent processor node;

Figure 4 is a schematic diagram, illustrating the available variations in configuration of a typical cluster; Figure 5 is a schematic block diagram of the general purpose processor provided in each node;

Figures 5A through 5G are diagrams illustrating the on-board memory feature of the present invention;

Figure 6 is a schematic diagram of the serial multiplexer controller:

Figure 7 is a schematic diagram of a mass storage controller; Figure 8 is a schematic diagram of the global memory arrangement; Figure 9 is a schematic diagram illustrating the memory address auto-configuration and bus identification feature of the present invention; and

Figure 10 is a schematic circuit diagram of the cluster communication link configuration. Best Mode For Carrying Out Invention

The present invention provides a multi-terminal document preparation and distribution system which utilizes distributed processing to provide a flexible, reliable system architecture with facilities for creation, revision, storage, and distribution of various types of documentation with capability for both word processing and data processing on an integrated basis. The system comprises one or more clusters of processor nodes to which one or more work stations and other peripheral devices may be selectively connected to provide two levels of modularity which establishes a high level of flexibility in design and function within the system . Each node may have one or more intelligent display /keyboard terminals with a self-contained microcomputer and sufficient memory and processing power to function as a stand-alone word processor work station or as an integral component in a shared-peripheral cluster configuration with other nodes . Figure 1 illustrates the basic configuration of the system cluster which includes two or more intelligent processing nodes 10 interconnected by one or more cluster communication links 15 to which the nodes 10 are connected by way of taps 14. To the intelligent processing nodes 10 there are connected in selectively-variable combinations various peripheral devices 12, including intelligent terminals, floppy disc storage units, rigid disc storage units, daisy-wheel printers, draft printers, typesetters, modems for remote communication with other systems, and similar peripheral devices. The cluster is built around the cluster communication link 15 which is a passive coaxial data link supporting up to sixteen active taps 14 for connection of nodes to the link. Nodes may be connected anywhere along the data link 15, which provides a half-duplex multiplexed interconnection, with data transfers between nodes 10 being broken into packets which are interleaved with other inter-node transfers . The cluster communication link 15 is the mechanism by which the intelligent work stations and other intelligent peripherals 12 connected to the nodes 10 interface with one another within the cluster. In terms of the cluster, a node 10 is defined as any element which attaches to the data link 15 via a tap 14 and is not restricted to a specific piece of hardware.

The primary purpose of the cluster communication link 15 is to provide a medium speed communications path for loosely coupling nodes 10 so that systems larger than a single node can be provided in a flexible manner. The use of a passive serial link 15 also provides improved reliability, physical dispersion of system elements, and increases the flexibility in system configuration. With the multi-layer configuration provided by the cluster, as seen in Figure 1, tightlycoupled high bandwidth processing takes place within the node 10 so that large systems can be partitioned into smaller functional units in a relatively-simple manner. Data transfer on the cluster communication link 15 is provided in accordance with high level data link control (HDLC) protocol and uses a rotating master scheme to avoid contention on the link, to provide load sharing and minimize the number of single point failures which can disable the link. During normal system operation, mastership of the link 15 is continuously exchanged between active nodes . A single node will retain the link for a maximum of 50 ms without allowing other nodes the chance to assume mastership. Master exchange is accomplished by polling the other nodes to determine if there is any wish to use the link. The current master will use the results of the poll cycle to determine which node is to be selected as the next master and will inform that node that it is to assume mastership . If no other node requests the use of the link during the poll cycle, the current master can retain control of the link. The actual polling is based on a round robin active/ inactive queue scheme. The master node polls the following nodes in the active queue, which is a circular queue, until it finds one which wants to assume control of the link or all other nodes have been polled. If another node wants control, then mastership is passed to that node. If no other nodes wants the link, the control is always retained by the current master. In this way, no dedicated bus master or other bus controller is required, lending to the simplicity of the cluster configuration.

The active queue contains all nodes which respond to a poll while the inactive queue contains all possible nodes except those on the active queue. In order to join in the link communications, a node must be transferred from the inactive queue to the active queue. This is accomplished by having a flag in the active queue which indicates that nodes on the inactive queue are to be polled, which is performed once every two passes through the active queue, and these nodes are then added to the active queue if they respond . When the current master detects the flag in the active queue indicating that the inactive queue is to be polled, then the inactive queue is used as a source of the poll addresses . Once a node is in the active queue, it remains there until it fails to respond to a poll three times, in which case it is then moved to the inactive queue.

Due to the rotating master concept of bus mastership, there will be only one master at a time and any node requiring use of the link must wait until it is selected . However, during system powerup or in case of failure in the current master, situations will exist where no node is master and one must be assigned to return to the normal mode of operation. When a node is first powered up, it can determine if the link is active by listening for traffic on the link, or if it is already active, it can determine that the master has failed if it does not receive a poll within two seconds . When a node detects that the link is inactive and it needs to use the link, it enters a contention mode in an attempt to acquire mastership . In the contention mode the node starts the poll cycle and listens to its own transmission as well as any responses . If the node hears its own transmission garbled, it enters a timeout routine with the delay based on the node identification and attempts the poll again if it has not seen any other transmission during the delay interval. If the node receives a response intended for another node, then it assumes that the other node has assumed control.

The intercommunication system formed by the cluster illustrated in Figure 1 provides message routing between tasks in different nodes , Thus, if a file is needed in one node which resides in memory in a second node, a request to read the file would be formatted into a message within the first node, the message including the identity of the first node and its reply exchange. The message would then be sent to the second node where the request would be processed. The second node would then format the required file into a message, which would be sent back to the first node, completing the request.

Thus , the cluster provides a multi-level interconnection system of intelligent processing modules which combines the best features of stand-alone units and shared-logic systems . Peripheral units 12, such as intelligent terminals, forming part of a node or work station can operate on a stand-alone basis or communicate with one another or with other intelligent peripheral units providing storage and other capabilities through the commonly-connected intelligent processing nodes 10 or communicate with other intelligent peripheral devices 12 connected to other intelligent processing nodes 10 via the cluster communication link 15. As seen in Figure 1, a plurality of intelligent processing nodes 10

(up to sixteen) can be interconnected via a single cluster communication link 15 and each intelligent processing node 10 can be connected via taps 14 to up to twenty-four cluster communication links 15. Such an arrangement provides multi-level flexibility in the configuration of the cluster both from the point of view of size and the available functions provided within the cluster. Thus, the cluster concept provides a system capable of inter-node communications and sharing of peripheral resources at a much lower per-terminal cost than typical shared-logic controller type systems.

Just as the cluster is built around the cluster communication link 15 using functional node types , the nodes 10 are built around a synchronous exchange bus 25 using functional hardware modules, as seen in Figure 2. The synchronous exchange bus 25 provides a tightlycoupled high bandwidth bus structure optimized for multi-processor use, and is a unified bus architecture which places minimum constraints on the internal structure of each node, allowing for a more long-term growth capability within the system .

Connected to the synchronous exchange bus 25 are one or more general purpose processors 30, a plurality of I/O subsystems 35 for connection between the bus 25 and one or more of the cluster communications links 15 or other peripherals and communication lines, a magnetic tape subsystem 40 connecting the bus 25 to one or more magnetic tape units 42, a floppy disc subsystem 45 connecting the bus to one or more floppy disc units 48, and a rigid disc subsystem 50 connecting the bus 25 to the one or more rigid disc units 52. All of the modules connected to the bus 25, as seen in Figure 2, are stand-alone microprocessor based subsystems which facilitate the layering of functions, contributing to the flexibility of design within the system.

The synchronous exchange bus 25 can accommodate up to sixteen modules in any mixture. Thus, even though some combinations, such as sixteen general purpose processors 30 or rigid disc subsystems 50, might not be particularly useful, there are no hardware limitations to preclude such combinations. Due to the multi-master nature of the synchronous exchange bus 25, multi-processor systems can be built by simply connecting more than one general purpose processor 30 to the bus 25, and incorporation of local memory in the general purpose processor 30 allows it to function more effectively in a multi-processor environment by reducing the number of bus accesses .

One of the most important elements in a computer system is the bus structure that holds all of the hardware components together. This bus structure contains the necessary signals to allow the various system components to interact with each other, i. e. , it allows memory and I/O data transfers, direct memory accesses, generation of interrupts, and the like. The synchronous exchange bus 25 is the flexible bus structure used to interface a family of products which include sixteen bit single board computers, memory expansion boards, digital I/O boards and peripheral controllers . The structure of the synchronous exchange bus 25 is built upon the master/slave concept where the master device in the system takes control of the bus 25 and the slave device, upon decoding its address, acts upon the command provided by the master. This handshake between master and slave device allows modules of different speeds to use the bus 25 and allows data rates of up to five million transfers per second in bytes, words or double words. The synchronous exchange bus 25 comprises address and data lines and those control lines necessary to carry the signals which allow the various system components to interact with each other. The arbitration for bus mastership between the various system components connected to the bus 25 occurs synchronously with priority being determined by physical location on the bus, as described more particularly in my cop ending U.S . Application Serial No. , filed January 12, 1981, entitled "Synchronous Bus Arbiter" . Although the arbitration for bus mastership on the synchronous exchange bus 25 occurs synchronously, the data transfers occur asynchronously at a rate determined by the particular master/slave pair passing data across the bus at a given point in time.

The synchronous exchange bus 25 is a time-division multiplexed bus with a unified bus architecture and no dedicated/required modules . This type of bus minimizes configuration problems and provides the maximum flexibility in system/module design. In order to cover the wide range of applications desired for the system, and allow future expansion in a flexible manner, the synchronous exchange bus 25 provides a high bandwidth, low cost, processor independent bus by using standard drivers/receivers and multiplexed address /data lines. Figure 3 shows the architectural configuration for a typical node including an intelligent work station terminal 125, a printer/typesetter unit 126, and a modem 127 connected to the intelligent processing node electronics in pedestal 100. Providing the terminal 125 and the pedestal 100 in physically-separate packages effectively separates the display and keyboard functions from the processing and communication functions, with the terminal 125 and the pedestal 100 being coupled by an asynchronous link 110. The pedestal 100 is in turn connected to the cluster communication link 15 by a tap 14 via line 18, as already described in connection with Figure 1.

The node electronics contains the general purpose processor 30, an I/O controller in the form of a serial multiplexer controller 35, a floppy, disc controller 45, and a global memory 43, and as already indicated, up to sixteen controller units may be connected to the asynchronous exchange bus 25 in virtually any mixture so that the particular combination illustrated in Figure 3 merely represents an example of a basic configuration available in accordance with the present invention. As seen in Figure 4, which illustrates an example of a typical cluster, a double pedestal 101, 104 provides a work station node interconnecting four intelligent terminals 125, four floppy disc units 48 and a printer 126a via the cluster communication link 15. At the same time an extended storage node 102 connects four bulk storage units 44 to the link 15, while single pedestal 103 provides a pair of terminals 125, four floppy disc units 48 and a printer 126a. The single pedestal 100 provides a terminal 125, two floppy disc units 48, a printer 126a and a modem 127, and the extended telecommunication node 105 provides for communication to remote systems via modem 127 as well as access to bulk storage 44, With such flexibility in the design of the system, the specific needs of each individual user on a present and future basis can be easily configured.

The work station terminal 125 is essentially a standard intelligent terminal of the type commonly available in the industry, such as the Harris standard terminal manufactured and sold by Harris Corporation. Such a standard terminal typically includes a processor module associated with ROM, RAM and a serial I/O port.

As seen in Figure 5, the general purpose processor 30 provided in each node 100 comprises an available microprocessor, such as an Intel 8086 microprocessor, a RAM 302 capable of providing 128 K bytes of storage, a bootstrap ROM 303, an I/O port 304 for coupling to a remote diagnostic facility, a synchronous exchange bus interface 306 and a synchronous exchange bus interrupt interface 305 along with the standard timing circuit 307 associated with the microprocessor 301. The RAM memory 302 is divided into two equal memory areas of 64 K each, which has special advantages in a multi-processor configuration . Where only a single general purpose processor 30 is provided in the node, the division of the RAM memory 302 is of no special consequence since together the two portions form a contiguous 128 K memory with no apparent boundary at the 64 K point. By providing the general purpose processor with a portion of dual ported memory, many small systems can be built without a global memory since the dual ported memory looks just like a shared global memory to the other elements of the system. When a global memory 43 is provided in the pedestal, the general purpose processor 30 will send each memory request either to its on-board memory area (RAM 302) or to the off-board global memory 43 depending on the address for that request. In a single processor configuration, there is no effective boundary at the end of the general purpose processor's memory 302 (128 K point) since the global memory 43 would respond to the next address (128 K+ 1 byte) . Again, programs and data could span this boundary without consequence except for perhaps a slightly-longer access time due to access to the synchronous exchange bus 25.

However, the 64 K/64 K split of the RAM memory 302 in the general purpose processor 30 does become a consideration in a multiprocessor configuration. For example, the first 64 K of the memory 302 in a first general purpose processor is made accessible to, and only to, the processor residing on the same card. Then, the second 64 K portion of the memory 302 acts exactly as if it were a global memory on the general purpose processor card itself, which can be read from or written into by any and every other general purpose processor or I/O controller in the system . Thus, each general purpose processor actually contains a microprocessor plus 64 K of local memory and 64 K of global memory. This memory splitting feature in a multi-processor configuration provides considerable advantages in the handling of tasks within the system, as will be described in conjunction with Figures 5A through 5G. Figure 5A schematically shows a single processor system executing three assigned tasks A, B and C . In a single processor system, the assignment of tasks is controller by a simple multi-tasking algorithm since there is only the single processor to handle the various tasks. Thus, the processor simply selects one of the tasks that it knows about for execution. The situation is only slightly more involved when two processors are available within the system, as seen in Figure 5B . Here there may be, but not necessarily, a choice in processors to be assigned to perform the tasks A, B and C , For example, if tasks A and B are assigned to CPU 1 and task C is assigned to CPU 2, then there is no choice in assignment. CPU 1 operates in a multi-tasking mode as it did before, and CPU 2 operates only oh the single task C . Conceptually, the two processors CPU 1 and CPU 2 are still totally independent, even though they contend for the common bus to which they are connected and their tasks are in the same memory.

If CPU 1 and CPU 2 are allowed to know about the other's software tasks, then there is a choice to be made in processor assignment. For example, if tasks A, B and C are allowed to execute on either CPU 1 or CPU 2, whichever is available, as depicted in Figure 5C, then the only complication is to guarantee that CPU 1 and CPU 2 are not executing the same task at the same time. They may alternate execution of a given task, or execute different tasks at the same time, without confusion. Each simply selects a task that is ready to execute but is not already executing from the lists of tasks it knows about (in this case, tasks A, B and C) . However, in a multi-processor system where processors are all connected to a common bus, the traffic on the bus carries the load for all processors . If the hardware were configured with the processors and memory as independent units on a common bus, as seen in Figure 5D, the bus would rapidly become a throughput bottleneck. This is especially true as additional processors are added to the system on the common bus . On the other hand, if each processor has its software in its own private on-board memory, it would have no need to use the bus . Performance would improve for this reason; however, this would totally prevent the ability to assign a task to more than one processor. The multi-processor/global memory concept of the present invention in which the on-board memory associated with each general purpose processor is subdivided into separate 64 K memory areas to provide an on-board global memory area on each board offers a solution to this problem, as demonstrated in Figure 5E , providing a system capable of supporting many processors with very little system bus contention.

If a copy of system software is placed in global memory, then all but one of the processors in the multi-processor system will use the synchronous exchange bus to execute its system code. If, however, an identical copy is placed in an identical position of each general purpose processor's local memory (0 - 64 K region) , then each processor will have its own copy of software and will stay off the synchronous exchange bus. Since the copies are identically placed, each processor would view the system software as if it were sharing one copy in global memory. This arrangement, as shown in Figure 5E, leaves a system capable of supporting many processors with very little system bus contention. Synchronous exchange bus loading in such an arrangement results primarily from I/O traffic and communication between tasks that reside on different general purpose processors. This inter-task bus communication can be minimized by grouping highly-interactive software tasks on the same general purpose processor global memory space.

In accordance with the present invention, the global 64 K memory portion of the RAM 302 has a programmable base address, while the local 64 K portion always starts at address 0. This allows the global memory portions of the RAMs 302 in each general purpose processor to be stacked to form a large contiguous addressing space. If software programs are loaded without care into global memory, as seen in Figure 5F, unnecessary synchronous exchange bus traffic will result from the processors going off-board to execute their assigned tasks. However, since a CPU reference to global memory residing on the same card as the requesting processor does not use the synchronous exchange bus, by taking more care in selecting the memory position for software, i.e. , by loading software into the proper area of memory so that it resides on the same card as its controlling processor, the synchronous exchange bus traffic can be significantly reduced, as shown in Figure 5G .

This special memory feature of the present invention also facilitates the handling of interrupts to the processors connected to the synchronous exchange bus 25. When dealing with multiple processors, it becomes necessary to alter other processors when an event has occurred, an I/O is complete, a task is ready to run, and the like. This is typically done using interrupts . It is highly desirable, however, to interrupt only those processors that need to be made aware of the event. Even more important is the ability to inform the processor of the reason for its being interrupted so that it need not search tables, lists, etc. , looking for the reason. This is accomplished by an Interrupt Coupling and Monitoring System, as disclosed in copending U .S . Application Serial No, , filed January 15, 1981, and assigned to the same assignee as the present application.

As seen in Figure 6, the serial multiplexer controller 35 incorporates a Z-80 microprocessor 350, RAM memory 351, ROM memory 352, four independent serial interfaces 353, a system data channel interface 354, a local direct memory access controller 355, and the standard CPU support logic 356 and timing generators 357 associated with this type of processor system. The basic objective of the serial multiplexer controller is to provide the real time I/O processing for the system so that the general purpose processors 30 do not have to contend with the interrupt and real time processing/latency requirements of the system . Another objective of the serial multiplexer controller is to provide a flexible interface so that different communication and peripheral interfaces can be handled by a common controller either directly or via simple adapters.

Each serial multiplexer controller 35 provides four independent serial interfaces, which may be used for connection to the cluster communication link 15, as shown in Figure 3, and for connection to work station terminals 125, printer/typesetters 126, modems 127 and similar intelligent peripheral devices in any mixture, as desired . As in the case of the general purpose processor 30, one or more serial multiplexer controllers 35 can be provided in each pedestal connected to the common synchronous exchange bus 25 depending upon design requirements to provide more or less interface capacity. As shown in Figure 7, the mass storage controllers connected to the synchronous exchange bus 25 in each node are very similar in configuration to the serial multiplexer controller 35 except that they interface to mass storage devices , such as a floppy disc drive, rigid disc drive, magnetic tape drive and the like. In this regard, a processor 701 is connected to a ROM 702 and RAM 703 via a processor bus

705, to which there is also connected address register 706, data input register 707, data output register 708, interrupt circuitry 709 and storage interface circuitry 710 providing interface to the storage devices . By interfacing the mass storage devices with an intelligent controller, it is possible to remove some of the real time processing from the general purpose processors connected to the bus 25 and also to make the interfaces to all mass storage devices look alike so that the rest of the system is not aware of the device characteristics. This also allows the mass storage controller to perform high level functions and relieve some of the processing requirements of the system.

The global memory unit 43, which may be optionally connected to the synchronous exchange bus 25, as seen in Figure 8, to provide additional memory in the node, is basically a RAM with software controlled address range setting. Since all other units connected to the bus 25 contain processors, their addressing is easily configured by the on-board processors. however, the global memory being a non-intelligent unit must have an external input to set its address allocation. This is accomplished by configuring the RAM to include control registers which another processor can read from and write into in order to control the global memory address range assigned thereto.

In addition to the problem of how to address the control registers of the global memory, all units connected to the bus 25 in each node share a common problem of establishing initial communications before memory addresses are assigned . In this regard, it is not desirable to use fixed memory addresses since this requires a discontinuity in the memory space and also additional decoding logic to decode the large number of bits in the memory address. An additional problem is how to set the memory addresses to be used on each card. In past systems, this has been accomplished by either using switches on the circuit boards , which require operator setting to configure the system, or by assigning addresses by device type, which requires a much larger number of addresses than would ever be present in a single system and limits future expansion of the system.

These problems are solved in accordance with the present invention in the manner shown in Figure 9. The synchronous exchange bus 25 includes a plurality of data/address lines to permit addressing of units on the bus and effect transfer of data to and from such units . The ASYNC line indicates when address information is stable on the bus and the DSYNC line indicates when data is stable on the bus. The bus 25 also includes bus identification lines BID (0) and BID (1) by which physical I/O addresses are assigned to each card as it is plugged into the bus . In this regard, a plurality of conductors C on each card engage contacts D which are connected to the bus identification lines BID (0) and BID ( 1) in a coded combination representing the physical address of the slot on the bus, so that this address is automatically assigned to the card as it is plugged in. The I/O or slot address of each card is stored in a register R2 on the card, which is also handwired to provide additional coding to identify the card type. This allows other cards to determine what type of card is in each slot simply by reading the contents of register R2 on the card . In place of the manually-operable switches to set the memory address assignment for each card, as typically provided in the prior art, each card connected to the bus 25 also includes a register Rl in which the memory address assignment for that card is stored. Thus, when an address appears on the data/address lines as indicated by the ASYNC line and the state of the IOEN line indicates that this address is a memory address , the received address is checked against the assigned block of memory addresses in register R1 to determine if memory space on that particular card is being addressed. On the other hand, if the state of the IOEN line indicates that the received address is an I/O address, then that address is compared to the contents of the R2 register. Once the card has been accessed via its I/O address, a new memory address assignment can be written into the register Rl. Of course, the contents of register R1 can be changed by its on-board processor at any time. These operations are carried out when control of the on-board processor and suitable logic circuitry, as represented , for example, by the arbitrator 310 in the processor 35 as shown in Figure 8

Thus, since each card is automatically assigned a fixed I/O address according to the slot it occupies on the bus 25, the memory address space assigned to that card can be varied to permit reconfiguration of the memory space in the system simply by addressing the board via its slot or I/O address and placing in the address register on the card the new memory address assignment for that card . In this way, all card slots have access to their slot number and information concerning the other cards connected to the bus and have the ability to assign memory addresses . This type of operation permits the system to configure itself and results in fewer operator errors in the setting of switches to assign memory addresses, as typical in the prior art. Further, the operators do not need to know about the internal details of the system. It also increases the reliability of the system by allowing it to automatically reconfigure around failed modules and continue operation.

Figure 10 shows the details of the cluster communication link which features a passive coaxial line to increase the system reliability and provide DC isolation so that a common system ground becomes unnecessary, As indicated with respect to Figure 1, up to sixteen nodes may be connected to the link 15 via transformer taps 14.

While I have shown and described several embodiments of the present invention, it is understood that the invention is not limited to the details shown and described herein but is susceptible of numerous changes and modifications as known to one of ordinary skill in the art, and I therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications obvious to those skilled in the art.

Claims

What Is Claimed Is :

1. A multi-processor system for data processing of the clustertype, comprising : a coaxial transmission line; a plurality of nodes, each node including a multiconductor bus for carrying both data and address signals, a general purpose processor connected to said bus, and microprocessor controlled serial multiplexer connected to said bus and providing plural I/O ports, at least one I/O port of the serial multiplexer in each node being connected to said coaxial transmission line; and a plurality of I/O devices connected to the I/O ports other than said one I/O port of said serial multiplexer means of said plurality of pedestals ,

2. A multi-processor system according to claim 1, wherein said I/O devices include intelligent terminals.

3. A multi-processor system according to claim 1, wherein each of said nodes includes a plurality of microprocessor controlled serial multiplexers, each having a plurality of I/O ports connected to I/O devices.

4. A multi-processor system according to claim 3, further including a plurality of coaxial transmission lines, a respective I/O port of said plural serial multiplexer means being connected to each of said coaxial transmission lines .

5. A multi-processor system according to claim 1, further including a plurality of mass storage devices, said memory controller means including plural memory ports for connection to respective mass storage devices.

6. A multi-processor system according to claim 1, wherein each of said pedestals includes a plurality of general purpose processors connected to said multi-conductor bus .

7. A multi-processor system according to claim 6, wherein each general purpose processor includes an on-board microprocessor and a random access memory having a first memory portion storing operating instructions or data for said on-board microprocessor and a second memory portion forming an on-board global memory accessible by the on-board microprocessors of all of the general purpose processors via said multi-conductor bus .

8. A multi-processor system according to claim 7, further including a global memory device connected to said multi-conductor bus providing data storage apart from that provided in each general purpose processor.

9. A multi-processor system according to claim 1, wherein said serial multiplexer means includes a microprocessor connected to an I/O bus, a plurality of I/O interface circuits connecting said respective I/O ports to said I/O bus and a data channel interface connecting said I/O bus to said multi-conductor bus.

10. A multi-processor system of the cluster type for both data and word processing, comprising: a plurality of coaxial transmission lines ; a plurality of microprocessor based intelligent processing nodes, each node being connected by taps to each of said coaxial transmission lines; and a plurality of groups of intelligent peripherals, each group connected to a respective intelligent processing node,

11. A multi-processor system according to claim 10, wherein each intelligent processing node includes a synchronous exchange bus, a general purpose processor connected to said synchronous exchange bus, microprocessor controlled memory controller means connected to said bus for providing data storage, and serial multiplexer means including a microprocessor and a plurality of I/O ports connected to said microprocessor via an I/O bus for coupling data between said I/O ports and said synchronous exchange bus.

12. A multi-processor system according to claim 11, wherein a respective I/O port of said multiplexer means is connected to said intelligent peripherals and said plurality of coaxial transmission lines .

13. A multi-processor system according to claim 12, wherein at least one of said intelligent processing nodes includes a plurality of general purpose processors connected to the synchronous exchange bus therein.

14. A multi-processor system according to claim 13, wherein each general purpose processor in said one intelligent processing node includes an on-board microprocessor and a random access memory having a first memory portion storing operating instructions and data for said on-board microprocessor and a second memory portion forming an onboard global memory accessible by the on-board microprocessors of all of the general purpose processors via said synchronous exchange bus .

15. A multi-processor system according to claim 14, wherein said intelligent peripherals include display terminals, hard copy terminals and printers connected in different combinations to respective intelligent processing nodes .

16. A multi-processor system according to claim 10, wherein at least one of said intelligent processing nodes includes a plurality of microprocessor controlled serial multiplexer means connected to the synchronous exchange bus therein.

17. A multi-processor system according to claims 10 or 16, wherein said serial multiplexer means includes a microprocessor con-r nected to an I/O bus, a plurality of I/O interface circuits each connecting at least one I/O port to said I/O bus and a data channel interface connecting said I/O bus to said synchronous exchange bus.

18. A data processing system comprising a synchronous exchange bus; a plurality of general purpose processors each connected to said synchronous exchange bus and each including a microprocessor and a random access memory having a first memory portion storing operating instructions and data for said microprocessor and a second memory portion forming an on-board global memory accessible by the microprocessors of all of the general purpose processors connected to said synchronous exchange bus ; microprocessor controlled memory controller means connected to said synchronous exchange bus for data storage; serial multiplexer means including a microprocessor, a plurality of I/O ports connected to said microprocessor via an I/O bus and a data channel interface connecting said I/O bus to said synchronous exchange bus ; and a plurality of intelligent peripheral devices connected to respective I/O ports .

19. A data processing system according to claim 18, wherein a plurality of serial multiplexer means are connected to said synchronous exchange bus .

20. A data processing system according to claim 18, further including a global memory device connected to said synchronous exchange bus providing data storage apart from that provided in each general purpose processor.

21. A data processing system according to claim 18, wherein said synchronous exchange bus includes bus identification means for providing a coded signal combination representing a slot address at each position on the bus at which a general purpose processor, memory controller means or serial multiplexer means is connected .

22. A data processing system according to claims 18 or 21, in which at least one of said general purpose processors includes register means for storing a range of memory addresses assigned to that processor and means for accessing the random access memory of that processor on the basis of addresses received on said synchronous exchange bus which fall within the range stored in said register means,

23. A data processing system according to claim 22, wherein said one general purpose processor is responsive to data on said synchronous exchange bus representing a revised range of memory addresses for storing said data in said register means .

24. A data processing system comprising a multi-conductor bus including data and address lines; a plurality of units each having a random access memory connected to said bus in respective slots along the bus by means of a plug-in connection: said plug-in connection including slot identification means for providing a respective coded signal combination representing a slot address to each unit as it is plugged into said bus, each unit having means for storing its slot address; register means in each unit for storing a range of memory addresses assigned to that unit; and means in each unit for accessing the random access memory of that unit on the basis of addresses received on said bus which fall within the range stored in said register means .

25. A data processing system according to claim 24, further including means in each unit responsive to detection of its slot address and data representing an assigned range of memory addresses on said bus for storing said data in said register means .

26. A data processing system according to claims 24 or 25, wherein at least two of said units include an on-board microprocessor and wherein the random access memory in each of said two units has a first memory portion storing operating instructions and data for said on-board microprocessor and a second memory portion forming an onboard global memory accessible by at least the on-board microprocessor of the other of said two units via said bus .

27. A data processing system according to claim 24, wherein said synchronous exchange bus includes a plurality of bus identification lines, and said slot identification means includes first conductor means connected to said bus identification lines in a coded combination at each slot and second conductor means in each unit engageable with said first conductor means when said unit is plugged into said bus .

28. A data processing system according to claim 24, wherein said units include a general purpose processor, a microprocessor controlled memory controller means for data storage, and serial multiplexer means including a microprocessor, a plurality of I/O ports connected to said microprocessor via an I/O bus and a plurality of intelligent peripheral devices connected to respective I/O ports .

29. A data processing system according to claim 28, wherein a plurality of said units are serial multiplexer means .

30. A data processing system according to claim 28, wherein one of said units is a non-intelligent global memory device providing data storage apart from that provided in the random access memory of the other units .