WO1982001619A1 - Method of making a planar iii-v bipolar transistor by selective ion implantation and a device made therewith - Google Patents

Method of making a planar iii-v bipolar transistor by selective ion implantation and a device made therewith Download PDF

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Publication number
WO1982001619A1
WO1982001619A1 PCT/US1981/001394 US8101394W WO8201619A1 WO 1982001619 A1 WO1982001619 A1 WO 1982001619A1 US 8101394 W US8101394 W US 8101394W WO 8201619 A1 WO8201619 A1 WO 8201619A1
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region
substrate
mask
implanted
collector
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PCT/US1981/001394
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French (fr)
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Aircraft Co Hughes
Kavasseri V Vaidyanathan
Carl L Anderson
Robert A Jullens
Howard L Dunlap
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Aircraft Co Hughes
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H01L21/26553—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

Definitions

  • This invention relates to the formation of devices comprising at least two p-n junctions in III-V materials, employing sequential ion implantation through openings in masks of dense material. This invention also relates to
  • III-V bipolar transistors formed by sequential ion implantation into a substrate of III-V material, employing the foregoing process; in particular, this invention relates to III-V bipolar transistors having a planar configuration 2.
  • GaAs MESFET metal-semiconductor FET
  • CaAs bipolar junction and transistor devices to form functional GaAs integrated circuits (ICs) . Accordingly, emphasis is shifting back to bipolar transistors, in an effort to improve device properties.
  • An example of such a development is described in Vol. 16, Electronics Letters, pp. 637-638 (1980).
  • GaAs n-p-n bipolar transistors are fabricated by sequentially implanting beryllium and selenium ions into bulk n-type substrate material. Devices with mesa collectors exhibit a DC current gain h FE of up to 8 and a reverse bias leakage current of less than 10 nA.
  • the device may represent a breakthrough in GaAs bipolar transistors
  • the device is of mesa configuration, not planar, and thus suffers the disadvantages characteristic of mesa-type devices.
  • integration with GaAs FETS on the same substrate to form planar ICs cannot be done with the above approach.
  • the process for fabricating the device requires two anneals at different temperatures, the second anneal being done at 700°C, which is not adequate to anneal out implant-induced damage sufficiently to obtain good minority carrier properties in the base. This in turn requires use of an overly thin base region to achieve adequate current gain, with consequent poor saturation in the transistor.
  • III-V bipolar transistors require the formation of at least two p-n junctions and reproducible control of the distance between the two junctions, namely, the base-width. Such techniques have not heretofore been available for III-V bipolar transistors.
  • sequentially ion-implanted p-n junctions in III-V materials are provided.
  • the process for forming at least two p-n junctions in a III-V material includes:
  • the III-V material may be of a conductivity type opposite to that of the first implant. In such a case, two p-n junctions are formed.
  • employing a material either of the same conductivity as the first implant or semi-insulating would require a third implantation to be done, within the second implanted region, using a third heavy metal mask provided with appropriate openings.
  • more than two p-n junctions may be formed by additional implants within preceding implanted regions.
  • the sequential ion implantation process provided herein is especially useful for fabricating planar III-V bipolar transistors.
  • the bipolar transistor which comprises emitter, base and collector, is formed by a process which includes: (a) providing a substrate of III-V material;
  • the first region may be epitaxially deposited on the substrate, followed by formation of the passivating layer thereon,. as set forth above.
  • the passivating layer may be formed directly on the substrate, and the collector region formed in a portion of the substrate, employing a mask of dense material in conjunction with an ion implantation, such as described above.
  • planar III-V bipolar transistors may be fabricated.
  • planar bipolar transistors permit full integration of both bipolar and MESFET devices on one substrate.
  • FIG. 1 depicts, in cross-section, a portion of the bipolar transistor of the invention during one stage of processing
  • FIG. 2 depicts, in cross-section, the bipolar transistor of the invention at a subsequent stage in processing
  • FIG. 3 depicts, partly in perspective and partly in cross-section, a fabricated bipolar transistor of the invention
  • FIG. 4 depicts, in cross-section, a combination of a planar bipolar transistor of the invention and a MESFET on one substrate;
  • FIG. 5 on coordinates of current in amps and voltage in volts, depicts the current/voltage characteristics of one embodiment of the bipolar transistor of the invention, employing GaAs.
  • the planar bipolar transistor of the invention may comprise any III-V compound semiconductor, such as InP, or mixed compound semiconductor, such as (In,Ga)As or ( In,Ga) (As,P), having the requisite properties, such as high electron mobility.
  • III-V compound semiconductor such as InP
  • mixed compound semiconductor such as (In,Ga)As or ( In,Ga) (As,P)
  • the device described below is of n-p-n configuration.
  • the corresponding complementary p-n-p configuration is also contemplated within the scope of the invention, making suitable substitution of p-type for n-type and vice versa.
  • the sequential ion implantation process employing masks of dense material may also be employed to form other devices comprising at least two p-n junctions, such as certain junction gate charge coupled devices.
  • GaAs The high electron mobilities and wide bandgap of GaAs make it an attractive material for high speed, high temperature device applications.
  • Integrated circuits employing MESFET devices have been fabricated.
  • the speed, packing density and drive capability advantages associated with bipolar devices are attractive, and devices fabricated from GaAs are desirable. ln particular, if both bipolar and MESFET devices can be integrated into a planar IC process, the material properties of GaAs can be more fully exploited.
  • the implanted regions will range up to about 1 to 1.5 ⁇ m in depth (for ion-implanted collector).
  • use of a photoresist layer to mask against ion implantation requires a photoresist thickness of about 7 to 10 urn.
  • Such thick photoresist layers are not capable of high pattern resolution (i.e., line widths of about 1.5 urn and less).
  • the doping profile of implanted regions must be controlled to about 0.1 ⁇ m. Without such control, considerable overlap of n and p regions may occur, with concomitant poor device operation.
  • the planar GaAs bipolar transistor described herein may be formed in a variety of ways.
  • the base and emitter regions may be implanted into n-type epitaxial GaAs, which acts as the collector.
  • the epitaxial layer is supported either on a highly doped substrate of the same conductivity or on a semiinsulating substrate.
  • the individual devices can be isolated by ion bombardment in the regions between devices, using ions such as protons, deuterons, tritons, boron ions or oxygen ions.
  • a semi-insulating substrate alone is employed, and the collector, base and emitter regions are implanted therein. No isolation implant is required, and parasitic capacitance is reduced.
  • Implantations of base and emitter regions are performed using a thin layer of dense material deposited on the substrate to serve as an implant mask.
  • Selective p-type base regions are formed by ion implantation with an acceptor. Ion implantation with a donor is then done to form the n-type emitter region, again employing a thin mask of dense material.
  • the devices are annealed to electrically activate the impurities, following which a passivating dielectric layer is deposited on the surface of the epitaxial layer.
  • Ohmic contacts to the collector and emitter regions are formed with Au:Ge/Ni, while ohmic contact to the base region is made with Ag:Mn or Au:Zn.
  • the use of masks of dense materials permits ion implantation depths of 1 to 1.5 u ⁇ and high pattern resolution.
  • Materials of high density resulting from high average atomic number and high atomic density, can prevent the unwanted implantation of ions into the substrate using much thinner layers than would be required using photoresist. For example, a 2.0 ⁇ m thick layer of germanium will stop ions that would penetrate 1.5 ⁇ m into GaAs, while allowing an ample safety margin. Even thinner layers of gold, tungsten, tantalum or lead would be required. The use of such thin layers permits improved lithographic resolution.
  • the density of the mask material should be at least equal to, and preferably greater than, the density of the layer being implanted and may comprise an elemental metal or an alloy having the requisite properties.
  • Annealing to activate the impurities need only be done once, and at a high enough temperature to obtain good minority carrier properties. Further, the combination of the sequential ion implantation, the use of thin masks of dense material and the one-time anneal at the high temperature permit control over the implanted profiles to about 0.1 ⁇ m.
  • FIGS. 1-3 The device and process for making the device (not to scale) are more fully illustrated in FIGS. 1-3.
  • a substrate 10 here of n-type GaAs, which is a portion of a wafer having been sliced from a single crystal boule and appropriately processed.
  • the n-type GaAs substrate may be highly doped, say to about I0 18 cm -3 .
  • the highly doped substrate can also act as a collector, and the heavy doping makes forming ohmic contacts easier.
  • a semi-insulating substrate of GaAs may be employed. The serai-insulating substrate permits closer spacing of devices and reduces parasitic capacitance.
  • the doping level in the collector region is kept in this range in order to achieve a reasonable doping level in the base region and also achieve a high emitter injection efficiency.
  • the epitaxial layer is formed by conventional liquid phase epitaxial growth processes and forms no part of this invention.
  • the thickness of the epitaxial layer ranges from about 2 to 3 ⁇ m , s ince for a th ickness greater than about 4 ⁇ m, device isolation bombardment may pose problems.
  • a passivating layer 12 is formed on the semiconductor surface to a thickness of about 200 to 600 A. Less than 200 A results in patchy growth, while more than 600 A begins to impede the ion implantation processes used below.
  • the passivating layer also protects the ion-implanted semiconductor surface, which is highly reactive. Dielectric materials such as silicon nitride (Si 3 N 4 ), silicon oxynitride (Si ⁇ OyN z ) and silicon dioxide (SiO 2 ) may be employed. Preferably, Si 3 N 4 is employed, since it forms a cap against gallium diffusion during a subsequent annealing step.
  • the passivating layer is deposited by a low temperature plasma enhanced process.
  • the mask comprises any dense material, such as gold, silver, tungsten, tantalum, lead or palladium, which is capable of masking selected areas of the semiconductor from ion penetration during ion implantation, as described above.
  • the thickness of the mask is dictated by the density of the mask material and the energy and mass of the implanted ion.
  • the thickness of the silver masks employed in the fabrication of the bipolar transistor described herein ranges from about 3,000 to 5,000 ⁇ . Use of gold masks would require about the same thickness.
  • a film of aluminum Prior to deposition of silver, a film of aluminum (not shown) is evaporated on the surface of layer 12.
  • the use of gold as a metal mask employs a chromium film.
  • the metal film enhances adherence cf the silver or gold to the dielectric layer 12.
  • An opening 14 is then formed completely through a portion of the mask 13, such as by chemical etching or a photolithographic lift-off process.
  • a photoresist layer (not shown) is deposited on the passivating layer prior to depositing the mask and is exposed and processed to form openings therein. Following deposition of the mask, the remaining photoresis is dissolved, resulting in lift-off of metal at the appropriate areas to form, e.g., opening 14.
  • Acceptor ions such as beryllium or other Group II elements such as magnesium, cadmium and zinc are then implanted to form base region 15 in the epitaxial layer.
  • the base region is formed, to a depth of about 0.6 to 0.9 ⁇ m to form p-n junction 16.
  • the control of the base-width and consequently the location of the base/collector junction are extremely crucial to efficient operation of the device.
  • the mask 13 is then removed by chemical etching using appropriate etchants such as a mixture of phosphoric acid, ethylene glycol and water, and a new mask 17 of dense material is formed on layer 12 and is processed to form openings 18 and 19, using the process described above.
  • the collector forms a ring around the base and emitter regions.
  • a donor implant employing silicon, or other donors such as sulfur, tellurium or selenium, forms emitter region 20.
  • the emitter/base junction should lie between about 0.3 to 0.5 ⁇ m from the surface, thus resulting in a base-width between about 0.3 to 0.4 ⁇ m.
  • a second p-n junction 21 is thereby formed.
  • portions 22 of the surface of the collector are doped rather heavily through openings 19 by the donor implant used to form the emitter.
  • the emitter it is necessary for the emitter to be shallower than the base, with base-widths ranging from about 0.3 to 0.4 ⁇ m, and for the emitter to be completely surrounded by the base.
  • the wafer is annealed.
  • annealing is advantageously carried out at about 850°C for about 30 minutes. The temperature is dictated by a desire to anneal at as high a temperature as possible, without causing diffusion of implanted dopants. The time of annealing is not so critical.
  • passivating dielectric layer 23 is deposited. It is convenient to strip off passivating layer 12 and to clean the semiconductor surface before depositing passivating layer 23. However, layer 12 could be left on and layer 23 deposited directly over it. Conveniently, passivating layer 23 is silicon oxynitride, Si ⁇ 0 N 2 . Other dielectrics such as Si 3 4 or Si0 2 may also he employed. The passivating layer is conveniently deposited by a low temperature plasma enhanced process or by other low temperature process such as by photochemical deposition.
  • Ohmic contact 24 is made to the base region employing Ag:Mn or Au:Zn, while ohmic contacts 25 and 26 to the emitter and collector regions, respectively, are made using Au:Ce/Ni.
  • Ohmic contacts employing other materials to the p and n regions, may, of course, be alternatively used. Formation of these ohmic contacts is conventional and does not form a part of this invention. Electrical connection to external circuitry is then done, employing well-known procedures.
  • At least one emitter region is formed in each base region. More than one emitter region may be formed in each base region, with the ohmic contacts to base and emitter regions forming an interdigitated structure, which is useful for fabricating high frequency devices.
  • the device technology is a planar one, and individual devices can be isolated from each other by proton or other appropriate ion bombardment, employing conventional process technology. The foregoing process has been directed to epitaxial layers formed on highly doped substrates. In such cases, ion bombardment is employed to isolate the devices.
  • a semi-insulating substrate such as Cr-doped GaAs, may be employed.
  • a collector region is formed in the substrate by ion implantation of donor species through a mask of dense material, employing the same procedures described above in connection with ion implantation to form base and emitter - regions. These regions are then formed as above, and the device is processed as above, except that ion bombardment for device isolation is not necessary, due to use of the semi-insulating substrate.
  • FIG. 4 shows a fabricated planar bipolar transistor 40 formed in a semi-insulating sub- strate 10'.
  • An ion-implanted, region 11' serves as the collector; the remaining numbers reference like-numbered parts in FIG. 3.
  • two p-n junctions, 16 and 21, are formed by sequential ion implantation.
  • An n-type collector may alternatively also be implanted into a p-type substrate, if desired. Again, the ion implantation in conjunction with a patterned mask of dense material is employed.
  • planar process described herein permits full integration of bipolar transistors with planar FET structures, such as MESFETs, MISFETs (metal-insulatorsemiconductor FETs) and JFETs (junction FETs).
  • planar process disclosed herein permits integration of bipolar devices with the MESFET technology presently available to fabricate high speed signal processing circuits such as microwave analog-to-digital converters.
  • the planar bipolar devices of the invention are particularly useful as elements used for bias current cancellation in differential amplifiers which, are vital to the operation of analog-to-digital converters.
  • FIG. 4 in cross-section depicts a combination of a bipolar transistor and a MESFET device on one substrate.
  • the emitter, base and collector are as described above, while the MESFET device 41 comprises a conventional source contact 42 and drain contact 43 formed over ion-implanted regions 45 and 46 having n-type conductivity; gate contact 44 is formed over channel 47, which connects the two regions.
  • a semi-insulating substrate 10' is employed.
  • a device substantially as shown in FIG. 3 was constructed.
  • An epitaxial layer of n-GaAs about 3 ⁇ m thick and doped to about 10 16 cm -3 was formed on one surface of an n + -GaAs substrate, about 250 ⁇ m thick, doped to about i0 18 cm -3 .
  • a passivating film of Si 3 N 4 o about 400 A thick was formed on the epitaxial layer by plasma enhanced deposition process, followed by deposition and patterning of photoresist. Next, an aluminum film about 400 A thick and a silver mask about 4,000 A. thick were deposited.
  • Portions of the silver mask were removed by photolithographic lift-off techniques and Be ions were implanted at multiple energies into a portion of the epitaxial layer to form a p-type region uniformly doped to about 5 x 10 l6 cm -3 to a depth of about 0.9 ⁇ m.
  • the metal mask was removed and a second silver over aluminum mask, again about 4,000 ⁇ thick, was formed on a new patterned photoresist formed on the Si 3 N 4 film.
  • Portions of the silver mask were removed by lift-off, and Si ions were implanted at multiple energies into a portion of the previously Be-implanted region to form an n + -type region uniformly doped to about 2 x 10 18 cm -3 to a depth of about 0.4 to 0.5 ⁇ m. Si ions were also implanted at the same time into portions of the epitaxial layer to form n + -type regions therein.
  • the silver mask was removed by chemical etching. A layer of Si0 2 about 1,500 ⁇ thick was deposited on the Si 3 N 4 layer and on the backside of the substrate. To remove radiation damage and activate the implanted impurities, the wafer was annealed at 850°C for 30 min.
  • the SiO 2 /Si 3 N 4 layers were removed and a passivating layer of Si ⁇ 0 y N z was formed on the epitaxial layer by plasma enhanced deposition process. Appropriate openings were made in the passivating layer by etching in buffered hydrofluoric acid, and alloyed ohmic contacts were made, employing Ag:Mn for the p-type regions and AutGe/Ni for the n-type regions.
  • FIG. 5 presents the current/voltage (I/V) characteristics of the bipolar transistor.
  • the vertical (current) scale is in 0.5 mA/division; the horizontal (voltage) scale is. in 1 V/division; the base current is 0.1 mA/step.
  • Typical devices exhibited breakdown voltages in excess of 40 V across the collector-base junction and common emitter current gains of about 6. Gains as high as 16 were observed.

Abstract

A planar, bipolar transistor is fabricated by sequential selective area ion-implantation in III-V material, such as GaAs, to form two p-n junctions (16, 21). In an n-p-n device, an acceptor, e.g., Be, is implanted into an n-type collector region (11) supported by a substrate (10) to create a p-type base layer (15). The collector region may be epitaxially deposited on a highly doped substrate of the same conductivity type or, alternatively, ion-implanted in a region of a semi-insulating substrate. A donor implant, e.g., Si, is implanted within the base region to form at least one emitter region (20). The radiation damage is annealed out and the device is passivated, e.g., by a plasma-deposited silicon oxynitride dielectric layer (23), and appropriate ohmic contacts (24, 25, 26) to the emitter, base and collector regions are formed. The selective implant process uses evaporated masks of dense material and results in a truly planar device, which may be integrated on the same substrate with MESFET devices.

Description

METHOD OF MAKING A PLANAR III-V BIPOLAR TRANSISTOR BY SELECTIVE ION IMPLANTATION AND A DEVICE MADE THEREWITH
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates to the formation of devices comprising at least two p-n junctions in III-V materials, employing sequential ion implantation through openings in masks of dense material. This invention also relates to
III-V bipolar transistors formed by sequential ion implantation into a substrate of III-V material, employing the foregoing process; in particular, this invention relates to III-V bipolar transistors having a planar configuration 2. Description of the Prior Art
Early work in CaAs transistors focused on bipolar configurations, which have base, emitter and collector regions. However, due to early discouraging experimental results and poor reproducibility, emphasis shifted to GaAs field effect transistors (FETs), which have source, gate and drain regions. The CaAs FET technology has matured; such devices have now advanced to a level where they exhibit useful microwave performance at frequencies above 2C GHz. Success in this maturing technology has been due, in part, to ion implantation.
Attempts are under way to integrate the GaAs MESFET (metal-semiconductor FET) technology with CaAs bipolar junction and transistor devices to form functional GaAs integrated circuits (ICs) . Accordingly, emphasis is shifting back to bipolar transistors, in an effort to improve device properties. An example of such a development is described in Vol. 16, Electronics Letters, pp. 637-638 (1980). As disclosed therein, GaAs n-p-n bipolar transistors are fabricated by sequentially implanting beryllium and selenium ions into bulk n-type substrate material. Devices with mesa collectors exhibit a DC current gain hFE of up to 8 and a reverse bias leakage current of less than 10 nA. While the device may represent a breakthrough in GaAs bipolar transistors, it should be noted that the device is of mesa configuration, not planar, and thus suffers the disadvantages characteristic of mesa-type devices. Further, integration with GaAs FETS on the same substrate to form planar ICs cannot be done with the above approach. Finally, the process for fabricating the device requires two anneals at different temperatures, the second anneal being done at 700°C, which is not adequate to anneal out implant-induced damage sufficiently to obtain good minority carrier properties in the base. This in turn requires use of an overly thin base region to achieve adequate current gain, with consequent poor saturation in the transistor.
Fabrication of planar III-V bipolar transistors requires the formation of at least two p-n junctions and reproducible control of the distance between the two junctions, namely, the base-width. Such techniques have not heretofore been available for III-V bipolar transistors.
SUMMARY OF THE INVENTION In accordance with the invention, sequentially ion-implanted p-n junctions in III-V materials are provided. The process for forming at least two p-n junctions in a III-V material includes:
(a) forming a passivating layer to protect the III-V material; (b) forming a first mask of dense material with appropriate openings therein;
(c) implanting through the openings ions of a first species to form a first implanted region having a first conductivity type;
(d) removing the first implant mask;
(e) forming a second mask of dense material with appropriate openings therein;
(f) implanting through the openings ions of a second species to form a second implanted region within the first implanted region, the second implanted region having a conductivity type opposite to that of the first implanted region; and
(g) removing the second implant mask. The III-V material may be of a conductivity type opposite to that of the first implant. In such a case, two p-n junctions are formed. Alternatively, employing a material either of the same conductivity as the first implant or semi-insulating would require a third implantation to be done, within the second implanted region, using a third heavy metal mask provided with appropriate openings. Of course, more than two p-n junctions may be formed by additional implants within preceding implanted regions. The sequential ion implantation process provided herein is especially useful for fabricating planar III-V bipolar transistors. The bipolar transistor, which comprises emitter, base and collector, is formed by a process which includes: (a) providing a substrate of III-V material;
(b) forming on one portion of the substrate a first region, a portion of which comprises the collector, having a first conductivity type;
(c) forming a passivating layer on at least the first regio ; (d) forming in at least one portion of the first region at least one second region, a portion of which comprises the base, said second region being formed by implanting an ionic species through appropriate openings in a first mask of dense material supported on the passivating layer to provide the second region with a conductivity type opposite to that of the first region;
(e) forming in at least one portion of the second region at least one third region, a portion of which comprises the emitter, said third region being formed by implanting an ionic species through appropriate openings in a second mask of dense material supported on the passivating layer to provide the third region with a conductivity type the same as that of the first region; (f) annealing to activate the implanted ions; and
(g) forming ohmic contacts to the emitter, base and collector regions.
The first region may be epitaxially deposited on the substrate, followed by formation of the passivating layer thereon,. as set forth above. Alternatively, the passivating layer may be formed directly on the substrate, and the collector region formed in a portion of the substrate, employing a mask of dense material in conjunction with an ion implantation, such as described above.
The masks of dense material permit ion implantation depths of 1 to 1-5 μm and high pattern resolution (e.g., 1.5 urn linewidths and less). Annealing to activate the impurities need only be done once and at a high enough temperature to obtain good minority carrier properties. Use of at least two sequential ion implantations permits formation of planar structures not heretofore successfully and reproducibiy realized. In particular, planar III-V bipolar transistors may be fabricated. Advantageously, such planar bipolar transistors permit full integration of both bipolar and MESFET devices on one substrate.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 depicts, in cross-section, a portion of the bipolar transistor of the invention during one stage of processing;
FIG. 2 depicts, in cross-section, the bipolar transistor of the invention at a subsequent stage in processing;
FIG. 3 depicts, partly in perspective and partly in cross-section, a fabricated bipolar transistor of the invention;
FIG. 4 depicts, in cross-section, a combination of a planar bipolar transistor of the invention and a MESFET on one substrate; and
FIG. 5, on coordinates of current in amps and voltage in volts, depicts the current/voltage characteristics of one embodiment of the bipolar transistor of the invention, employing GaAs.
DETAILED DESCRIPTION OF THE INVENTION The description which follows below is given in terms of a particular III-V material, GaAs. However, it will be understood that the planar bipolar transistor of the invention may comprise any III-V compound semiconductor, such as InP, or mixed compound semiconductor, such as (In,Ga)As or ( In,Ga) (As,P), having the requisite properties, such as high electron mobility. Further, the device described below is of n-p-n configuration. However, the corresponding complementary p-n-p configuration is also contemplated within the scope of the invention, making suitable substitution of p-type for n-type and vice versa. Further, the sequential ion implantation process employing masks of dense material may also be employed to form other devices comprising at least two p-n junctions, such as certain junction gate charge coupled devices.
The high electron mobilities and wide bandgap of GaAs make it an attractive material for high speed, high temperature device applications. Integrated circuits employing MESFET devices have been fabricated. The speed, packing density and drive capability advantages associated with bipolar devices are attractive, and devices fabricated from GaAs are desirable. ln particular, if both bipolar and MESFET devices can be integrated into a planar IC process, the material properties of GaAs can be more fully exploited.
In order to apply ion implantation to the fabrication of GaAs bipolar transistors, however, the implanted regions will range up to about 1 to 1.5 μm in depth (for ion-implanted collector). use of a photoresist layer to mask against ion implantation requires a photoresist thickness of about 7 to 10 urn. Such thick photoresist layers are not capable of high pattern resolution (i.e., line widths of about 1.5 urn and less). Further, the doping profile of implanted regions must be controlled to about 0.1 μm. Without such control, considerable overlap of n and p regions may occur, with concomitant poor device operation.
The planar GaAs bipolar transistor described herein may be formed in a variety of ways. For example, the base and emitter regions may be implanted into n-type epitaxial GaAs, which acts as the collector. In such a case, the epitaxial layer is supported either on a highly doped substrate of the same conductivity or on a semiinsulating substrate. Following fabrication of an array of bipolar transistors in epitaxial layers, the individual devices can be isolated by ion bombardment in the regions between devices, using ions such as protons, deuterons, tritons, boron ions or oxygen ions.
Alternatively, a semi-insulating substrate alone is employed, and the collector, base and emitter regions are implanted therein. No isolation implant is required, and parasitic capacitance is reduced.
In either case, sequential ion implantation is performed to form the two p-n junctions.
Implantations of base and emitter regions (and, where appropriate, collector regions) are performed using a thin layer of dense material deposited on the substrate to serve as an implant mask. Selective p-type base regions are formed by ion implantation with an acceptor. Ion implantation with a donor is then done to form the n-type emitter region, again employing a thin mask of dense material. The devices are annealed to electrically activate the impurities, following which a passivating dielectric layer is deposited on the surface of the epitaxial layer. Ohmic contacts to the collector and emitter regions are formed with Au:Ge/Ni, while ohmic contact to the base region is made with Ag:Mn or Au:Zn.
The use of masks of dense materials permits ion implantation depths of 1 to 1.5 uπ and high pattern resolution. Materials of high density, resulting from high average atomic number and high atomic density, can prevent the unwanted implantation of ions into the substrate using much thinner layers than would be required using photoresist. For example, a 2.0 μm thick layer of germanium will stop ions that would penetrate 1.5 μm into GaAs, while allowing an ample safety margin. Even thinner layers of gold, tungsten, tantalum or lead would be required. The use of such thin layers permits improved lithographic resolution. The density of the mask material should be at least equal to, and preferably greater than, the density of the layer being implanted and may comprise an elemental metal or an alloy having the requisite properties.
Annealing to activate the impurities need only be done once, and at a high enough temperature to obtain good minority carrier properties. Further, the combination of the sequential ion implantation, the use of thin masks of dense material and the one-time anneal at the high temperature permit control over the implanted profiles to about 0.1 μm.
The device and process for making the device (not to scale) are more fully illustrated in FIGS. 1-3. In FIG. 1 is shown a substrate 10, here of n-type GaAs, which is a portion of a wafer having been sliced from a single crystal boule and appropriately processed. The n-type GaAs substrate may be highly doped, say to about I018 cm-3. The highly doped substrate can also act as a collector, and the heavy doping makes forming ohmic contacts easier. Alternatively, as described below, a semi-insulating substrate of GaAs may be employed. The serai-insulating substrate permits closer spacing of devices and reduces parasitic capacitance.
An epitaxial layer 11, again of n-type GaAs, is formed on one surface of the substrate and is of the same conductivity type as the substrate, having a carrier concentration of about 5 x 1015 to 3 x 10l6 cm-3. The doping level in the collector region is kept in this range in order to achieve a reasonable doping level in the base region and also achieve a high emitter injection efficiency. The epitaxial layer is formed by conventional liquid phase epitaxial growth processes and forms no part of this invention. The thickness of the epitaxial layer ranges from about 2 to 3 μm , s ince for a th ickness greater than about 4 μm, device isolation bombardment may pose problems.
In order to perform selective area ion implantation, a passivating layer 12 is formed on the semiconductor surface to a thickness of about 200 to 600 A. Less than 200 A results in patchy growth, while more than 600 A begins to impede the ion implantation processes used below. The passivating layer also protects the ion-implanted semiconductor surface, which is highly reactive. Dielectric materials such as silicon nitride (Si3N4), silicon oxynitride (SiχOyNz) and silicon dioxide (SiO2) may be employed. Preferably, Si3N4 is employed, since it forms a cap against gallium diffusion during a subsequent annealing step. Advantageously, the passivating layer is deposited by a low temperature plasma enhanced process.
A mask 13 of dense material is then formed over layer 12. Advantageously, the mask comprises any dense material, such as gold, silver, tungsten, tantalum, lead or palladium, which is capable of masking selected areas of the semiconductor from ion penetration during ion implantation, as described above. The thickness of the mask is dictated by the density of the mask material and the energy and mass of the implanted ion. For example, the thickness of the silver masks employed in the fabrication of the bipolar transistor described herein ranges from about 3,000 to 5,000 Å. Use of gold masks would require about the same thickness.
Prior to deposition of silver, a film of aluminum (not shown) is evaporated on the surface of layer 12. The use of gold as a metal mask employs a chromium film. The metal film enhances adherence cf the silver or gold to the dielectric layer 12. An opening 14 is then formed completely through a portion of the mask 13, such as by chemical etching or a photolithographic lift-off process. In the lift-off process, a photoresist layer (not shown) is deposited on the passivating layer prior to depositing the mask and is exposed and processed to form openings therein. Following deposition of the mask, the remaining photoresis is dissolved, resulting in lift-off of metal at the appropriate areas to form, e.g., opening 14. Acceptor ions, such as beryllium or other Group II elements such as magnesium, cadmium and zinc are then implanted to form base region 15 in the epitaxial layer. The base region is formed, to a depth of about 0.6 to 0.9 μm to form p-n junction 16. The control of the base-width and consequently the location of the base/collector junction are extremely crucial to efficient operation of the device.
The mask 13 is then removed by chemical etching using appropriate etchants such as a mixture of phosphoric acid, ethylene glycol and water, and a new mask 17 of dense material is formed on layer 12 and is processed to form openings 18 and 19, using the process described above. As is typical, the collector forms a ring around the base and emitter regions. A donor implant employing silicon, or other donors such as sulfur, tellurium or selenium, forms emitter region 20. The emitter/base junction should lie between about 0.3 to 0.5 μm from the surface, thus resulting in a base-width between about 0.3 to 0.4 μm. A second p-n junction 21 is thereby formed. To facilitate making ohmic contacts, portions 22 of the surface of the collector are doped rather heavily through openings 19 by the donor implant used to form the emitter. For transistor action, it is necessary for the emitter to be shallower than the base, with base-widths ranging from about 0.3 to 0.4 μm, and for the emitter to be completely surrounded by the base. To remove the radiation damage and to activate the implanted impurities by restoring minority carrier lifetime, the wafer is annealed. For GaAs, annealing is advantageously carried out at about 850°C for about 30 minutes. The temperature is dictated by a desire to anneal at as high a temperature as possible, without causing diffusion of implanted dopants. The time of annealing is not so critical. Following the anneal, a passivating dielectric layer 23 is deposited. It is convenient to strip off passivating layer 12 and to clean the semiconductor surface before depositing passivating layer 23. However, layer 12 could be left on and layer 23 deposited directly over it. Conveniently, passivating layer 23 is silicon oxynitride, Siχ0 N2. Other dielectrics such as Si3 4 or Si02 may also he employed. The passivating layer is conveniently deposited by a low temperature plasma enhanced process or by other low temperature process such as by photochemical deposition.
Appropriate openings are then made in the dielectric layer 23 by chemical etching through which ohmic contacts to the n and p regions of the device are. made, as shown in FIG. 3.
Ohmic contact 24 is made to the base region employing Ag:Mn or Au:Zn, while ohmic contacts 25 and 26 to the emitter and collector regions, respectively, are made using Au:Ce/Ni. Ohmic contacts employing other materials to the p and n regions, may, of course, be alternatively used. Formation of these ohmic contacts is conventional and does not form a part of this invention. Electrical connection to external circuitry is then done, employing well-known procedures.
At least one emitter region is formed in each base region. More than one emitter region may be formed in each base region, with the ohmic contacts to base and emitter regions forming an interdigitated structure, which is useful for fabricating high frequency devices. The device technology is a planar one, and individual devices can be isolated from each other by proton or other appropriate ion bombardment, employing conventional process technology. The foregoing process has been directed to epitaxial layers formed on highly doped substrates. In such cases, ion bombardment is employed to isolate the devices. In an alternate embodiment, a semi-insulating substrate, such as Cr-doped GaAs, may be employed. A collector region is formed in the substrate by ion implantation of donor species through a mask of dense material, employing the same procedures described above in connection with ion implantation to form base and emitter - regions. These regions are then formed as above, and the device is processed as above, except that ion bombardment for device isolation is not necessary, due to use of the semi-insulating substrate. Such a device is depicted in FIG. 4, which shows a fabricated planar bipolar transistor 40 formed in a semi-insulating sub- strate 10'. An ion-implanted, region 11' serves as the collector; the remaining numbers reference like-numbered parts in FIG. 3. Again, two p-n junctions, 16 and 21, are formed by sequential ion implantation.
An n-type collector may alternatively also be implanted into a p-type substrate, if desired. Again, the ion implantation in conjunction with a patterned mask of dense material is employed.
The planar process described herein permits full integration of bipolar transistors with planar FET structures, such as MESFETs, MISFETs (metal-insulatorsemiconductor FETs) and JFETs (junction FETs). In particular, the planar process disclosed herein permits integration of bipolar devices with the MESFET technology presently available to fabricate high speed signal processing circuits such as microwave analog-to-digital converters. The planar bipolar devices of the invention are particularly useful as elements used for bias current cancellation in differential amplifiers which, are vital to the operation of analog-to-digital converters. FIG. 4, in cross-section, depicts a combination of a bipolar transistor and a MESFET device on one substrate. For the bipolar device 40, the emitter, base and collector are as described above, while the MESFET device 41 comprises a conventional source contact 42 and drain contact 43 formed over ion-implanted regions 45 and 46 having n-type conductivity; gate contact 44 is formed over channel 47, which connects the two regions. To achieve the required device isolation and to reduce parasitic capacitance, a semi-insulating substrate 10' is employed. EXAMPLE
A device substantially as shown in FIG. 3 was constructed. An epitaxial layer of n-GaAs about 3 μm thick and doped to about 1016 cm-3 was formed on one surface of an n+-GaAs substrate, about 250 μm thick, doped to about i018 cm-3. A passivating film of Si3N4 o about 400 A thick was formed on the epitaxial layer by plasma enhanced deposition process, followed by deposition and patterning of photoresist. Next, an aluminum film about 400 A thick and a silver mask about 4,000 A. thick were deposited. Portions of the silver mask were removed by photolithographic lift-off techniques and Be ions were implanted at multiple energies into a portion of the epitaxial layer to form a p-type region uniformly doped to about 5 x 10l6 cm-3 to a depth of about 0.9 μm. The metal mask was removed and a second silver over aluminum mask, again about 4,000 Å thick, was formed on a new patterned photoresist formed on the Si3N4 film. Portions of the silver mask were removed by lift-off, and Si ions were implanted at multiple energies into a portion of the previously Be-implanted region to form an n+-type region uniformly doped to about 2 x 1018 cm-3 to a depth of about 0.4 to 0.5 μm. Si ions were also implanted at the same time into portions of the epitaxial layer to form n+-type regions therein. The silver mask was removed by chemical etching. A layer of Si02 about 1,500 Á thick was deposited on the Si3N4 layer and on the backside of the substrate. To remove radiation damage and activate the implanted impurities, the wafer was annealed at 850°C for 30 min. The SiO2/Si3N4 layers were removed and a passivating layer of Siχ0yNz was formed on the epitaxial layer by plasma enhanced deposition process. Appropriate openings were made in the passivating layer by etching in buffered hydrofluoric acid, and alloyed ohmic contacts were made, employing Ag:Mn for the p-type regions and AutGe/Ni for the n-type regions.
The epitaxial layer served as the collector through the implanted n+-type regions; the p-type region was the base and the n+-type region therein was the emitter. Completed devices were tested using a curve tracer. FIG. 5 presents the current/voltage (I/V) characteristics of the bipolar transistor. The vertical (current) scale is in 0.5 mA/division; the horizontal (voltage) scale is. in 1 V/division; the base current is 0.1 mA/step. Typical devices exhibited breakdown voltages in excess of 40 V across the collector-base junction and common emitter current gains of about 6. Gains as high as 16 were observed.

Claims

CLAIMSWhat is Claimed is:
1. A sequential process for forming at least two p-n junctions in III-V materials which includes:
(a) providing a substrate of III-V material of a given conductivity type; (b) forming on a surface of said substrate a passivating film to protect said III— V material;
(c) forming a first mask of dense material on said passivating layer with appropriate openings therein;
(d) implanting through said openings ions of a first species to form a first implanted region having a first conductivity type;
(e) removing said first mask;
(f) forming a second mask of dense material on said passivating layer with appropriate openings therein; (g) implanting through said openings ions of a second species to form a second implanted region within said first implanted region, said second implanted region having a conductivity type opposite to that of said first implanted region; and (h) removing said second mask.
2. The process of Claim 1 in which said first conductivity type of said first implanted region is opposite to that of said substrate.
3. The process of Claim 1 in which said substrate is of the same conductivity type as said first implanted region or is semi-insulating, said process further comprising after removal of said second metal mask: (i) forming a third mask of dense material on said passivating layer with appropriate openings therein; (j) implanting through said openings ions of a third species to form a third ion-implanted region within said second ion-implanted reσion having a conductivity type the same as that of said first implanted region; and
(k) removing said third mask.
4. The process of Claims 1 or 3 in which a photoresist layer is formed on said passivating layer and patterned prior to forming each of said masks of dense material and is removed subsequent to removing each of said masks.
5. The process of Claim 1 in which said masks of dense material comprise a material having a density at least that of the material being ion implanted.
6. The process of Claim 5 in which said mask of dense material consists essentially of an element selected from the group consisting of gold, silver, tungsten, tantalum, lead and palladium.
7. The process of Claim 6 in which a metal coating is deposited prior to depositing said mask of dense material.
8. The process of Claim 7 in which said metal coating is chromium and said mask is gold.
9. The process of Claim 7 in which said metal coating is aluminum and said mask is silver.
10. The process of Claim 1 in which said III-V material consists essentially of GaAs.
.
11. The process of Claim 1 in which said passivating film consists essentially of a material selected from the group consisting of silicon nitride, silicon oxynitride and silicon dioxide.
12. The process of Claim 11 in which said passivating film consists essentially of Si3N4.
13. The process of Claim 1 in which said passivating film ranges from about 2C0 to 600 Å in thickness.
14. The process of Claim 13 in which said passivating film is about 400 Å thick.
15. A process for forming a planar III-V bipolar transistor comprising an emitter, base and collector, said process including:
(a) providing a substrate of III-V material; (b) forming on one portion of said substrate a first region, a portion of which comprises said collector, having a first conductivity type;
(c) forming a passivating layer on at least said first region; (d) forming in at least one portion of said first region at least one second region, a portion of which comprises said base, said second region being formed by implanting an ionic species through appropriate openings in a first mask of dense material supported on the passivating layer to provide said second region with a conductivity type opposite to that of said first region;
(e) forming in at least one portion of said second region at least one third region, a portion of which comprises said emitter, said third region being formed by implanting an ionic species through appropriate openings in a second mask of dense material supported on said passivating layer to provide said third region with a conductivity type the same as that of said first region;
(f) annealing to activate said implanted ions; and
(g) forming ohmic contacts to said emitter, base and collector regions.
16. The process of Claim 15 in which said substrate is semi-insulating.
17. The process of Claim 16 in which said passivatin layer is formed on said substrate and said first region is formed by implanting into a portion of said substrate an ionic species through appropriate openings in a mask of dense material to provide said first region with said first conductivity type.
18. The process of Claim 17 comprising:
(a) providing a substrate of semi-insulating GaAs;
(b) forming a first passivating layer of silicon nitride on at least a portion of said substrate;
(c) implanting ions of a donor species in at least one portion of said substrate through appropriate openings in a first mask of dense material supported on said first passivating layer to form at least one n-type collector region;
(d) implanting ions of an acceptor species in a portion of said collector region through appropriate openings in a second mask of dense material supported on said first passivating layer to form a p-type base region;
(e) implanting ions of a donor species in at least one portion of said base region through appropriate openings in a third mask of dense material supported on said first passivating layer to form at least one n+-type emitter region;
(f) annealing at about 850°C to activate said implanted ions;
(g) removing said first passivating layer;
(h) forming a second passivating layer of silico oxynitride on said substrate; and
(i) forming ohmic contacts of Ag:Mn or Au:Zn to said base region and Au:Ge/Ni to said collector and said emitter regions.
19. The process of Claim 15 in which said substrateis highly doped.
20. The process of Claim 19 in which said first region is formed by epitaxially depositing a layer of III-V material of the same conductivity type as said substrate and said passivating layer is formed thereon.
21. The process of Claim 20 comprising:
(a) providing a substrate of n+-GaAs;
(b) forming an epitaxial layer of GaAs on one surface of said substrate; (c) forming a first passivating layer of silicon nitride on said epitaxial layer;
(d) implanting ions of an acceptor species in a portion of said epitaxial layer through appropriate openings of a first mask of dense material supported on said first passivating layer to form a p-type base region;
(e) implanting ions of a donor species in at least one portion of said base region through appropriate openings in a second mask of dense material supported on said first passivating layer to form at least one an n+- type emitter region;
(f) annealing at about 850°C to activate said implanted ions;
(g) removing said first passivating layer; (h) forming a second passivating layer of silicon oxynitride on the surface of said epitaxial layer; and
(i) forming ohmic contacts of Ag:Mn or Au:Zn to said base region and Au:Ge/Ni to said collector and said emitter regions.
22. The process of Claim 21 in which said epitaxial layer of GaAs ranges from about 2 to 3 μm.
23. The process of Claims 18 or 21 in which said acceptor species is one selected from the group consisting of beryllium, magnesium, cadmium and zinc.
24. The process of Claims 18 or 21 in which said donnor species is one selected from the group consisting of silicon, sulfur, tellurium and selenium.
25. The process of Claims 18 or 21 in which said masks of dense material consist essentially of an element selected from the group consisting of gold, silver, tungsten, tantalum, lead and palladium.
26. The process of Claim 25 in which a metal coating is deposited prior to depositing said masks of dense material.
27. The process of Claim 26 in which said metal coating is chromium and said mask is gold.
28. The process of Claim 26 in which said metal coating is aluminum and said mask is silver.
29. Product formed by the process of Claim 15.
30. In combination, at least one planar, bipolar transistor of III-V material, said bipolar transistor formed by sequential ion implantation through appropriate openings in masks of dense material to form two p-n junctions, and at least one planar, field effect transistor of III-V material.
' 31. The combination of Claim 30 in which said III-V material consists essentially of gallium arsenide.
32. A planar III-V bipolar transistor comprising emitter, base and collector, said transistor comprising:
(a) a substrate of III-V material;
(b) a region of III-V material of a first conductivity type supported by said substrate, at least a portion of which region forms said collector region, said collector region having formed therein at least one first ion-implanted region of a species providing a region of conductivity type opposite to that of said collector region to form said base region, said first ion-implanted region having formed in at least one portion therein second ion-implanted region of a species providing a region of conductivity type the same as that of said collector region and completely surrounded by said base region to form at least one emitter region; (c) a passivating layer on at least the surface of said collector region; and
(d) ohmic contacts formed through sa id passivating layer to said emitter, said base and said collector regions .
33. The bipolar transistor of Claim 32 comprising:
(a) a substrate of semi-insulating GaAs;
(b) at least one ion-implanted region of an acceptor species providing at least one collector region of n-type conductivity formed in said substrate;
(c) an ion-implanted region of a donor species providing a base region of p-type conductivity formed in a portion of said collector region;
(d) at least one ion-implanted region of an. acceptor species providing at least one emitter region of n+-type conductivity formed at least one portion of said base region;
(e) a passivating layer of silicon oxy- nitride on the surface of said substrate; and (f) ohmic contacts of Ag:Mn or Au:Zn to said base region and AutGe/Ni formed to said collector and emitter regions.
34. The bipolar transistor of Claim 32 comprising:
(a) a substrate of n÷-type GaAs;
(b) an epitaxial layer of n-type GaAs forming a collector region, said epitaxial layer having formed therein at least one first ion-implanted region of a donor species providing a base region of p-type conductivity, said base region having formed in at least one portion therein a second ion-implanted region of an acceptor species providing at least one emitter region of n+-type conductivity and completely surrounded by said base region; (c) a passivating layer of silicon oxynitride on the surface of said epitaxial layer; and
(d) ohmic contacts of Ag:Mn or Au:Zn formed to said base region and Au:Ge/Ni formed to said collector and emitter regions.
35. The bipolar transistor of Claim 34 in which the thickness of said epitaxial layer of GaAs ranges from about 2 to 3 μm.
36. The bipolar transistor of Claims 33 or 34 in which said acceptor species is one selected from the group consisting of beryllium, magnesium, cadmium and zinc.
37. The bipolar transistor of Claims 33 or 34 in which said donor species is one selected from the group consisting of silicon, sulfur, tellurium and selenium.
PCT/US1981/001394 1980-10-28 1981-10-15 Method of making a planar iii-v bipolar transistor by selective ion implantation and a device made therewith WO1982001619A1 (en)

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US9478424B2 (en) 2014-09-26 2016-10-25 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for fabricating an improved GAN-based semiconductor layer
US9496348B2 (en) 2014-09-26 2016-11-15 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for doping a GaN-base semiconductor
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See also references of EP0063139A4 *
Solid State Electronics, 15, 1972, NUESE et al, "GaAS Vapor Grown Bipolar Transistors", p. 81 *
Solid State Electronics, 18, 1975, JAROS et al, "An Understanding of Ohmic Contact Formation with Ge Doping of n-GaAs", p. 1029 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0260473A1 (en) * 1986-09-08 1988-03-23 International Business Machines Corporation Method of forming silicon oxynitride films on silicon substrates
US4945394A (en) * 1987-10-26 1990-07-31 North Carolina State University Bipolar junction transistor on silicon carbide
US5389552A (en) * 1993-01-29 1995-02-14 National Semiconductor Corporation Transistors having bases with different shape top surfaces
EP3001447A1 (en) * 2014-09-26 2016-03-30 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for activating dopants in a gan semiconductor layer by consecutive implantations and heat treatments
FR3026555A1 (en) * 2014-09-26 2016-04-01 Commissariat Energie Atomique METHOD FOR ACTIVATING DOPANTS IN A GAN SEMICONDUCTOR LAYER THROUGH IMPLANTATIONS AND SUCCESSIVE THERMAL TREATMENTS
US9478424B2 (en) 2014-09-26 2016-10-25 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for fabricating an improved GAN-based semiconductor layer
US9496348B2 (en) 2014-09-26 2016-11-15 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for doping a GaN-base semiconductor
US9514962B2 (en) 2014-09-26 2016-12-06 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for performing activation of dopants in a GaN-base semiconductor layer
US9536741B2 (en) 2014-09-26 2017-01-03 Commissariat à l'Energie Atomique et aux Energies Alternatives Method for performing activation of dopants in a GaN-base semiconductor layer by successive implantations and heat treatments
CN112071904A (en) * 2020-08-11 2020-12-11 西安理工大学 High-voltage avalanche transistor
CN112071904B (en) * 2020-08-11 2024-01-30 陕西炬脉瑞丰科技有限公司 High-voltage avalanche transistor

Also Published As

Publication number Publication date
EP0063139A1 (en) 1982-10-27
JPS57501656A (en) 1982-09-09
EP0063139A4 (en) 1984-02-07

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