WO1980001526A1

WO1980001526A1 - Control for direct-current motor with separately excited field

Info

Publication number: WO1980001526A1
Application number: PCT/US1979/000017
Authority: WO
Inventors: D Urbanc; R Nieukirk; D Stafford; J Huxtable
Original assignee: Caterpillar Tractor Co; D Urbanc; R Nieukirk; D Stafford; J Huxtable
Priority date: 1978-02-09
Filing date: 1979-01-15
Publication date: 1980-07-24
Also published as: SG60184G; IT8019195A0; DE2934898A1; EP0022774A4; IT1129676B; DE2934898C2; EP0022774A1

Abstract

A digital logic control system for a battery-powered direct current motor having an armature (20) and a separately excited field (21). The operator-demanded speed and the actual motor speed are continuously compared to determine whether the motor should operate in power or braking mode, and also the degree of acceleration or deceleration of the motor to demanded speed. In power mode: field current is controlled as an inverse function of demanded and actual speeds throughout the entire speed range; and lower speeds armature current is controlled as a function of demanded speed; at higher speeds the armature (20) is connected continuously to the battery (22), until top speed limit is reached when armature current is intermittently allowed or inhibited so as to maintain speed at such limit. In braking mode: at higher speeds, the armature (20) is connected to the battery (22) for regenerative braking; at lower speeds, the armature (20) is shorted for resistive braking; the direction of field current is unchanged and the level thereof is controlled to maintain armature brake current at a maximum allowable limit. When plugging, the motor operates in braking mode and operation of the field reversing contacts (40, 41, 44, 45) is delayed until decay of field current to a low value. In the unique SCR chopper circuit, conduction of the main SCR (SCRMA) is controlled as a function of both the pulse frequency and the pulse length of a monostable multivibrator (226). A fault detection circuit (410-412) provides immediate detection of a failure of the main SCR (SCRMA) to commutate.

Description

Control For Direct-Current Motor With Separately Excited Field

Technical Field This invention relates to a control system for a direct current motor having a separately excited field, and more particularly to a motor as used in a batterypowered vehicle such as a lift truck.

Background Art Various systems are in use for the control of direction and speed of motor-driven vehicles. In general, such vehicles are provided with two operator controls, a direction selector member and a speed control. The direction selector functions to cause the field to be connected for flow of field current therethrough in the appropriate direction to cause the motor to rotate in the forward or reverse direction selected by the operator. The speed control, typically a depressible foot pedal, is used to control the amount of power supplied to the motor from the battery. Typically, such control is accomplished by use of an SCR (silicon controlled rectifier) chopper circuit in which a main SCR in series with the armature is repeatedly gated into conduction and then commutated, the average armature current being a function of the ratio of on-time to off-time of the SCR conduction.

The usual method of controlling the speed of the motor is to set and maintain the level of armature current through the main SCR in accordance with the position of the speed control. The more the pedal is depressed, the greater the ratio of on-time to off-time of the main SCR, the greater the average armature current and the higher the speed of the motor. Such control has a disadvantage in that the vehicle speed is dependent upon the position of the speed control and on the load on the motor. With a particular level of armature current being maintained, the vehicle speed will be significantly lower if the vehicle is heavily laden and/or is going uphill than it will be if the vehicle is carrying no load and/or is going downhill. As a consequence, if the operator wishes to maintain a substantially constant speed, it is necessary for him to keep depressing or releasing the foot pedal as the load on the vehicle changes.

The controls in use generally employ analog systems to control motor operation in accordance with changes in the primary and feedback information utilized in the control. That is, voltage signals are developed which have a magnitude dependent on the level of the condition being monitored. The system will then produce the end result desired in accordance with the magnitude of the voltage level of the various signals that are used. Analog systems, however, have disadvantages in that frequent adjustment of circuit values is necessary to maintain voltage levels at proper values. Nonlinearity of response is often a problem, as well as undesirable circuit interaction. Also, it is difficult at times to design and maintain reliable analog circuits which compare two continually changing conditions and determine the magnitude of difference therebetween. The present control systems also function to control the armature current by the SCR chopper circuit throughout most of the speed range of the motor. If full speed is desired, as by full pedal depression, the controls function to bypass the chopper circuit and connect the motor to the battery for full application of power thereto. Such bypass mode operation, however, has the attendant disadvantage in that the operator has no further control of the motor until such time as he causes the system to go out of bypass mode by releasing the foot pedal.

Another problem which has been encountered is that of arcing at the armature brushes which problem increases in severity at higher motor speeds. As a consequence it is desirable to provide some way of regulating the armature current in relation to the speed of the motor to reduce the current and arcing as the speed increases.

Present control systems also provide for dynamic braking, wherein the motor is driven as a generator by the momentum of the vehicle, the generated current being used to develop braking torque. Typically, the system is put into a dynamic braking mode by disconnecting the field and reconnecting it for flow of current therethrough in the opposite direction. Heavy duty and relatively expensive contactors are required to handle the large field currents present when the field connection is reversed. Contactor burn-out, from the arc created as the contactors open, is a common problem. Oftentimes the arc will weld the contactors together. When in dynamic braking at high speeds the motor will develop a counter emf greater than that of the battery. It is desirable to use the generated current at such time to recharge the battery so that the efficiency of the system is increased. However, problems do exist in the design of a reliable and efficient circuit which will connect the motor to the battery for regenerative charging of the battery and which will disconnect the motor from the battery when sufficient counter emf for charging is not present and then connect the motor for resistive braking.

The degree of acceleration of the motor as it comes up to speed is a function of the armature power current from the battery. The higher the current, the greater the acceleration. Likewise, the degree of deceleration is a function of the level of armature brake current generated by the motor. The higher the current, the greater the deceleration. It is often desirable to provide different current limits for power mode and braking mode so that the maximum acceleration can be established independently of the maximum deceleration. Likewise it is desirable to provide different current limits during regenerative and resistive braking so that the braking torque in the two modes may be equalized. In the present systems it is difficult to sense whether the current flow through the armature is power current from the battery or brake current generated by the motor, and it is difficult to provide reliable, separate, noninteracting current limit controls that will provide for separate, and preferably variable, current limits for power and brake current.

Existing controls also provide "anti-jerk" circuits which will control the rate at which power is applied to the motor in the event that acceleration is demanded, and will thus establish the rate at which the acceleration may be increased to the maximum allowable acceleration. Such circuits will generally control the rate at which the deceleration rate can increase to the maximum allowable deceleration when the field is reversed and the motor is put into the braking mode. However, again it is difficult to provide circuits which will provide for different rates of increase of acceleration and deceleration. Further, it is difficult to provide circuits wherein the maximum acceleration and/or maximum deceleration can be varied without affecting the rate at which the acceleration or deceleration levels are brought up to maximum. As a consequence, a need exists for a control wherein the rate of increase of the acceleration level, the rate of increase of the deceleration level, the maximum acceleration and the maximum deceleration can each be separately and independently set without interaction therebetween, Another drawback of present controls is that the SCR chopper circuits include pulse transformers in series with the main SCR and armature, such pulse transformers being used to charge the commutating capacitor as load current flows therethrough. When the main SCR is in conduction the voltage drop across such pulse transformers thus limits the amount of power that can be applied to the motor from the battery. As a consequence, there is a need for an SCR chopper circuit wherein no load current-carrying component is in series with the load and the main SCR so that maximum power of the battery can be applied to the load.

The present SCR chopper circuits typically operate to control the ratio of on-time to off-time of the main SCR by frequency modulation or by pulse width modulation. In the first, and most commonly used system, the SCR is repeatedly gated into conduction at a desired and variable rate, with the SCR being cornmutated at a fixed length of time after it has been gated on. Thus, the ratio of on-time to off-time will increase as the frequency of application of gate pulses is increased and vice versa. In a pulse width modulation system, the gate pulses are applied to the main SCR at a fixed rate, and the length of time until commutation occurs is varied. For full flexibility of control it would be desirable to provide a system wherein the frequency of the gate pulses can be varied and wherein the length of time that the main SCR conducts each time before commutation can be varied, and wherein the variance of one can be accomplished independently of the other.

Perhaps the most common malfunction of an SCR system is a "misfire", i.e., a failure of the SCR to commutate. When a misfire occurs, the SCR remains in continuous conduction and maximum power is applied to the motor. Various circuits have been devised to detect a misfire and to open the power circuit to the motor in such an event. Typically, misfire detection . circuits use a timer which is turned on each time the main SCR is gated on. When the timer times out, the conduction state of the main SCR is examined. If it is still in conduction, the main power circuit is interrupted. in systems wherein the main SCR is on for variable lengths of time each time it is gated on the present misfire detection circuits have a significant disadvantage. Obviously, for such a circuit to be effective, the time period of the timer must be longer than the longest time that the main SCR is normally on. Otherwise, if the timer timed out while the main SCR is properly on, the system would be shut down. When the current level is high, i.e., with long lengths of normal conduction of the main SCR, a misfire is detected very shortly after it occurs. However, at high current levels, the degree of difference in current level if there is a misfire is not too great. On the other hand, if the system is operating at low current levels, i.e., with short periods of on-time of the main SCR, and the SCR misfires, the current level will increase greatly before the timer times out and corrective action is taken. Accordingly there is a need for a misfire circuit which will detect a misfire as soon as it occurs, regardless of how long the SCR may have been on prior to its failure to commutate.

Disclosure of Invention

The present invention is directed to solving one or more of the problems and/or fulfilling one or more of the needs referred to above.

The control system of the present invention is basically a speed control system wherein the speed demanded by the operator (as by way of a conventional foot pedal) and the actual speed of the motor are continuously compared, and the level and direction of armature current and the level of field current are controlled to bring the actual speed to the demanded speed and maintain it thereat. The control system thus enables the operator to demand a desired speed and have the motor operate at that speed independently of the load on the motor.

In more particular, the demanded and actual speeds are compared to see whether the armature is to be connected to the battery for power mode operation, i.e., power current flows from the battery to the armature, or for braking mode operation, i.e., brake current flows through the armature in the reverse direction to cause a deceleration of the motor. If the demanded speed is a predetermined degree less than the actual speed (regardless of what the actual speed is) the armature is connected for braking mode operation. Otherwise, the armature is connected for power mode operation.

In power mode operation, the armature current is primarily controlled as a function of the magnitude of the demanded speed when the speed of the motor is below a predetermined base speed, the latter being substantially below top speed of the motor. Thus, as the demanded speed is increased, the ratio of on-time to off-time of the main SCR connecting the armature and battery is increased and vice versa. When the actual speed is above the base speed, the main SCR conducts continuously. The field current is primarily controlled as an inverse function of the demanded and actual speeds throughout the entire speed range of the motor. As a consequence, even though the motor is operating at a speed wherein the armature is continuously connected to the battery, the operator continues to have control over the speed thereof by the control of the field current, In addition to determining whether the demanded speed is greater than the actual speed, the present control system also determines how much greater. If the demanded speed is sufficiently greater than the actual speed, acceleration signals are generated and used to boost the armature current and weaken the field so that the motor will be rapidly brought up to speed. As the actual speed increases, the boosting effect reduces,

The present control also provides for separate and non-interacting control over the rate of acceleration and peak acceleration, the rate of acceleration being controlled by the rate at which armature current can increase in response to a demand for acceleration, and the maximum, or peak, acceleration being controlled by setting the maximum allowable power current limit. The present control further provides for limiting the speed of the motor to a predetermined top speed less than that which the operator can otherwise demand. The top speed limit circuits do not come into operation until the actual speed of the motor has reached such limit, and thus do not affect control of the motor or the degree of acceleration when the motor speed is below such limit. As a consequence, the operator can obtain a maximum rate of acceleration by demanding a speed greater than the top speed limit. When the motor has accelerated to such speed the top speed limit circuits operate to take control of the motor and to maintain the speed thereof at such limit until such time as the operator demands a slower speed.

The present control also provides for reducing the maximum allowable power current limit as an inverse function of the actual and demanded speeds so that less power current can flow through the armature at higher speeds, thereby reducing sparking at the armature brushes. In the braking mode of operation, initiated in response by moving the foot pedal so that the demanded speed is less than the actual speed, the power connection of the armature to the battery is interrupted and the armature is connected for reverse flow of brake current therethrough, such current being generated as the motor is driven as a generator. If the motor speed is high enough, the armature is connected to the battery and the regenerative brake current is used to charge the battery. If the motor speed is not high enough to charge the battery, the armature is shorted for resistive braking. In either case, the field is controlled by monitoring the level of armature brake current and by regulating the field current so that the brake current is maintained at a maximum allowable brake current limit level. A higher brake current limit level is provided during resistive braking than in regenerative braking to equalize the braking torque.

In addition to determining whether the demanded speed is lower than the actual speed (i.e., deceleration is commanded) the present control system determines how much lower, and uses such determination in controlling the degree of deceleration. In more particular, the lower the demanded speed is, relative to the actual speed, the greater will be the allowable brake current. As the actual speed reduces towards the demanded speed, the allowable brake current is reduced so that the system will come smoothly out of deceleration.

The continuing comparison of the demanded and actual speeds causes the motor to come out of the braking mode and go back into the power mode when the actual speed drops to the speed demanded by the operator. A further aspect of the invention is that a "dead band" is set, relative to the particular speed demanded by tht operator, wherein the actual speed of the motor is allowed to vary in accordance with the load on the motor. If the load increases somewhat the motor is allowed to slow enough to provide the necessary torque. Conversely, if the load increases somewhat, the speed is allowed to increase. However, if the load increases sufficiently so that the actual speed would fall below the lower limit of the dead-band range, an acceleration signal will be generated to cause the speed to increase and return the speed to within the range. Conversely, if the motor should speed up, because of a lower load thereon, to a point where it goes beyond the other end of the range, the system will go into a braking mode and return the speed to the range set by the foot pedal.

A yet further point of the invention is that the field current is maintained at a constant level when the actual speed is within the dead-band range so that the system will not be uncomfortably sensitive.

A still further aspect of the invention is the manner in which "plugging" is carried out, plugging being an operation wherein the motor is rotating in one direction, e.g., forward, with the field being connected to the battery for flow of current through the field in the direction to cause forward rotation of the motor, and the operator shifts to reverse. In the present invention, such shift puts the system into a braking mode, as if the operator had commanded a slower forward speed. The speed and field current are monitored as the motor is braked towards a stop. When, and only after, the speed and field current have reduced to predetermined minimum values, the field is disconnected and reconnected for reverse power operation. As a result, the relay contacts which connect the field to the battery will only open when minimum current is passing therethrough, thus preventing sparking damage to the contacts. In the present invention, the system responds to changes in magnitude of the actual speed, demanded speed, armature current and field current. In order to obtain reliable operation, condition signals are generated for each of these variables, the codnition signals having a frequency which varies in accordance with the magnitude of the condition. The frequencies of the condition signals are then compared with each other or with fixed frequency reference signals, with digital control signals, i.e., high or low, being generated to indicate whether one compared signal is higher or lower than the other. The digital control signals are then used in logic circuits to produce digital command signals to cause the armature and field currents to produce the desired τesults.

Another aspect of the invention is the manner in which the demanded and actual speeds are compared.

As mentioned previously, the demanded and actual speeds are continuously compared to determine whether the actual speed should be increased (demanded speed is greater than actual speed) or decreased (demanded speed is lessthan actual speed). Moreover, the magnitude of difference must be determined to see how fast the motor should accelerate or decelerate to a demanded speed.

In the present system, such comparison is made by counting the number of cycles of the demandedspeed frequency signal per cycle of the actual speed frequency signal. Regardless of what the actual speed is, the digital count obtained will be the same if the demanded and actual speeds are equal. If the demanded speed is increased relative to the actual speed (or if the actual speed decreases relative to the demanded speed) the count will go up from that obtained when the speeds are equal. The greater the differences between demanded and actual speeds, the higher the count. Predetermined high count numbers are used to control the degree of acceleration. Conversely if the demanded speed is decreased relative to the actual speed (or if the actual speed increases relative to the demandedspeed) the count will go down from that obtained when the speeds are equal. Again, the greater such difference, the lower the count. When the count reaches a predetermined value lower than the equal speed count the system is put into a braking mode. The lower the count, the greater the degree of braking. The digital count obtained does not tell what the actual or demanded speeds are, but does tell accurately whether they differ and to what degree, regardless of what the particular speeds may be.

Also as mentioned above, the field current is controlled as an inverse function of the demanded and actual speeds, i.e., as an inverse function of the products of these two speeds. In the present invention, control is achieved by counting the number of cycles of a signal having a frequency proportional to the actual speed per cycle of a signal having a frequency inversely proportional to the demanded speed. If the demanded speed goes up and the actual speed remains unchanged, the count will increase. If the demanded speed is the same and the actual speed increases, the count will increase. If both demanded and actual speeds are increased, the count will increase as a result of both speed increases. The digital count is inverted and used to control the field so that the field current decreases as the count increases, and vice versa.

Further as mentioned above, the magnitude and direction of armature current is monitored. In the present invention an armature current signal is generated having a predetermined frequency when no current flows through the armature. As current flows in one direction through the armature, e.g., power current, the frequency of the armature current signal increases from the predetermined zero-current frequency, and increases proportionally to the magnitude of the power current. When current flow is in the opposite direction, e.g., brake current, the frequency of the armature current is decreased from the zero-current frequency, again with the degree of decrease of frequency being proportional to the magnitude of brake current. As a result, a single armature current signal is obtained, and the frequency thereof will tell whether the current flow is power or brake current and will tell the magnitude of the current. As a consequence, non-interacting current limit references may be set. A power current limit reference signal may be provided having a frequency above the zero-current frequency of the armature current signal while a brake current limit reference is provided having a frequency below the zero-current frequency. The frequency of the armature current signal is then compared to both current limit reference signals. If the frequency of the armature control signal is above the high frequency power current limit reference signal an excessive power current signal will be generated.

Such signal cannot be generated when brake current flows through the armature since the frequency of the armature current signal is always less than the zero-current frequency during brake current flow. Conversely, if the frequency of the armature current signal is less than the low frequency brake current limit reference signal, then a separate excessive brake current signal will be generated.

The present invention also provides an improved SCR chopper circuit for control of armature current wherein the main SCR and load, e.g., the armature, are connected directly across the battery so that no other load components, such as a pulse transformer, are required to handle load currents , thus maximizing power transfer from the battery to the load. An inductor in parallel with the load charges a commutating capacitor to about twice battery voltage, thereby minimizing the size of capacitor and inductors needed. The commutating capacitor discharges in parallel with the main SCR so that full advantage of the charge on the capacitor is had during commutation.

The SCR system also provides separate SCR's for connection of the armature to the battery for regenerative braking or for shorting of the armature for resistive braking. The SCR system further utilizes a single capacitor for commutating the main SCR or the resistive braking SCR, depending on which one is in conduction.

Another aspect of the invention is the use of a monostable multivibrator in the pulsing circuit for the main SCR in the armature circuit, such multivibrator producing a single pulse in response to each trigger pulse applied thereto. In the present invention, the beginning of each monostable is used to gate on the main SCR and the end of each pulse is used to initiate commutation of the main SCR. Such use of a monostable multivibrator results in a very flexible control since the rate of pulsing can be varied by varying the rate at which trigger pulses are applied and the duration of the monostable pulses can be varied as desired. The pulse rate and pulse width can be independently varied. In addition, the monostable multivibrator also enables retrigger operation so that a continuous pulse is produced.

Another advantage of the present invention is the manner in which a "misfire", i.e., a failure of a main SCR to commutate, is detected so that the system may be shut down. In the present system, the conduction state of the SCR is looked at during the time interval beginning at a predetermined time after commutation is initiated (i.e., beginning when the SCR should be commutated) and ending prior to the time that the SCR would normally be gated back on. If the SCR is conducting during this time interval, a signal is generated to indicate a misfire. The misfire detection circuit operates independently of the length of time that the SCR is supposed to be on since the beginning of the time interval for inspection is dependent upon the time that commutation is initiated.

A similar misfire circuit is provided for the main SCR for the field, but with a delay so that the conduction state of the SCR is not looked at until the second time interval following a misfire. Such delay provides a second chance for the SCR to commutate. If it still fails to do so, a misfire signal will be generated.

Brief Description of the Drawings

In the drawings, wherein like parts are designated by like character references throughout the same,

FIG. 1 is a block diagram of the various components of the motor control system of the present invention showing the flow of control signals between the components;

FIG. 2 is a schematic diagram of the power portion of the motor control of FIG. 1; FIG. 3 is a schematic diagram of the operator demand and armature and field current sensor amplifiers portion of the motor control of FIG. 1;

FIGS. 4, 5 and 6 are schematic diagrams of the reference signal and comparator circuits portion of the motor control; FIGS. 7, 8 and 9 are schematic diagrams of the control logic portion of the motor control;

FIG. 10 is a schematic diagram of the armature pulsing circuits of the motor control; FIG. 11 is a schematic diagram of the field pulsing circuits of the motor control;

FIG. 12 is a schematic diagram of the gate pulse amplifiers portion of the motor control;

FIG. 13 is a graph illustrating the relationship of the direction and magnitude of armature current flow to the armature current voltage signal V_IA;

FIG. 14 is a graph illustrating the relationship of the armature current frequency signal F_IA to the armature current voltage signal V_IA and to the armature current monitor signals;

FIG. 15 is a graph illustrating the relationship of the fixed speed signals relative to actual motor speed;

FIG. 16 is a graph illustrating the relationship of the field current and the field current frequency signal F_IA to the field current monitor signals;

FIG. 17 is a chart illustrating the time relation of the signals involved in the detection of a misfire of the main armature SCR; FIG. 18 is a schematic diagram of a modification of the field pulsing circuits of the motor control.

Best Mode for Carrying Out the Invention

In the following description, specific figures are given from time to time for voltages, currents, motor speeds and the like. Such figures relate to a particular motor that has been used in a reduction to practice of the invention and are given here to facilitate an understanding of the invention. If a different motor is used, one or more of the values given herein may have to be changed in order to obtain the desired relationship of components and operation set forth herein. Accordingly, the specific figures used are to be understood as exemplary rather than as absolute, Referring now to the drawings, wherein is shown a preferred embodiment of the invention, FIG. 1 shows the overall system for a silicon-controlled rectifier (SCR) control for a direct current motor having an armature 20 and a separately excited field 21 powered from a direct current source such as battery 22. The illustrated control has particular suitability in the drive system of a vehicle such as a lift truck (not shown). The control is provided with three operatoractuated devices: a main power switch 23, a control lever 24 for commanding a forward or reverse direction, and an accelerator pedal 25.

FIG. 2 illustrates the power portion of the control of FIG. 1. Closure of main switch 23 will develop a supply of regulated voltages V_S1, V_S2 and V_S3 across zener diodes 27, 28 and 29, respectively. Typically these regulated voltages may be 20, 13.6 and 6.8 volts, respectively.

Supply voltage V_S1 is applied to the first transistor 30 of the four-stage transistor amplifier 31, transistors 32, 33 and 34 being powered from battery 22 through circuit breaker contact 35 and circuit breaker trip coil 36. Circuit breaker contacts 35 and 37 are manually closable and will remain closed unless trip coil 36 is driven by amplifier 31. If the voltage V_S1 is not present (such as when the main switch 23 is opened) or if a V_CBT signal is applied to transistor 30, trip coil 36 will be energized and contacts 35 and 37 will be opened to remove voltage from the amplifier 31 and the armature and field circuits of the motor. The field 21 of the motor is powered as follows. Assuming that the motor is to be driven in a forward direction, a forward signal FWD is received at the bottom center of FIG. 2 from the control logic, FIG. 8 (a number in a circle adjacent a control signal on the drawings indicates the particular figure of the drawings whereinthe signal is generated or to which the signal is sent), is amplified by amplifier 38 and drives coil 39 of the forward relay to close the forward relay contacts 40 and 41 and thus connect one terminal of the field winding to ground and the other terminal to the cathode of the main field SCR, SCR_MF, (The connection of the field winding terminals would be reversed if a reverse signal REV had been applied through amplifier 42 to the coil 43 of the reverse relay and reverse relay contacts 44 and 45 had been closed). Microswitches 46 and 47 are mechanically actuated to closed position upon closure of the forward or reverse contacts, respectively, and when closed will provide voltage signals DR_F or DR_R, to confirm that the forward or reverse contacts, respectively, have in fact closed. As indicated on the drawings, these signals are sent to the control logic of FIGS, 7 and 9,

With circuit breaker contact 37 closed, battery voltage will be applied through fuse 48 to the anode of SCR_MF. When SCR_MF is gated on, current will then flow from the battery through the field winding. The charging SCR, SCR_LF, is also gated on at the same time so that the commutatin capacitor C_CF will charge through SCR_LF and choke L_CF so that the left plate of C_CF is charged positively with respect to the right plate. The charge on C_CF will reach approximately twice the battery voltage, and when C_CF is fully charged, the charging current through SCR_LF will cease and SCR_LF will turn itself off. A subsequent gating on of the commutating SCR, SCR_CF, will then result in connecting the commutating capacitor C_CF in parallel with SCR_MF, back-biasing SCR_MF and turning it off. C_CF will charge through SCR_CF so that its right plate will be positive with respect to its left plate. After charging, the current flow through C_CF and SCR_CF will cease and SCR_CF will turn off.

Regating of SCR_MF and SCR_LF will restart the sequence. The power to the field is controlled by varying the ratio of the on-time to the off-time of SCR_MF.

A current shunt 49 in the field circuit monitors the current flowing through the field and produces voltage signal +V_F and -V_F having a potential difference therebetween proportional to the amount of field current.

As is conventional, a free-wheeling diode D_FWF is connected across the field winding to allow current to flow during the periods when SCR_MF is not conducting. A zener diode 50 and resistor 51 are also connected across the field, and a control signal V_FM is obtained from the junction of zener 50 and resistor 51. Signal V_FM will be high or low, respectively, depending on whether SCR_MF is conducting or not, thereby providing a signal as to the state of conduction of SCR_MF, which signal is used in the subsequently described misfire circuit illustrated on FIG. 7.

The armature 20 of the motor is powered as follows. With circuit breaker contact 35 closed, battery voltage will be applied through fuse 55 to the anode of the main SCR for the armature, SCR_MA. When this SCR is gated on, current will flow therethrough and through armature 20, inductance L_FA and back to the battery. Inductance L_FA is used to provide more inductance in the armature circuit for smoother operation. Charging SCR, SCR_LA, is gated on to conduct before SCR_MA is gated on, so that current will flow through commutating capacitor C_CA and choke L_CA to charge the capacitor to approximately twice battery voltage with its left plate negative with respect to its right plate. When such charging current ceases, SCR_LA will turn itself off. SCR_MA will continue to conduct, and power current from the battery will flow through the armature until such time as the commutating SCR, SCR_CA, is gated on. When this occurs, capacitor C_CA will be connected in parallel to SCR_MA to back-bias and turn SCR_MA off.

As with the field, the power supplied from the battery to the armature will be a function of the on-time to off-time of SCR_MA.

A free-wheeling diode D_FWA is connected across the armature, A current shunt 56 is connected in the armature circuit to monitor armature current and produce voltage signals +V_A and -V_A at the shunt terminals. The voltage difference between these terminals is proportional to the level of armature current. A given level of armature power current will produce the same voltage difference between the shunt terminals as will the same level of armature brake current. However, since the direction of power current through the armature, when the armature is being powered from the battery, is opposite to the direction of brake current, when the motor is braking and acting as a generator, signal +V_A will be positive relative to signal -V_A during power current flow and will be negative relative to signal -V_{A during brake current flow,} A misfire signal (indicative of a failure of the main SCR_MA to commutate) is obtained from junction 57 of SCR_CA, SCR_LA and C_CA. In normal operations, when SCR_CA is gated on capacitor C_CA will cause SCR_MA to be turned off and C_CA will charge through SCR_CA so that the charge thereacross will be about twice the battery voltage, with its left plate positive with respect to its right. As a consequence, after commutation of SCR_MA, the potential at junction 57 will be either about twice battery voltage above ground (if free-wheeling current is flowing through the armature and diode D_FWA) or about three times battery voltage above ground (if no free- wheeling current is flowing). However, if SCR_MA is not successfully commutated and it continues to conduct, then the capacitor C_CA cannot charge so that its left plate is positive with respect to its right and junction 57 will be at approximately battery voltage above ground.

Zener diode 58, diode 59 and resistor 60 are connected in series from junction 57 to ground, zener diode 58 being used to drop battery voltage thereacross. As a consequence, the potential at junction 61 between diode 59 and resistor 60 will be approximately at ground if SCR _MA has not commutated, or will be one or two times battery voltage if it has. Zener diode 62 and resistor 63 are connected from junction 61 to ground, with voltage signal V_AM being taken across zener 62. Signal V_AM accordingly will be high (zener 62 potential) if it has been commutated, and low if it has not.

When the motor is in the braking mode, i.e., when the vehicle is moving and the main SCR_MA is not gated on, the momentum of the vehicle will cause the armature to be driven so that the motor acts as a generator. If the motor speed and field strength are sufficiently high, the emf developed across the armature will be greater than that of the battery. In such event, the regenerative braking SCR, SCR_RB, connected across and oppositely poled to the main SCR_MA is gated on to allow braking current to flow back and charge the battery. The SCR_RB will commutate itself as the armature slows arid the emf across the armature becomes insufficient to continue charging the battery. After SC_RRB is commutated, the resistive braking SCR, SCR_B, is gated on to effectively short-circuit the armature for resistive braking of the motor.

If it is desired to commutate the braking SCR_B while brake voltage still exists, SCR_CA is first gated on to allow C_CA to charge with its left plate positive relative to its right. Then, SCR_LA is gated on connect C_CA across SCR_B, back-biasing and commutating it. After such commutation, SCR_MA is gated on to resume power operation of the motor.

The particular disclosed arrangement of SCR_MA , SCR_LA, SCR_CA, C_CA, L_CA and the armature 20 has several significant advantages. The armature and SCR_MA are connected directly across the battery so that no other components, such as a pulse transformer are required to handle load current. As a consequence, power transfer from the battery to the armature is maximized. The inductor L_CA is used to charge C_CA to about twice battery voltage which minimizes the size of the capacitor, and no load current flows through the inductor, which minimizes its size. The commutating capacitor C_CA discharges in parallel with SCR_MA, enabling full advantage to be had of the charge thereacross during commutation. The field arrangement is the same, and has the same advantages.

The disclosed arrangement of SCR_B, is also advantageous in that it permits the single commutating capacitor C_CA to be used for commutation of either SCR_MA or SCR_B. In commutating SCR_MA, C_CA is first charged in one direction through SCR_LA and is then connected across SCR_MA by use of SCR_CA . In commutating SCR_B, C_CA is charged in the opposite direction through SCR_CA, SCR_LA then being used to connect the charged capacitor across SCR_B. The actual speed of the motor is monitored by a speed pickup 65. A toothed gear 66 is driven by the armature, with its teeth rotating past a magnetic Hall effect sensing device 67, so that a low voltage (approximately 1 volt) ripple signal N_MP is produced which rides on approximately a 5-volt d.c. signal. For example, if gear 66 has sixty teeth, sixty pulses will be produced for each revolution of the armature and gear 66, and the number of pulses per unit time will be accordingly sixty times the number of revolutions per unit time. The frequency of the N_MP signal is accordingly directly proportional to actual motor speed, and sensing is provided down to zero speed.

Referring now to FIG. 3, the operator-actuated direction-selection lever 24 is mechanically linked to switches 70 and 71. As lever 24 is moved to "forward" position, switch 70 will close and produce a forward-operator-demand signal F_OD equal to supply voltage V_S2. This signal passes through filter 72 to produce a high B signal and an inverted low

signal for use in the various control and logic circuits indicated. Similarly, movement of the direction-control lever to reverse position will generate a high A signal and a low

signal, Switches 70 and 71 are mechanically interlocked to prevent simultaneous closure.

Accelerator pedal 25 is mechanically linked to switch 73 and to the adjustment member 74 of potentiometer 75. Switch 73 will close in response to initial depression of the pedal 25 and will remain closed until the pedal is fully released. The accelerator-switch signal A_S is filtered and appears as signal F.

The degree of movement of adjustment member 74 will depend on the amount that the accelerator pedal is depressed, and the operator-demand signal V_OD will vary from 0 to V_S2 volts in accordance with the degree of such depression. The V_OD signal is also applied to the base of transistor 76 to vary the conductance thereof and produce a positive voltage signal that

varies inversely with V_OD. The V_OD signal is applied to voltage-controlled oscillator (VCO) 77 to produce a frequency signal F_DM whose frequency is directly proportional to the voltage input thereto, i.e., to the degree of pedal depression and thus to the speed demanded by the operator. An RCA CD4046 may be used for this VCO as well as for the VCO's in the circuits described hereinbelow.

The inverse signal is applied to VCO 78

to produce a frequency signal T₂ whose frequency is proportional to the magnitude of signal and thus

inversely proportional to the operator demand. Signal T₂ is applied to and down-counted by counter 79 to produce a frequency signal T₁ whose frequency is also inversely proportional to the operator-demanded speed. The T₁ signal is used in FIG. 11 to control the field current.

Thus, as the operator depresses the pedal to demand more speed, the frequency of the speed demand signal F_DM increases while the frequency of the field control signal T₁ goes down, and vice versa, FIG. 3 also includes a pair of operational amplifiers 80 and 81, and associated conventional circuitry to amplify the millivolt signals produced by the field and armature shunts 49 and 56 (FIG . 2) . The amplifiers have gains of about 100 to amplify the input current signals to more workable voltage levels . A zero millivolt s ignal from shunt 56 (corresponding to zeτo current flow in the armature) will result in an output V_IA from amplifier 81 equal to V_{S 3} (nominally 6.8 volts) . As will be noted from FIG. 13 , a +50 millivolt signal from shunt 56 resulting from power flow through the armature causes the output of amplifier 81 to be V_{S 3} plus 5.0 volts. The level of the signal V_IA above the zero current reference level of V_S3 is proportional to the magnitude of the power current flowing through the armature. If in a braking or plugging mode the direction of current flow through the armature will be reversed and the polarity of the signals applied to amplifier 81 will be reversed, A -50 millivolt signal from shunt 56, during braking or plugging mode, will decrease the level of signal V_IA from V_S3 by 5.0 volts. The degree by which the level of signal V_IA is decreased from the 6.8-volt zero-reference level is proportional to the magnitude of brake current through the armature. The output signal V_IA is always positive, however, whether power, brake or no current is flowing through the armature.

Operational amplifier 80 will also have a V_S3 (6.8 volts) output (signal V_IF) if the field current is zero. Since current can only flow in one direction through the field shunt 49, the signal V_IF will only vary upwardly from the 6.8-volt zero-reference level and in an amount therefrom proportional to the magnitude of the field current.

FIG. 4 illustrates a portion of the reference signal generators and comparator circuits of the motor control, and more particularly the portion which compares the actual speed of the motor and the speed demanded by the operator by actuation of the accelerator pedal. The Nwp signal generated by the speed pickup 65 (FIG. 2) is passed through an a.c. amplifier 82 to remove the d.c. bias level and to amplify the ripple pulses. The signal is then passed through a Schmitt trigger 83, a logic inverter 84 and a delay/filter circuit 85 to produce square wave pulses N_M1 which have a frequency proportional to the actual motor speed. Transmission gate 86, controlled by NAND gate 87, is used to affect the time delay of delay/filter circuit 85. At lower speeds a longer delay is needed to get good squaring. At higher speeds, resistor 88 is not needed and is shorted by transmission gate 86 to yield shorter squaring delays. The square wave pulses Nw. are fed into a phase locked loop consisting of phase/frequency comparator (ØC) 89, a low pass filter 90, VCO 91, and two counters 92 and 93, The external capacitor and resistors of VCO 91 are chosen so that the frequency of actual motor speed signal, F_AM, generated by VCO 91, is 64 times that of the N_M1 signal for all motor speeds above 45 rpm. Resistor 94 sets a minimum frequency of F_AM corresponding to an actual motor speed of 45 rpm even though the actual speed is below 45 rpm. The F_AM signal from VCO 91 is down-counted by counters 92 and 93 to produce signals F_AM2 and F_AM1, signal F_AM2 having a frequency 1/32 that of F_AM, or twice the frequency of signal N_M1 for any actual motor speed above 45 rpm. The frequency of signal F_AM1 is 1/64 that of F_AM and thus is equal to the frequency of the N_M1 signal for actual motor speeds above 45 rpm. The F_AM1 signal is fed back to comparator 89 to lock the frequencies of the F_AM, F_AM2 and F_AM1 signals relative to the frequency of the N_M1 signal for all actual motor speeds above 45 rpm.

An inverter oscillator 95 (used for speed governing) produces a constant frequency reference signal F_TSM proportional to the desired top speed limit of the motor. The control may be customized for a particular vehicle to limit the top speed thereof by changing the value of resistor 96. The F_TSM and F_AM signals are fed to a phase/frequency comparator 97 whose output will pulse high, and thereby (through filter arrangement 98) produce a high signal G when the actual motor speed signal F_AM is greater than the top speed reference signal

Fmgw. Logic inverter 99 will produce an inverted G signal. In the present system the speed demanded by the operator (by the accelerator pedal) and the actual speed of the motor are continuously monitored and compared in order to determine whether the motor should accelerate or decelerate. Regardless of what the demanded and actual speeds might be at any given time, if the demanded speed is greater than the actual speed, then the motor should accelerate so that its speed will increase to the speed which the operator wishes. conversely, if the demanded speed is less than the actual speed, then the motor should decelerate.

As set forth above, the F_DM signal has a frequency proportional to the demanded speed and the F_AM signal (and the derivative F_AM1 and F_AM2 signals) has a frequency proportional to the actual speed of the motor. When the actual and demanded speeds are equal -- regardless of the speed -- the frequency of the F_AM and F_DM signals are equal.

The F_AM and F_DM signals are compared to generate a deceleration signal as follows. The F_DM signal from FIG. 3 is passed through transmission gate 100 (which is closed for transmission therethrough as long as the actual motor speed is below the top speed reference and signal G is high) and is fed to the phase/frequency comparator 102 together with the F_AM signal. As long as the frequency of the demanded speed signal F_DM is equal to or greater than that of the actual speed signal F_AM, the output of comparator 102 is low. If the frequency of the demanded speed signal is less than that of the actual motor speed, the output of comparator

102 will pulse high, generating signal U which signifies that deceleration is desired. The absence of the U signal indicates that the actual and demanded speeds are equal or that acceleration is desired. The demanded and actual speed signals are also compared to determine the magnitude of difference therebetween so that the rate of acceleration or deceleration may be controlled. In general, the higher the demanded speed is relative to the actual speed, the greater the acceleration rate should be so that the motor may be quickly brought up to the demanded speed. Conversely, the lower the demanded speed is relative to the actual speed, the greater the deceleration rate should be to reduce the motor speed to that which is desired.

In the present system, the magnitude of the difference between the demanded and actual speeds is obtained by counting the number of cycles of the demanded speed signal F_DM per cycle of the actual motor speed signal F_AM2 (derived from the F_AM signal and thus proportional to the actual motor speed).

The F_DM signal which passes through gate 100 is also passed through transmission gates 103 and 104 and buffer 104a to the clock input of counter 105.

Gate 104 is closed by a high F_AM2 signal and will remain closed until the F_AM2 signal goes low. Thus, gate 104 will be closed during the time that thirty-two F_AM pulses are generated. The gate will then open after the thirty-second F_AM pulse and reclose after thirtytwo more F_AM pulses have been generated. The length of time that gate 104 will remain closed, each time it closes, is thus inversely proportional to the actual speed of the motor. If the actual and demanded speeds are the same, then the F_DM and F_AM frequencies will be equal and thirty-two F_DM pulses will pass through gate 104 each time it is closed and will be counted by counter 105. This will be true, regardless of what the actual speed may be at the time. Thus, a count of thirty-two by the counter signifies that the demanded and actual speeds are the same, but does not provide an indication of whether those speeds are high or low. Counter 105 is reset by the F_AM1DD signal which is double-delayed by delay circuits 106 and 107 so that counter 105 is reset during the time that gate 104 is open.

If the demanded speed is greater than the actual speed (again regardless of what the actual speed may be), then more F_DM pulses will pass through gate

104 each time it is closed to be counted by the counter 105. Thus, when acceleration is demanded the count in counter 105 will be greater than thirty-two. As is apparent, the higher the demanded speed is relative to the actual speed, the higher the count in counter

105 will be. Conversely, if the demanded speed is less than whatever the actual speed may be, fewer F_DM pulses will pass through gate 104 each time, and the count will decrease from thirty-two. Again, the lower the demanded speed is, relative to the actual speed, the lower the count of counter 105 will be.

Thus, if the frequency of the actual motor speed signal F_AM2 were to remain constant, the count in counter 105 will increase or decrease as the demanded speed signal F_DM increases or decreases. If the frequency of the demanded speed signal remains constant, the count in counter 105 will increase if the motor slows and will decrease as the motor speeds up.

The third through seventh binary outputs of counter 105 are combined by NAND gates 108 and 109 and NOR gate 110 and applied to the D input of flip-flop 111 and clocked therethrough to the Q output by the delayed F_AM1 signal, F_AMID. The ACC_OO deceleration signal at the Q output is low if the demanded speed per actual speed count is less than 24, and is high if the count is 24 or greater. The third, fourth and fifth binary outputs of counter 105 are combined by NAND gates 112 and 113 and NOR gate 114 (FIG. 4), and applied to the first and second inputs of shift register 115. The sixth and seventh outputs of counter 105 are applied directly to the third and fourth inputs of shift register 115. The inputs of shift register 115 are clocked through to the corresponding Q outputs by the F_AMID pulse during the time that transmission gate 104 is open.

Acceleration signals ACC₁, ACC₂, ACC₃ and ACC₄ and their inverses are obtained

from the Q outputs of shift register 115, and the levels of these signals to the demanded/actual speed count in counter 105 is as follows:

The sixth and seventh outputs of counter 105 are combined by logic gate 116 to maintain transmission gate 103 closed as long as the count of counter 105 does not exceed 192, thereby preventing overflow of the counter. The first through fourth outputs of counter 105 are also applied to the inputs of shift register 117. Flip-flop 116a, inverter 116b and NAND gate 116c enable the inputs of shift register 117 to be clocked to the outputs thereof by either a high fifth output of counter 105 or the F_AMID signal. The latched output signals of register 117 are fed into an R/2R resistor network 118 for digital-to-analog conversion to establish the level of voltage signal V_CLB which is used in FIG. 6 to establish a reference for current-limiting in the armature during braking. The lower the count in counter 105

(i.e., the greater the demanded deceleration), the lower will be the level of voltage signal V_CLB.

In the event the actual motor speed exceeds the top speed reference, so that signals G and

go high and low, respectively, transmission gates 100 and 101 will open and close, respectively, to disconnect the F_DM signal from counter 105 and instead apply the frequency signal F_TSM thereto.

FIG. 4 also includes a fixed frequency voltage controlled oscillator 119 which generates reference frequency F_RC for creep speed. This reference frequency is compared with the operator-demand frequency F_DM in comparator 120, and the output signal M will be high if the demanded speed is less than the established creep speed of the vehicle. The M signal is applied to shift register 115 to reset the register and thus inhibit the generation of the acceleration signals ACC₁-ACC₄ when in the creep mode, i.e., when the signal M is high. The high M signal is also used in FIG. 10 to shorten the armature pulse width,

FIG. 5 illustrates another portion of the reference signal generators and comparator circuits of the control system. A fixed-frequency voltagecontrolled oscillator 125 generates a reference frequency 2F_B, which for the disclosed embodiment has a frequency equal to the frequency of the actual speed signal F_AM1 when the actual motor speed is 1920 rpm. This reference frequency is applied to counter 126 and downcounted thereby, with the second through fourth binary outputs being applied to comparators 129, 128 and 127. The reference frequency 2F_B is applied directly to comparator 130. The F_AM1 signal, having a frequency proportional to actual motor speed, is also applied to these comparators. The output signals from the comparators are as follows:

The relation of these signals to actual motor speed is also illustrated on FIG. 15.

The sixth output of counter 126, having a frequency corresponding to 30 rpm, is used in FIG. 6. FIG. 6 illustrates the remaining portion of the reference signal generators and comparator circuits of the control system, wherein the field and armature currents are compared to established references.

The variable voltage signal V_IF which is proportional to the current in field 21 is applied to VCO

140 to generate a frequency signal F_IF whose frequency is also proportional to the magnitude of field current. Signal F_IF is applied to phase/frequency comparators

141 and 142. A VCO 143 generates a fixed frequency signal F_IFMAX whose frequency corresponds to a predetermined maximum allowable level of field current, this frequency signal being applied to comparator 141. Fixed frequency VCO 144 generates a frequency signal F_IFMIN whose frequency corresponds to a predetermined minimum level of field current, this frequency signal being applied to comparator 142. The outputs of comparators 141 and 142 generate the following control signals (see also FIG. 16):

The E signal is used in FIG. 6 in the generation of the "last-commanded-direction" signals C and

which are used subsequently in FIG. 8 to control operation of the contacts 40, 41, 44 and 45 of the field relays, and prevent them from opening when more than minimum field current is passing therethrough. The E signal is combined with the motor speed signal

(from FIG. 5) by logic gate 145 whose output, is low when

field current is below minimum reference and the actual motor speed is below 120 rpm. (This signal is in

verted to form signal V_DE which is used in FIG. 10). The signal is applied to NOR gates 146 and 147.

If the operator commands a forward direction, signal at the input of gate 146 will be low. If at the same time signal is also low, the output of gate 146

will go high to set flip-flop 148, so that the C signal from the Q output of the flip-flop will go high. If the field current rises above minimum or the motor speed increases above 120 rpm, signal will go high and

the outputs of gates 146 and 147 will go low. The C signal will continue to be high. If now the operator should decide to reverse direction and shifts the direction control lever to reverse, signal

will go high and signal

(at the input to gate 147) will go low. The low reverse-signal

however, cannot change the output of gate 147 as long as the signal remains

high. As a consequence a reset voltage is not applied to the flip-flop 148 at such time and the C signal remains high. If and when the field current drops below the minimum E reference and the motor speed falls below 120 rpm D reference, then signal will go low and

the output of gate 147 will go high (provided that a reverse-direction is still being commanded). The highoutput of gate 147 will then reset flip-flop 148 so that its Q output goes low, causing signal C to go low and signal

to go high. Similarly, if the operator had shifted from forward to neutral the C s ignal from flip-flop 148 would remain high. Flip-flop 148 thus serves as a memory for the last commanded direction. Signal C is high if the last commanded direction is forward, while signal

is high if the last commanded direction is reverse.

Armature current signals are generated in FIG. 6 as follows. The variable voltage signal V_IA, from amplifier 81 of FIG. 3 is applied to VCO 150 to generate a frequency signal F_IA proportional to the magnitude of signal V_IA As will be noted from FIG.

14, with zero armature current, signal V_IA will be 6.8 volts and VCO 150 will generate a frequency signal F_IA of approximately 60 KHz, As the signal V_IA increases in magnitude (from an increase in power current through the armature) the frequency of signal F_IA will increase proportionally. If in a plug mode, an increase in plug current will reduce the level of the signal V_IA from 6.8 volts and will cause the frequency of signal F_IA to decrease proportionally. Thus, the frequency of signal F_IA provides information as to the magnitude of armature current and whether such current is power current or brake current.

The armature current frequency signal F_IA is applied to phase/frequency comparators 151, 152 and 153, which provide signals that indicate where the armature current is, relative to predetermined minimum and maximum levels of power current, or relative to a maximum level of brake current. (See FIG. 14).

A fixed frequency reference signal F_IAO is generated by VCO 154, this signal having a frequency somewhat above 60 KHz and corresponding to a predeterr mined minimum amount of power current through the armature (e.g., approximately 80 amperes). Signal F_IAO is applied to comparator 151 for comparison with signal F_IA. If the two signals indicate that the magnitude of actual power current through the armature is less than this predetermined minimum, the output of comparator 151 will produce a high signal J. If brake current is flowing through the armature, the frequency of the F_IA signal will always be less than the frequency of the signal F_IAO and the signal J will be high, regardless of the amount of brake current. Inverted signal

is also available.

The maximum allowable level of armature power current is set by the F_CLA signal generated by VCO 155 and applied to comparator 152, If the armature power current is belov/ the maximum allowable level, signal K will be high. If the power current exceeds such level, the signal K will go low. The inverse signal

will be low or high, depending upon whether the armature power current is less or greater than the F_CLA current limit level.

It is desirable to lower the current limit level at high speeds of operation to decrease sparking at the brushes. This is accomplished by applying the variable voltage signal F_CLA to the Input of VCO 155 so that the frequency of the F_CLA signal will vary (between the minimum and maximum frequencies established by the external resistors and capacitor connected to the VCO) in accordance with the level of the Vp.. signal. As will be brought out more fully in connection with FIG. 11, the level of the V_CLA signal will vary inversely as a function of the actual and demanded speeds. Accordingly, the greatest allowable armature current level will be set at low speeds of operation, with such current level limit being decreased when operating at high speeds.

Transmission gate 156 is used to apply the fixed voltage at the junction of voltage-dividing resistors 156a and 156b to the input of VCO 155. Such fixed voltage is between the maximum and minimum limits of the V_CLA voltage and thus serves to establish a minimum voltage level to the input of VCO 155 whenever the demanded acceleration is sufficient to generate the signal ACC₃. For example, if the motor is accelerating, the V_CLA voltage signal will decrease and the current limit signal F_CLA will decrease. At some point, the V_CLA signal will be the same as that between the junction of resistors 156a and 156b. If only a relatively small degree of acceleration is demanded at such time, gate 156 will be open and the frequency of the F_CLA signal will continue to drop as the level of V_CLA drops. However, if at such time the demand for acceleration is still great enough to generate the ACC₃ signal, gate 156 will close, so that the frequency of the F_CLA signal will stay the same even though the level of the V_CLA signal drops. This enables the motor to continue in operation at a relatively high current limit level for high torque, as long as the demand for acceleration is high. When the speed increases sufficiently so that the ACC₃ signal is lost, gate 156 will open and VCO 155 will be controlled in response to the magnitude of the V_CLA signal again.

Maximum possible torque will occasionally be required when the motor is operating at low speed and the load thereon is high, as for example when the vehicle is driven uphill at low speeds. In order to provide for such torque, external resistor 157 of VCO 155 is arranged to be shorted out by transmission gate 158 in the event of such occurrence. With resistor

157 shorted out, the frequency of operation of VCO 155., i.e., the frequency of signal F_CLA, will increase to allow higher armature power current to be maintained. The circuit operates as follows. Normally transmission gate 158 is open and external resistor 157 is in the circuit. If the load on the motor is such that the armature current increases above the current limit level, i.e., if the frequency of signal F_IA is greater than the frequency of the current limit signal F_CLA, the overcurrent signal K will go low. This signal is applied to NOR gate 159, and if the motor speed is below 120 rpm (so that D is low) NOR gate 159 will output a high to close transmission gate 160 so that F_BM/4 pulses will be applied to counter 161. By other circuits to be described hereinafter, the overcurrent signals K and K will affect the operation of the armature and field pulsing circuits so that the armature current reduces, with normal operations being resumed when the armature current reduces below the current limit level (F_CLA). A continued load on the motor again causes the armature current to increase above the current limit level so that the K signal again goes low to allow more F_BM/4 Pulses to go to counter 161. In normal operation, the speed of the motor will increase to above 120 rpm before the count accumulated in. counter 161 is enough to cause its seventh output to go high. However, if the load is such that the speed remains below 120 rpm while the cumulative count of F_BM/4 pulses is sufficient to cause the seventh output of counter 161 to go high, flip-flop 162 will be set and will close transmission gate 158. This will then boost the current limit signal F_CLA so that higher armature current is permitted. With higher torque now available the speed of the motor will increase. When the speed increases above 240 rpm, the speed signal W goes low, causing NAND gate 163 to output a high which resets counter 161 and flip-flop 162. Transmission gate 158 opens and restores resistor 157 to the RC circuit of VCO 155 for normal operation. Thus, when the motor is operating in a power mode, the maximum allowable armature current is set by the power current limit signal F_CLA. The maximum allowable armature current when the motor is operating in a braking mode is set by the brake current limit signal F_CLB which is generated by VCO 165.

As brought out previously, when brake current flows through the armature, the frequency of the armature current signal F_IA will be lower than when power current flows therethrough, and the frequency of signal F_IA will progressively decrease as the amount of brake current increases. Comparator 153 continuously compares the armature current signal F_IA and the brake current limit signal F_CLB. As long as the armature brake current is less than the allowable current limit, the frequency of the signal F_IA will be greater than that of the signal F_CLB and the signal L will be high. If excessive brake current flows through the armature, F_IA will be lower than F_CLB and the signal L will go low.

The frequency of operation of VCO 165 will vary in accordance with the magnitude of the V_CLB signal applied to the input thereof and within the range set by the external capacitor and resistors of the VCO. The minimum frequency of operation of VCO 165 (with zero Vp.g input thereto) is set as a function of capacitor 166 and resistors 168a and 168b, while the maximum frequency of operation (with maximum V_CLB input) is the minimum frequency plus a function of capacitor 166 and resistors 167a and 167b.

As brought out previously, the level of the V_CLB signal will vary inversely with the degree of demanded deceleration. The greater the demanded deceleration, the lower the level of the V_CLB signal, and vice versa. Since the frequency of the brake current limit signal F_CLB varies directly with V_CLB the frequency of the F_CLB signal also varies inversely with the degree of demanded deceleration, so that as more deceleration is demanded, the amount of maximum allowable armature brake current will increase.

As mentioned previously, when the motor is being operated in the braking mode, braking will either be regenerative (with brake current flowing through SCR_RB, to recharge the battery) of resistive (with the armature shorted by SCR_B) . During regenerative braking the field strength will be considerably higher than during resistive braking. In order to reduce the disparity between the regenerative braking torque and the resistive braking torque the present circuit operates to allow a higher armature brake current during resistive braking, as follows. The and signals from FIG.

10 and the

signal from FIG. 5 are all applied to NAND gate 169 which logically combines them to produce a high output if the system is in a regenerative braking mode or a low output if in resistive braking. Thus, if in a regenerative braking mode, the high output of NAND gate 169 will close transmission gate 168c to short out resistor 168b and thereby raise the minimum frequency of the F_CLB signal generated by VCO 165 and thereby decrease the maximum allowable armature brake current. When in a resistive braking mode, transmission gate 168c opens, putting resistor 168b back in the circuit so that the minimum frequency of VCO 165 is reduced, allowing a greater amount of armature brake current to flow. A change in the minimum frequency of operation of a VCO will normally produce a corresponding change in the maximum frequency thereof. In order to keep the maximum frequency the same, the output of NAND gate 169 is inverted by inverter 169a and applied to transmission gate 167c to short out resistor 167b when in resistive braking. With a proper relation between the external resistors the maximum frequency of VCO 165 will remain substantially the same whether resistor 168b is shorted by transmission gate 168c or not.

As may be seen from FIG. 14, an indication of excessive armature power current (the K and it signals) is obtained when the F_IA signal exceeds the predetermined maximum frequency set by F_CLA while an indication of excessive armature brake current is obtained when the frequency of the F_IA signal goes in the opposite direction from the zero-current reference frequency and goes below the predetermined minimum frequency set by F_CLB As a result, the level of excessive power current can be set completely independently of the level of excessive brake current, and vice versa, and each level can be varied without affecting the other,

FIGS. 7-9 illustrate the control logic portion of the control system wherein various of the control signals generated in the system are combined to produce command signals. FIG. 7 will be discussed after the armature and field pulsing circuits have been described.

FIG. 8 illustrates the logic portion wherein the forward and reverse signals FWD and REV are produced, these signals being used in FIG. 2 to energize one or the other of the coils 39 or 43 of the direction relays and close the contacts thereof to connect the motor field into the power circuit.

Signals A, B, C, D, , E and E are logically

combined by NAND gates 170, 171, 172, 173 and 174. The forward signal FWD at the output of gate 174 will be operatively high if one or more of the following conditions exist.

(1) The last commanded direction was forward (C) and the field current is above minimum reference level (E);

(2) a forward direction is being commanded (B), the motor speed is less than 120 rmp (D) and the field current is below minimum reference level (E); (3) the last commanded direction was forward

(C) reverse direction is now being commanded (A) and the motor speed is above 120 rpm

;

(4) the last commanded direction was forward (C) and a forward direction (B) is presently commanded. Similarly, the A, B,

D,

, E and E signals are combined by NAND gates 175, 176, 177, 178 and 179 to produce the REV signal at the output of gate 179. The REV signal will be high if one or more of the following conditions exist: (1) The last commanded direction was reverse and the field current is above minimum

(2) reverse direction is being commanded (A), the motor speed is less than 120 rpm (D), and the field current is below minimum reference (E); (3) the last commanded direction was reverse , forward direction is being commanded (B), and the motor speed is above 120 rpm

;

(4) the last commanded direction was reverse ( and reverse direction is presently commanded (A). In FIG. 9, the A, B, C,

, DR_F and DR_R signals are combined by NAND gates 18υ, 181, 182, 183 and 184 to produce signal V_FE which must be high in order for the field 21 and armature 20 to be energized. The signal V_FE will be high if any one of the following conditions exist: (1) Reverse direction is being commanded (A), the last commanded direction was reverse

, the reverse contacts 44 and 45 have closed and have actuated microswitch 47 to closed position (DR_R); or, (2) forward direction is being commanded

(B), the last commanded direction was forward (C), the forward contacts 40 and 41 have closed and have actuated microswitch 46 to closed position (DR_F); or,

(3) the last commanded signal was forward (C), the forward contact microswitch 46 is closed (DR_F), a reverse direction is now commanded (A) and the motor speed is above 120 rpm (

; or

(4) the last commanded signal was reverse

(C), the reverse contact microswitch 47 is closed (DR_R), a forward direction is now commanded (B) and the motor speed is above 120 rpm

.

The V_FE signal is combined with the L and H signals by NAND gate 185, whose output, V_FO, will be low if V_FE is high and the field current is below maximum reference (H) and if the armature brake current level is less than the allowable braking reference (L) .

The DR_F and DR_R signals are combined by NOR gate 186, whose output will be low if either the DR_F or DR_R signal is present. If both the output of gate 186 and the V_FO signal are low, the output of NOR gate 187 will be high. This output is combined with the Vwr signal from FIG. 10, and when both are high the output of NAND gate 188, V_FI, will be low.

The V_FI signal, when low, is used in FIG. 11 to allow the main SCR for the field, SCR_MF, to be turned on and off to supply power to the field. If the field inhibit signal V_FI goes high, SCR_MF will be inhibited from turning on.

Also in FIG. 9, the deceleration signal ACC_OO is combined with the signal by NAND gate 190 whose output is inverted by logic inverter 191 to produce a deceleration command signal V_DEC, which signal will be high if the demanded/actual speed count from counter 105 (FIG. 4) is below 24 and the motor speed is above 120 rpm (

high). Otherwise, V_DEC will be low.

A plugging condition, i.e., when the motor is being powered in one direction and the opposite direction is commanded by the operator by movement of lever 24, is indicated as follows. The B, C, A and signals are combined by NAND gates 192, 193 and 194. If a plugging situation does not exist, i.e., if the motor is operating in a forward direction (B) and the last commanded direction is forward (C), or if the motor is operating in a reverse direction (A) and the last commanded direction is reverse

, the signal

will be high. If the motor is being operated in one direction and the opposite direction is commanded, signal will go low. Logic inverter 195 thus causes signal V_PG to be high when a plugging condition exists, this signal being used in FIG. 4 to close transmission gate 196 and ground V_CLB during plugging. The deceleration and plugging signals V_DEC and V_PG are both applied in FIG. 9 to NOR gate 197, whose output

, will be operatively low if either input is high. The low output signal is used in

FIG. 10 to turn on the braking oscillator F_BRR for the regenerative and braking SCR's, SCR_RB and SCR_B during plugging or deceleration.

The plugging and deceleration signals V_PG and V_DEC are also used in FIG. 9 to generate a high signal during either plugging or deceleration.

The V_DEC signal is applied to NOR gate 198, so that when the V_DEC signal is high, the output of gate 198 will be low and be inverted to high by logic inverter 199. If either V_DEC or V_PG is high, the output of NOR gate 200 will go low and be inverted to a high

signal by logic inverter 201. The high signal is

used in FIG. 11 to boost the pulse frequency and pulse width of the oscillator for the main field SCR, SCR_MF.

A high signal is also produced by combining

the K and T signals. When both of these signals are low, i.e., when there is excessive armature power current at speeds below 1920 rpm, the output of NOR gate 202 will go high, causing the output of NOR gate 198 to go low. Again, such low signal will be inverted and applied to NOR gate 200 so that its output will go low to produce an inverted high signal.

Thus, a high, and operative,

signal will be produced if the motor is plugging, or decelerating, or if there is excessive armature power current at motor speeds below 1920 rpm.

FIG. 9 also includes logic circuits for producing or inhibiting the production of a high V_AO signal. This signal, when high, is used to turn on the pulse generator for the main armature SCR_MA When the V_AO signal is low, the pulse generator is inhibited from operating.

Signals A and B are applied to NOR gate 203 whose output will be low if either a forward or reverse direction is being commanded by the operator. The output of gate 203 and the E signal are applied to NOR gate

204 whose output, V_CLC will be high if a direction is being commanded and if the field current is above minimum reference. (The high V_CLC signal is used in FIG. 6 to reset counter 161 and flip-flop 162 when the motor speed increases to more than 240 rpm and signal W goes low).

The V_CLC signal is inverted by logic inverter

205 and combined with signal D (high when the motor speed is less than 120 rpm) by NAND gate 206. The output of gate 206 is combined with signal F (high when the accelerator switch 27 is closed), and

by NAND gate 207, whose output is fed to NOR gate 208. The output of gate 198 is combined with the V_FE signal by NAND gate 209 whose output is also fed to gate 208, The V_CBT signal (used to open circuit breaker contacts 35 and 37) is also applied to gate 208. The output of gate 208 is signal V_AO, which will permit operation of the main SCR for the armature, SCRw., when the V_AO signal is high. The V_A0 signal will be high if all of the following conditions exist:

(1) The circuit breaker trip signal, V_CBT, is low (as it will be normally unless a malfunction exists, as described in connection with FIG. 7) ;

(a) the supply voltage V_S2 is not present;

(2) a high field enable signal, V_FE, has been produced; (3) the motor is not decelerating, i.e.,

V_DEC is low;

(4) the armature power current is less than maximum reference (K is high) while the motor speed is below 1920 rpm (T is low);

(5) plugging is not called for, i.e.,

is high;

(6) the accelerator switch is closed (F is high); (7) the field current is above minimum reference (E is low) and a direction is being commanded (A or B is high). If any one of these seven conditions is not met, then the V_AO signal will be low and the main SCR for the armature will be prevented from firing. FIG. 10 discloses the armature pulsing circuitry.

In general, the circuits of FIG. 10 are used to control the operation of the SCR's associated with the armature, both in power mode and in braking. In the power mode, and at motor speeds below 1920 rpm, the armature current is controlled by repeatedly turning the main armature SCR_MA on and off to vary the average power current through the armature. If acceleration is not being demanded, the rate at which the SCR_MA is turned on is dependent upon the degree of operatordemanded speed and the SCRw. will remain in conduction for a fixed length of time each time it is turned on. If acceleration is being demanded, the rate at which the SCR_MA is turned on will be boosted and the time of conduction will be lengthened, such boosting and lengthening being a function of the degree of demanded acceleration . In the power mode and at motor speeds above 1920 rpm the main SCR_MA will remain in continuous conduction and the speed of the motor will be controlled by varying the field current with the circuits of FIG. 11.

The circuits of FIG. 10 function in the braking mode to inhibit the turning on of the main SCR_MA and to turn on the regenerative braking SCR_RB if the motor speed is above 1920 rpm or to turn on the resistive braking SCR_B if the motor speed is below 1920 rpm. A one-second delay is provided before the resistive braking SCR_B is turned on to ensure against both SCR_RB and SCR_B being in conduction at the same time.

The circuits of FIG. 10 further function when the motor comes out of a braking mode and returns to a power mode to turn on the commutating SCR_CA and commutate the resistive braking SCR_B before the main SCR is turned back on. The basic operation of the power mode circuitry starts with the operator demand signal V_OD from FIG. 3, the voltage of which is proportional to the setting of the accelerator-pedal-controlled variable resistor 75. This signal is passed through an RC filter (resistor

220 and capacitor 221) and applied to the voltage-controlled oscillator 222 to produce a frequency signal F_ADI proportional to the operator demand. Resistor 220 and capacitor 221 are used for jerk control to allow a gradual increase of the voltage applied to VCO 222 in the event the magnitude of signal V_OD is suddenly increased by an abrupt depression of the accelerator pedal by the operator.

The frequency signal F_ADI is downcounted by counter 223 and NAND gate 224 to produce frequency signal F_AD which is also proportional to the degree of the operator demand signal V_OD. The F_AD signal clocks flipflop 225 to generate trigger pulses being then applied to the trigger input of monostable multivibrator 226 (MONO 2).

Monostable multivibrator 226 (as well as the other monostable multivibrators hereinafter identified) will produce a single pulse in response to each trigger pulse applied thereto, the length of the monostable pulse being dependent on the values of the external capacitor and resistors connected to terminals 1, 2 and 3 of the monostable, i.e., capacitor 227 and resistors 228-232. In the monostable mode, positive-edge triggering is accomplished by application of a leading-edge pulse to the "+T" input and a low level to the "-T" input. For negative-edge triggering7 a trailing-edge pulse is applied to the "-T" input and a high level is applied to the "+T". Input trigger pulses may be of any duration relative to the output pulse. The monostable can be retriggered, on the leading edge only, by applying a common pulse to both the "+T" and "RT" inputs. In this mode the output pulse, at Q, remains high as long as the period between the leading edge of consecutive trigger pulses is shorter than the pulse period of the monostable as determined by its RC components. In the period between monostable pulses, its Q and

outputs will be low and high, respectively. Such monostable multivibrators as described and used herein are commercially available, as for example, the RCA series CD4047A COS/MOS Low-Power Monostable/Astable Multivibrator.

When the monostable 226 is triggered by a pulse fτom flip-flop 225, its Q output goes high and passes through logic gates 233 and 234 to form signal GA_LA which is passed to FIG. 12 for amplification and then to FIG. 2 for gating the charging SCR, SCR_LA, for the armature into conduction to enable the commutating capacitor C_CA to charge when SCR_MA conducts.

When monostable 226 is triggered, its Q output goes low and passes through delay circuit 235 and logic gate 236 to form signal GA_MA which is passed to FIG. 12 for amplification and then to FIG. 2 for triggering the main SCR, SCR_MA, for the armature into conduction. With SCR_MA now conducting, commutating capacitor C_CA can charge and current can flow from the battery through the armature.

When the pulse of the monostable 226 has timed out, the now high, but delayed, Q output passes through an RC circuit (Resistor 237 and capacitor 238) and NOR gate 239 for trailing-edge triggering of monostable

240 (MONO 3). (The first downcounteά. pulse F_AD passes through transmission gate 241 and NOR gate 239 to monostable 240). Monostable 240 generates a fixed length pulse for each triggering thereof. The Q output, which goes high during the duration of the pulse, forms signal GA_CA which is passed to FIG. 12 for amplification and then to FIG. 2 for triggering of the commutating SCR, SCR_CA, for the armature. The length of the monostable pulse should be such that normal commutation of SCR_MA will occur before the pulse ends.

Signal

and delayed signal are obtained

from the

output of monostable 226, these signals being high in the period between the end of a pulse and the beginning of the next pulse of monostable 226. Similarly, signal

is obtained from the

output of monostable 240, this signal being high in the interpulse period of monostable 240. These signals are used in FIG. 7 in the generation of a misfire signal in case the main SCR_MA fails to commutate. Capacitor 242 and resistor 243 are connected between supply voltage V_S2 and ground to produce a reset voltage signal R upon initial start-up, which signal is used to reset monostables 226 and 240 and the monostables in the field pulsing circuitry (FIG. 11). In the basic operation described above, monostable 226 will pulse, and the main and charging SCR's for the armature will be gated on at a rate proportional to the degree of operator demand. As V_OD increases, the pulse rate of monostable 226 will increase, and vice versa. The on-time of the main SCR_MA will be substantially the same as the pulse duration of monostable 226 since the commutating SCR_CA is not gated on by monostable 240 until the end of the pulse of monostable 226. Conduction of SCR_MA is thus dependent upon the pulse frequency and. pulse length of monostable 226.

The pulse frequency and pulse width of monostable 226 is affected by the acceleration signals produced in FIG. 4 in response to a difference between actual motor speed and demanded speed. In the upper left corner of FIG. 10 the acceleration signals ACC₁, ACC₂, ACC₃ and ACC₄ are applied to transmission gates 245, 246, 247 and 248 to close these gates when the acceleration signals are high and thereby connect the supply voltage V_S2 through one or more of the weighted network of resistors 249, 250 and 251 and thereby cause a boosting of the voltage input into VCO 222 so that the frequency F_ADI is increased beyond that demanded by signal V_OD. This increases the pulsing rate of monostable 226 during acceleration, with the pulse rate being increased proportionally to the degree of acceleration being demanded.

The pulse length of monostable 226 is dependent upon the resistance values of resistors 228-232. When the motor speed is below 1920 rpm, signal

will be high, and transmission gate 255 will be closed. If no acceleration is called for, the

and

signals will all be high, closing transmission gates 256, 257 and 258, thereby connecting resistors 230, 231 and 232 in parallel with resistor 228. If acceleration is called for, so that one or more of the ,

or signals goes low, its transmission gate

will open, resulting in an increase in resistance between terminals 2 and 3 of monostable 226 and a longer pulse length of the monostable. As a consequence, when acceleration is demanded the acceleration signals increase both the pulse frequency and pulse length of the monostable and thereby increase the amount of current flowing to the armature through SCR_MA beyond that called for by the operator-demand signal. When the motor speed increases to above 1920 rpm, gate 255 opens, to increase the pulse length whether or not acceleration is demanded.

Signals K, T and M are combined by NOR gates 260 and 261, the output of gate 261 being inverted by logic inverter 262 and applied to transmission gate

263, which when closed connects resistor 229 in parallel with resistor 228 to lower the resistance and decrease the pulse duration. If an armature current limit level is reached while the motor speed is below 1920 rpm (K/T is high) or if the demanded speed is less than creep speed reference (M) then transmission gate 263 will be closed to reduce the width of the then existing pulse. If the motor speed is above 1920 rpm, gates 255 and 263 will both be open, leaving resistor 228 alone connected in the external circuit of monostable 226. Resistor 228 is sized so that when it alone is in the circuit, the pulse length of monostable 226 is sufficiently long relative to the frequency of the trigger pulse from flip-flop 225 at this speed that the monostable operates in its retTigger mode, i.e., the

output remains high and the Q output remains low. In such mode, the commutating SCR_CA does not fire and the main SCR_MA remains on continuously so that full battery power is applied to the armature and no commutating power is lost. As may be seen from the foregoing, the single monostable 226 provides great flexibility in the control of armature current. The leading edge of the output pulse is used to gate the main SCR_MA into conduction, while the trailing edge of the pulse is used (by monostable 240) to commutate the main SCR_MA. The pulse rate and pulse width of the monostable are independently controllable so that the rate at which the main SCR_MA is gated on is controlled by this monostable as well as the length of time that SCR_MA remains in conduction each time it is gated on. In addition, the monostable can be put into retrigger operation for continuous current flow to the armature.

In the braking mode, i.e,, when deceleration or plugging is being commended, signal will be low.

This signal is combined with signals GA_MA, GA_CA and signal

by NOR gate 265 whose brake enable output, , will be high if all inputs are low will be low

when the armature power current decays below minimum reference value). If signal

is also high (motor speed above 120 rpm), the output of NAND gate 266 goes low to initiate oscillation of the gated oscillator circuit which includes NOR gate 267 and inverter 268. The oscillator generates a control frequency for braking, F_BRK, of approximately 200 Hz, which is applied to NOR gates 269 and 270. If the motor speed is above 1920 (the speed at which the emf is sufficient to charge the battery), signal

will be low and the F_BRK pulses will pass through gate 269 as signals GA_RB which are passed to FIG. 12 for amplification and then to FIG. 2 to gate the regenerative SCR, SCR_RB, into conduction.

When the motor speed drops below 1920 rpm, signal

will go high to prevent F_BRK pulses from passing through gate 269. Signal T will go low to allow the F_BRK Pulses to pass through gate 270, and through NAND gate 271 and delay circuit 272 to form signals GA_B.

These signals are passed to FIG. 12 for amplification and then to FIG. 2 to gate SCR_B, into conduction.

Also, if the signal is low and the motor

speed is below 1920 rpm (T is low), the output of NOR gate 275 will go high to clock the voltage at the D input of flip-flop 276 through to its Q output, which will pulse high if the D input is high and thereby trigger monostable 277 (MONO 5). The speed signal D is applied to the D input of flip-flop 276 so that the flip-flop will only pulse high if the actual speed is greater than 120 rpm. This monostable produces a fixed-length pulse of approximately one second duration. The Q output, which goes low for the one-second time, is applied to NAND gate 271 to provide a one-second delay between the time that the GA_RB, signals cease and the GA_B, signals start, to ensure against simultaneous conduction of SCR_RB and SCR_B.

The Q output of monostable 277 is applied to the inhibit input of VCO 222 to inhibit operation and ground the output of VCO 222 during the one-second pulse of monostable 277. The G signal, high when the actual motor speed is above top reference speed, is used at such time to reset counter 223 and maintain it reset so that no F_AD pulses are produced and the monostable 226 is thereby inhibited from pulsing until the actual speed reduces to below the top reference speed.

Signals U and are combined by NOR gate

280 to apply a set pulse to flip-flop 281 when signal U is low (demanded speed is greater than actual speed) and signal is low (monostable 240 is pulsing).

Without this set pulse, the Q output of flip-flop 281 will be low, and the input to NOR gate 282 will be low. The Q output of flip-flop 281 is inverted by logic inverter 283 and applied to NOR gate 284, so that when the Q output of flip-flop 281 is low the output of gate 284 is low and flip-flop 225 is inhibited from operating. When the signal V_AO goes high, it will be inverted by logic inverter 285 and applied to gate 282 so that the output of gate 282 will go high to close transmission gate 241. The first F_AD pulse can thus pass through gate 241 and cause monostable 240 to generate a pulse. During this pulse, signal goes low, so that the

output of gate 280 goes high to set flip-flop 281 so that its Q output goes high. The high output of flip-flop 281, inverted by inverter 283, together with the low inverted V_AO signal causes the output of gate 284 to go high and thereby enable flip-flop 225 to begin generating trigger pulses for monostable 226. If the high signal V_AO should not be present, the output of gate 284 will be low and will maintain the output of flip-flop 225 low to thereby prevent pulsing of monostable 226. Signals A, B, J and U are combined by NOR. gate 286, inverter 287, and NAND gates 288 and 289 to deliver a reset pulse to flip-flop 281 in case the operator shifts into neutral (A and B both low) or in case the demanded speed is less than actual speed (U) and the armature current falls to below minimum reference (J). When flip-flop 281 is reset, its Q output goes low, inhibiting operation of flip-flop 225 and conditioning gate 282 to open transmission gate 241 the next time a V_AO signal is generated, The J, U and

signals are applied to NOR gate 290 to close transmission gate 291 and thereby connect the +T and retrigger inputs of monostable 226 when all of the J, U and signals are low, i.e.,

when the armature power current is greater than minimum reference level, when the demanded speed is greater than the actual speed, and when the motor is operating in a power mode. With the inputs so conencted, monostable 226 is allowed to operate in the retrigger mode. If any of the J,U or signals are high, transmission

gate 291 will open and monostable 226 will be taken out of retrigger mode operation. The

_E signal, high during braking, is used to take monostable 226 out of retrigger mode to prevent a lockage condition, wherein the monostable 226 stayed on even though the input pulses thereto were resumed during braking. Disconnecting the retrigger input from the +T input at such time alleviates such lockup.

The VDE signal, when high, i.e., when the motor speed is less than 120 rpm and the field current is less than minimum reference, will close transmission gate 292 and allow jerk capacitor 221 to discharge through resistor 293 so thatjerk control is provided on the next acceleration.

FIG. 11 discloses the field pulsing circuit. In general, the field is controlled in power operation by varying the field excitation as an inverse function of the demanded and actual speeds, i.e.,

Thus, if either (or both) the demanded or the actual speed increases, the field is weakened,

Contrarily, if either decreases, the field is strengthened.

In more particular, the excitation of the field is varied by controlling the field current as an inverse function of the demanded and. actual speeds. Since the demanded speed signal T₁ from FIG. 3 is inversely proportional to the degree of the operatordemanded speed and since the actual speed signal F_AMI from FIG. 4 is directly proportional to the actual speed of the motor, field excitation is controlled as follows:

In the particular embodiment shown herein, the frequency of the F_AMI signal is substantially higher than the frequency of the T₁ signal and a count is repeatedly obtained which is proportional to the number" of cycles of the F_AM1 signal occurring during each cycle of the T₁ signal. The field current is then regulated so that it varies inversely with the magnitude of such count. In addition, the field pulsing circuit provides automatic field weakening in the event acceleration is demanded and automatic field strengthening in case of excessive armature power current. In the braking mode, the field pulsing circuit functions to maintain the armature brake current at the maximum permissible brake current limits.

Basic operation of the field pulsing circuits is as follows. The T₁ pulses from FIG. 3 pass through logic inverter 301 and delay circuits 302 and 303 to the reset input of binary counter 304, so that the counter is reset at a rate inversely proportional to the demanded speed. The T. pulses also act through NOR gate 305 to close transmission gate 306 so that the F_AM1 pulses (proportional to actual motor speed) can pass therethrough to the counter. With this arrangement, the count in counter 304 will be a function of the demanded speed and the actual motor speed. If the demanded speed increases while the actual motor speed remains the same, the T₁ frequency will decrease so that more F_AM1 pulses are counted for each T₁ pulse. As the motor speed increases, more F_AM1 pulses will be counter for each T₁ pulse. Contrarily, if the demanded speed is reduced and/or the actual motor speed is reduced, the count in counter 304 will decrease. The four highest counter outputs are combined by NAND gates 307 and 308 and NOR gate 309 and fed back to NOR gate 305 to prevent counter overflow. The second through seventh outputs of counter

304 are continuously applied to the inputs of shift register 310, the inputs being clocked to the outputs

thereof by the delayed T₁ pulse if acceleration is being demanded or if the system has just come out of a braking mode and has returned to power mode, as follows. The ACC₁, ACC₂, ACC₃ and ACC₄ signals are all applied to NOR gate 310a whose output will go low if any one of the acceleration signals is high. This in turn causes NAND gate 310b to output a high to the D input of flipflop 310c. As a consequence each delayed T₁ pulse will clock the high D input of flip-flop 310c to the Q output thereof to thereby clock shift register 310. Thus, when in the power mode, the shift register 310 will be continuously clocked as long as acceleration is demanded. When the actual speed increases sufficiently near the demanded speed such that the acceleration signals all go low, clocking of shift register 310 will stop, and the

outputs will remain latched at the last clocked state until such time as acceleration is again demanded and the shift register is newly clocked.

The shift register 310 is also clocked once after return of the system to power mode from a braking mode. During braking, the demanded and actual speeds will have decreased so that the count in counter 304 will have increased. During such time the

outputs of shift register 310 will not have changed, since no clock pulse has been applied thereto. Referring to the previous description of FIG. 10, when the system returns to power mode from braking operation the output of NOR gate 282 will go high and then low after the first F_AD pulse. The output of NOR gate 282 is inverted in FIG. 11 by logic inverter 310d and momentarily causes gate 310b to output a high to flip-flop 310c. The next T. pulse can then clock shift register 310 so that the increased count at the inputs thereof are clocked to the outputs. NOR gate 282 then goes high and shift register 310 will not then be clocked again until such time as acceleration is demanded.

Since the

outputs of shift register 310 are used, the binary count at the inputs will be inverted at the outputs. The latched and inverted count is applied to the R/2R resistor network 311 for digital-to-analog conversion. The output voltage of network 311 is applied to the voltage divider comprised of resistors 312, 313, 314 and 315, and then through a negative jerk filter comprised of resistor 316 and capacitor 317 to the input of voltage-controlled oscillator 318. VCO 318 thus oscillates and produces pulses F_D1 at a frequency which varies inversely with the count in counter 304, i.e., inversely with the operator demanded speed and actual motor speed.

The digital-to-analog conversion network 311 utilizes six inputs from register 310 and thus provides sixty-four discrete steps of conversion so that the incremental change of output voltage is relatively small, for smoother operation, as the count increases or decreases.

The output of the digital-to-analog R/2R network 311 is also used as the source of the F_CLA signal which is used in FIG. 6 to set the frequency of the armature power current limit signal F_CLA as an inverse function of the count in counter 304. Resistors 312 through 315 are sized relative to those of the R/2R network 311 so as not to load the output of the R/2R network.

The F_D1 pulses from VCO 318 clock flip-flop

319 to provide trigger pulses to monostable multivibrator

320 (MONO 1). As before, the monostable 320 will produce one pulse for each trigger pulse applied thereto, the length of the pulse being dependent upon the values of capacitor 321 and resistors 322 and 324-331 in the RC circuit of the monostable.

The normally high

output of monostable 320 is fed to monostable multivibrator 332 (MONO 4), having a fixed length pulse, so that the end of the pulse of monostable 320, monostable 332 will generate a pulse. The

output of monostable 320 and the Q output of monostable 332 are combined by NOR gate 333 so that each time monostable 320 pulses a high signal GA_MF/LF is produced at the output of gate 333, which passes to FIG. 12 for amplification and then to FIG. 2 to gate the commutating SCR, SCR_CF, for the field.

The operational states of monostables 320 and 332 are indicated by the and signals taken

from the

outputs, these signals being high during the interpulse periods of the monostables.

As described above, the pulse frequency of monostable 320 is inversely proportional to the demanded and actual motor speeds, so that the main field SCR_MF will pass less current and thereby provide field weakening at high speeds. Conversely, field strengthening is provided at low speeds.

The pulse frequency of monostable 320 is also automatically increased if the armature power current is excessive or if the system is in a regenerative braking mode. The

T, and signals are logically

combined by NAND gate 336, inverter 337 and NOR gate 340, so that if there is excessive armature power current (K is high) or if the system is in regenerative braking (T, and are all high) the output of NOR gate

340 will go low. Such low is inverted by logic inverter

341 and closes transmission gate 342 to apply supply voltage V-2 to the junction of resistors 313, 314 and 316 and thereby boost the voltage applied to VCO 318, raise the frequency of the pulses to the main field SCR_MF and cause the field to be strengthened.

The highest

output of shift register 310 is applied to transmission gate 343. When this gate is closed, resistor 313 will be shorted out so that the amount of the output from the R2R output applied to VCO 318 is boosted to cause field strengthening. The voltage divider network of resistors 312-315 is also affected by transmission gate 344 which will short out resistor 315 when the output of NOR gate 345 is high, i.e., when both of the signals

and

are low. If the motor speed is below 480 rpm (3 is high) or if in a plugging or decelerating mode (Vwp is high) , gate 344 will open, putting resistor 315 in series with resistor 316 to boost the voltage to VCO 318 and cause field-strengthening. If the motor speed is above 480 rpm in a power mode (and the armature current is not excessive at speeds below 1920 rpm), gate 344 will close to short out resistor 315 and reduce the input to VCO 318 for field-weakening. The V_M5 signal (high during the one-second pulse period of monostable 277) is used to close transmission gate 346 to allow the negative jerk capacitor 317 to discharge through resistor 347 during that period. The V_FI signal from FIG. 9 is applied to VCO 318 and flip-flop 319 to allow operation thereof when the V_FI signal is low and to inhibit operation when the V_FI signal is high. As will be described in more detail hereinafter, when the system is in a power mode, signal V_FI will normally be continuously low so that the field will be continuously pulsed. When operating in a braking mode, the V_FI signal will be low or high primarily in dependence upon whether the armature brake current is below or above the maximum allowable limit set by the F_CLB signal, and the V_FI signal will thus control the operation of the VCO 318, flip-flop 319 and monostable 320 to maintain the armature brake current at the F_CLB level.

As mentioned above, monostable 320 has a plurality of resistors 322-331 in its external RC circuit, these resistors being provided to enable the pulse length of the monostable to be varied,

The four highest outputs of counter 304 are logically combined by NOR gate 350, NAND gates 351 and 352 and logic inverters 353 and 354 and applied to the inputs of shift register 355, At the same time, the latched

outputs of shift register 310 are logically combined by NAND gate 356, inverter 357, and NOR gate 358 and applied to the input of shift register 355, the inputs to shift register 355 being latched in the Q outputs by the clock pulse from the output of flipflop 310C. The Q outputs of shift register 355, and the highest Q output of shift register 310 (inverted by inverter 359) are applied to transmission gates 360, 361, 362 and 363. These gates, when closed, will connect resistors 326, 327, 328 and 325 in parallel with resistor 322 to decrease the resistance and shorten the pulse length. The higher the actual motor speed and/or the demanded speed, the shorter the pulse length of monostable 320 so that the field is progressively weakened. Thus, the count of counter 304 is used to provide high pulsing frequencies and longer pulses at low speeds (resulting in high field currents) and low pulsing frequencies and shorter pulses at high speeds (resulting in low field currents). The acceleration signals ACC₁, ACC₂ , ACC₃ and ACC. are applied to transmission gates 365, 366, 367 and 368 respectively so that resistors 329 and/or 330 may be shorted out. The higher the demanded acceleration, the shorter the pulse width of monostable 320 and the lower the field current.

The output of NOR gate 340, which (when inverted) is used to operate transmission gate 342 and thereby affect the pulse frequency, is also used to operate transmission gate 369 and thereby affect the pulse length. If the system is neither in a regenerative braking mode nor in an armature current limit condition, transmission gate 369 will be closed, shorting out resistor 324. If in a current limit condition, or if in a regenerative braking mode, transmission gate 369 will open, placing resistor 324 in the timing circuit. This will increase the resistance and provide a longer pulse duration so that the field current is increased.

FIG. 12 illustrates the gate pulse amplifiers which isolate the control circuits from the power circuits and which develop the actual pulses used to gate the SCR's on.

Gate pulse amplifier 380 utilizes three transistors 381, 382 and 383 all of which are off when the input signal GAw. from the armature monostable 226 (FIG. 10) is low, allowing capacitor 384 to charge to supply voltage V_S1 through resistor 384a. When the signal GA_MA goes high, all three transistors turn on, allowing capacitor 384 to discharge through the primary of pulse transformer 385 and transistor 383, causing the secondary to apply a pulse across the gate and cathode of the main armature SCR_MA and gate it into conduction.

Similar three-transistor amplifiers 386 and 387 develop gate pulses G_CA and G_RB when signal GA_CA and GA_RB are applied thereto. Gate pulse amplifier 390 utilizes two transistors 391 and 392 which are turned on by a high GA_LA signal to allow capacitor 393 to discharge through transistor 392 and the primary of pulse transformer

394. The resulting pulse G_LA from the transformer secondary will gate SCR_LA into conduction.

In the same manner, two-transistor amplifiers

395, 396, 397 and 398 will develop gate pulse G_B, G_MF, G_LF, and G_CF when signals GA_B, GA_MF, GA_LF and GA_CF are applied thereto. Returning to FIG. 7, this figure illustrates the portion of the control logic used to generate the circuit breaker trip signal V_CBT. This signal, when high, is used in FIG. 2 to cause trip coil 36 to open contacts 35 and 37 and remove power from the armature 20 and field 21. Also, as explained in connection with FIG. 9, when the V_CBT signal is high, it will prevent the V_AO signal from being high and will thereby inhibit the armature pulsing circuitry of FIG. 10,

Referring to FIG. 7, the output of NAND gate 405 will be low (for normal operation), providing all of the inputs thereto are high. If any input is low, a high V_CBT signal will be generated, A transient suppression filter 406 is provided at the output of gate 405 to prevent spurious generation of a high V_CBT signal. The first condition monitored by this circuit utilizes the DR_F, DR_R, F and J signals, these signals being logically combined by NOR gate 407, inverter 408 and NAND gate 409, It has been found from vehicle operation that electrical transients can cause the main SCR, SCR_MA, for the armature to be turned on when the accelerator switch 73 is open and the field is not connected. To safeguard against such an event, the output of gate 407 will be high if the field is not connected (the microswitch signals DR_F and DR_R will be both low) while inverter 408 will output a high if the accelerator switch is open. If the main SCR_MA does happen to be gated into conduction, as soon as the armature current increases beyond the minimum reference value (set in FIG. 6) , signal

will go high causing gate 409 to output a low to gate 405. Gate 405 will then output a high V_CBT signal which will cause the circuit breaker to trip and disconnect the armature from the battery.

A second condition monitored by NAND gate 405 is the logical combination of the A and B signals applied to NAND gate 410. Under normal circumstances only one of these signals will be high. If a malfunction causes both to occur simultaneously, a high V_CBT signal will be generated,

A third condition resulting in the generation of a high V_CBT signal is a "misfire" of the main armature SCR_MA, i.e., a failure of this SCR to commutate. As brought out previously, such misfire is sensed by monitoring the conduction state of SCR_MA and generating a V_AM signal in response thereto. The V_AM signal is low if the SCR_MA is conducting and high if it is not. NAND gate 411 is used herein to see if the SCR_MA is conducting at a time when it should be off. If so, the gate 411 will output a low, a situation which will occur if all of its inputs are simultaneously high. FIG. 17 illustrates the time sequence of the conditions which affect gate 411. Each time flipflop 225 (FIG. 10) delivers a trigger pulse to the armature monostable 226, the monostable will pulse for a length of time determined by capacitor 227 and its associated resistors. During this time its Q output goes low to produce a low

signal. The signal is delayed to form a low signal. The beginning of the

pulse is used to gate on the main SCR_MA while the end of the pulse is used to trigger the commutating

monostable 240. The high Q output of monostable 240 is used to gate on the commutating SCR_CA, and the

output goes low during the pulse period.

The

and signals are all applied

(FIGS. 7 and 17) to NAND gate 411. As is noted, one or more of these signals will be low during the time from the beginning of the pulse of the armature monostable 226 until the end of the pulse of the commutating monostable 240, and thus NAND gate 411 cannot have a low output during such time. However, during the time from the end of the monostable 240 pulse until the beginning of the next pulse of monostable 240, all three of the and signals will be high. As a

consequence a "window" in time is provided, for the period that all three signals are high, in which to see if the main armature SCR_MA is in conduction or not. The V_AM misfire signal is combined in FIGS. 7 and 17 with signal J by NOR gate 412, the output of which is applied to NAND gate 411. The misfire circuit is not to produce a misfire signal if the armature power current is below minimum reference level. If the current is below such level, the signal J will be high and will inhibit NOR gate 412 from outputting a high. If the power current is above minimum, the output of NOR gate 412 will depend upon whether the V_AM misfire signal is high or low. If the main armature SCR_MA is conducting, gate 412 will output a high to NAND gate 411, and vice versa.

In a normal cycle of operation, the main armature SCR_MA will be gated on shortly after the beginning of the monostable 226 pulse and will be commutated during the pulse time of monostable 240. As a consequence, in normal operation, SCR_MA will be off during the entire time of the window provided by the

and signals. With SCR_MA off and the armature misfire

signal V_AM high, NOP, gate 412 will have a low output to maintain NAND gate 411 with a high output.

In the event of a failure of SCR_MA to commutate, the Vw, signal will stay low and the output of NOR gate 412 will remain high during the immediately succeeding time window. Since this high input to gate 411 will no\tf have time coincidence with all of the high inputs of the and signals, the output of NAND

gate will go low. In turn, this causes the output of NAND gate 405 to go high so that the circuit breaker trip signal V_CBT is generated.

When the motor is operating at speeds above 1920 rpm and the SCR_MA is in continuous conduction, the armature misfire signal V_AM will be continuously low and the output of NOR gate 412 will be continuously high. However, such continuous high from gate 412 will not cause a Vp_BT signal to be generated because, with the armature monostable 226 operating in retrigger mode, its

output (the and signals) will be contin

uously low and no time window is provided. If the armature monostable 226 is taken out of retrigger operation, e.g., by a U signal if operating above 1920 rpm or by being braked to below 1920 rpm and returned to power mode operation, a time window will again be provided to see if SCR_MA has failed to commutate. The present misfire circuit has a particular advantage in that the length of time from the occurrence of the misfire, a.e., the time that SCR_MA should have been commutated but was not, until NAND gate 411 goes low is quite short and independent of the length of the pulse of monostable 226, Thus, no matter how short or how long the pulse of monostable 226 is, a misfire condition can exist only for the portion of the fixed pulse length of the commutating monostable 240 that occurs after misfire and up to the end of the monostable 240 pulse. As soon as that pulse ends, goes high

and NAND gate 411 can go low to cause generation of the V_CBT signal. As a consequence, a misfire can be detected just as quickly when the SCR_MA is being operated by short pulses from monostable 226 as when it is being operated by long pulses.

The V_CBT signal is also generated in the event of a misfire of the main field SCR_MF by the use of NAND gate 413. In case there is a misfire of the main armature SCR_MA, as just described, it is desirable to generate the V_CBT signal immediately and gate 412 will do so by looking at the armature misfire signal V_AM through the first time window occurring after SCR_MA fails to commutate. A misfire of the main field SCR_MA is not as critical a malfunction and the present system will operate so that if, during a cycle of operation, SCR_MF should fail to commutate, it is allowed to remain in conduction for a next cycle of operation. If SCR_MF is successfully commutated in that cycle, the system will continue in operation. However, if SCR_MF still fails to commutate, the circuit breaker trip signal V_CBT will be generated.

The and signal from the Q outputs

of the field monostables 320 and 332 (FIG. 11) are applied to NAND gate 413 to provide a time window, during each cycle of operation, from the end of the commutating monostable 332 pulse until the beginning of the next pulse of monostable 320, signals and being both

high during such time. The

signal is also used, to inhibit generation of a V_CBT signal if the field current is below minimum reference value,

being low at such time.

The field misfire signal V_FM (high if SCR _MF is conducting and low if SCR _MF has been commutated) is applied to NAND gate 413 through delay circuit 414 comprised of resistor 415, capacitor 416 and buffer

417. During normal operation, with SCR _MF being gated on and then commutating during each cycle of operation, and with the misfire signal going high then low, capacitor 416 will charge and discharge through resistor 415. If the V_FM signal is high for a sufficiently long time, capacitor 416 can charge to a voltage sufficient to cause buffer 417 to output a high to NAND gate 413. The values of capacitor 416 and resistor 415 are chosen to provide a time delay between V_FM going high and the output of buffer 417 going high so that if SCR _MF should fail to commutate and V_FM remains high; the buffer will not go high until after the commutating portion of the next cycle of operation. If SCR _MF does commutate in the next cycle, capacitor 416 will discharge and the output of buffer 417 will remain low. If SCR _MF fails to commutate, and V_FM stays high, then buffer 417 will output a high. Thus, when the output of buffer 417 is looked at through the time window immediately following a misfire, it will appear that a mis'fire has not yet occurred. If the misfire condition still exists when the next time window occurs, the misfire condition will be seen and the V_CBT signal generated.

Generated Used in in Fig. Fixed Frequency Signals Fig.

5 F_B Base frequency (960 rpm) 5

5 2F_B Base frequency X2 (1920 5 rpm)

5 F_BM Base frequency/8 5 (120 rpm)

5 F_BM/4 Base frequency/32 (30 rpm) 6

5 F_BM1 Base frequency/4 (240 rpm) 5

5 F_BM2 Base frequency/2 (480 rpm) 5

10 F_BRK Braking frequency to gate 10 on SCR_B and SCR_RB (200 Hz) 6 F_CLA Frequency to establish 6 armature current limit reference 6 F_CLB Frequency to establish 6 armature current limit reference during braking 6 F_IAO Frequency to establish 6 armature current zero reference 6 F_IFMAX Frequency to establish 6 maximum field current reference 6 F_IFMIN Frequency to establish 6 minimum field current reference 4 F_RC Frequency to establish 4 creep speed reference 4 F_TSM Frequency to establish top 4 motor speed reference Generated Used in in Fig. Variable Frequency Signals Fig.

10 F _AD1 Proportional to operator- 10 demanded speed

4 F _AM Proportional to actual 4 motor speed × 64 4 F _AM1 Proportional to actual 5,11 motor speed 4 F _AM1D Proportional to actual 4 motor speed, delayed 4 F _AM1DD Proportional to actual 4 motor speed, double delayed 4 F _AM2 Proportional to actual 4 motor speed × 2 3 F _DM Proportional to operator- 4 demanded speed × 64

11 F _D1 Proportional to operator- 11 demanded speed and acceleration signals 6 F _IA Proportional to armature 6 current

6 F_IF Proportional to field current 6 3 T₂ Inversely proportional to 3 operator-demanded speed 3 T₁ Inversely proportional to 11 operator-demanded speed

^(T2/64⁾ Industrial Applicability

As brought out above, the system will function primarily in either a power mode or a braking mode. The power mode is the mode of operation wherein the armature is connected to the battery by SCR _MA and is driven by the battery. Power mode operations during acceleration, at demanded speed and during deceleration, are separately discussed below.

The system functions in a braking mode when the direction of the field current remains the same and the direction of armature current is reversed so that the counter emf of the motor provides a braking torque. The operator can choose to operate in either a "deceleration" or a "plugging" form of braking. Assume that the operator has commanded a forward dirction and the vehicle is operating in a power mode and travelling in that direction. If the operator desires "deceleration", he merely lets up on the accelerator pedal. Assuming a sufficient release of the accelerator pedal so that the system is taken out of the power mode, the system will go into a braking mode and the vehicle will be slowed down to the speed commanded by the new accelerator pedal position. The system will then return to power mode operation in the same direction at the lower speed. If instead the operator desires "plugging", he operates the direction control lever to command a reverse direction. (The position of the accelerator pedal may be left the same, increased or decreased). The system is immediately taken out of the power mode and put into the braking mode to brake the speed of the vehicle. When the speed has decreased to a low value, the direction of field current is reversed, the system is put back into a power mode and the speed of the vehicle in the reverse direction is brought up to the speed demanded by the setting of the accelerator pedal. When operating in either deceleration or plugging, the system will operate in a regenerative braking mode or in a resistive braking mode, depending upon the speed of the mehicle. If the speed is high enough to develop a counter emf sufficient to charge the battery, the armature is connected to the battery by the regenerative braking SCR, SCR _RB. If the motor speed is insufficient to charge the battery, the armature is shorted out by the resistive braking SCR, SCR.,, A "coasting" mode of operation is also described below wherein the vehicle is neither operating in a power mode nor a braking mode.

Start-up In order to start operation of the vehicle, the operator first closes the main switch 23 to obtain the supply voltages V_S1, V_S2 and V_S3 for the control system.

With the direction control lever 24 moved to command a direction, e.g., a forward direction, switch 70 will close (FIG. 3) causing voltage F_OD to generate the forward command signal B, This signal goes to FIG. 8, and through NAND gates 171 and 174 to generate the FWD signal. This latter signal goes to FIG. 2, is amplified and used to energize the forward coil 39 to close the forward contacts 40 and 41 and connect the field 21 to the power circuit. Microswitch 46 closes and sends signal DR_F back to FIG. 9, wherein it passes through NAND gates 181 and 184 to generate the field enable signal V_FE and also to NOR gate 186 so that signal V_FI will be low to allow the VCO 318 and flip-flop 319 in the field pulsing circuits, FIG. 11, to operate.

In FIG. 11, shift register 310 will not yet have been clocked and all of its

outputs will be high. The input to VCO 318 will also be high so that monostables 320 and 332 will begin pulsing. Battery current is thus supplied through SCR_MF and the forward contacts 40 and 41 (FIG, 2) to the field.

In due time, the field current rises above the minimum reference (e.g., 3 amperes) and signal E goes low (FIG. 6). The field current can continue to rise, but if it goes to the maximum reference level (e.g., 55 amperes) signal H goes high, and, in FIG. 9, will act on gate 185 to cause the field inhibit signal V_FI to go high and shut off the field pulsing circuit so that the field current will be held below the maximum reference level.

The field is similarly energized in the opposite direction in response to movement of the control lever 24 to reverse position. Power Mode -- Acceleration

The operator may now command foτward movement by depressing foot pedal 25. Assume the pedal is depressed halfway and held in such position.

In FIG. 9, the F signal, resulting from the closing of the accelerator switch 73, and the V_FE signals will generate the V_AO signal which, in FIG . 9 , is used to allow the armature pulsing circuitry to operate. (If the accelerator pedal had been depressed at the same time that the operator initially moved the control lever to forward position, signal V_AO would be delayed and would not go high until the field current had built up above minimum level, since a high E signal inhibits generation of the V_AO signal),

The position of the accelerator pedal 25 will determine the level of signal V_OD (FIG. 3) that is applied (FIG. 10) to VCO 222 and will thus determine the pulse rate of monostable 226 which is used to gate on the main SCR _MA for armature 20. In general, the moτe the accelerator pedal is depressed, the higher the level of armature current. Additionally, the operator demand voltage V_OD is used in FIG. 3 to generate frequency signal F_DM whose frequency is proportional to the degree of depression of the accelerator pedal. This frequency signal F_DM is compared in FIG. 4 to the frequency of signal F_AM which is proportional to the actual motor speed. Since the motor is initially at a standstill, F_DM is considerably greater than F_AM, and the acceleration signals ACC₁, ACC₂, ACC₃ and ACC₄ will be produced. In FIG. 10, these acceleration signals will artificially boost the input voltage to VCO 222 to increase the pulse frequency of monostable 226. Also, in FIG, 10, the now low inverted acceleration signals and

will close transmission gates 256, 257 and 258 to increase the pulse width of monostable 226. Thus, the acceleration signals will cause the armature current to be appreciably greater than that demanded in FIG. 10 by the operator demand signal V_OD alone.

Jerk capacitor 221 and resistor 220 allow the voltage applied to the input of VCO 222 to rise gradually so that the motor will accelerate smoothly.

During start-up, the actual and demanded signals

F_AM1 and T₁ will De low and high, respectively, and the counter 304 (FIG. 11) will have minimum count. The depression of the accelerator pedal will cause the frequency of the T₁ signal to decrease and the count in counter 304 to increase. The count is clocked through shift register 310 and inverted to decrease the pulse rate of VCO 318 and the field monostable 320. This will reduce the field current, thereby weakening the field and reducing the counter emf of the motor to enable its speed to increase. The acceleration signals ACC₁- ACC₄ are used to shorten the pulse width of monostable and provide further field weakening during acceleration. The actual speed of the motor is continuously monitored by speed pickup 65 and, as the speed increases, the frequency of the actual motor speed signal F_AM (FIG. 4) will increase proportionately.

In FIG. 5, the derivative F_AM1 pulses are continuously compared with the reference frequencies from fixed frequency oscillator 125 and counter 126 so that the relationship of the actual motor speed to the fixed reference speed points of 120, 240, 480 and 1920 rpm is known at all times.

In order to provide sufficient torque during initial acceleration, the § signal is used in FIG. 11 to open transmission gate 344 so that resistor 315 is in series with resistor 314, to provide a boosting of the input to VCO 318 and thus boost the field current. When the actual motor speed increases to 480 rpm signal will go low, causing transmission gate 344 to close and remove the boosting effect on the field.

During initial acceleration, VCO 155 (FIG. 6) will set a maximum power current limit level F_CLA which will allow the power current to rise to about 450 amperes. In the event the low speed load on the vehicle is high enough so that the vehicle cannot increase its speed at such armature power current level, transmission gate 158 will close, raising the frequency of the F_CLA signal so that the armature can operate with a maximum limit of about 600 amperes (the top rating of the motor). When the motor speed has increased to 240 rpm, the W signal will cause gate 158 to open and thus reduce the F_CLA. signal to normal.

During acceleration the actual motor speed signal F_AM is continuously compared with the operator demand signal F_DM on FIG. 4. Assuming that the accelerator pedal remains in its half-depressed position, so that the F_DM signal remains constant, then, as the motor speed and F_AM signal increases, the difference between the actual and demanded speed signals F_DM and F_DM becomes progressively less. The count in counter 105 progressively decreases, resulting in a progressive loss of the ACC₄, ACC₃, ACC₂ and ACC₁ acceleration signals .and a progressive reinstatement of high

and signals. The boosting of the frequency of

the armature monostable 226 (FIG. 10) by the ACC₄-ACC₁ signals and the boosting of the pulse width of the monostable will accordingly decrease as the actual motor speed increases. When all of the ACC₄-ACC₁ signals disappear, the armature monostable 226 will be controlled as a function of the V_OD signal from the accelerator pedal alone.

Additionally, when the ACC₃ signal is lost, gate 156 will open (FIG. 6) so that the armature power current limit signal F_CLA is controlled by the decreasing

V_CLA signal.

With respect to the field, and with the accelerator pedal held in its half-depressed position, so that the frequency of the T. signal remains constant, the increasing motor speed and derivative actual motor speed signal F_SM1 will cause the count in counter 304 (FIG. 11) to increase. With acceleration signals ACC₁- ACC₄ present, the increasing count of counter 304 will be clocked through shift register 310. The frequency of the pulsing of the field monostable 320 and the field strength will progressively decrease. In addition, the progressive loss of the acceleration signals ACC₄- ACC₁ will cause the transmission gates 365-368 to open and thus remove the artificial field weakening effect desired during acceleration.

When all acceleration signals ACC₁-ACC₂ 4ave been lost, shift register 310 will no longer be clocked and the count of counter 304 which was present when the last acceleration signal was lost will be latched (in inverted form) at the outputs of the shift register. The field strength is now set by the latched count. With the field monostable pulsing field strength now set in response to the latched inverted count of counter 304 and the armature monostable pulsing set by the operator demand signal V_OD, the speed of the motor will stabilize according to the torque demand on the motor.

For speeds below 1920 rpm, motor speed is controlled in response to the operator demand by setting the on-off ratio of conduction of the main armature

SCR _MA (by the V_OD control, of the armature monostable 226) and by setting the on-off ratio of conduction of the main field SCR_MF (by the F_AM1/T₁ control of the field monostable 320).

If the accelerator pedal had been depressed to demand a speed above 1920, the motor will accelerate in a manner as described above until the motor speed reaches 1920 rpm. At such time the speed comparison signal T goes low and opens gate 255 (FIG. 10), increasing the pulse width of the armature monostable 226 so that it operates in the retrigger mode with its Q and outputs continuously high and low, respectively. The main armature SCR _MA will now remain on continuously to supply full battery power to the armature.

With the armature now continuously connected to the battery, motor speed is controlled by varying the field strength alone. The count in counter 304 (FIG. 11) will continue to increase and be clocked through shift register 310 so that the field will continue to be weakened, for increased speed, until such time as the motor speed is sufficiently near the demanded speed so that the ACC₁ signal is lost.

If operating at a demanded speed above 1920 rpm, the operator may increase motor speed by a further depression of the accelerator pedal. With the frequency of the T₁ signal decreased, the count in counter 304 will increase. If the newly demanded speed is sufficiently high to generate an ACC₁ acceleration signal, the higher 304 count will be clocked through shift register 310 and will cause the field to be weakened. The speed of the motor will thus increase and eventually stabilize at a higher speed.

If operating at a demanded speed below 1920, the operator may also increase motor speed by further depressing the accelerator pedal. Such depression will raise the V_OD signal and increase the armature current. If the newly demanded speed is insufficient to generate an ACC ₁ signal, the field strength will remain the same and the speed will stabilize in accordance with the same field strength and the increased armature current. If an ACC₁ signal had been generated in response to the newly demanded speed, the increased count in counter 304 will be clocked through shift register 310 to weaken the field.

Power Mode -- Operation in the Event of Excessive Armature Current

In the event that the motor is operating in the power mode above 1920 rpm, and the armature current becomes excessive, i.e., the F_IA signal exceeds the F_CLA reference, signal

goes high, and, in FIG. 11, transmission gates 342 and 369 will close and open, respectively. This will immediately increase the pulse frequency and pulse width of the field monostable 320 to boost the field strength. The increased counter emf thus reduces the armature current which is flowing continuously through the armature. When the armature current reduces to below the current 1-imit level, signal will go low again, allowing normal operation of the field monostable to resume.

If operating at speeds below 1920, the excessive armature power signal also acts, as last described, to boost field strength. In addition, the K and T signals, in FIG, 10, are applied to gate 260 so that transmission gate 263 is closed. Gate 263 puts resistor 229 into the circuit and shortens the duration of the existing monostable pulse so that commutation of the main CR _MA is hastened. Otherwise, SCR _MA tvould continue to conduct for the full normal length of such pulse. In FIG. 9, the K and T signals are applied to gate 202, and will cause the V_AO signal from gate 208 to go low so that the armature monostable 226 (FIG. 10) will not be retriggered by flip-flop 225. When the armature current reduces to below the current level limit, the V_AO signal will be restored and normal operation of the armature and field monostables will resume.

Power Mode -- Degree and Rate of Acceleration In the present system, the circuits controlling the peak acceleration and the rate of acceleration are independent of each other, thereby enabling the system to be customized so that one can be varied without affecting the other. The degree of acceleration will depend upon the amount of armature current flow and peak acceleration is thus a function of the maximum allowable armatre power current during acceleration. Since the maximum allowable power current is set by the current limit signal F_CLA, the frequency of such signal can be set to whatever is desired by appropriate selection of the values of the external resistors of VCO 155 (FIG. 6).

The rate of acceleration is a function of the rate of change of the voltage applied to VCO 222 (FIG. 10), and this rate of change is dependent upon the value of positive jerk capacitor 221, jerk resistor

220 and the other resistors through which capacitor

221 charges when an increased operator demand signal V_OD is applied. The acceleration rate may be customized for a particular application by changing the value of the jerk resistor 220. Current-limiting operation, by the F_CLA signal and resultant signals K and K, is independent of the rate of acceleration. Signal K will go low when there is excessive armature power current, regardless of how slowly or how quickly such current has reached and exceeded the F_CLA limit. Likewise, the acceleration-rate control at the input of VCO 222 is independent of the current limit signal K. For given values of capacitor 221 and resistor 220, the rate of change of the input voltage to VCO 222 will be the same, regardless of the frequency of the F_CLA signal, or if the armature power current is excessive or not.

Power Mode -- Deceleration Normally, the system will be put into a braking mode in order to slow the vehicle. However, the present system allows a small degree of deceleration to occur while still remaining in the power mode. Such deceleration can be demanded by the operator by slightly letting up on the accelerator pedal, Although the new pedal position will result in a higher T₁ signal, such that the count in counter 304 increases (FIG. 11), the field strength will remain the same since an acceleration signal is required to clock the new count through shift register 310. However, at motor speeds below 1920 rpm the new pedal position will result in a lower V_OD signal (FIG. 10) and will cause a decrease in the armature current. Less torque is produced and the speed will slow and stabilize at a lower speed. The operation at motor speeds above 1920 rpm is as follows. In FIG. 4, a U signal will be generated when the newly demanded speed is less than the actual motor speed. In FIG. 10, the U signal will open transmission gate 291 and take the armature monostable out of retrigger operation. Thus, if operating at a speed above 1920 rpm, there will be a period of time between the end of the monostable pulse and the next trigger pulse from flip-flop 225, thereby turning the main armature SCR_MA on and off to reduce the armature current. With reduced current and available torque, the motor will slow. When the actual speed decreases to the newly demanded speed, the U signal goes low, allowing the armature monostable to go back into retrigger operation and maintain SCR_MA in continuous conduction. If the operator lets up on the accelerator pedal sufficiently so that the difference between the newly demanded speed and the actual speed is sufficient to generate the ACC₀₀ signal, the system will be taken out of power mode and put into a braking mode, as described hereinafter.

Power Mode -- Operation at Demanded Speed Assume that the motor has been brought up to demand speed and that the acceleration pedal is held at a fixed position. If the vehicle is travelling on level ground so that the torque requirement to propel the vehicle at such speed does not vary, then the field and armature currents and the motor speed will remain the same.

Now assume that the vehicle goes up a slight slope. Because of the increased torque demand the vehicle will begin to slow. The field strength will remain the same and more armature power current will flow. With more armature current, the torque will increase. If the slope is constant, the speed of the motor will stabilize at a speed wherein the motor torque is sufficient to meet the increased torque demand,

If the uphill slope is sufficiently steep that the motor slows to speed wherein the actual motor speed is sufficiently less than the demanded speed, the ACC₁ acceleration signal will be generated. When it is, it will cause the pulse width of the field monostable to decrease the field strength. If below 1920 rpm, the armature monostable pulse frequency is boosted to provide more armature current to provide the necessary torque to drive the vehicle up the slope at near demanded speed. If above 1920 rpm, the reduced field and decreased speed causes more armature current so that the torque demand is met. In either event, the speed will stabilize at about the speed relative to demanded wherein the ACC₁ signal is produced.

If the vehicle now returns to level operation (still with a fixed pedal position), the torque demand will lessen, the speed will increase and the armature power current will decrease. The motor will stabilize at the speed xvherein the torque delivered meets the torque demand.

If the vehicle noxv goes down a slight slope, the speed will increase somewhat, the increased speed with the same field strength causing a decrease in armature current so that the delivered torque is reduced.

The speed will again stabilize if delivered and demanded torques are the same.

If the downhill slope is sufficiently great, the motor speed will increase to a point wherein the difference between actual and demanded speeds is such as to cause the deceleration signal ACC₀₀ to be generated. This will cause the motor to be put into a braking mode, and the resultant dynamic braking will slow the vehicle. The speed will stabilize at approximately the speed wherein the ACC₀₀ signal is produced.

As is thus apparent, if the"accelerator pedal is held at a fixed position, the actual motor speed will be somewhere within the range wherein the speed is neither slow enough to produce an ACC₁ signal nor fast enough to produce an ACC₀₀ signal. As is thus apparent, if the accelerator pedal is held at a fixed position, the actual motor speed will Nary in accordance with the torque demand. However, the actual speed will be held within a range relative to the demanded speed, the low speed of the range being that wherein an ACC₁ signal is generated and the high speed of the range being that wherein the ACC₀₀ signal is generated. The width of the range is a matter of choice. The smaller the difference between the actual and demanded speed signals F_AM and F_DM, required to produce the ACC₁ or ACC₀₀ signals, the narrower the range of speed at which the motor will be held. However, with a narrower range, smaller variations in torque demand will put the system into acceleration (ACC₁) or braking (ACC₀₀) . Since a perceptible change of acceleration will be felt by the operator each time the system goes into and out of acceleration or braking, making the width of the range too narrow will lead to operator fatigue. Thus, the wider the range, the smoother the operation. For any particular application the need for constant speed must be balanced against the need for smooth operation and the proper width chosen.

As will be noted, during the time that the acceleration pedal is fixed and the speed is varying within the above-described range, the actual motor speed signal F_AM1 is varying with the speed and the count in counter 304 is likewise varying (since the operator demand signal T₁ is constant). If the actual speed goes down, the count in counter 304 goes down. If desired, the count in counter 304 could be clocked by each T₁ delayed pulse (instead of being inhibited from clocking if there is no acceleration signal) so that such decrease in motor speed will result in a strengthening of the field and thereby increase the delivered torque to meet the increase in demanded torque. Likewise, if the motor speed increase above demanded, the count in counter 304 will increase, and the field will be weakened to reduce the delivered torque. Thus, small variations between actual and demanded speeds would produce changes in the field strength which would cause the speed to stabilize near the demanded speed. By so doing the sensitivity of the system can be increased.

However, it is not always desirable to have a highly sensitive system, since the system may be too "goosey". In lift truck operations, this is undesirable. Accordingly, in the present described embodiment, changes in the count of counter 304 are used to change the field strength only when an acceleration signal is present. Power Mode-Top Speed Limiting Without the use of the top speed limit reference oscillator 95 (FIG. 4) and its associated circuits, the top speed of the motor would be determined by the maximum speed demandable by the accelerator pedal, i.e., the speed demanded when the pedal is fully depressed. If the accelerator pedal is fully depressed and maintained in such position, the motor would accelerate to such maximum demandable speed. After reaching such speed, the motor would stabilize thereat, A sufficient slowing of the motor would cause the system to go into an acceleration mode to bring the speed back up to the demanded speed, A sufficient increase in speed would put the system into a braking mode to reduce the speed.

Also, as previously described, the operator can control the rate of acceleration by use of the accelerator pedal. A gradual depression of the pedal to its fully depressed position as the motor speed increases will result in a slow rate of acceleration. An initial full depression of the pedal will result in a maximum rate of acceleration to the demanded speed. The top speed reference oscillator 95 (FIG. 4) is used to limit the top speed of the motor to a predetermined desired speed which is below the maximum speed demandable by full depression of the accelerator pedal, but without affecting the control by the operator of the rate of acceleration. In more particular, the components of oscillator 95 are selected so that its frequency of oscillation, F_TSM will he the same as the frequency of the actual speed signal F_AM when the motor speed is at the desired top speed limit.

The F_TSM and F_AM signals are continuously compared by comparator 97. As long as the actual speed of the motor is less than the top speed limit, transmission gate 100 will allow the operator demand signal F_DM to go to comparator 102 and counter 105, and transmission gate 101 will block the F_TSM output of oscillator 95 from having any effect on the system. As a consequence, as long as the actual speed is below the top speed limit, the operator has full control of the rate of acceleration.

For example, suppose the operator wants to go to full speed and with the maximum rate of acceleration. He does so by depressing the accelerator pedal fully, i.e., to demand a speed greater than the top speed limit. During acceleration, and as long as the motor speed has not increased to the top speed limit, the armature monostable 226 (FIG. 10) will be controlled as a function of the V_OD signal corresponding to full pedal depression up to the base speed of the motor, after which monostable 226 goes into retrigger operation with continuous armature current, Ther field monostable 320 (FIG. 11) will be controlled by the count of counter 304 derived from the T₁ signal corresponding to full depression of the accelerator pedal and the actual speed signal F_AM1, with the armature current being boosted and field current being weakened by the affect of the acceleration signals ACC₁-ACC₄ developed in response to the count of counter 105 (FIG. 4) derived from the demanded speed signal Fnw (corresponding to full pedal depression) and the actual speed signal F_AM, all as previously described.

In due course, the motor will have accelerated so that the actual speed reaches the top limit speed. As soon as the actual speed increases above the top limit speed (in an attempt to reach the higher speed demanded by full accelerator pedal depression), comparator 97 (FIG. 4) causes the G and G signals to go high and low respectively. Transmission gates 100 and 101 open and close, respectively, to substitute the lower frequency top speed limit signal F_TSM for the F_DM. demand signal. With the F_TSM signal applied to comparator 102, and with the actual speed being greater than the top limit speed, comparator 102 will cause the U signal to go high. In FIG. 10, the U signal will take the armature monostable 226 out of retrigger operation and the G signal will reset counter 223 and hold it reset so that the armature monostable will be inhibited from being triggered. Accordingly, armature current will be cut off.

The effect on the field in response to the actual speed going above the top limit speed is as follows. In FIG. 4, the F_TSM signal is now applied to counter 105 in place of the F_DM signal. The counter 105 will then have a count indicating that the actual speed has gone above the top speed limit and the acceleration signal ACC₁ will go low (if it was still high).

In FIG. 11, during acceleration, the field had been progressively weakened in response to the count of counter 305 as the actual speed had increased. With the disappearance of the ACC₁ signal, the count in counter 304, corresponding to the T₁ signal and the actual speed signal F_AM1 at the time that the actual speed exceeded the top speed limit, will be latched in the outputs of shift register 310.

With the armature current cut-off, and with the field maintained at a level corresponding to the actual speed F_AM1 signal for the top speed limit, the vehicle will slow. As soon as the actual speed drops below the top speed limit, comparator 97 (FIG. 4) causes the G and

signals to revert to their normally low and high states. The U signal also goes low, since the higher F_DM signal is now reapplied to comparator 102. In FIG. 10, with the U and G signals being low, the armature monostable 226 is put back into retrigger operation to resume continuous armature current. In FIG. 11, the field current will remain the same since it will still be a function of the same full demanded speed signal T₁ and the actual speed signal F_AM1 which corresponds to the speed the motor is at, namely the top limit speed.

As long as the accelerator pedal remains fully depressed, the field strength will remain essentially constant and at a strength determined by the actual speed signal corresponding to the top speed limit, while armature current is allowed or inhibited depending on whether the actual speed falls below or increases above the top speed limit. Such self-regulation will maintain the level of power to the motor to stabilize the actual speed at the top speed limit.

As before, if the vehicle is so operating at top speed limit and the vehicle should go downhill, the inhibition of armature current (when the top speed limit is exceeded) may not be sufficient to cause the vehicle to slow. If such is the case, the actual speed may continue to increase. However, since the count in counter 105 (FIG. 4) is based on a comparison of the top speed limit signal F_TSM and the actual speed signal F_AM when the actual speed is above the top speed limit, when the actual speed increases enough relative to the top speed limit, the count in counter 105 will become low enough to cause the ACC₀₀ signal to be generated so that the system is put into a braking mode to cause an affirmative slowing of the vehicle back down to the top speed limit.

Braking Mode -- Deceleration As mentioned previously, the operator can put the system into a braking mode simply by letting up on the accelerator pedal to demand a speed sufficiently below actual speed such that an ACC₀₀ signal is generated.

Suppose the motor is operating at a demanded speed substantially above 1920 rpm and the operator lets up on the pedal to a position demanding a speed substantially below 1920 rpm.

Since the newly demanded speed is less than the actual speed, the U signal (FIG. 4) is generated. Also, since the newly demanded speed is substantially below actual speed, signal ACC₀₀ will go high. In FIG. 9, the ACC_{0 0} signal cause the V_DEC signal to go high, which, in turn, causes the V_AO and signals to go low and the signal to go high.

With the V_AO signal now low, the armature monostable 226 is inhibited from operating and the main armature SCR_MA is prevented from being further gated into conduction. With SCR_MA now off to disconnect the armature from the battery the power current will drop. When the power current decays to below the minimum reference level, set by signal F_IAO (FIG. 6) the

signal will go low. In FIG. 10 this signal is logically combined with the now low signal to generate a high brake enable signal and start the braking oscillator F_BRK

into operation. Since the motor speed is above 1920 rpm, the braking oscillator pulses will pass through gate 269 and the regenerative braking SCR_RB will be gated on to connect the armature to the battery for flow of charging current to the battery.

In FIG. 11 the brake enable signal

and T signals are combined by NAND gate 336 and cause the transmission gates 342 and 369 to close and open respectively, to apply supply voltage V_S2 to the input of VCO 318 so that it will operate at maximum frequency and to increase the external resistance of the field monostable 320, both of which will cause the field monostable to operate so that maximum field strength can be provided. The charging of the negative jerk capacitor 317 at the input of VCO 318 will control the rate at which the field strength is raised.

The inertia of the vehicle will continue to drive the armature in the same direction, causing the motor to act as a generator. With the motor speed being above 1920 rpm base speed, the increasing field will cause the motor to develop sufficient voltage thereacross so that the generated current will flow back to the battery through SCR_RB to recharge the battery as the motor decelerates.

The generated voltage (and brake current produced thereby) is a function of armature speed and field strength. The higher the speed, the lesser the field strength required to generate a desired amount of brake current. In the present invention, the armature: brake current is continuously monitored and the field is controlled so that the brake current is held at a desired level. Thus when the field is first applied, the armature brake current will rise as the field is built up, and the frequency of the armature current signal F_IA will decrease. In due course, the frequency of the F_IA signal will decrease below the frequency of the brake current limit signal F_CLB (FIG. 6) and the excessive brake current signal L will go low. In FIG. 9, the low L signal will cause the field inhibit signalV_FI to go high, so that, in FIG. 11, the operation of the field monostable will be inhibited and current to the field will be shut off. The field will decay and reduce the generated brake current. When the level of such current reduces below the F_CLB limit, the L signal will again go high, causing the field to be energized. This action repeats continuously so that the field monostable will operate to maintain the field at a level wherein the armature brake current is maintained at the F_CLB level. Assuming that the speed is sufficient to generate brake current at the F_CLB limit (without the generation of excessive field current) the control of the field monostable in response to the L signal will automatically set the field strength at the proper level for any speed so that the generated brake current is held at the F_CLB limit.

The generation of braking current produces a braking torque so that the vehicle decelerates. A the speed reduces, the L signal will cause the field monostable to go into and out of operation at a progressively high level of field strength so that the armature brake current remains at the F_CLB level.

In due course, the motor will be slowed to a speed wherein excessive field current will be required to generate armature brake current at the F_CLB level. At this point, the signal, which is generated in FIG. 6 in response to the presence of excessive field current, is used in FIG. 9 to cause the field inhibit signal V_FI to go low so that the field monostable operates to hold the field strength at the level produced by maximum allowable field current (approximately 55 amperes).

As the motor speed further decreases, the generated voltage will now decrease and will drop to a level wherein it is insufficient to overcome the battery voltage and supply current thereto. Thus, the maximum allowable field current will determine the lowest speed at which the motor can be operated to recharge the battery. In general, the "base speed" referred to herein, is substantially near this lowest recharging speed.

In due course, the motor speed will decrease to the base speed of 1920 rpm and the actual speed signals T and

will go low and high respectively. In FIG, 10, the now high T signal, applied to gate 269, will inhibit further braking pulses F_BRK from passing through gate 269 so that a gate pulse will not be applied to the regenerative braking SCR_RB. If in fact the 1920 rpm speed is below that required to produce sufficient emf to charge the battery, the potential on the cathode of SCR_RB will have become more positive than on the anode and SCR_RB will have ceased to conduct.

To ensure that SCR_RB is commutated when the motor speed drops to the 1920 rpm base speed, the T pulse and signals are used, on FIG. 10, to clock

on flip-flop 276 and trigger on the one-second monostable 277. The Q output of this monostable is applied to gate 271 so that the F_BRK brake pulses now passing through gate 270 (since T is now low) will be prevented from passing through gate 271 and being used to gate on SCR_B. The V_M5 signal from the Q output of the one-second monostable is used in FIG. 9 to cause the field inhibit signal V_F1 to go high and shut off the field for the one-second duration of the pulse from monostable 277. With the field shut off, the emf produced by the armature will decay so that SCR_RB will commutate if it is still in conduction. The V_M5 signal from monostable 277 is also used, in FIG. 11, to cause a rapid discharge of the negative jerk capacitor 317 during the one-second monostable pulse period, so that the field will not be abruptly increased as deceleration continues.

At the end of the one-second pulse period, signal V,,-. goes high and allows F_BRK signals to pass through gate 271 so that the resistive braking SCR_B is turned on to effectively short circuit the armature for resistive braking.

Also at the end of the one-second pulse period, signal V_M5 goes low so that the field inhibit signal V_FI goes high, allowing the field monostable to resume operation. In the previously described operation above the 1920 rpm base speed, the signal had been used

in FIG. 11 to cause the field monostable to operate at maximum frequency and pulse width to produce the relatively high field strength required for generation of charging current. Since a considerably lesser field strength is required in the resistive braking mode, the now low 1920 rpm base speed signal T prevents the signal from affecting monostable operation. Trans¬

mission gate 342 opens, so that VCO 318 will pulse at a frequency determined by the output from the R/2R network 311, i.e., at the relatively low level existing when deceleration began. Transmission gate 369 closes to reduce the pulse width of the field monostable 320.

As in regenerative braking, the armature brake current is continuously monitored and compared to the

F_CLB brake current limit signal. The resultant excessive brake current signal L again affects the V_FI signal to allow or inhibit the operation of the field monostable 320 and thereby maintain the armature brake current at the F_CLB limit. As has been mentioned previously, in order to provide substantially the same braking torque in resistive braking and regenerative braking, the armature brake current should be greater during resistive braking. In FIG. 6, the brake current limit VCO 165 is controlled so that the current limit signal F_CLB is lower than when in regenerative braking, to allow more brake current during resistive braking. For example, during regenerative braking in the deceleration mode, the maximum allowable brake current may be held to about 150 amperes, with the maximum allowable brake current limit being about 400 amperes during resistive braking.

As the speed of the motor continues to decrease towards the demanded speed, the difference between the continuatlly monitored actual and demanded speeds decreases and the count in counter 105 increases (FIG. 4). As a consequence, the level of the voltage signal V_CLB increases, and the frequency of the F_CLB signal increases, so that the maximum allowable brake current reduces. Since the rate of deceleration is a function of the maximum allowable brake current, the rate of deceleration becomes gradually less as the actual speed approaches the demanded speed so that the motor will come smoothly out of deceleration. In due course, the actual motor speed will reduce sufficiently so that the difference between the actual and demanded speeds is small enough to cause the deceleration signal ACC₀₀ to go low. In FIG. 9, the V_AO and signals again go high and the signal

goes low. In FIG. 10, the now high signal shuts

off the brake oscillator which produces F_BRK. The resistive braking SCR_B will remain in conduction, however, until it is commutated. As will be seen in FIG. 2, if the main armature SCR_MA and the resistive braking SCR_B are both on, the battery will be short-circuited. Accordingly, the resistive braking SCR_B must be commutated before the main armature SCR_MA is turned back on. The re-establishment of the V_AO signal is used to accomplish this, in FIG. 10, as follows. During initial deceleration, when both signals and U went high (armature power current less than minimum reference level and demanded speed less than actual speed) a reset pulse to flip-flop 281 drove its Q output low to inhibit operation of gate 284 and to condition gate 282 for operation. When the V_AO signal goes high at the end of deceleration, the output of gate 282 will go high and close transmission gate 241 so that the next F_AD pulse will trigger monostable 240 and cause the commutating SCR_CA to go into conduction (FIG. 2) which causes the commutating capacitor to charge with its left plate positive relative to its right plate.

During the deceleration of the motor, the reduced remanded speed and the reducing actual speed will cause the count in counter 304 (FIG. 11) to decrease. When the V_AO signal is reestablished towards the end of deceleration and the output of gate 282 (FIG. 10) goes high, the high output of gate 282 is used in FIG. 11 to apply a high to the D input of flip-flop 310c so that the reduced count in counter 304 will be clocked through shift register 310.

With the resistive braking SCR_B still on and with the field still on, the motor will continue in the braking mode. The F_AD pulses will continue to trigger monostable 240. Also, the shift register 310 (FIG. 11) will continue to be clocked.

Finally, the motor slows to'the demanded speed. At such time, the U signal will go low. The coincidence of the low U signal and the next low signal from

monostable 240 will set flip-flop 281 with a high Q output. Gate 284 now allows the V_AO signal to restore the armature monostable 226 into operation. The first pulse therefrom will gate SCR_LA on to connect the commutating capacitor across SCR_B to back-bias it and cause it to commutate. The delayed signal GAw. from the armature monostable will then gate the main armature SCR_MA into conduction.

When flip-flop 281 is set, the output of gate 282 goes low (FIG. 10), removing (FIG. 11) the high D input of flip-flop 310c, The shift register 310 will now have latched into its outputs the inverse of the count in counter 304, i.e., the count established by the newly demanded speed and the same actual speed.

Normal operation in the power mode now again resumes with the armature power current being established by the magnitude of the operator demand signal V_OD and with the field current level being established by the last clocking of the shift register 310.

The same deceleration sequence will occur if the original motor speed had been less than 1920 rpm except that the regenerative braking operation involting SCR_RB will not occur. The one-second monostable 277 (FIG. 10) will be triggered on at the beginning of deceleration, in order that the V_M5 output therefrom will discharge the negative jerk capacitor 317 for smooth deceleration. However, if the motor speed is less than

120 rpm, the signal

will be low, so that the one-second monostable will not operate, thereby allowing the system to go into immediate braking.

If, during deceleration, the operator depresses the accelerator pedal sufficiently so that the newly demanded speed is equal to or greater than the actual speed, the deceleration signals ACC₀₀ and U will disappear, putting the system back into the power mode. If the newly demanded speed is sufficiently higher than the actual speed so that one or more of the acceleration signals ACC₁-ACC₄ are generated, the system will go into the acceleration mode as soon as it returns to the power mode.

Brake Mode -- Degree and Rate of Deceleration As mentioned previously, the operator can command deceleration by simply letting up on the accelerator pedal. In addition, the operator can control the degree of deceleration by the amount that he releases the pedal. For any given actual speed, the more the pedal is released, the greater will be the degree of deceleration.

In more particular, the greater the release of the accelerator pedal, the greater the difference will be between the actual speed signal F_AM and the demanded speed signal F_DM. In FIG. 4, the magnitude of the difference between these two signals is ascertained by counter 105 and is applied through shift register 117 to the digital-to-analog resistor network 118. The lower the demanded speed is, relative to the actual speed, the lower the count in counter 105 and the lower the voltage output of signal V_CLB. Since this signal is inputted into VCO 165 (FIG. 6) the frequency of the brake current limit signal F_CLB is a function of the count in counter 105. The greater the difference between actual and demanded speed, the greater the allowable maximum armature brake current and the greater the braking torque.

The operator, if he wishes, can release the accelerator pedal all the waywhile moving in one direction. This produces a minimum F_CLB signal and maximum braking. While decelerating, the operator can depress the pedal to a position still calling for a reduced speed. This will raise the frequency of the F_CLB signal which will reduce the level of brake current and decrease the braking torque. As in the acceleration mode, the present system provides for independent control of the peak deceleration and the rate of deceleration.

As mentioned, peak deceleration is a function of the brake current limit signal F_CLB generated by VCO 165 (FIG. 6).

As mentioned, when in the braking mode, the armature brake current is maintained at the F_CLB limit generated by VCO 165 (FIG. 6). Thus, the degree of braking torque and deceleration will depend on the level of the F_CLB signal.

The rate of deceleration is a function of the rate of rise of the voltage applied to VCO 318 (FIG. 11) for the field monostable, i.e., the rate at which the field is built up to produce brake current and braking torque. This rate of change is dependent upon the values of the negative jerk capacitor 317 and the negative jerk resistor 316.

The frequency of the F_CLB signal is completely independent of the deceleration rate. Current-limiting will occur when the brake current reaches the F_CLB, limit regardless of how quickly or how slowly the brake current rises to that limit. Contrarily, the rate of rise of the brake current is independent of the maximum allowable brake current.

The degree of deceleration can be customized for a particular application by changing the values of the external resistors of VCO 165, Likewise, the rate of deceleration can be customized by changing the value of the negative jerk resistor 316.

Additionally, the peak acceleration and acceleration rate are independent of the peak deceleration and deceleration rate. Peak acceleration and peak deceleration are functions of maximum power and maximum plug currents through the armature. The current limit signals F_CLA and F_CLB come into effect at opposite ends of the F_IA curve and thus there is no interaction between the F_CLB and F_CLB signals. The acceleration rate is a function of the rate of change of the input voltage to VCO 222 for the armature monostable, while the deceleration rate is a function of the rate of change of the input voltage to VCO 318 for the field monostable. Varying the rate of change of input to the VCO for the armature monostable will not affect the rate of change of the input to the VCO for the field monostable, and vice versa.

Braking Mode -- Plugging The system will enter the plugging form of the braking mode when the motor is being powered in one direction and the operator moves the direction control lever 24 to command the opposite direction.

For example, suppose the motor is being powered in a forward direction, with the direction control lever in forward position and with the accelerator pedal depressed to command a particular speed, and the operator shifts the control lever to reverse. Insofar as the braking mode is concerned, it is immaterial whether the operator also changes the accelerator pedal or not. Let it be assumed that the operator continues to hold the pedal in the same depressed position.

In FIG. 3, the movement of the control lever 24 from forward to reverse causes the switch 70 to open and switch 71 to close, so that the forward signal B goes low and the reverse signal A goes high. In FIG. 6, the last commanded direction signal C remains high since flip-flop 148 will not be reset until signal V_DE goes low, i.e., until the motor speed drops below 120 rpm and the field current drops below minimum reference. In FIG. 8, with signals A and C both high, and with signal D high (motor speed above 120 rpm), the output of gate 172 will be low, maintaining the output of gate 174 high so that the FWD signal continues to maintain the forward contacts 40 and 41 (FIG. 2) closed. Thus, the shifting of the control lever from forward to reverse does not at this time cause the field to be reversely connected to the battery.

In FIG. 9, with signals D_RF, C, A and D all high, gate 182 will output a low, so that gate 184 will continue to output a high field-enabling signal V_FE to maintain the field pulsing circuitry of FIG. 11 in operation.

Also in FIG. 9, with signals A and C both high, and signals B and

both low, gates 192 and 193 will both output a high to gate 194 so that the

signal will go low. The plugging signal V_PG goes high.

The low signal is applied to gate 207,

and, by gate 208 causes the V_AO signal to go low and inhibit the armature pulsing circuitry of FIG. 10.

The high V_PG signal is applied to gates 197 and 200 so that signals and go low and high

respectively.

Thus, the control signals V_AO, and

are affected by the plugging signal V_PG in the same way as they are by the deceleration signal V_DEC. In addition, the now high V_PG signal is used in FIG. 4 to close transmission gate 196 and ground the brake current limit signal V_CLB. This in turn (FIG. 6) causes VCO 165 to operate at its lowest frequency. Thus, when operating in the plugging form of the brake mode, the brake current limit signal F_CLB is not affected by accelerator pedal position as previously described but is instead set for maximum braking effect. For example, the F_CLB signal may permit up to 450 amperes during regenerative braking and up to the maximum Tating of the motor, e.g., 600 amperes, during resistive braking, Other than the fact that the V_PG signal is used, instead of the difference between actual and demanded s.peeds, to affect the brake current limit signal F_CLB, the motor will be braked in the same manner as previously described.

If the initial speed is above 1920 rpm, SCR_RB will be gated on for regenerative braking, and the

will boost the pulse frequency and pulse width of the field monostable as before. Field strength will be maintained, by the L and V_FI signals, at a level to hold the brake current at the F_CLB limit. The only difference is that deceleration will be greater since more brake current is allowed to flow through the armature. The motor will go out of regenerative braking in the same manner. Again as it does so, the boosting of the pulse frequency and pulse width of the field monostable 320 by the signal will terminate and

the monostable will pulse at the lower frequency set by the output of the R/2R network 311. During resistive braking the L and V_FI signals will allow or inhibit operation of the field monostable to maintain the armature brake current at the F_CLB limit.

In due course, the motor will decelerate so that its speed drops below the lowest speed reference, 120 rpm. At such time the D and

motor signals will go high and low, respectively.

In FIG. 9, at least one input to each of gates 180-183 is now low (i.e.,

for gate 180, B for gate 181 and D for gates 182 and 183), causing each gate to output a high to gate 184 so that the field enable signal V_FE goes low. The field inhibit signal V_FI goes and stays high to inhibit operation of the field monostable 320 (FIG. 11). With the field cut off, the field current will begin to decay. The forward contacts 40 and 41 will remain closed, since signal C and

are both high, and will, in FIG. 8, cause gate 170 to maintain the FWD signal.

When the field current does finally decay to below the minimum reference level, signal

goes low and E goes high. With one input of each of gates 170-173, FIG. 8, now low (i.e., E for gate 170, B for gate 171,

for gate 172 and B for gate 173), the FWD signal will go low. The forward relay coil 39, FIG. 2, will open. With signal A, D and E now all high (reverse direction commanded, motor speed less than 120 rpm and field current less than minimum reference), gate 177 will cause the reverse signal REV to go high. The reverse relay coil 43 is energized and the reverse relay contacts 44 and 45 will close to connect the field for operation in a reverse motor direction.

With this arrangement, switching of the field relay contacts is delayed until the field current has decayed to its low reference level. As a result, the field contacts can open only when tthe field current is at a low level and contact burn-out from arcing is thus avoided. With motor speed below 120 rpm and field current below minimum reference, signals D and E will both be high, and signal (FIG. 6) will go low, thus enabling

the low A signal to reset flip-flop 148. The C and signals accordingly go low and high respectively. The high VDE signal is used in FIG. 10 to discharge the positive jerk capacitor 221 so that it can function in the next acceleration.

In FIG. 9, with the C and

signals now low and high, gates 192, 193 and 194 cause the plugging signal V_PG and to revert to their non-plugging low

and high states, respectively. Signals

and

also revert to their non-braking high and low states, respectively.

As soon as the reverse relay contacts actually close, the D_RR signal, together with the A and signals,

will cause gate 180 to reinstitute the field enable signal V_FE which causes the field pulsing circuitry to begin functioning again to rebuild the field. When the field current rises above minimum reference level, the low E signal will act on gat 204 and cause the armatureon signal V_AO to be generated.

In FIG. 10, flip-flop 281 will have been reset when the direction-control lever was shifted through neutral from forward to reverse. When the V_AO signal is re-established, transmission gate 241 closes and the commutating monostable 240 is triggered by an V_AD pulse so that SCR_LA is gated on to charge the commutating capacitor C_CA. Flip-flop 281 then sets so that the V_AO signal will now enable the main armature monostable 226 to be triggered. The first pulse gates on SCR_LA to connect the charged commutating capacitor across SCR_B to commutate it and then gates on the main armature SCR_MA. The system is now in the power mode and the motor speed is then brought, in the reverse direction, up to the speed demanded by the operator in the manner as previously described.

Coasting Mode This mode is one in which the vehicle is moving and is neither in the power nor braking mode. The coasting mode will hot normally be used, but it is available to the operator in case he wishes it.

Assume that the vehicle is being operated in a forward direction and in either a power or braking mode, and the operator shifts the direction control from forward to neutral. As a first result, the forward direction signal B goes low. Since a reverse direction is not being commanded, signal A is also low. The last commanded signal C will remain high, since flip-flop 148 (FIG. 6) cannot be reset until the motor speed drops below

120 rpm. With field current being still above the minimum level, signal

is high, and in conjunction with the high C signal will cause gates 170 and 174 (FIG. 8) to maintain a high FWD signal so that the forward field relay contacts 40 and 41 remain closed.

In FIG. 9, with both of the A and B direction signals low, gates 180-183 will all output a high to gate 184 and the field enable signal V_FE will go and stay low, causing the field inhibit signal V_FI to go and stay high. The field pulsing circuit will thus be inhibited so that no more current will be delivered to the field through the main field SCR_MF. If the motor had been in a braking mode, the armature-on signal V_AO, would already have been low. If the motor had been in a power mode when the shift to neutral occurred, the low V_PE signal will cause the V_AO signal to go low so that the armature pulsing circuit will be inhibited from triggering the main armature SCR_MA.

In FIG. 9, with both the A and B signals being low, gates 192 and 193 will both output a high so that gate 194 outputs a low. The plugging signal V_PG will go high, braking signal goes low and signal

goes high, as if a plugging mode were being commanded. However, very little braking will occur since the field has been cut off.

The field current will decay. When it drops to the minimum reference level, signal

will go low. In FIG, 8, this will result in a loss of the FWD signal, the forward relay contacts 40 and 41 will now open, to disconnect the field, and the motor will now coast with no power applied to either the field or the armature. Again, the contacts 40 and 41 will not open until the field current has dropped below the minimum reference level and arcing at the contacts is thus prevented. The last commanded direction signal C will remain high as long as the motor speed remains above 120 rpm.

If while coasting forwardly, the operator moves the direction control from neutral back into forward again, signals B and C will both be high, and gates 173 and 174 (FIF. 8) will re-establish the FWD signal to reconnect the field by closing the forward relay contacts 40 and 41, The field enable signal V_FE (FIG. 9) will go high so that the field will be reenergized. The motor will go into a power mode or a braking mode, dependent upon the setting of the accelerator pedal, i.e., whether it is calling for a speed below or above the actual speed when the shift back into forward direction is made. If, while coasting forwardly at a motor speed greater than 120 rpm, the operator instead moves the control lever 24 from neutral to reverse, the high signals A, C and

will, by gates 172 and 174 (FIG. 8), reestablish the FWD signal, so that the field is again reconnected by the forward field relay contacts 40 and 41. In FIG. 9, the V_FE signal goes high and the field pulsing circuit again energizes the field. Also in FIG. 9, the V_PG and signals go high, while the

and V_AO signals go low. Thus, shifting into revers

e from a forward coasting mode reconnects the field in a forward direction and puts the system into the previously described plugging form of the braking mode.

Control Loop As may be seen from the foregoing, when operating in the power mode, the primary control of the motor is achieved by using the Voτ. (and derivative signals) signal proportional to the demanded speed and the F_AM signal (and derivative signals) proportional to the actual speed of the motor and using such signals so that the actual speed is brought to the demanded speed. The demanded speed signals are independent of the load on the vehicle. They are dependent only upon the degree of depression of the accelerator pedal. For a given pedal position, the V_OD, F_DM and T₁ signals will be set, regardless of whether the vehicle is loaded or empty or whether it is going up or downhill. Likewise, the actual speed signals are independent of the load on the vehicle. For any given actual speed, the frequency of the F_AM signal will be the same, whether the vehicle is loaded or not.

Thus, the operator can control the speed of the motor, and of the vehicle propelled thereby, in a very positive manner. If he wishes to travel at a certain speed, he sets the accelerator pedal to demand that speed. The speed of the vehicle will then stabilize at or near that speed (within the dead-band range between ACC₀₀ and ACC₁ signals) whether the vehicle is loaded or empty or whether the vehicle goes up or down slopes. This is true whether the motor is accelerating or decelerating to the demanded speed.

Although the actual and demanded speeds are continuously monitored and the resultant signals are used for control of the motor, the armature current is also continually monitored. In the event of excessive armature current, either power or brake current, the system operates to regulate the operation of the field so that the excessive current is reduced to allowable limits. Such feedback of armature current information is not used, however, to control the speed of the motor -- it is used to keep armature current within allowable limits as the motor changes speed during acceleration or deceleration to reach a demanded speed.

The present system also enables the operator to continue to control the speed of the motor after full power is applied to the armature. It is customary to regulate speed of a motor by using an SCR control to vary the amount of average power supplied to the armature from the battery. Full speed in such systems is obtained by bypassing the SCR control and connecting the motor directly across the battery. When this occurs the operator has no further control over the motor except to take it out of the bypass mode and return to SCR control.

In the present system, armature current can be increased by the main SCR_MA up to a point (1920 rpm) wherein the SCR_MA is in continuous conduction and the armature is essentially connected across the battery (save foτ the relatively small voltage drop through the conducting SCR). However, the operator still has direct control of the motor speed above that point by virtue of the field control obtained in response to further pedal depression.

The present system also utilizes a digital, rather than analog, control. In all instances wherein the magnitude of a variable signal must be ascertained and compared with other signals, the signals are either generated directly as frequency signals or else the underlying variable voltage signal is converted to a corresponding frequency signal. For example, the actual speed of the motor is indicated by the frequency signal

F_AM. The operator demand signal from the pedal-controlled potentiometer is converted to the frequency signals

F_DM and T₁. The magnitude of armature and field current is indicated by the frequency signals F_IA and F_IF. These signals are compared in frequency with each other or with the frequency signals generated by the various oscillators in the control, such as the current reference signals F_CLA, F_IAO, F_CLB, F_IFMAX, and F_IFMIN, or the speed reference signals from VCO 119 (FIG. 4), VCO 125 (FIG. 5) and oscillator 94 (FIG. 4). The comparison results in high or low signals or the differnece in frequency between compared signals results in digital information used to produce high or low signals in accordance with the count, Such a digital control is far more reliable in operation than an analog control, and is much less prone to drift from temperature and voltage changes and from aging. Analog controls require numerous adjustment potentiometers to maintain desired operation, As will be noted, none are used, or required, in the present system. It is very difficult to design analog systems so that the various circuits do not interact. The present digital system greatly avoids this problem. The present system is also usable, without modification, with batteries of different voltages, as long as the battery voltage exceeds the V_S1 value. The only difference in operation is that, with a battery of lower voltage, the maximum torque and speed for a given load will be decreased. Modification of FIG. 18

FIG. 18 discloses a modification of the field pulsing circuit. The end results of a system using the FIG. 18 circuit are essentially the same as if the previously described circuit of FIG. 11 is used. That is, during power operation, the excitation of the field, is controlled as an inverse function of the demanded and actual speeds so that the field current is high at low demanded and actual speeds and low at high demanded and actual speeds. During braking, the field is controlled by regulating the field current so that the armature brake current is held at the maximum allowable brake current limit set by the brake current limit signal

F_CLB.

In general, both circuits function in the same manner during braking. The field monostable 320 is operated at a pulse rate and pulse width such that if the monostable was allowed to operate continuously the generated armature current would be excessive.

The armature current signal F_IA is continuously compared to the brake current limit signal F_CLB, and tne resultant

L signal is used to allow the field monostable to operate as long as the armature brake current is not excessive and to inhibit operation during such time as the armature brake current is excessive. By so doing, the field strength is regulated to maintain the armature brake current at the F_CLB limit.

The circuits of FIGS. 11 and 18 differ primarily in the manner in which the field current is regulated during the power mode of operation. In FIG. 11, the field monostable operates continuously, with the field strength being regulated by varying the pulse frequency and pulse width as an inverse function of the count in counter 304.

In FIG. 18, the field monostable 320 operates at a fixed pulse frequency and pulse width sufficient to produce maximum field strength if the monostable were to operate continuously. Field current is then regulated by allowing or inhibiting operation of the monostable so as to maintain the field current at a desired level, namely at a level which varies as an inverse function of the count in counter 304. More specifically, the maximum allowable field current signal F_{I FMAX} is varied as an inverse function of the count in counter 304. The actual field current is continuously monitored and the resultant actual field current signal F_IF is continuously compared to the field current limit signal F_IFMAX. The comparison signal H (high if the field current is less than the current limit and low if the field current exceeds the current limit) is then used to allow or inhibit operation of the field monostable and thereby maintain the field current at the

F_IFMAX level.

Thus, operation of the field pulsing circuit of FIG. 18 is of the same character during braking and power modes of operation. In braking, the L signal is used to allow or inhibit operation of the field monostable to maintain armature brake current at the F_CLB level. In power mode, the II signal is used to allow or inhibit operation of the field monostable to maintain field current at the F_IFMAX level.

Referring now to the specific details of FIG. 18, the components which are the same as in FIG. 11 are identified by like reference numerals. As before, the field monostable 320 is triggered by the pulses from flip-flop 319 which is clocked by the output of

VCO 318, In this case, the input of VCO 318 is connected by resistor 430 to the supply voltage V_S2 so that VCO 318 oscillates at a fixed frequency. The pulse width of monostable 320 is normally a function of capacitor 321 and resistor 322, resistor 324 being shorted out by transmission gate 369 which is closed except when in a regenerative mode or if excessive armature power current is present. The pulse frequency and pulse width of the field monostable 320 are such that the field current will exceed the maximum allowable limit (e.g., about 55 amperes) if the monostable 320 were to operate continuously.

As before, the T. and F_AM1 pulses are applied to counter 304 so that a count is continuously obtained of the number of cycles of actual speed signals F_AM1 per cycle of the demanded speed signal T₁. This count is applied to shift registers 310 and 355 and clocked therethrough by the Q output of flip-flop 310c in the same manner as previously described in connection with FIG. 11. The

outputs of shift register 310 are applied to the R/2R digital-to-analog resistor network 311 to produce an output voltage which varies inversely with the count in counter 304. As before, this output is sent to FIG. 6 as the V_CLA signal to set the frequency of the armature power current limit signal F_CLA.

The analog output of the R/2R network 311 is also applied to the voltage dividing network of series resistors 431, 432, 433, and 434, the latter being connected to ground. Transmission gates 436, 437 and 438 are connected across resistors 431, 432 and 433, respectively, to short out these resistors when the gates are closed. The values of the resistors in the voltage dividing network are chosen so that the V_CLA utput of the R/2R network 311 is not unduly loaded as resistors 431, 432 and 433 are selectively shorted out. When the binary count in counter 304 is low enough so that both of the sixth and seventh outputs thereof are low, the output of shift register 355 will be high, gate

437 will be closed and resistor 432 will be shorted. If the count is higher, such that either or both the sixth and seventh outputs are high, gate 437 will open and resistor 432 will be put in the circuit. Similarly, if the binary count in counter 304 is such that the seventh output is high, and any of the sixth, fifth or fourth outputs is high, gate 436 will open and put resistor 431 in the circuit, A lessen count in counter 304 will close gate 436 to short out resistor 431, The acceleration signal ACC₄, when high, will close gate 438, to short out resistor 433. The voltage appearing at the junction of resistors 433 and 434 is applied through resistors 441 and 442, as signal V_{I FMAX} , to tne input of VCO 143, (When the modification of FIG. 18 is utilized in the overall circuit in place of FIG, 11, the circuit of FIG. 6 is, of course, modified so that the input of VCO 143 is connected as shown herein rather than being connected to the fixed supply voltage V_S2) .

VCO 143 produces a frequency signal V_{I FMAX} which varies in frequency according to the level of the V_IFMAX signal, the F_IFMAX signal and the actual field current signal F_IF being applied to comparator 141. If the level of field current is below the F_IFMAX limit set by VCO 143, the comparison signal H will be high. If the field current exceeds such limit the H signal will go low.

As before, the H signal is used in the logic circuit of FIG. 9 to cause the field inhibit signal V_FI to go low if the field current is excessive and the H signal is low. Also, as before, when the field inhibit signal V_FI goes low, the VCO 318 and flip-flop 319 are inhibited so that the field monostable 320 is not triggered. When the field current reduces below the maximum limit, the H and V_FI signals go high, so that the field monostable can resume operation and pulse at its fixed frequency and pulse width. The H signal thus causes the field current to be maintained at whatever the F_IFMAX level may be.

The system operates in an acceleration mode as follows. Assume that the actual and demanded speeds are both quite low. The count in counter 304 will be low and the output of the R/2R network 311 will be high. Gates 436 and 437 will both be closed, shorting out resistors 431 and 432. V_IFMAX will be a proportion (as determined by the values of resistors 433 and 434) of the R/2R output . If the accelerator pedal is depressed, the count in counter 304 will increase and the R/2R output will decrease so that the level of the V_{I FMAX} signal applied to VCO 143 is decreased proportionally. The F_IFMAX signal is accordingly decreased in frequency so that a lesser amount of field current can flow. The H signal regulates the operation of the field monostable 320 so that the field current is reduced and maintained at this new F_IFMAX level. If the demanded acceleration is sufficiently high, the ACC₄ signal will close gate 438 so that the V_IFMAX signal is taken directly from the output of the R/2R network 311. This will serve to allow more field current and more torque on initial acceleration. When the actual motor speed increases to a point where the

ACC₄ signal goes low, gate 438 will open to put resistor 433 back into the circuit and decrease the level of the V_IFMAX signal.

As the actual motor speed continues to increase, the count in counter 304 will progressively increase and the R/2R output will progressively decrease so that the V_IFMAX level will decrease and provide field weakening.

If full speed had been demanded, the count in counter 304 will increase, as the motor speed increases, to a point wherein the count is sufficient to open transmission gate 437, With resistor 432 now in series with resistor 433, the level of signal V_IFMAX will drop. A further increase in speed will cause gate 436 to open, putting resistor 431 in the circuit so that the proportion of the R/2R voltage appearing at VCO T43 is further reduced. Capacitor 443, connected between the input of VCO 143 and ground enables the voltage level of V_IFMAX to change smoothly as resistors 431, 432 and 433 are shorted out or cut back into the circuit. If during power operation the level of armature power current becomes excessive, the

signal will go high to close transmission gate 444 and boost the level of the V_IFMAX signal. This in turn raises the frequency of the V_IFMAX signal to allow the field strength to build up and thereby reduce the armature current.

The operation of the circuit of FIG. 18 in deceleration is as follows. Assume that the motor is operating above 1920 rpm and the operator releases the acceleration pedal to demand a speed substantially below 1920. As before the demanded deceleration will generate a signal, and the V_AO signal will go low to shut

off the armature monostable (FIG, 10). When the armature power current decays below minimum reference, the

signal goes loxv and the brake enables signal goes

high. The regenerative braking SCR, SCR_RB, is gated on to connect the armature to the battery.

In FIG. 18, the high and signals cause

the output of NAND gate 447 to go low. This low causes gate 369 to open and put resistor 324 in series with resistor 322 to lengthen the pulses of field monostable 320. The low output of gate 447 is inverted by inverter 448 to close gate 451 and apply supply voltage V_S2 to the input of VCO 143, to raise the field current limit signal F_IFMAX to its maximum.

Capacitor 443, in conjunction with resistors 441 and 442, limits the rate at which the V_IFMAX signal will rise at the input of VCO 143 when gate 451 is closed, to prevent jerk as the system gates into braking. As before, the rate of deceleration may be customized for a particular application by changing tfie value of the negative jerk resistor 441.

With maximum field now allowed to be applied, the armature will generate braking current to recharge the battery. As before, the armature brake current is continuously monitored and the L signal is used to control the state of the field inhibit signal V_F1 and thereby allow the field monostable 320 to pulse or to be inhibited from operating so that the armature brake current is maintained at its maximum allowable limit (set by the F_CLB signal).

In due course, the motor will slow to its base speed. SCR_RB is commutated. When the speed drops below 1920 rpm, the one-second monostable 277 is turned on. In FIG. 9 the signal

from this monostable will cause the field inhibit signal to go low, so that

the field monostable 320 (FIG. 18) will cease pulsing for this one-second period.

Also in FIG, 18, the Vwr signal will close gate 453 so that the negative jerk capacitor 443 may discharge through resistor 454 and ground the input of VCO 143,

At the end of the one-second period, SCR_B will be gated on to short across the armature for resistive braking. The field inhibit signal V_FI goes high to allow the field monostable 320 to begin pulsing again. Gate 453 will open, allowing capacitor 443 to charge and raise the frequency of the F_IFMAX signal, with the rate of rise being governed by the charge time of the negative jerk capacitor 443. During resistive braking, the excessive armature brake current signal L is again used to control the field inhibit signal V_FI to regulate the field strength at a level which maintains the armature brake current at the F_CLB current limit. Since a lower level of field current is required to produce maximum armature brake current during resistive braking, the field monostable 320 is triggered at a lower rate during such time to provide smoother operation. This is accomplished by combining the and signals by NAND gate 456.

These signals will all be high when braking, when the speed decreases below 1920 rpm and after the one-second delay of monostable 277. The output of NAND gate 456 will go low, the output of inverter 457 will be high and close transmission gate 458 to connect resistor 459 and capacitor 460 in series with resistor 430. The voltage input to VCO 318 will rise from ground p potential, at a rate determined by the values of resistor 430 and capacitor 460, to a reduced level determined by the values of voltage dividing resistors 430 and 459.

The system will come out of deceleration, and back into the power mode of operation in the same manner as previously described when the FIG. 11 circuit is used. When the brake enable signal goes low

at the end of deceleration, gate 369 closes and gate 458 opens so that the field monostable will pulse in the power mode as previously described. Likewise, gate 451 opens so that the input of VCO 143 and the V_IFMAX signal are again controlled by the output of the R/2R network 311, As the system goes back into power mode, the output of gate 282 (FIG. 10) is used to clock shift registers 310 and 355 and thus apply a V_TFMAX signal to VCO 143 in accordance with the then existing count in counter 304. When the system is in a plugging form of braking, the FIG. 18 field control circuit will operate to regulate the armature brake current during regenerative and resistive braking in the same manner as just described. Other aspects, objects, and advantages of this invention can be obtained from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A power control comprising: a) a direct-current voltage source having positive and negative terminals, b) a load connected to one terminal of said voltage source, c) a first silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to said load and the other of which is connected to the other of said voltage source terminals, d) a second silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to said other terminal of said voltage source, e) a third silicon-controlled rectifier having main anode and cathode electrodes, f) an inductance connected to one of the main electrodes of said third silicon-controlled rectifier, g) means connecting one end of the series-connected inductance and third silicon-controlled rectifier to said one of said voltage source terminals and connecting the other end thereof to the other main electrode of said second silicon-controlled rectifier, h) a commutating capacitor having one side thereof connected to said one main electrode of said first silicon-controlled rectifier and the other side thereof connected to said other main electrode of said second silicon-controlled rectifier, i) means for repeatedly gating said first and third silicon-controlled rectifiers into simultaneous conduction at a controlled rate, j) means for gating said second silicon-controlled rectifier into conduction at a controlled time after each gating of said first silicon-controlled rectifier.

2. A power control as set forth in claim

1 wherein said one terminal of said voltage source is the negative polarity terminal thereof.

3. A power control as set forth in claim 1 and including a direct-current motor the armature of which is said load.

4. A power control as set forth in claim 1 and including a direct-current motor the armature of which is said load, said motor having a separately excitable field connectable to said voltage source for excitation therefrom.

5. A power control as set forth in claim

4 and further including: k) means for monitoring the level of armature current through said first silicon-controlled rectifier and for generating a signal when said current exceeds a predetermined level. l) means responsive to the presence of said signal for increasing the excitation of said field.

6. A power control as set forth in claim

5 and further including: m) means responsive to the presence of said signal for inhibiting the gating on of said first silicon-controlled rectifier during the existence of said signal.

7. A power control as set forth in claim 4 and further including: k) a fourth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to one of said voltage source terminals, l) means for connecting said field to the other main electrode of said fourth silicon-controlled rectifier and to the other terminal of said voltage source and for reversing the connection of said field to said fourth silicon-controlled rectifier and said voltage source, m) a fifth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to the same voltage source terminal as is said one main electrode of said fourth silicon-controlled rectifier, n) a sixth silicon-controlled rectifier having main anode and cathode electrodes, o) an inductance connected to one of the main electrodes of said sixth silicon-controlled rectifier, p) means connecting one end of the series-connected inductance and sixth silicon-controlled rectifier to the voltage source terminal to which said field is connected and connecting the other end thereof to the other main electrode of said fifth silicon-controlled rectifier, q) a commutating capacitor connected from said one main electrode of said fourth silicon-controlled rectifier to said other main electrode of said fifth silicon-controlled rectifier, r) means for repeatedly gating said fourth and sixth silicon-controlled rectifiers into conduction at 8wcontrolled rate, s) means for gating said fifth silicon-controlled rectifier into conduction at a controlled time after each gating of said fourth silicon-controlled rectifier.

8. A power control circuit as set forth in claim 1 including a direct-current motor, the armature of which is said load, wherein said second silicon-controlled rectifier is connected directly to said third silicon-controlled rectifier, and further including: k) a fourth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to the corresponding main electrode of said third silicon-controlled rectifier and the other of which is connected to the junction of said first silicon-controlled rectifier and said armature, l) means operable during operation of said motor for inhibiting the gating of said first and third silicon-controlled rectifier into conduction, m) means for gating said fourth silicon-controlled rectifier into conduction during the time said first silicon-controlled rectifier is inhibited from being gated into conduction, n) means for gating said second silicon-controlled rectifier into conduction during the conduction of said fourth silicon-controlled rectifier. o) means for thereafter gating said third silicon-controlled rectifier into conduction while preventing said first silicon-controlled rectifier from being gated into conduction prior to commutation of said fourth silicon-controlled rectifier.

9. A power control circuit as set forth in claim 8 wherein said motor includes a separately excitable field connected to said voltage source for excitation therefrom.

10. A power control circuit as set forth in claim 9 and further including: p) means for monitoring the level of current through said armature during the time that said fourth silicon-controlled rectifier is in conduction and for generating a signal when said current exceeds a predetermined level, q) means responsive to the presence of said signal for decreasing the excitation of said field.

11. A power control as set forth in claim 9 and further including: p) means for monitoring the level of armature current through said first silicon-controlled rectifier and for generating a signal when said current exceeds a predetermined level, q) means responsive to the presence of said signal for increasing the excitation of said field.

12. A power control circuit as set forth in claim 11 and further including: r) means for monitoring the level of current through said armature during the time that said fourth silicon-controlled rectifier is in conduction and for generating a second signal when said current exceeds a predetermined level, s) means responsive to the presence of said second signal for decreasing the excitation of said field .

13. A power control as set forth in claim 9 and further including: p) a fifth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to one of said voltage source terminals, q) means for connecting said field to the other main electrode of said fifth silicon-controlled rectifier and to the other terminal of said voltage source and for reversing the connection of said field to said fourth silicon-controlled rectifier and said voltage source, r) a sixth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to the same voltage source terminal as is said one main electrode of said fifth silicon-controlled rectifier, s) a seventh silicon-controlled rectifier having main anode and cathode electrodes, t) an inductance connected to one of the main electrodes of said seventh silicon-controlled rectifier, u) means connecting one end of the seriesconnected inductance and seventh silicon-controlled rectifier to the voltage source terminal to which said field is connected and connecting the other end thereof to the other main electrode of said sixth silicon-controlled rectifier, v) a commutating capacitor connected from said one main electrode of said fifth silicon-controlled rectifier to said other main electrode of said sixth silicon-controlled recitfier, w) means for repeatedly gating said fifth and seventh silicon-controlled rectifier into conduction at a controlled rate, x) means for gating said sixth silicon-controlled rectifier into conduction at a controlled time after each gating of said fifth silicon-controlled rectifier.

14. A power control as set forth in claim 13 and further including: y) means for monitoring the level of armature current through said first silicon-controlled rectifier and for generating a signal when said current exceeds a predetermined level, z) means responsive to the presence of said signal for increasing the conduction time per cycle of operation of said fifth silicon-controlled rectifier.

15. A power control as set forth in claim

13 and further including: y) means for monitoring the level of armature current during the time said fourth silicon-controlled rectifier is in conduction and for generating a signal when said current exceeds a predetermined level, z) means responsive to said signal for inhibiting conduction of said fifth silicon-controlled rectifier.

16. A power control as set forth in claim 13 and further including: y) means for monitoring the level of current through said armature and for generating a first signal when the armature current flowing through said first silicon-controlled rectifier exceeds a predetermined level and for generating a second signal when the armature current exceeds a predetermined level during the time that said fourth silicon-controlled rectifier is in conduction, z) means responsive to said signals for increasing the conduction time per cycle of operation of said fifth silicon-controlled rectifier during the presence of said first signal and for inhibiting conduction of said fifth silicon-controlled rectifier during the presence of said second signal.

17. A power control as set forth in claim 8 and further including: p) a fifth silicon-controlled rectifier connected across said first silicon-controlled rectifier and reversely poled relative thereto, q) means for gating said fifth siliconcontrolled rectifier into conduction during the time said first silicon-controlled rectifier is inhibited, r) means responsive to the speed of said motor for enabling said fifth silicon-controlled rectifier to be gated into conduction only when the motor speed is above a predetermined value and for enabling said fourth silicon-controlled rectifier to be gated into conduction only when the motor speed is below said predetermined value.

18. A power control as set forth in claim 17 wherein said motor includes a separately excitable field and further including: s) means connecting said field to said voltage source for excitation therefrom, t) means for automatically increasing the excitation of said field during conduction of said fifth silicon-controlled rectifier.

19. A power control as set forth in claim 17 wherein said motor includes a separately excitable field and further including: s) means connecting said field to said voltage source for excitation therefrom, t) means for removing and then restoring the excitation of said field when the speed of said motor is substantially at said predetermined speed and prior to gating said fourth silicon-controlled rectifier into conduction.

20. A power control as set forth in claim 17 wherein said motor includes a separately excitable field and further including: s) means connecting said field to said voltage source for excitation therefrom, t) means for monitoring the level of current flow through said armature during conduction of either of said fourth and fifth silicon-controlled rectifiers and for generating a signal when said current exceeds a predetermined level, u) means responsive to said signal for inhibiting excitation of said field during the presence of said signal.

21. A power control as set forth in claim 17 wherein said motor includes a separately excitable field, and further including: s) a sixth silicon-controlled rectifier having main anode and cathode electrodes one of which is connected t4 one of said voltage source terminals, t) means for connecting said field to the other main electrode of said sixth silicon-controlled rectifier and to the other terminal of said voltage source and for reversing the connection of said field to said sixth silicon-controlled rectifier and said voltage source, u) a seventh silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to the same voltage source terminal as is said one main electrode of said sixth silicon-controlled rectifier, v) an eight silicon-controlled rectifier having main anode and cathode electrodes, w) an inductance connected to one of the main electrodes of said eight silicon-controlled rectifier, x) means connecting one end of the series-connected inductance and eight silicon-controlled rectifier to the voltage source terminal to which said field is connected and connecting the other end thereof to the other main electrode of said seventh silicon-controlled rectifier, y) a commutating capacitor connected from said one main electrode of said sixth silicon-controlled rectifier to said other main electrode of said seventh silicon-controlled rectifier, z) means for repeatedly gating said sixth and eight silicon-controlled rectifiers into conduction at a controlled rate, aa) means for gating said seventh silicon-controlled rectifier into conduction at a controlled time after each gating of said sixth silicon-controlled rectifier.

22. A power control as set forth in claim 21 and further including: bb) means for monitoring the level of armature current through said first silicon-controlled rectifier and for generating a signal when said current exceeds a predetermined level, cc) means responsive to the presence of said signal for increasing the conduction time per cycle of operation of sixth silicon-controlled rectifier.

23. A power control as set forth in claim

21 and further including: bb) means for monitoring the level of armature current during conduction of either said fourth or fifth silicon-controlled rectifiers and for generating a signal when said current exceeds a predetermined level, cc) means responsive to said signal for inhibiting conduction of said sixth silicon-controlled rectifier.

24. A power control as set forth in claim 21 and further including: bb) means for monitoring the level of current through said armature and for generating a first signal when the armature current flowing through said first silicon-controlled rectifier exceeds a predetermined level and for generating a second signal when the armature current exceeds a predetermined level during the time that said either of said fourth or fifth silicon-controlled rectifiers is in conduction, cc) means responsive to said signal for increasing the conduction time per cycle of operation of said sixth silicon-controlled rectifier during the presence of said first signal and for inhibiting conduction of said sixth silicon-controlled rectifier during the presence of said second signal.

25. A power control as set forth in claim

1, wherein said load is the armature of a direct-current motor, and further including: k) a free-wheeling diode connected across said armature, l) a first zener diode and a first resistorconnected in series with each other, said zener diode being connected to said other side of said commutating capacitor and said resistor being connected to said one terminal of said voltage source, m) a second zener diode and a second resistor connected in series with each other, said second zener diode being connected to said one terminal of said voltage source and said second resistor being connected to the junction of said first zener diode and first resistor.

26. A power control as set forth in claim 25 wherein said first zener diode has a voltage drop thereacross substantially equal to the voltage of said voltage source.

27. A power control as set forth in claim

7, and further including: t) a freewheeling diode connected across said field, u) a zener diode and resistor connected in series with each other, said zener diode being connected to one side of said freewheeling diode and said resistor being connected to the other side of said freewheeling diode.

28. A power control as set forth in claim

27 and further including: v) a freewheeling diode connected across said armature, w) a second zener diode and second resistor connected in series with each other, said second zener diode being connected to said other side of said commutating capacitor and said second resistor being connected to said one terminal of said voltage source, x) a third zener diode and third resistor connected in series with each other, said third zener diode being connected to said one terminal of said voltage source, and said third resistor being connected to the junction of said second zener diode and said second resistor.

29. A power control as set forth in claim

28 wherein said second zener diode has a voltage drop thereacross substantially equal to the voltage of said voltage source.

30. A power control as set forth in claim

7 and further including: t) means responsive to the level of current through said field for preventing reversal of the field connection by said means (l) during the time that said field current is greater than a predetermined minimum level.

31. A power control as set forth in claim 7 wherein said means (l) includes a manually operable member for initiating reversal of the field connection in response to actuation of said member, and further including: t) means responsive to the level of current through said field for preventing reversal of the field connection by said means (l) during the time that said field current is greater than a predetermined minimum level.

32, In a system for use in the control of power delivered to a load from a source of direct current, said system including a main silicon-controlled rectifier through which load current can flow when the main siliconcontrolled rectifier is in conduction, a commutating capacitor which charges to a commutating voltage and a commutating silicon-controlled rectifier which when gated into conduction will connect the commutating capacitor across the main silicon-controlled rectifier, the improvement comprising: a) a pulse generator means for generating a single pulse in response to the application of a trigger pulse thereto, b) trigger means for generating a series of trigger pulses at a controlled rate and for applying said trigger pulses to said pulse generator means. c) first gating means responsive to the initiation of each pulse of said pulse generator means for gating said main silicon-controlled rectifier into conduction. d) second gating means responsive to the termination of each pulse of said pulse generator means for gating said commutating silicon-controlled rectifier into conduction.

33. An improvement as set forth in claim 32, said improvement further including: e) an operatobe-operable variable resistor, f) means for varying the rate of generation of said trigger pulses by said trigger means in accordance with the setting of said variable resistor.

34. An improvement as set forth in claim 32, said improvement further including: e) means for adjusting the duration of the pulse generated by said pulse generator means.

35. An improvement as set forth in claim 32, said improvement further including: e) an operator-controllable variable resistor, f) means for varying the rate of generation of said trigger pulses by said trigger means in accordance with the setting of said variable resistor, g) means for adjusting the duration of the pulse generated by said pulse generator means.

36. An improvement as set forth in claim 32 wherein said second gating means includes: (i) a second pulse generator means for generating a single pulse in response to the application of a trigger pulse thereto; (ii) means for triggering said second pulse generator means in response to the termination of each pulse of said just-mentioned pulse generator means (a), and (iii) means responsive to each generation of a pulse by said second pulse generator means for gating said commutating silicon-controlled rectifier into conduction.

37. In a system as set forth in claim 32 wherein said load with which said system is usable is the armature of a direct-current motor and wherein the improvement of said system further includes: e) an operator-controlled speed-demand member, f) means for varying the rate of generation . of said trigger pulses by said trigger means in accordance with the demanded speed setting of said speed-demand member.

38. The improvement as set forth in claim

37, said improvement further including: g) means for determining the actual speed of said motor, h) means for comparing the actual speed of said motor and the speed demanded by the setting of said speed-demand member and for generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, i) means responsive to the presence of said acceleration signal for increasing the duration of the pulse generated by said pulse generator means.

39. The improvement as set forth in claim 37, the improvement further including: g) means for determining the actual speed of said motor, h) means for comparing the actual speed of said motor and the speed demanded by the setting of said speed-demand member and for generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, i) means responsive to the presence of said acceleration signal for increasing the rate of generation of the trigger pulses generated by said trigger means.

40. The improvement as set forth in claim 37, the improvement further including: g) means for determining the actual speed of said motor, h) means for comparing the actual speed of said motor and the speed demanded by the setting of said speed-demand member and for generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, i) means responsive to the presence of said acceleration signal for increasing the duration of the pulse generated by said pulse generator means, j) means responsive to the presence of said acceleration signal for increasing the rate of generation of the trigger pulses generated by said trigger means.

41. The improvement as set forth in claim 37, the improvement further including: g) means for generating an actual-speed signal proportional to the actual speed of said motor, h) means for generating a demanded-speed signal proportional to the setting of said speed-demand, member, i) means for comparing said actual-speed signal and said demanded-speed signal and for generating a first acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a first predetermined degree and for generating a second acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a second, and greater, predetermined degree, j) means responsive to the presence of said first acceleration signal and the absence of said second acceleration signal for increasing the duration of the pulse generated by said pulse generator means by a first amount, k) means responsive to the presence of said second acceleration signal for increasing the duration of the pulse generated by said pulse generator means by a second, and greater, amount.

42. The improvement as set forth in claim 37, the improvement further including: g) means for generating an actual speed signal proportional to the actual speed of said motor, h) means for generating a demanded speed signal proportional to the setting of said speed-demand member, i) means for comparing said actual speed signal and said demanded speed signal and for generating a first acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a first predetermined degree and for generating a second . acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a second, and greater, predetermined degree , j) means responsive to the presence of said first acceleration signal and the absence of said second acceleration signal for increasing the rate of generation of trigger pulses by said trigger means by a first degree, k) means responsive to the presence of said second acceleration signal for increasing the rate of generation of trigger pulses by said trigger means by a second, and greater, degree.

43. The improvement as set forth in claim 37, the improvement further including: g) means for generating an actual speed signal proportional to the actual speed of said motor, h) means for generating a demanded-speed signal proportional to the setting of said speed-demand member. i) means for comparing said actual speed signal and said demanded-speed signal and for generating a first acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a first predetermined degree and for generating a second acceleration signal when the demanded-speed signal is greater than the actual-speed signal by a second, and greater, predetermined degree, j) means responsive to the presence of said first acceleration signal and the absence of said second acceleration signal for increasing the duration of the pulse generated by said pulse generator means by a first amount, k) means responsive to the presence of said second acceleration signal for increasing the duration of the pulse generated by said pulse generator means by a second, and greater, amount, l) means responsive to the presence of said first acceleration signal and the absence of said second acceleration signal for increasing the rate of generation of trigger pulses by said trigger means by a first degree, m) means responsive to the presence of said second acceleration signal for increasing the rate of generation of trigger pulses by said trigger means by a second, and greater, degree.

44. In a system as set forth in claim 32 wherein said load with which said system is usable is the armature of a direct-current motor and wherein said pulse generator means is a monostable multivibrator connected for retrigger operation, and further including: e) means for determining the speed of said motor for increasing the duration of the pulse of said monostable oscillator to an amount greater than the period of the trigger pulses generated by said trigger means when the speed of said motor is determined to be above a predetermined level.

45. A power control comprising: a) a direct-current voltage source having positive and negative terminals, b) a load connected to one terminal of said voltage source, c) a first silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to said load and the other of which is connected to the other terminal of said voltage source, d) a second silicon-controlled rectifier having main anode and cathode electrodes one of which is connected to said other terminal of said voltage source, e) a third silicon-controlled rectifier having main anode and cathode electrodes, f) an inductance connected to one of the main electrodes of said third silicon-controlled rectifier, g) means connecting one end of the series-connected inductance and third silicon-controlled rectifier to said one terminal of said voltage source and the other end thereof to the other main electrode of said second silicon-controlled rectifier, h) a commutating capacitor having one side thereof connected to said one main electrode of said first silicon-controlled rectifier and the other side thereof connected to said other main electrode of said second silicon-controlled rectifier, i) a pulse generator means for generating a single pulse in response to the application of a trigger pulse thereto, j) trigger means for generating a series of trigger pulses at a controlled rate and for applying said trigger pulses to said pulse generator means, k) means responsive to the initiation of each pulse by said pulse generator means for gating said first and third silicon-controlled rectifiers into conduction, l) means responsive to the termination of each pulse by said pulse generator means for gating said second silicon-controlled rectifier into conduction.

46. In a system as set forth in claim 45 and further including: m) an operator-controllable variable demand member, n) means for varying the rate of generation of said trigger pulses by said trigger means in accordance with the setting of said demand member.

47. In a system as set forth in claim 45 and further including: m) means for adjusting the duration of the pulses generated by said pulse generator means.

48. In a system as set forth in claim 45 and further including: m) an operator-controllable variable demand member, n) means for varying the rate of generation of said trigger pulses by said trigger means in accordance with the setting of said demand member, o) means for adjusting the duration of the pulses generated by said pulse generator means.

49. In a system for controlling the operation of a direct-current motor having an armature and a separately excited field, said system including a first silicon-controlled rectifier connectable to said armature and through which armature current can flow when said first silicon-controlled rectifier is in conduction, a first commutating capacitor which charges to a commutating voltage a second silicon-controlled rectifier which when gated into conduction will connect the first commutating capacitor across the first silicon-controlled rectifier, a third silicon-controlled rectifer connectable to said field and through which field current can flow when said third silicon-controlled rectifier is in conduction, a second commutating capacitor which charges to a commutating voltage and a fourth silicon-controlled rectifier which when gated into conduction will connect the second commutating capacitor across the third silicon-controlled rectifier, the improvement comprising: a) a first pulse generator means for generating a single pulse in response to the application of a trigger pulse thereto, b) first trigger-pulse means for generating a series of trigger pulses at a controllable rate and for applying said trigger pulses to said first pulse generator means, c) means responsive to the initiation of each pulse of said first pulse generator means for gating said first silicon-controlled rectifier into conduction, d) means responsive to the termination of each pulse of said first pulse generator means for gating said second silicon-controlled rectifier into conduction, e) a second pulse generator means for generating a single pulse in response to the application of a trigger pulse thereto, f) second trigger-pulse means for generating a series of trigger pulses at a controllable rate and for applying said trigger pulses to said second pulse generator means, g) means responsive to the initiation of each pulse of said seocnd pulse generator means for gating said third silicon-controlled rectifier into conduction, h) means responsive to the termination of each pulse of said second pulse generator means for gating said fourth silicon-controlled rectifier into conduction, i) an operator-controlled variable speed-demand member, j) means for varying the rate of generation of said trigger pulses by said first trigger-pulse means in direct accordance with the setting of said speed-demand member, k) means for varying the rate of generation of said trigger pulses by said second trigger-pulse means in inverse accordance with the setting of said speed-demand member.

50. In a control for a direct-current motor system, said motor having an armature and a separately excited field, said armature being connected to a source of direct current through a first silicon-controlled rectifier, said field being connected to said source through a second silicon-controlled rectifier, said system including an operator-controlled speed-demand member, a first pulse-generator means for turning said first silicon-controlled rectifier on and off in accordance with the setting of said speed-demand member to control the flow of power current through said armature, a second pulse-generator means for turning said second silicon-controlled rectifier on and off in accordance with the setting of said speed-demand member, and means for disabling said first pulse generator means and for connecting said armature for reverse flow of brake current therethrough in the event of a demanded deceleration, the imrovement comprising: a) first means for monitoring the level of armature current flowing through said armature, b) second means for generating an armature- current signal having a frequency indicative of the level of armature current, said signal having a predetermined frequency corresponding to zero armature current, said signal having a frequency which differs from said predetermined frequency and in one direction therefrom in response to the presence of armature power current and which differs from said predetermined frequency in said one direction to a degree proportional to the level of armature power current, said signal having a frequency which differs from said predetermined frequency and in the opposite direction therefrom in response to the presence of armature brake current and which differs from said predetermined frequency in said opposite direction to a degree proportional to the level of armature brake current, c) third means for generating a current-limit reference signal having a frequency different from said predetermined frequency, d) fourth means for comparing said armature-current signal and said current-limit signal and for generating a control signal dependent upon whether the frequency of said armature-current signal is above or below the frequency of said current-limit reference signal, e) fifth means responsive to the generation of said control signal for varying the operation of said second pulse generator means to change the level of current flow through said second silicon-controlled rectifier and field.

51. In a control as set forth in claim 50, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said one direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, and wherein said fifth means (e) includes means for varying the operation of said second pulse generator means to increase the level of current flow through said second silicon-controlled rectifier and field in response to the generation of said control signal.

52. In a control as set forth in claim 51, and further including: f) means responsive to the generation of said control signal for inhibiting operation of said first pulse generator means.

53. In a control as set forth in claim 50, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said opposite direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, and wherein said fifth means (e) includes means for varying the operation of said second pulse generator means to decrease the level of current flow through said second silicon-controlled rectifier and field in response to the generation of said control signal.

54. In a control system as set forth in claim 53 and further including: f) means for generating a speed-demand signal proportional to the setting of said speed-demand member, g) means for generating an actual-speed signal proportional to the actual speed of said motor, h) means for comparing said speed-demand and actual-speed signals and for determining the magnitude of difference therebetween, and wherein said third means (c) includes means for varying the frequency of said current-limit signal such that the degree of difference between the frequency of said current-limit signal and said predetermined frequency varies proportionally to the magnitude of difference between said actual-speed and speed-demand signals.

55. In a control as set forth in claim 50, the improvement further comprising: f) sixth means for generating a second current-limit reference signal having a frequency different from said predetermined frequency, the frequency of one of said current-limit reference signals of said fourth and sixth means (d) and (f) being greater than said predetermined frequency and the frequency of the other of said current-limit reference signals being less than said predetermined frequency, g) seventh means for comparing said armature-control signal and said second current-limit reference signal and for generating a control signal dependent upon whether the frequency of said armature-control signal is above or below the frequency of said second current-limit reference, h) eighth means responsive to the generation of said control signal by said seventh means (g) for varying the operation of said second pulse generator to change the level of current flow through said second silicon-controlled rectifier and field in a manner opposite to that effected by said fifth means (e).

56. In a control as set forth in claim 55, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said one direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, wherein said fifth means (e) includes means for varying the operation of said second pulse generator means to increase the level of current flow through said second silicon-controlled rectifier and field in response to generation of said control signal of fourth means (d), wherein said sixth means (f) includes means for generating said second current-limit reference signal such that its frequency differs from said predetermined frequency in said opposite direction therefrom, wherein said seventh means (g) includes means for generating said second control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said second current-limit signal and said predetermined frequency, and wherein said eighth means (h) includes means for varying the operation of said second pulse generator means to decrease the level of current flow through said second silicon-controlled rectifier and field in response to the generation of said second control signal.

57. In a control as set forth in claim 56 and further including: i) means responsive to the generation of said first control signal for Inhibiting operation of said first pulse generator means.

58. In a control system as set forth in claim 56 and further including: i) means for generating a speed-demand signal proportional to the setting of said speed-demand member, j) means for generating an actual-speed signal proportional to the actual speed of said motor, k) means for comparing said speed-demand and actual-speed signals and for determining the magnitude of difference therebetween, and wherein said sixth means (f) includes means for varying the frequency of said second currentlimit signal such that the degree of difference between the frequency of said second current-limit signal and said predetermined frequency varies proportionally to the magnitude of difference between said actual-speed and speed-demand signals.

59. In a control as set forth in claim 58, and further including: l) means responsive to the generation of said first control signal for inhibiting operation of said first pulse generator means.

60. In a control system as set forth in claim

50 , wherein said firs t means (a) includes means for sensing armature current and having a pair of output terminals in which the magnitude of voltage between said terminals is proportional to the magnitude of armature current and in which the relative polarities of voltage at said terminals will vary in accordance with the direction of current flow through said armature, and wherein said second means (b) includes an operational amplifier having its inputs connected to said output terminals of said first means (a), and wherein said second means (b) further includes a voltage-controlled oscillator having its input connected to the output of said operational amplifier.

61. In a control as set forth in claim 60, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said one direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, and wherein said fifth means (e) includes means for varying the operation of said second pulse generator means to increase the level of current flow through said second silicon-controlled rectifier and field in response to the generation of said control signal.

62. In a control as set forth in claim 60, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said opposite direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, and wherein said fifth means (e) includes means for varying operation of said second pulse generator means to decrease the level of current flow through said second silicon-controlled rectifier and field in response to generation of said control signal.

63. In a control system as set forth in claim 62 and further including: f) means for generating a speed-demand signal proportional to the setting of said speed-demand member, g) means for generating an actual-speed signal proportional to the actual speed of said motor, h) means for comparing said speed-demand and actual-speed signals and for determining the magnitude of difference therebetween, and wherein said third means (c) includes means for varying the frequency of said current-limit signal such that the degree of difference between the frequency of said current-limit signal and said predetermined frequency varies proportionally to the magnitude of difference between said actual-speed and speed-demand signals.

64. In a control system as set forth in claim 62 and further including: f) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, g) means for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, h) counter means for continuously counting the number of cycles of said speed-demand signal per cycle of said actual-speed signal, and wherein said third means (c) includes means for varying the frequency of said second current-limit signal such that the degree of difference between the frequency of said second current-limit signal and said predetermined frequency varies inversely to the count of said counter means.

65. In a control as set forth in claim 60, the improvement further comprising: f) sixth means for generating a second current-limit reference signal having a frequency different from said predetermined frequency, the frequency of one of said current-limit reference signals of said fourth and sixth means (d) and (f) being greater than said predetermined frequency and the frequency of the other of said current-limit reference signals being less than said predetermined frequency, g) seventh means for comparing said armature-control signal and said second current-limit reference signal and for generating a control signal dependent upon whether the frequency of said armature-control signal is above or below the frequency of said second current-limit reference, h) eighth means responsive to the generation of said control signal by said seventh means (g) for varying the operation of said second pulse generator to change the level of current flow through said second silicon-controlled rectifier and field in a manner opposite to that effected by said fifth means (e).

66. In a control as set forth in claim 65, wherein said third means (c) includes means for generating said current-limit reference signal such that its frequency differs from said predetermined frequency in said one direction therefrom, wherein said fourth means (d) includes means for generating said control signal when the difference between the frequency of said armature-current signal and said predetermined frequency is greater than the difference between the frequency of said current-limit signal and said predetermined frequency, wherein said fifth means (e) includes means for varying the operation of said second pulse generator means to increase the level of current flow through said second silicon-controlled rectifier and field in response to generation of said control signal of said fourth means (d), wherein said sixth means (f) includes means for generating said second current-limit reference signal such that its frequency differs from said predetermined frequency in said opposite direction therefrom, wherein said seventh means (g) includes means for generating said second control signal when the difference between the frequency of said armature-current signal and said predetermined frequency, and wherein said eighth means (h) includes means for varying the operation of said second pulse generator means to decrease the level of current flow through said second silicon-controlled rectifier and field in response to generation of said second control signal.

67. In a control system as set forth in claim 66 and further including: i) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) means for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, k) counter means for continuously counting the number of cycles of said speed-demand signal per cycle of said actual-speed signal, and wherein said sixth means (f) includes means for varying the frequency of said second current-limit signal such that the degree of difference between the frequency of said second current-limit signal and said predetermined frequency varies inversely to the count of said counter means.

68. In a system for controlling the power delivered to a load from a source of direct current and including main power contacts in series with said load for connecting said load to said source, a main silicon-controlled rectifier through which load current can flow when the main silicon-controlled rectifier is in conduction, a commutating capacitor which charges to a commutating voltage and a commutating silicon-controlled rectifier which when gated into conduction will connect the commutatin capacitor across the main silicon-controlled rectifier, the improvement comprising: a) first means for generating a series of first pulses, b) second means for gating on said mail silicon-controlled rectifier in response to the generation of each of said first pulses, c) third means for generating a second pulse in response to the generation of each of said first pulses, each said second pulse terminating before the generation of the next of said first pulses, d) fourth means for gating on said commutating silicon-controlled rectifier in response to each of said second pulses, e) fifth means for monitoring the conduction state of said main silicon-controlled rectifier and for generating a signal during conduction of said main silicon-controlled rectifier, f) sixth means operable during the time period from the end of a second pulse until the beginning of the next of said first pulses and responsive to said conduction state signal for actuating said main power contacts to disconnect said load from said source in the event said conduction state signal is present during said time period.

69. In a system as set forth in claim 68, the improvement further including: g) means for monitoring the level of current through said load and for generating a second signal when said current is below a predetermined minimum, h) means responsive to the presence of said third signal for inhibiting said sixth means (f) from responding to the presence of said conduction state signal during said time period.

70. in a system as set forth in claim 68 , wherein said third means (c) is responsive to the termination of each of said first pulses .

71. In a system as set forth in claim 70, the improvement further comprising: g) operator-controlled means for adjusting the frequency of generation of said first pulses to a desired rate.

72. In a system as set forth in claim 70, the improvement further comprising: g) means for adjusting the length of said first pulses to a desired value.

73. In a system as set forth in claim 70, the improvement further comprising: g) operator-controlled means for adjusting the frequency of generation of said first pulses to a desired rate, h) means for adjusting the length of said first pulses to a desired value.

74. In a system as set forth in claim 73, the improvement further including: i) means for monitoring the level of current through said load and for generating a second signal when said current is below a predetermined minimum, j) means responsive to the presence of said third signal for inhibiting said sixth means (f) from responding to the presence of s aid conduction state signal during said time period,

75. In a system as set forth in claim 68 and further including: g) means for delaying the response of said sixth means (f) to said conduction state signal until said conduction state signal has been present for at least two consecutive of said time periods.

76. In a system for controlling the power delivered to a load from a source of direct current and including main power contacts in series with said load for connecting said load to said source, a main silicon-controlled rectifier through which load current can flow when the main silicon-controlled rectifier is in conduction, a commutating capacitor which charges to a commutating voltage and a commutating silicon-controlled rectifier which when gated into conduction will connect the commutating capacitor across the main silicon-controlled rectifier, the improvement comprising: a) first means for generating a series of first pulses, b) second means for gating on said main silicon-controlled rectifier in response to the generation of each of said first pulses, c) third means for generating a second pulse in response to the generation of each of said first pulses, d) fourth means for gating on s aid commutating silicon-controlled rectifier in response to each of said second pulses, e) fifth means for generating a first signal beginning with the end of each of said first pulses and ending with the beginning of the next of said first pulses, f) sixth means for generating a second signal beginning with the end of each of said second pulses and ending with the beginning of the next of said second pulses, g) seventh means for monitoring the state of conduction of said main silicon-controlled rectifier and for generating a third signal during conduction of said main silicon-controlled rectifier, h) eighth means responsive to a time coincidence of said first, second and third signals for actuating said main power contacts to disconnect said load from said source.

77. In a system as set forth in claim 76, the improvement further including: i) means for monitoring the level of current through said load and for generating a fourth signal when said current is below a predetermined minimum, j) means responsive to the presence of said third signal for inhibiting operation of said eighth means (h).

78. In a system as set forth in claim 76 wherein said third means (c) is responsive to the termination of each of said first pulses.

79. In a system as set forth in claim 78, the improvement further comprising: i) operator-controlled means for adjusting the frequency of generation of said first pulses to a desired rate.

80. In a system as set forth in claim 78, the improvement further comprising: i) means for adjusting the length of said first pulses to a desired value.

81. In a system as set forth in claim 78, the improvement further comprising: i) operator-controlled means for adjusting the frequency of generation of said first pulses to a desired rate, j) means for adjusting the length of said first pulses to a desired value.

82. In a system as set forth in claim 81, the improvement further including: k) means for monitoring the level of current through said load and for generating a fourth signal when said current is below a predetermined minimum, l) means responsive to the presence of said third signal for inhibiting operation of said eighth means (h).

83. In a system for controlling the power delivered to a load from a source of direct current and including main power contacts in series with said load for connecting said load to said source, a main silicon-controlled rectifier through which load current can flow when said main silicon-controlled rectifier is in conduction, a commutating capacitor which charges to a commutating voltage and a commutating silicon-controlled rectifier which when gated into conduction will connect the commutating capacitor across the main silicon-controlled rectifier, the improvement comprising: a) a first monostable means for generating a single pulse in response to the application of a trigger pulse thereto and for generating a first signal during the time that said first monostable means is not generating pulses, b) a second monostable means for generating a single pulse in response to the application of a trigger pulse thereto and for generating a second signal during the time that said second monostable means is not generating pulses, c) means for generating a series of trigger pulses at a controlled rate and for applying said trigger pulses to said first monostable means, d) means responsive to the initiation of each pulse of said monostable generator means for gating said main silicon-controlled rectifier into conduction, e) means responsive to the termination of each pulse of said first monostable means for triggering said second monostable means, f) means for gating said commutating silicon-controlled rectifier into conduction in response to the initiation of each pulse of said second monostable means. g) means for monitoring the state of conduction of said main silicon-controlled rectifier and for generating a third signal during conduction of said main silicon-controlled rectifier, h) actuating means responsive to said first, second and third signals and to a time coincidence thereof for actuating said main power contacts to disconnect said load from said source.

84. In a system as set forth in claim 83 and further including: i) means for delaying the response of said actuating means (h) to said third signal until at least the second successive time coincidence of said first, second and third signals.

85. A system for reversing the connection of the field of a direct-current motor to a source of direct current, comprising: a) a manually operable direction-selection member having forward and reverse positions, b) first means for connecting said field in one direction to said source of direct current for forward operation of said motor in response to movement of said direction-selection member to its forward position, c) second means for connecting said field in the opposite direction to said source of direct current for reverse operation of said motor in response to movement of said direction-selection member to its reverse position, d) third means for monitoring the level of field current and for generating signals indicative of whether the field current is above or below a predetermined minimum level, e) fourth means responsive to the signals of said third means (d) for maintaining a connection made by one of said first or second means (b) or (c) and for inhibiting operation of the other of said first or second means (b) or (c) for as long as the field current is above said predetermined minimum level.

86, A system as set forth in claim 85 and further including: f) a silicon-controlled rectifier in series with said field and said source of direct current, g) fifth means for repeatedly gating said silicon-controlled rectifier into conduction and for then commutating said rectifier, h) sixth means responsive to the actual speed of said motor and to movement of said direction-selection member from one of its positions to the other for preventing operation of said fifth means (g) when said motor has slowed down to below a predetermined minimum speed.

87. A system for connecting and disconnecting the field of a direct-current motor from a source of direct current, said system comprising: a) a manually-operable direction-selecting member having forward and reverse position, b) forward-field-connecting means for connecting said field in one direction to said source of direct current for forward operation of. said motor, c) first means for generating signals indicative of whether the field current is above or below a predetermined minimum value, d) second means for generating signals indicative of whether the direction-selecting member is in or out of its forward position, e) third means for generating signals indicative of whether the direction-selecting member is in or out of its reverse position, f) a flip-flop having outputs indicative of whether the flip-flop is in set condition or reset condition, g) fourth means responsive to the signals of said first, second and third means (c), (d) and (e) for:

1) setting said flip-flop when the direction-selection member is in forward position and the field current is below said minimum value;

2) resetting said flip-flop when the direction-selection member is in reverse position and the field current is below said mimumum value, h) fifth means responsive to the signals of said first and second means (c) and (d) and the outputs of said flip-flop for generating a forward control signal when: 1) said direction-selection member is in forward position and the field current is below said minimum value, or 2) said flip-flop is in set condition and the field current is above said minimum value, i) sixth means responsive to the presence of said forward control signal for actuating said forward-field-connecting means (b) and for maintaining said forward-fieldconnecting means (b) actuated as long as said forward control signal is present, and for deactuating said forward-field-connecting means (b) when said forward control signal is not present.

88. A system as set forth in claim 87 wherein said fifth means (h) includes means for generating said forward control signal during the time that said direction-selection member is in forward position and said flip-flop is in set condition,

89. A system as set forth in claim 88 wherein said fifth means (h) includes means also responsive to the signal of said third means (e) for generating said forward control signal during the time that said direction-selection member is in reverse position and said flip-flop is in set condition.

90. A system as set forth in claim 87 and further including: j) reverse- field- connecting means for connecting said field in the opposite direction to said source of direct current for reverse operation of said motor, k) seventh means responsive to the signals of said first and third means (c) and (e) and the outputs of said flip-flop for generating a reverse control signal when:

1) said direction-selection member is in reverse position and the field current is below said minimum value, or

2) said flip-flop is in reset condition and the field current is above said minimum value, l) means responsive to the presence of said reverse control signal for actuating said reverse-field-connecting means (j) and for maintaining said reverse-field-connecting means (j) actuated as long as said reverse control signal is present, and for deactuating said reverse-field-connecting means (j) when said reverse control signal is not present,

91. A system as set forth in claim 90 wherein said fifth means (h) includes means for generating said forward control signal during the time that said direction-selection member is in forward position and said flip-flop is in set condition, and wherein said seventh means (k) includes means for generating said reverse control signal during the time that said direction-selection member is in reverse position and said flip-flop is in reset condition.

92. A system as set forth in claim 91 wherein said fifth means (h) includes means also responsive to the signal of third means (e) for generating said forward control signal during the time that said direction-selection member is in reverse position and said flip-flop is in set condition, and wherein said seventh means (k) includes means also responsive to the signals of second means (d) for generating said reverse control signal during the time that said direction-selection member is in forward position and said flip-flop is in reset condition.

93. A system for connecting and disconnecting the field of a direct-current motor from a source of direct current, said system comprising: a) a manually operable direction-selecting member having forward, reverse and neutral position, b) forward-field-connecting means for connecting said field in one direction to said source of direct current for forward operation of said motor, c) first means for generating signals indicative of whether the field current is above or below a predetermined minimum value, d) second means for generating signals indicative of whether the actual speed of s aid motor is above or below a predetermined minimum speed, e) third means for generating signals indicative of whether the direction-selecting member is in or out of its forward position, f) fourth means for generating signals indicative of whether the direction-selecting member is in or out of its reverse position, g) a flip-flop having outputs indicative of whether the flip-flop is in set condition or reset condition, h) fifth means responsive to the signals of said first, second, third and fourth means (c), (d), (e) and (f) for:

(1) setting said flip-flop if, and only if, the direction selection member is in forward position, the field current is below said minimum value and the actual motor speed is below said minimum value; and for 2) resetting said flip-flop if, and only if, the direction selection member is in reverse position, the field current is below said minimum value and the actual motor speed is below said predetermined speed, i) sixth means responsive to the signals of said first, second and third means (c), (d) and (e) and said flip-flop for generating a forward control signal if, and as long as:

1) said direction-selection member is in forward position, the field current is below said minimum value and the actual motor speed is below said minimum speed, or

2) said flip-flop is in set condition and the field current is above said minimum value, j) seventh means responsive to the presence of said forward control signal for actuating said forward-field-connecting means (b), and for maintaining said forward field-connecting means (b) actuated as long as said forward control signal is present, and for deactuating said forward-field-connecting means (b) when said forward control signal is not present.

94. A system as set forth in claim 93 wherein said sixth means (i) includes means for generating said forward control signal, if, and as long as, said direction-selection member is in forward position and said flip-flop is in set condition.

95. A system as set forth in claim 94 wherein said sixth means (i) includes means also responsive to the signal of fourth means (f) for generating said forward control signal, if, and as long as, said direction-selection member is in reverse position, said flip-flop is above said minimum speed.

96 . A system as set forth in claim 93 and further including: k) reverse-f ield-connecting means for connecting said field in the opposite direction to said source of direct current for reverse operation of said motor, l) e ight means responsive to the signals of said first , second and fourth means (c ) , (d) and (f ) and said flip-flop for generating a reverse control s ignal if , and as long as :

(1) said direction-selection member is in reverse position, the field current is below said minimum value and the actual motor speed is below said minimum speed, or

(2) said flip-flop is in reset condition and the field current Is above said minimum value, m) means responsive to the presence of said reverse control signal for actuating said reverse-f ield-connecting means (k) and for maintaining said reverse-f ieId-connecting means (k) actuated as long as said reverse control signal is present, and for deactuating said reverse-f ield-connecting means (k) when said reverse control signal Is not present .

97. A system as set forth in claim 96 wherein said sixth means (i) Includes means for generating said forward control signal, If, and as long as, said direction-selection member is in forward position and said flip-flop is in set condition, and wherein said eighth means (l) includes means for generating said reverse control signal If, and as long as, said direction-selection member is in reverse position and said flip-flop is in reset condition.

98. A system as set forth in claim 97 wherein said sixth means (i) Includes means also responsive to the signal of said fourth means (f ) f or generating said forward control signal, If , and as long as , said direction-selection member is in reverse position, said flip-flop is in set condition and the actual speed of said motor is above said minimum speed, and wherein said eighth means (l) includes means also responsive to the signals of third means (e) for generating said reverse control signal If, and as long as, said direction-selection member is in forward position, said flip-flop is in reset condition and the actual speed of said motor is above said minimum speed.

99. A control system for a direct-current motor having an armature and a separately excited field, said armature being connected to a source of direct current through a first silicon-controlled rectifier and said field being connected to said source of direct current through a second silicon-controlled . rectifier, and there being an adjustable operator-controlled speed-demand member, the system comprising: a) means for generating an armature-control signal having a frequency normally proportional to the setting of said speed-demand member, b) first pulse generator means responsive to the generation of said armature-control signal for repeatedly gating on and commutating said first sillcon-controlled rectifier at the rate of the frequency of said armature-control signal, c) means responsive to rotation of said armature for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, d ) means for generating a speed-demand signal having a frequency inversely proportional to the s etting of said speed-demand member, e ) counter means for continuously obtaining a count of the number of cycles of said actual-speed s ignal per cycle of said speed-demand signal, f ) means for generating a field-control s ignal having a frequency which varies inversely with changes in the count obtained by said counter means , g ) second pulse generator means for repeatedly gating on and commutating said second s ilicon-controlled rectif ier, h) means for operating said second pulse generator means to vary the ratio of on-t ime to off-time of said second silicon-controlled rectifier as a function of the frequency of said field-control signal.

100. A control system as set forth in claim 99 and further including: i) means for generating a reference-speed signal having a predetermined frequency corresponding to a reference motor speed substantially less than maximum allowable speed, j) means for comparing said actual-speed signal of means (c) and said reference-speed signal and for generating a reference-speed control signal when and for as long as the actual speed of said motor is greater than said reference speed, k) means responsive to the presence of said reference-speed control signal for operating said first pulse generator means to maintain said first silicon-controlled rectifier in continuous conduction.

101. A control system as set forth in claim 99 and further including: i) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, j) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, k) means for comparing said power current signal and said power current reference signal and for generating a power current limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, l) means responsive to the presence of said power current limit control signal for preventing said first pulse generating means from gating on said first silicon-controlled rectifier, m) means responsive to the presence of said power current limit control signal for operating said second pulse generator means to Increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

102. A control system as set forth in claim 101 and further including: n) means for changing the frequency of said power current reference signal as a function of the count obtained by said counter means to decrease the maximum allowable level of power current as said count increases.

103. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) means for generating an acceleration signal when the count obtained by said second counter means is greater than a predetermined number, l ) means responsive to the generation of said acceleration signal for enabling said field-control signal generating means to respond to changes in the count obtained by said first counter means only when said acceleration signal is present.

104. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) means for generating an acceleration signal when the count obtained by said second counter means is greater than a predetermined number, l) means responsive to the generation of said acceleration signal for operating said first pulse generator means to increase the on-time to off-time of said first silicon-controlled rectifier beyond that normally called for by said armature-control signal.

105. A control system as set forth in claim 104 and further including: m) means responsive to the generation of said acceleration signal for operating said second pulse generator means to decrease the ratio of on-time to off-time of said second silicon-controlled rectifier from that normally called for by said field-control signal.

106. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actualspeed signal, k) means for generating a first acceleration signal when the count obtained by said second counter means is greater than a first predetermined number, l) means responsive to the generation of said acceleration signal for operating said second pulse generator means to decrease the ratio of on-time to off-time of said second silicon-controlled rectifier from that normally called for by said field-control signal.

107. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) means for generating a first acceleration signal when the count obtained by said second counter means is greater than a first predetermined number, l) means for generating a second acceleration signal when the count obtained by said second counter means is greater than a second predetermined number, said second predetermined number being higher than said first predetermined number, m) means responsive to the generation of said first acceleration signal for operating said first pulse generator means to Increase the on-time to off-time of said first silicon-controlled rectifier beyond that normally called for by said armature-control signal, n) means responsive to the generation of said second acceleration signal for operating said first pulse generator means to increase the on-time to off-time of said first silicon-controlled rectifier beyond that normally called for by said first acceleration signal.

108. A control system as set forth in claim 107 and further including: o) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, p) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, q) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, r) means responsive to the presence of said power current-limit control signal for preventing said first pulse generating means from gating on said first silicon-controlled rectifier, s) means responsive to the presence of said power current-limit control signal for operating said second pulse generator means to increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

109. A control system as set forth in claim 108 and further including: t) means for changing the frequency of said power current reference signal as a function of the count obtained by said first mentioned counter means (e) to decrease the maximum allowable level of power current as said count increases.

110. A control system as set forth in claim 108 and further including: t) means responsive to the generation of said second acceleration signal for changing the frequency of said power current reference signal to increase the maximum allowable level of power current during the time said second acceleration signal is present.

111. A control system as set forth in claim

107 and further including: o) means responsive to the generation of said first acceleration signal for operating said second pulse generator means to decrease the ratio of on-time to off-time of said second silicon-controlled rectifier from that normally called for by said field-control signal, p) means responsive to the generation of said second acceleration signal for operating said second pulse generator means to decrease the ratio of on-time to off-time of said second silicon-controlled rectifier from that called for by said first acceleration signal.

112. A control system as set forth in claim 107 and further including: o) means responsive to the generation of said first and second acceleration signals for enabling said field-control signal generating means to respond to changes in the count obtained by said first counter means only when at least one of said acceleration signals is present.

113. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand s ignal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) means for generating a deceleration signal when the count obtained by said second counter means is less than a first predetermined number, l) means responsive to the generation of said deceleration signal for preventing said first pulse generating means from gating on said first silicon-controlled rectifier, m) means responsive to the generation of said deceleration signal for connecting said armature for flow of brake current therethrough.

114. A control system as set forth in claim 113 and further including: n) means for generating an armature brake current signal having a frequency which varies in accordance with the level of brake current through said armature, o) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, p) means for comparing said armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, q) means responsive to the generation of said brake current-limit control signal for preventing said second pulse generator means from gating on said second silicon-controlled rectifier when said control signal is present and for allowing said second pulse generator means to gate on said second silicon-controlled rectifier when said control signal is not present.

115. A control system as set forth in claim 114 and further including: r) means for changing the frequency of said brake current reference signal as a function of the count obtained by said second counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

116. A control system as set forth in claim 113 and further including: n) means for generating a base-speed reference-speed signal having a predetermined frequency corresponding to the base speed of said motor, o) means for comparing said actual-speed signal and said base-speed reference signal and for generating a base-speed control signal Indicative of whether the actual speed of said motor is above or below the base speed thereof, p) means responsive to the presence of said deceleration signal and said base-speed control signal for connecting said armature to said source of direct current for flow of current from said armature to said source when the actual motor speed is above said base speed, q) means responsive to the presence of said deceleration signal and said base-speed control signal for shorting across said armature when the actual motor speed is below said base speed.

117. A control system as set forth in claim 116 and further including: r) means responsive to the presence of said deceleration signal and to said base-speed control signal for operating said second pulse generation means to increase the ratio of on-time to off-time of said second silicon-controlled rectifier when the actual motor speed is above said base speed.

118. A control system as set forth in claim 117 and further including: r) means for generating an armature brake current signal having a frequency which varies in accordance with the level of brake current through said armature, s) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, t) means for comparing said armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, u) means responsive to the generation of said brake current-limit control signal for preventing said second pulse generator means from gating on said second silicon-controlled rectifier when said control signal is present and for allowing said second pulse generator means to gate on said second silicon-controlled rectifier when said control signal is not present.

119. A control system as set forth in claim 118 and further including: v) means for changing the frequency of said brake current reference signal as a function of the count obtained by said second counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

120. A control system as set forth in claim 118 and further including: v) means responsive to said base-speed control signal for changing the frequency of said brake current reference signal to Increase the maximum allowable level of brake current when the motor speed is below said base speed beyond the maximum allowable level of brake current when the motor speed is above said base speed.

121. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) means for generating a deceleration signal when the count obtained by said second counter means is less than a first predetermined number, l) means for generating an acceleration signal when the count obtained by said second counter means is greater than a second predetermined number, said second predetermined number being higher than said first predetermined number, m) means responsive to the generation of said acceleration signal for enabling said field-control signal generating means to respond to changes in the count obtained by said first counter means only when said acceleration signal is present, n) means responsive to the generation of said deceleration signal for preventing said first pusle generating means from gating on said first silicon-controlled rectifier, o) means responsive to the generation of said deceleration signal for connecting said armature for flow of brake current therethrough.

122. A control system as set forth in claim 99 and further including: i) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actualspeed signal, k) means for generating a deceleration signal when the count obtained by said second counter means is less than a first predetermined number, l) means for generating an acceleration signal when the count obtained by said second counter means is greater than a second predetermined number, said second predetermined number being higher than said first predetermined number, m) means responsive to the generation of said acceleration signal for operating said first pulse generator means to Increase the ratio of on-time to off-time of said first silicon-controlled rectifier beyondthat normally called for by said armature-control signal, n) means responsive to the generation of said deceleration signal for preventing said first pulse generating means from gating on said first silicon-controlled rectifier, o) means responsive to the generation of said deceleration signal for connecting said armature for flow of brake current therethrough.

123. A control system as set forth in claim

122 and further including: p) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, q) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, r) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, s) means responsive to the presence of said power current-limit control signal for preventing said first pulse generating means from gating on said first silicon-controlled rectifier, t) means responsive to the presence of said power current-limit control signal for operating said second pulse generator means to increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

124. A control system as set forth in claim

123 and further including: u) means for changing the frequency of said power current reference signal as a function of the count obtained by said first mentioned counter means (e) to decrease the maximum allowable level of power current as said count increases.

125. A control system as set forth in claim 122 and further including: p) means for generating an armature brake current signal having a frequency which varies in accordance with the level of brake current through said armature, q) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, r) means for comparing said armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, s) means responsive to the generation of said brake current-limit control signal for preventing said second pulse generator means from gating on said second silicon-controlled rectifier when said control signal is present and for allowing said second pulse generator means to gate on said second silicon-controlled rectifier when said control signal is not present.

126. A control system as set forth in claim 125 and further including: t) means for changing the frequency of said brake current reference signal as a function of the count obtained by said second counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

127. A control system as set forth in claim 122 and further including: p) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, q) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, r) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, s ) means responsive to the presence of said power current-limit control signal for preventing said f irst pulse generating means from gating on said first silicon-controlled rectifier, t) means responsive to the presence of said power current-limit control signal for operating said second pulse generator means to Increase the ratio of on-time to off-time of said second silicon-controlled rectifier, u) means for generating an armature brake current signal having a frequency which varies in accordance with the level of brake current through said armature, v) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, w) means for comparing said armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, x) means responsive to the generation of said brake current-limit control signal for preventing said second pulse generator means from gating on said second silicon-controlled rectifier when said control signal is present and for allowing said second pulse generator means to gate on said second silicon-controlled rectifier when said control signal is not present.

128. A control system as set forth in claim 127 and further including: y) means for changing the frequency of said power current reference signal as a function of the count obtained by said first mentioned counter means (e) to decrease the maximum allowable level of power current as said count increases.

129. A control system as set forth in claim 127 and further including: y) means for changing the frequency of said brake current reference signal as a function of the count obtained by said second counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

130. A control system as set forth in claim 127 and further including: y) means for changing the frequency of said power current reference signal as a function of the count obtained by said first mentioned counter means(e) to decrease the maximum allowable level of power current as said count increases, z) means for changing the frequency of said brake current reference signal as a function of the count obtained by said second counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

131. A control system for a direct-current motor having an armature and a separately excited field, said armature being connected to a source of direct current through a first silicon-controlled rectifier and said field being connected to said source through a second silicon-controlled rectifier, the system comprising: a) an adjustable operator-controlled speed-demand member, b) a voltage-controlled oscillator, c) voltage applying means for applying a voltage to the input of said voltage-controlled oscillator which is proportional to the setting of said speed-demand member, d) a monostable multivibrator having a trigger input and having external capacitor and resistor means for governing the duration of the monostable pulse, e) trigger means for applying trigger pulses to the trigger input of said monostable at a rate proportional to the oscillation rate of said voltage-controlled oscillator, f) means for gating said first silicon-controlled rectifier Into conduction in response to the beginning of each pulse of said monostable, g) means for commutating said first silicon-controlled rectifier in response to the termination of each pulse of said monostable, h) means for controlling the ratio of on-time to off-time of said second silicon-controlled rectifier as an inverse function of the setting of said speed-demand member.

132. A control system as set forth in claim 131 wherein said monostable multivibrator has a retrigger Input and wherein said trigger means is further operable to apply said trigger pulses to said retrigger Input, said control system further including: i) means responsive to the actual speed of said motor and operable when such speed is above a predetermined speed less than maximum speed for maintaining the resistance of the external resistor means of said monostable at a value such that the duration of the monostable pulse is longer than the period between successive trigger pulses applied to said monostable when the demanded speed is greater than said predetermined speed.

133. The system as set forth in claim 132 and further including: j) means for Inhibiting the application of trigger pulses to the retrigger input of said monostable when the demanded speed is less than the actual speed of said motor.

134. A control system as set forth in claim 132 and further including: j) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, k) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, l) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, m) means responsive to said power current-limit control signal for inhibiting the application of said trigger pulses to said monostable during the presence of said power current-limit control signal.

135. A control system as set forth in claim

134 and further including: n) means for changing the frequency of said power current reference signal as a function of the actual speed of said motor to decrease the maximum allowable level of power current as said actual motor speed increases and vice versa.

136 . A cont rol system as set f orth in claim 134 and further including: n ) means respons ive to rotat ion of said armature for generat ing an actual-speed signal having a f requency proportional t o the actual speed of said motor, o ) means for generating a speed-demand signal having a f requency inversely proportional to the s etting of said speed-demand member, p ) counter means for obtaining a count of the number of cycles of said actual-speed signal per cycle of said speed-demand signal, q) means for changing the f requency of said power current reference signal as a function of the count obtained by said counter means to decrease the maximum allowable level of power current as said count increases and vice versa.

137 . A cont rol system as set forth in claim 131 and further including: i) positive jerk means including a capacitor and a resistor connected to the input of said voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

138. The system as set forth in claim 131 and further including: i) means for continuously monitoring the level of power current flowing through said armature and first silicon-controlled rectifier and for generating a power current-limit control signal when such power current exceeds a predetermined level, j) means responsive to the presence of said power current-limit control signal for inhibiting the application of trigger pulses to said monostable for as long as said signal is present.

139. The system as set forth in claim 138 and further including: k) means including a capacitor and a resistor connected to the input of said voltage-controlled oscillator for limiting the rate of rise of voltage at said input to the rate of charging of said capacitor through said resistor.

140. A control system as set forth In claim 131 and further including: i) means for generating an armature power current signal having a frequency which varies In accordance with the level of power current through said armature, j) means for generating a power current reference signal having a frequency corresponding to a maximum allowable level of power current through said armature, k) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, l) means responsive to said power current-limit control signal for inhibiting the application of said trigger pulses to said monostable during the presence of said power current-limit control signal.

141. The system as set forth in claim 140 and further including: m) means responsive to the presence of said power current-limit control signal for decreasing the resistance of the external resistor means of said monostable to decrease the duration of the existing pulse thereof.

142. The system as set forth in claim 140 and further including: n) positive jerk means including a capacitor and a resistor connected to the input of said voltage-controlled oscillator for limiting the rate of rise of voltage at said Input to the rate of charging of said capacitor through said resistor.

143. A control system as set forth in claim 140 and further including: m) means for changing the frequency of said power current reference signal as a function of the actual speed of said motor to decrease the maximum allowable level of power current as said actual motor speed increases and vice versa.

144. A control system as set forth In claim 140 and further including: m) means responsive to rotation of said armature for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, n) means for generating a speed-demand signal having a frequency Inversely proportional to the setting of said speed-demand member, o) counter means for obtaining a count of the number of cycles of said actual-speed signal per cycle of said speed-demand signal, p) means for changing the frequency of said power current reference signal as a function of the count obtained by said counter means to decrease the maximum allowable level of power current as said count increases and vice versa.

145 . The system as set f orth in claim 131 and further including: i) means responsive to the rotation of said armature for generating an actual-speed signal having a f requency proportional to the speed of said motor, j ) means for generat ing a speed-demand signal having a frequency proportional to the setting of said speed-demand member, k) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal, l) means for generating an acceleration signal when the count obtained by said counter means exceeds a predetermined number, m) means responsive to the generation of said acceleration signal for performing at least one of the following functions:

(1) boosting the voltage at the input of said voltage-controlled oscillator beyond that applied thereto by said voltage applying means (c),

(2) Increasing the resistance of the external resistor means of said monostable to increase the duration of the pulses thereof.

146. The system as set forth in claim 131 and further including: i) means responsive to the rotation of said armature for generating an actual-speed signal having a frequency proportional to the speed of said motor, j) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, k) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal, l) means for generating an acceleration signal when the count obtained by said counter means exceeds a predetermined number, m) means responsive to the generation of said acceleration signal for

(1) boosting the voltage at the input of said voltage-controlled oscillator beyond that applied thereto by said voltage applying means (c), and for

147. The system as set forth in claim 131 and further including: i) means responsive to the rotation of said armature for generating an actual-speed signal having a frequency proportional to the speed of said motor, j) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, k) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal, l) means for generating a deceleration signal when the count obtained by said counter means is less than a predetermined number, m) means responsive to the generation of said deceleration signal for Inhibiting application of trigger pulses to said monostable, n) means responsive to the generation of said deceleration signal for connecting said armature for flow of brake current therethrough.

148. The system as set forth in claim 131 and further including: i) means responsive to the rotation of said armature for generating an actual-speed signal having a frequency proportional to the speed of said motor, j) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, k) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal,

(l) means for generating an acceleration signal when the count obtained by said counter means exceeds a first predetermined number, m) means responsive to the generation of said acceleration signal for performing at least one of the following functions:

1) boosting the voltage at the input of said voltage-controlled oscillator beyond that applied thereto by said voltage applying means (c), (2) increasing the resistance of the external resistor means of said monostable to Increase the duration of the pulses thereof, n) means for generating a deceleration signal when the count obtained by said counter means is less than a second predetermined number, said second predetermined number being less than said first predetermined number, o) means responsive to the generation of said deceleration signal for inhibiting application of trigger pulses to said monostable, p) means responsive to the generation of said deceleration signal for connecting said armature for flow of brake current therethrough.

149. The system as set forth in claim 131 and further including: i) means for generating a speed-demand signal having a magnitude proportional to the setting of said speed-demand member, j) means for generating an actual-speed signal having a magnitude proportional to the actual speed of said motor, k) means for comparing said speed-demand and actual-speed signals and for generating a first acceleration signal when the demanded speed exceeds the actual speed by a first predetermined degree and for generating a second acceleration signal when the demanded speed exceeds the actual speed by a second and greater predetermined degree, l) means responsive to the generation of said first acceleration signal and operable during the existence thereof for increasing the resistance of the external resistor means of said monostable to increase the duration of the monostable pulses, m) means responsive to the generation of said second acceleration signal and operable during the existence thereof for further increasing the resistance of said monostable to further Increase the duration of the monostable pulses.

150. The system as set forth in claim 131 and further including: i) means for generating a speed-demand signal having a magnitude proportional to the setting of said speed-demand member, j) means for generating an actual-speed signal having a magnitude proportional to the actual speed of said motor, k) means for comparing said speed-demand and actual-speed signals and for generating a first acceleration signal when the demanded speed exceeds the actual speed by a first predetermined degree and for generating a second acceleration signal when the demanded speed exceeds the actual speed by a second and greater predetermined degree,

1) means responsive to the generation of said first acceleration signal and operable during the existence thereof for boosting the voltage at the input of said voltage-controlled oscillator beyond that applied thereto by said voltage applying means (c), m) means responsive to the generation of said second acceleration signal and operable during the existence thereof for further boosting the voltage at the Input of said voltage-controlled oscillator.

151. The system as set forth in claim 131 and further including: i) means for generating a speed-demand signal having a magnitude proportional to the setting of said speed-demand member, j) means for generating an actual-speed signal hving a magnitude proportional to the actual speed of said motor, k) means for comparing said speed-demand and actual-speed signals and for generating a first acceleration signal when the demanded speed exceeds the actual speed by a first predetermined degree and for generating a second acceleration signal when the demanded speed exceeds the actual speed by a second and greater predetermined degree, l) means responsive to the generation of said first acceleration signal and operable during the existence thereof for performing at least one of the following functions: (1) boosting the voltage at the Input of said voltage-controlled oscillator beyond that applied thereto by said voltage applying means (c), (2) increasing the resistance of the external resistor means of said monostable to Increase the duration of the pulses thereof, m) means responsive to the generation of said second acceleration signal and operable during the existence thereof for performing the same functions performed in the previous step but to a greater degree, n) means for continuously monitoring the level of power current flowing through said armature and for generating a power current-limit control signal when such power current exceeds a maximum allowable power current level, o) means responsive to the presence of said power current-limit control signal for Inhibiting the application of trigger pulses to said monostable for as long as said control signal is present.

152. The system as set forth in claim 151 and further including: p) means responsive to the presence of said second acceleration signal for increasing said maximum allowable power current level.

153 . A control system for a direct-current motor having an armature and a separately excited f ield, said armature being connected to a source of direct current through a f irst silicon-controlled rectif ier and said f ield being conne cted to said source through a second silicon-controlled rectif ier and said f ield being connected to said source through a second s ilicon-controlled rectifier, the system comprising: a) an adjustable operator-controlled speed-demand member, b ) means for controlling the conduction of said first silicon-controlled re ctif ier as a function of the setting of said speed-demand member, c ) means responsive to the rotation of said armature for generating an actual-speed signal having a f requency proportional to the speed of said motor, d ) means for generat ing a speed-demand signal having a f requency inversely proportional to the s etting of said speed-demand member, e ) counter means for continuously obtaining a count of the number of cycles of said actual-speed signal per cycle of said speed-demand signal, f ) a voltage-controlled oscillator, g) voltage generating and applying means for generating a voltage inversely proportional to the count obtained by said counter means and for applying such voltage to the input of said voltage-controlled o scillator, h ) a monostable multivibrator having a trigger input and external capacitor and resistor means f or determining the duration of said monostable pulse, i) means for gating said second silicon-controlle d rectif ier into conduction in response to the beginning of each pulse of said monostable, j ) means for commutating said second silicon-controlled re ctifier in response to the termination of each pulse of said monostable , k) means for operating said monostable to vary the ratio of on-time to off -time of said second silicon-controlled rectif ier as a function of the f requency of oscillation of said voltage-controlled oscillator.

154. A control system as set forth in claim 153 and further including: l) means responsive to the presence of a predetermined high count obtained by said counter means for reducing the amount of voltage generated by said voltage generating and applying means (g) which is applied to the input of said voltage-controlled o scillator.

155 . A control system as set foeth in claim 153 and further including: l) means responsive to the presence of a predetermined high count obtained by said counter means f or reducing the external resistance means of said monostable to reduce the pulse length thereof .

156. A control system as set forth in claim 153 and further including: l) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, m) means for generating a power current reference signal corresponding to a maximum allowable level of power current through said armature, n) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, o) operating means responsive to the presence of said power current-limit control signal for operating said monostable to Increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

157. A control system as set forth in claim 156 wherein said operating means includes means for increasing the voltage applied to said voltage-controlled oscillator.

158. A control system as set forth in claim

156 wherein said operating means includes means for Increasing the external resistance means of said monostable to increase the pulse length thereof.

159. A control system as set forth in claim 156 and further including: p) means for changing the frequency of said power current reference signal as a function of the count obtained by said counter means to decrease the maximum allowable level of power current as said count increases.

160. A control system as set forth in claim 153 and further including: l) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, m) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, n) means responsive to the count obtained by said second counter means for enabling said voltage generating and applying means (g) to respond to changes in the count obtained by said first counter means only when the count obtained by said second counter means exceeds a predetermined number.

161. A control system as set forth in claim 153 and further including: l) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, m) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, n) means for generating an acceleration signal when the count obtained by said .second counter means is greater than a predetermined number, o) means responsive to the presence of said acceleration signal for decreasing the external resistance means of said monostable to shorten the pulse length thereof.

162. A control system as set forth in claim 153 wherein said voltage generating and applying means (g) comprises means for applying trigger pulses to the trigger input of said monostable at a rate proportional to the frequency of the output of said voltage-controlled oscillator.

163. A control system as set forth in claim l62 and further including: l) means responsive to the presence of a predetermined high count obtained by said counter means for reducing the external resistance means of said monostable to reduce the pulse length thereof.

164. A control system as set forth in claim 162 and further including: l) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, m) means for generating a power current reference signal corresponding to a maximum allowable level of power current through said armature, n) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, o) means responsive to the presence of said power current-limit control signal for performing at least one of the following functions:

(1) Increasing the voltage applied to said voltage-controlled oscillator,

(2) increasing the external resistance means of said monostable to Increase the pulse length thereof.

165. A control system as set forth in claim l62 and further including: l ) means for generating a second speed-demand signal having a f re quency proportional to the setting of said speed-demand member, m) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, n) means for generating an acceleration signal when the count obtained by said second counter means is greater than a predetermined number, o) means responsive to the presence of said acceleration signal for decreasing the external resistance means of said monostable to decrease the pulse length thereof.

166. A control system as set forth in claim l62 and further including: l) means for generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, m) a second counter means for continuously obtaining a count of the number of cycles of said second speed-demand signal per cycle of said actual- speed signal, n) means for generating a first acceleration signal when the count obtained by said second counter means is greater than a first predetermined number, o) means for generating a second acceleration signal when the count obtained by said second counter means is greater than a second predetermined number, said second predetermined number being higher than said first predetermined number, p) means responsive to the presence of said first acceleration signal for decreasing the external resistance means of said monostable to decrease the pulse length thereof, q) means responsive to the presence of said second acceleration signal for further decreasing the external resistance means of said monostable to further decrease the pulse iength thereof.

167. A control system as set forth in claim 166 and further including: r) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, s) means for generating a power current reference signal corresponding to a maximum allowable level of power current through said armature, t) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current , u) means responsive to the presence of said power current-limit control signal for Increasing the external resistance means of said monostable to Increase the pulse length thereof, and for boosting the voltage applied to said voltage-controlled oscillator.

168 . A control system as set forth in claim 153 where in said voltage generating and applying means (g) comprises : g1 ) means for generating a f ield-current s ignal having a frequency proportional to the level of the average current flowing through said field, g2 ) means for continuously comparing the f requencies of said f ield-current signal and the oscillation of said voltage-controlled os cillator, g3 ) means for generating trigger pulses at a predetermined rate , g4 ) means for applying said trigger pulses to said trigger input of said monostable when the f requency of said field-current signal is less than that of said voltage-controlled oscillator and for prevent ing such application of trigger pulses when the f re quency of said field-current signal Is greater than that of said voltage-controlled oscillator .

169 . A control system as set forth in claim 168 and further including: l) means responsive to the presence of a predetermined high count obtained by said counter means for reducing the amount of voltage generated by said voltage generating and applying means (g) which Is applied to the input of said voltage-controlled oscillator .

170. A control system as set forth in claim 168 and further including: l) means for generating an armature power current signal having a frequency which varies in accordance with the level of power current through said armature, m) means for generating a power current reference signal corresponding to a maximum allowable level of power current through said armature, n) means for comparing said power current signal and said power current reference signal and for generating a power current-limit control signal when and for as long as the level of power current through said armature exceeds the maximum allowable level of power current, o) operating means responsive to the presence of said power current limit control signal for operating said monostable to Increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

171. A control system as set forth in claim 170 wherein said operating means (o) includes means for increasing the voltage applied to said voltage-controlled oscillator.

172. A control system as set forth in claim

170 wherein said operating means (o) includes means for increasing the external resistance means of said monostable to increase the pulse length thereof.

173. A control system for a direct-current motor having an armature and a separatuely excited field, and a silicon-controlled rectifier connecting said field to a source of direct current, the system comprising: a) an adjustable operator-controlled speed-demand member, b) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, c) means for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, d) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal, e) means operable to connect said armature to said source of direct current for flow of power current to said armature from said source when the count obtained by said counter means is above a predetermined number, f) means operable to connect said armature for flow of brake current therethrough when the count obtained by said counter is less than said predetermined number, g) a voltage-controlled oscillator, h) a monostable multivibrator having a trigger input and external capacitor and resistor means for determining the duration of the pulse when said monostable is triggered, i) means for gating said silicon-controlled rectifier Into conduction in response to the beginning of each pulse of said monostable, j ) means for commutating said silicon-controlled re ctif ier In response to the termination of each pulse of said monostable , k) means for applying a predetermined voltage to the Input of said voltage-controlled oscillator, l) means for generating trigger pulses at a rate equal to the frequency of oscillation of said voltage-controlled oscillator and for applying said trigger pulses to the trigger input of said monostable, m) means for generating an armature brake current signal having a frequency which varies as a function of the magnitude of brake current flowing through said armature, n) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, o) means for comparing said armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, p) means for inhibiting said trigger pulse generating means from operating when said brake current-limit control signal is present and for allowing said trigger pulse generating means to operate when said control signal is not present.

174. A control system as set forth in claim 173 and further including: o) negative jerk means including a resistor and a capacitor connected to the input of said voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

175. A control system as set forth in claim 173 and further including: o) means for changing the frequency of said brake current reference signal as a function of the count obtained by said counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

176. A control system as set forth in claim

175 and further including: o) negative jerk means including a resistor and a capacitor connected to the input of said voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

177. A control system for a direct-current motor having an armature and a separately excited f ield, and a silicon-controlled rectifier connecting said field to a source of direct current, the system comprising: a) an adjustable operator-controlled speed-demand member, b ) means for generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, c ) means for generating an actual-speed signal having a frequency proportional to the actual speed of said motor, d) counter means for continuously obtaining a count of the number of cycles of said speed-demand signal per cycle of said actual-speed signal, e) means operable to connect said armature to said source of direct current for flow of power current to said armature from said source when the count obtained by said counter means is above a predetermined number, f) means operable to connect said armature for flow of brake current therethrough when the count obtained by said counter is less than said predetermined number, g) a voltage-controlled oscillator, h) a monostable multivibrator having a trigger input and external capacitor and resistor means for determining the duration of the pulse when said monostable is triggered, i) means for getting said silicon-controlled rectifier Into conduction in response to the beginning of each pulse of said monostable, j) means for commutating said silicon-controlled rectifier in response to the termination of each pulse of said monostable, k) means for applying a predetermined voltage to the Input of said voltage-controlled oscillator, l) trigger pulse generating means for generating trigger pulses at a predetermined rate and for applying them to the trigger input of said monostable, m) means for generating a field-current signal having a frequency which varies with the magnitude of field current, n) means for comparing the frequencies of said field-current signal and said voltage-controlled oscillator, o) means for inhibiting the operation of said trigger pulse generating means when the frequency of said field-current signal is greater than that of said voltage-controlled oscillator and for allowing said trigger pulse generating means to operate when the frequency of said field-current signal is less than that of said voltage-controlled oscillator, p) means for generating an armature brake current signal having a frequency which varies as a function of the magnitude of brake current flowing through said armature, q) means for generating a brake current reference signal having a frequency corresponding to a maximum allowable level of brake current through said armature, r) means for comparing sald"armature brake current signal and said brake current reference signal and for generating a brake current-limit control signal when and for as long as the level of brake current through said armature exceeds the maximum allowable level of brake current, s) means for Inhibiting said trigger pulse generating means from operating when said brake current-limit control signal is present and for allowing said trigger pulse generating means to operate when said control signal is not present.

178. A control system as set forth in claim 177 and further including: o) negative jerk means including a resistor and a capacitor connected to the Input of said voltagecontrolled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

179. A control system as set forth in claim 177 and further including: o) means for changing the frequency of said brake current reference signal as a function of the count obtained by said counter means to increase the maximum allowable level of brake current as said count decreases and vice versa.

180. A control system as set forth in claim

179 and further including: o) negative jerk means including a resistor and a capacitor connected to the Input of said voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

181. A control system for a direct-current motor having an armature and a separately excited f ield, said armature being connectable to a source of direct current through a f irst silicon-controlled rectif ier for flow of power current from said source to said armature , said field being connectable to said source through a second silicon-controlled rectif ier, said system comprising: a) an adjustable operator-controlled speed-demand member, b ) controlling means for controlling the conduction of said first silicon-controlled rectifier as a function of the setting of said speed-demand member, throughout its range, c ) means responsive to the rotation of said armature for generating first and second actual-speed signals each having a frequency proportional to the actual speed of said motor, d) means for generating a f irst speed-demand signal having a frequency proportional to the setting of said speed-demand member throughout its range , e ) means for generating a second speed-demand s ignal having a frequency inversely proportional to the setting of said speed-demand member throughout Its range, f) first counter means for continuously obtaining a count of the number of cycles of said first speed-demand signal per cycle of said first actual-speed signal, g) second counter means for continuously obtaining a count of the number of cycles of said second actual-speed signal per cycle of said second speed-demand signal, h) a voltage-controlled oscillator, i) voltage generating and applying means for generating a voltage inversely proportional to the count obtained by said second counter means and for applying such voltage to the Input of said voltage-controlled oscillator, j) a monostable multivibrator having a trigger input and external capacitor and resistor means for determining the duration of the monostable pulse, k) means for gating said second silicon-controlled rectif ier into conduction in response to the beginning of each monostable pulse, l) means for commutating said second silicon-controlled rectifier into conduction in response to the termination of each monostable pulse, m) operating means for operating said monostable to vary the ratio of on-time to off-time of said second silicon-controlled rectifier as a function of the frequency of oscillation of said voltage controlled oscillator, n) means responsive to the count obtained by aid first counter means for enabling said first silicon-controlled rectifier to be turned on when the count of said first counter means is above a predetermined number, o) inhibiting and connecting means responsive to the count obtained by said first counter means for inhibiting said first silicon-controlled rectifier from being turned on, and for connecting said armature for flow of brake current therethrough when the count of said first counter means is below said predetermined number, p) means responsive to the level of brake current through said armature for generating a brake current limit control signal when and for as long as said brake current exceeds a maximum permissible brake current reference, q) means for enabling said monostable to operate when said brake current-limit control signal is not present and for Inhibiting such operation when said control signal is present.

182. A control system as set forth in claim 181 wherein said controlling means (b) includes means for varying the ratio of on-time to off-time of said first silicon-controlled rectifier as a function of the setting of said speed-demand member when the actual speed of said motor is below a predetermined speed and for maintaining said silicon-controlled rectifier on continuously when the actual speed of said motor is above said predetermined speed and the count obtained by said first counter means is greater than said predetermined number.

183. A control system as set forth in claim 181 wherein said Inhibiting and connecting means (o) Includes means for connecting said armature to said source for flow of brake current from said armature to said source when the speed of said motor is above a predetermined speed and for shorting said armature for flow of brake current therethrough when the speed of said motor is below said predetermined speed.

184. A control system as set forth in claim 183 wherein said controlling means (b ) includes means f or varying the ratio of on-t ime to off t ime of said f irst silicon-controlled rectif ier as a function of the setting of said speed-demand member when the actual speed of said motor Is below said predetermined speed and for maintaining said silicon-controlled rectifier on continuously when the actual speed of said motor is above said predetermined speed and the count obtained by said first counter means is greater than said predetermined number.

185 . A control system as set forth in claim 181 and further including: r) means responsive to the count obtained by said first counter means for enabling said voltage generating and applying means (i) t o respond to changes in the count of said second counter means when the count of said f irst counter means is above a second predetermined number and for inhibiting such response when the count of said first counter means is below said second predetermined number, said seeond predetermined number being greater than said first-mentioned predetermined number.

186. A control system as set forth in claim 185 and further including: s) means for generating an acceleration signal when the count of said first counter, means is above said second predetermined number, t) means responsive to the presence of said acceleration signal for increasing conduction of said first silicon-controlled rectifier beyond that called for by controlling means (b) and decreasing the conduction of said second silicon-controlled rectifier below that called for by said operating means (m).

187. A control system as set forth in claim 181 and further including: r) means responsive to the level of power current through said armature for generating a power current-limit control signal when and for as long as said power current exceeds a maximum permissible power current reference, s) means for enabling said monostable to operate when said power current-limit control signal is not present and for Inhibiting such operation when said control signal is present.

188. A control system as set forth in claim 187 and further including: t) means for inhibiting conduction of said first silicon-controlled rectifier when said power current-limit control signal is present.

189 . A control system for a direct-current motor having an armature and a separately excited f ield, said armature being connectable to a source of direct current through a f irst silicon-controlled rectifier for flow of power current from said source to said armature , said f ield being connectable to said source through a second silicon-controlled rectifier, said system comprising: a) an adjustable operator-controlled speed-demand member, b) a f irst voltage-controlled oscillator, c) means for generating a voltage proportional to the setting of said speed-demand member and for applying such voltage to the input of said voltage-controlled oscillator, d) a f irst monostable multivibrator having a trigger input and external capacitor and resistance means for determining the length of the pulse of said monostable , e ) means responsive to the termination of eachpulse of said first monostable for commutating said f irst silicon-controlled rectifier, g) means responsive to the rotation of said armature for generating f irst and second actual-speed signals each having a frequency proportional to the actual speed of said motor, h) means for generating a first speed-demand signal having a frequency proportional to the setting of said speed-demand member throughout its range , i) means for generating a second speed-demand s ignal having a frequency inversely proportional to the setting of said speed-demand member throughout its range, j) first counter means for continuously obtaining a count of the number of cycles of said first speed-demand signal per cycle of said first actual-speed signal, k) second counter means for continuously obtaining a count of the number of cycles of said second actual-speed signal per cycle of said second speed-demand signal, l) a second voltage-controlled oscillator, m) voltage generating and applying means for generating a voltage Inversely proportional to the count obtained by said second counter means and for applying such voltage to the input of said second voltage-controlled oscillator, n) a second monostable multivibrator having a trigger input and external capacitor and resistor means for determining the duration of the monostable pulse, o) means for gating said second silicon-controlled rectifier into conduction in response to the beginning of each pulse of said second monostable, p) means for commutating said second silicon-controlled rectifier into conduction in response to the termination of each pulse of said second monostable, q) operating means for operating said second monostable to vary the ratio of on-time to off-time of said second silicon-controlled rectifier as a function of the frequency of oscillation of said second voltage-controlled oscillator, r) means responsive to the count obtained by said first counter means for enabling said first monostable to pulse when the count of said first counter means is above a predetermined number, s) inhibiting and connecting means responsive to the count obtained by said first counter means for inhibiting said first monostable from pulsing and for connecting said armature for flow of brake current therethrough when the count of said first counter means is below said predetermined number, t) means responsive to the level of brake current through said armature for generating a brake current-limit control signal when and for as long as said brake current exceeds a maximum permissible brake current reference, u) means for enabling said second monostable to pulse when said brake current-limit control signal is not present and for inhibiting such pulsing when said control signal is present.

190. A control system as set forth in claim 189 wherein said inhibiting and connecting means (s) includes means for connecting said armature to said source for flow of brake current from said armature to said source when the speed of said motor is above a predetermined speed and for shorting said armature for flow of brake current therethrough when the speed of said motor is below said predetermined speed.

191. A control system as set forth in claim 189 and further including: v) means for generating an acceleration signal when the count obtained by said first counter means is above a second predetermined number, said second predetermined number being greater than said first-mentioned predetermined number, w) means responsive to the presence of said acceleration signal for performing at least one of the following functions:

(1) increasing the frequency of trigger pulses to said first monostable,

(2) Increasing the external resistance of said f irst monostable, (3) decreasing the external resistance of said second monostable.

192. A control system as set forth in claim 189 and further including: v) means responsive to the count obtained by said first counter means for enabling said voltage generating and applying means (m) to respond to the changes in the count of said second counter means when the count of said first counter means is above a second predetermined number and for Inhibiting such response when the count of said first counter means is below said second predetermined number, said second predetermined number being greater than said first-mentioned predetermined number.

193. A control system as set forth in claim 192 and further including: w) means for generating an acceleration signal when the count obtained by said first counter is above said second predetermined number, x) means responsive to the presence of said acceleration signal for performing at least one of the following functions:

(1) increasing the frequency of trigger pulses to said first monostable, (2) increasing the external resistance of said first monostable, (3) decreasing the external resistance of said second monostable.

194. A control system as set forth in claim 189 and further including: v) means responsive to the level of power current through said armature for generating a power current-limit control signal when and for as long as said power current exceeds a maximum permissible power current reference, w) means responsive to the presence of said power current-limit control signal for inhibiting said first monostable from pulsing, x) means responsive to the presence of said power current-limit control signal for operating said second monostable to increase the ratio of on-time to off-time of said second silicon-controlled rectifier.

195. A control system as set forth in claim 194 and further including: y) positive jerk means Including a capacitor and resistor connected to the input of said first voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor, z) negative jerk means including a capacitor and resistor connected to the input of said second voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

196. A control system as set forth in claim 194 and further including: y) means for varying the level of said maximum permissible power current reference as a function of the count obtained by said second counter means such that said level decreases as said count increases.

197. A control system as set forth in claim

194 and further including: y) means for varying the level of said maximum permissible brake current reference as a function of the count obtained by said first counter means such that said level decreases as said count increases.

198. A control system as set forth in claim 197 and further including: z) means for varying the level of said maximum permissible power current reference as a function of the count obtained by said second counter means such that said level decreases as said count Increases.

199. A control system as set forth in claim 198 and further including: aa) positive jerk means including a capacitor and resistor connected to the input of said first voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor, bb) negative jerk means including a capacitor and resistor connected to the input of said second voltage-controlled oscillator for limiting the rise of voltage at said input to the rate of charging of said capacitor through said resistor.

200. A control system as set forth in claim 189 wherein said operating means (q) comprises means for applying trigger pulses to the trigger input of said second monostable at a rate proportional to the frequency of oscillation of said second voltage-controlled oscillator.

201. A control system as set forth in claim 189 wherein said operating means (q) comprises : q1) means for generating a field-current s ignal having a f requency proportional to the level of current flowing through said field, q2) means for continuously comparing the f requencies of said field-current signal and the oscillation of said second voltage-controlled oscillator, q3) means for generating trigger pulses at a predetermined rate, q4) means for applying said trigger pulses to the trigger input of said second monostable when the f requency of said f ield-current signal is less than that of said second voltage-controlled oscillator and f or inhibiting such application when the f requency of said field-current signal is greater than that of said second voltage-controlled oscillator .

202. The method of operating a direct-current motor wherein one side of the armature is connectable through a main silicon-controlled rectifier to one terminal of a direct-current source and is connectable through a braking silicon-controlled rectifier and an inductance to the other terminal of said source, wherein the other side of said armature is connected to said other terminal of said source, and wherein a commutating capacitor has one side thereof connected to said one said of said armature, the method comprising: a) connecting said capacitor across said main silicon-controlled rectifier and disconnecting such connection when the capacitor has charged, b) connecting said capacitor across said braking silicon-controlled rectifier and disconnecting such connection after the capacitor has discharged and has charged in the reverse direction, c) gating said main silicon-controlled rectifier into conduction, d) commutating said main silicon-controlled rectifier by connecting said reversely charged capacitor across said main silicon-controlled rectifier and disconnecting such connection when the reversely charged capacitor has discharged and recharged, e) repeating steps (b), (c) and (d) for as many times as desired and ending with a step (d), f) then operating said motor as a generator, g) gating said braking silicon-controlled rectifier into conduction, h) commutating said braking silicon-controlled rectifier at a desired time by first connecting said capacitor across said main silicon-controlled rectifier and disconnecting said connection after said capacitor has charged and then connecting said capacitor across said braking silicon-controlled rectifier and disconnecting such connection after the capacitor has discharged and has charged in a reverse direction.

203. The method as set forth in claim 202 and further including repeating steps (c) and (d) after step (h) and then repeating steps (b), (c) and (d) for as many times as desired.

204. The method as set forth in claim 202 and further including the following steps carried out between steps (f) and (g): connecting said one side of said armature to said one terminal of said source when the counter emf of said motor operating as a generator is greater than that of said source, disconnecting such connection at a time when the counter emf of said motor acting as a generator is substantially the same as that of said source.

205. The method as set forth in claim 204 and further including repeating steps (c) and (d) after step (h) and then repeating steps (b), (c) and (d) for as many times as desired.

206. In a method of controlling the operation of a direct-current motor having an armature through which current will flow and in which the direction of flow of said current through said armature is dependent upon whether said motor is being powered from a source of direct current or whether said motor is being driven as a generator, the steps comprising: a) continuously monitoring the level of current flowing through said armature, b) generating a current level signal having a predetermined frequency when no current flows through said armature, c) increasing the frequency of said current level signal from said predetermined frequency when current flows in one direction through said armature, with the amount of such increase from said predetermined frequency being proportional to the level of such current flow In said one direction, d) decreasing the frequency of said current level signal from said predetermined frequency when current flows In the opposite direction through said armature, with the amount of such decrease from said predetermined frequency being proportional to the level of such current flow in said opposite direction.

207. In a method as set forth in claim 206 the further steps of: d) generating a reference signal having a frequency greater than said predetermined frequency, f) continuously comparing the frequencies of said current level signal and said reference signal, g) effecting a control function on said motor in accordance with whether the frequency of said current level signal is greater or lesser than the frequency of said reference signal.

208. In a method as set forth in claim 206, the further steps of: d) generating a reference signal having a frequency lesser than said predetermined frequency, f) continuously comparing the frequencies of said current level signal and said reference signal, g) effecting a control function on said motor In accordance with whether the frequency of said current level signal is greater or lesser than the frequency of said reference signal.

209. In a method as set forth in claim 206, the further steps of: e) generating a first reference signal having a frequency greater than said predetermined frequency, f) generating a second reference signal having a frequency greater than said predetermined frequency but less than that of said first reference signal, h) continuously comparing the frequency of said current level signal with the frequencies of said reference signals, i) effecting a first control function on said motor In accordance with whether the frequency of said current level signal is above or below the frequency of said first reference signal, j) effecting a second control function on said motor in accordance with whether the frequency of said current level signal is above or below the frequency of said second reference signal.

210. In a method as set forth in claim 206, the further steps of: e) generating a f irst reference signal having a fre quency greater than said predetermined f re quency, f) generating a second reference signal having a frequency lesser than said predetermined frequency, h) continuously comparing the frequency of said current level signal with the frequencies of said reference signals, i) effecting a first control function on said motor In accordance with whether the frequency of said current level signal is above or below the frequency of said first reference signal, j) effecting a second control function on said motor In accordance with whether the frequency of said current level signal is above or below the frequency of said second reference signal.

211. In a method as set forth in claim 206, the further steps of: e) generating a first reference signal having a frequency greater than said predetermined frequency, f) generating a second reference signal having a frequency lesser than said predetermined frequency, g) generating a third reference signal having a frequency between the frequencies of said first and second reference signals and other than said predetermined frequency, h) continuously comparing the frequency of said current level signal with the frequencies of said reference signals, i) effecting a first control function on said motor in accordance with whether the frequency of said current level signal is above or below the frequency of said first reference signal, j) effecting a second control function on said motor In accordance with whether the frequency of said current level signal is above or below the frequency of said second reference signal, k) effecting a third control function on said motor in accordance with whether the frequency of said current level signal is above or below the frequency of said third reference signal.

212. In a method as set forth in claim 206 wherein said motor has a separately excited field, wherein the current flows through said armature in said one direction when said motor is powered from said source of direct current and wherein the current flows through said armature In said opposite direction when said motor is driven as a generator, the further steps of: e) generating a first reference signal having a frequency greater than said predetermined frequency, f) generating a second reference signal having a frequency less than said predetermined frequency, g) continuously comparing the frequency of said current level signal with the frequencies of said reference signals, h) substantially increasing the excitation of said field when the frequency of said current level signal is greater than the frequency of said first reference signal.

213. In a method as set forth in claim 212 the further step of: i) increasing the excitation of said field when the frequency of said current level signal is less than said predetermined frequency and greater than the frequency of said second reference signal and decreasing the excitation of said field when the frequency of said current level signal is less than the frequency of said second reference signal to maintain said armature current at a level whlcn causes said current level signal to have a frequency substantially the same as that of said second reference signal.

214. In a method as set forth in claim 213, the further steps of: j) generating an operator-demand signal having a frequency proportional to the desired speed of said motor, k) generating an actual speed-signal having a frequency proportional to the actual speed of said motor, l) continuously comparing the frequencies of said operator-demand and actual-speed signals and determining the degree in difference therebetween, m) increasing the frequency of said second reference signal as the difference between the frequencies of said operator-demand and actual-speed signals decreases, and vice versa.

215. In a method as set forth in claim 213, the further steps of: j) generating an operator-demand signal having a frequency proportional to the desired speed of said motor, k) generating an actual-speed signal having a frequency proportional to the actual speed of said motor, l) continuously counting the number of cycles of said operator-demand signal per cycle of said actual-speed signal, m) lowering the frequency of said second reference signal as the count in step (l) decreases, and raising the frequency of said second reference signal as the count in step (l) increases.

216. In a method of controlling the operation of a direct-current motor having an armature and a separately excited field, and in which brake current will flow through said armature in one direction when the motor is driven as a generator, the steps of: a) continuously monitoring the level of brake current flow through said armature in said one direction, b) generating a current level signal having a frequency which varies from a predetermined frequency by an amount proportional to the level of brake current flow through said armature, c) generating a brake current limit signal having a frequency different from said predetermined frequency, d) comparing said current level signal and said brake current-limit signal, e ) increasing the excitation of said field when the f requency of said current level signal differs f rom said predetermined fre quency by an amount less than the difference between the frequency of said brake current-limit signal and said predetermined frequency, f ) decreasing the excitation of said f ield when the frequency of said current level signal differs from said predetermined frequency by an amount greater than the difference between the frequency of said brake current-limit signal and said predetermined frequency.

217. in a method as set forth in claim 216 , wherein step (e ) includes increasing the excitation of said field such that the level of armature brake current produces a current level signal having a f requency substantially the same as the frequency of said brake current limit signal.

218. in a method as set forth in claim 217 and further including the steps of : g) generating an operator-demand signal having a fre quency proportional to the desired speed of said motor, h) generating an actual-speed signal having a f requency proportional to the actual speed of said motor, i) continuously comparing the f requency of aid operator-demand and actual-speed signals and determining the difference therebetween, j ) decreasing the difference between the f requency of said brake current-limit signal and said predetermined f requency as the difference between the f requencies of said operator-demand and actual-speed s ignals decreases , and vice versa.

219. In a method as set forth in claim 217 and further including the steps of: g) generating an operator-demand signal having a frequency proportional to the desired speed of said motor, h) generating an actual-speed signal having a frequency proportional to the desired speed of said motor, i) continuously counting the number of cycles of said operator-demand signal per cycle of said actual-speed signal, j) Increasing the difference between the frequency of said brake current-limit signal and said predetermined frequency as the count in step (i) decreases, and vice versa.

220. A method for controlling the operation of a circuit in which a load is connected to a source of direct current through a silicon-controlled rectifier, comprising: a) generating a series of time-spaced gate pulses and applying them to said silicon-controlled rectifier, b) connecting a charged commutating capacitor across the silicon-controlled rectifier at a desired time after each of said gate pulses, c) providing an inspection period each time said capacitor is connected across said silicon-controlled rectifier, said inspection period beginning, at a fixed time after said connection and ending no later than the next of said gate pulses, d) determining at all times if said silicon-controlled rectifier is conducting or not, e) interrupting said circuit if said silicon-controlled rectifier is conducting during an inspection period.

221. The method as set forth in claim 220 wherein the inspection period of step (e) is the first inspection period in which the silicon-controlled rectifier is conducting.

222. The method as set forth in claim 220 wherein the inspection period of step (e) is one immediately following an inspection period in which the silicon-controlled rectifier is conducting.

223. A method as set forth in claim 220 wherein said step (c) Includes: c1) generating a first signal which begins at the end of each gate pulse and ends at the beginning of the next gate pulse, c2) generating a second signal which begins at each of said fixed time and ends at the next connection of said capacitor across said silicon-controlled rectifier, wherein said step (d) includes generating a third signal coincident with the time that said silicon-controlled rectifier is in conduction, and wherein said step (e) includes: e1) determining whether there is a time coincidence of the first, second and third signals during the inspection period of step (e), e2) interrupting said circuit in response to time coincidence of the first, second and third signals during said inspection period.

224. The method as set forth in claim 223 wherein the inspection period of step (e) is the first inspection period in which there is a time coincidence of said first, second and third signals.

225. The method as set forth in claim 223 wherein the inspection period of step (e) is one immediately following an inspection period in which the silicon-controlled rectifier is conducting.

226. A method of controlling the operation of a direct-current motor having an armature and a separately excited field, said armature being connectable to a source of direct current, said field being reversibly connectable to said source of direct current, said motor being provided with an operator-controlled member having forward= and reverse-direction positions to select the direction of connection of said field to said source of direct current and a neutral position to select a disconnection of said field from said source of direct current, the method comprising: a) moving said operator-controlled member to one of the direction positions thereof, b) connecting said field to said source of current In response to said movement and in the direction selected by such movement, c) connecting said armature to said source of direct current for flow of power current to said armature from said source, d) controlling the levels of armature current and field current to power said motor from said source and to drive said motor at a desired speed, e) continuously monitoring the level of field current, f) moving said operator-controlled member from the direction position to which it had been moved in step (a), g) maintaining the connection of said field to said source of direct current made in step (b) as long as the field current remains above a predetermined low level.

227. The method as set forth in claim 226 wherein said step (f) includes moving said operator-controlled member to the opposite direction position, and further including the following steps to be carried out after step (f): h) disconnecting the connection of said armature to said source of direct current, made in step (c), in response to the movement of said operator- controlled member to said opposite direction position, i) connecting said armature for flow of brake current therethrough in response to the movement of said operator-controlled member to said opposite direction position, j) continuously monitoring the actual speed of said motor, k) removing the excitation from said field in response to the actual speed of said motor being below a predetermined minimum speed, l) disconnecting the connection of said field to said source of direct current made in step (b) only after the level of field current is below said predetermined low level and the actual motor speed is below said predetermined minimum speed.

228. The method as set forth in claim 227 and further including: m) reconnecting said field to said source of direct current and in the opposite direction after step (l) and in delayed response to the movement of said operator-controlled member to said opposite direction position effected in step (f).

229. The method as set forth in claim 226 wherein said step (f) includes moving said operator-controlled member to the opposite direction position, and further including the following steps to be carried out after step (f): h) disconnecting the connection of said armature to said source of direct current, made in step (c), in response to the movement of said operator-controlled member to said opposite direction position, i) connecting said armature for flow of brake current therethrough In response to movement of said operator-controlled member to said opposite position, j) continuously monitoring the actual speed of said motor, k) moving said operator-controlled member back from said opposite direction position to said one direction position while the actual speed of said motor is above a predetermined low speed, l) disconnecting the connection of said armature made in step (i) in response to step (k), m) reconnecting the armature to said source as in step (a) in response to step (k), n) maintaining the connection of said field to said source as effected in step (b) during all of steps (c) through (m).

230. The method as set forth in claim 226 wherein said step (f) includes moving aaid operator-controlled member to its neutral position, and further including: h) removing the excitation of said field in response to movement of said operator-controlled member to Its neutral position, i) disconnecting the connection of said field to said source, made in step (b), only after the field current has decreased to said predetermined low level.

231. The method as set forth In claim 230 and further including: j) continuously monitoring the actual speed of said motor, k) moving said operator-controlled member from its neutral position to either of its direction positions after a disconnection of step (i) and while the actual speed of said motor is above a predetermined minimum speed, l) reconnecting said field to said source of current in the direction of step (b) in response to the movement of said operator-controlled member made in step (a).

232 . A method of controlling the operation of a direct-current motor having an armature and a separately excited f ield, where in the armature is connected to a source of direct current through a first s ilicon-controlled rectifier, wherein the field is connectable to said source through a second silicon-controlled rectifier, wherein an operator controlled direction-selecting member is provided for selecting the direction that said field is to be connected to said current source and wherein an adjustable operator-controlled speed-demand member is provided, the method comprising: a) actuating said direction-selecting member to select a direction of connection of said field to said current source, b ) connecting said field to said source of direct current in response to actuation of said direction-selecting member, c) initiating conduction of said second silicon-controlled rectifier in response to actuation of said direction-selecting member, d) continuously monitoring the level of current flowing through said field, e ) inhibiting conduction of said first silicon-controlled rectifier during the time that the f ield current is below a predetermined minimum level, f ) generating a speed-demand signal proportional to the setting of said speed-demand member, g) initiating conduction of said f irst s ilicon-controlled rectifier after the field current has increased to above said predetermined minimum level, h) controlling the conduction of said first silicon-controlled rectifier in response to and as a direct function of the degree of magnitude of said speed-demand signal, i) controlling the conduction of said second silicon-controlled rectifier in response to and as an inverse function of said speed-demand signal.

33. The method as set forth in claim 232 and further including the step of controlling conduction of said second silicon-controlled rectifier to limit the field current to a predetermined maximum allowable level prior to step (g).

34. The method as set forth in claim 232 and further including: continuously monitoring the level of armature current, controlling the conduction of said first and second silicon-controlled rectifier to limit the armature current to a predetermined maximum allowable amount, continuously generating an actual speed signal proportional to the actual speed of said motor, setting the maximum allowable amount of armature current at a relatively high level during the time that the actual speed of said motor is below a predetermined speed and reducing the setting when the actual speed of said motor is above said predetermined speed.

235. The method as set forth in claim 232 and further including: continuously generating an actual-speed signal proportional to the actual speed of said motor, Increasing the conduction of said second silicon-controlled rectifier beyond that called for by said speed-demand signal during the time that the actual speed of said motor is below a predetermined minimum speed.

236. The method as set forth in claim 232 and further including: continuously monitoring the level of armature current, controlling the conduction of said first and second silicon-controlled rectifier to limit the armature current to a predetermined maximum allowable amount, continuously generating an actual speed signal proportional to the actual speed of said motor, setting the maximum allowable amount of armature current at a relatively high level during the time that the actual speed of said motor is below a predetermined speed and reducing the setting when the actual speed of said motor is above said predetermined speed, increasing the conduction of said second silicon-controlled rectifier beyond that called for by said speed-demand signal during the time that the actual speed of said motor is below a predetermined minimum speed.

237. A method of controlling the operation of a direct-current motor having an armature and a s eparately excited f ield, wherein said armature is connected to a source of direct current through a first silicon-controlled rectifier for flow of power current from said source to said armature, wherein said field is connected to said source of direct current through a second silicon-controlled rectifier, and wherein an adjustable operator-controlled speed-demand member is provided, the method comprising: a) generating a speed-demand signal proportional to the setting of said speed-demand member, b ) generating an actual-speed signal proportional to the actual speed of said motor, c) varying the ratio of on-t ime to off-time of conduction of said f irst silicon-controlled rectifier as a direct function of the magnitude of said speed-demand at actual motor speeds less than a predetermined speed, said predetermined speed being substantially less than the maximum allowable speed of said motor, d) maintaining said first silicon-controlled rectifier in continuous conduction at actual motor speeds greater than said predetermined speed, e ) varying the conduction of said second silicon-controlled rectifier as an inverse function of the magnitudes of both said speed-demand and actual-speed signals at motor speeds below and above said predetermined speed.

238. A method of controlling the operation of a direct-current motor having an armature and a separately excited field, wherein said armature is connectable to a source of direct current through a first silicon-controlled rectifier for flow of power current from said source to said armature, wherein said field is connected to said source of direct current through a second silicon-controlled rectifier, and wherein an adjustable operator-controlled speed-demand member is provided, the method comprising: a) continuously monitoring the demanded speed setting of said speed-demand member, b) continuously monitoring the actual speed of said motor, c) continuously comparing the demanded speed and the actual speed, d) generating a deceleration signal when the demanded speed is less than the actual speed by a predetermined degree, e) controlling the conduction of said first silicon-controlled rectifier as a function of the demanded speed during the time that said deceleration signal is not present, f) controlling the conduction of said second silicon-controlled rectifier as an inverse function of the demanded and actual speeds during the time when said deceleration signal is present, g) inhibiting said first silicon-controlled rectifier from conducting when said deceleration signal is present, h) connecting the armature for reverse flow of brake current therethrough when said deceleration signal is present, i) continuously monitoring the level of brake current flowing through said armature, j) controlling the conduction of said second silicon-controlled rectifier to maintain the level of brake current flowing through said armature at a maximum allowable level when said deceleration signal is present.

239. The method as set forth in claim 238 and further including: k) generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, and wherein step (f) includes: f1) controlling the conduction of said second silicon-controlled rectifier, when said acceleration signal is present, as an inverse function of the demanded and actual speeds which are present during the time said acceleration signal is present, f2) maintaining the conduction of said second silicon-controlled rectifier, when neither said acceleration signal nor said deceleration signal is present, as an Inverse function to the demanded and actual speeds which were present at the time said acceleration signal was last present.

240. The method as set forth in claim 238 and further including: k) generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, l) carrying out at least one of the following functions when said acceleration signal is present:

(1-1) increasing the conduction of said first silicon-controlled rectifier beyond that called for in step (e),

(1-2) decreasing the conduction of said second silicon-controlled rectifier below that called for in step (f).

241. The method as set forth in claim 240 and wherein step (f) includes: f1) controlling the conduction of said second silicon-controlled rectifier, when said acceleration signal is present, as an Inverse function of the demanded and actual speeds which are present during the time said acceleration signal is present, f2) maintaining the conduction of said second silicon-controlled rectifier, when neither said acceleration signal nor said deceleration signal is present, as an inverse function of the demanded and actual speeds which were present at the time said acceleration signal was last present.

242. The method as set forth in claim 238 wherein said step (e) Includes: e-1) varying the ratio of on-time to off-time of said first silicon-controlled rectifier as a function of the demanded speed when the actual speed is below a predetermined speed which is substantially below the maximum speed of said motor, e-2) maintaining the first silicon-controlled rectifier in continuous conduction when the actual speed is greater than said predetermined speed, and wherein step (f) Includes controlling the conduction of said second silicon-controlled rectifier as an Inverse function of the demanded and actual speeds both when said actual speed is below said predetermined speed and when It is greater than said predetermined speed.

213. The method as set forth in claim 238 wherein said step (h) includes: h-1) connecting said armature to said source of direct current for flow of brake current from said armature to said source when the actual speed is greater than a predetermined speed which is substantially below the maximum speed of said motor, h-2) connecting said armature for flow of brake current therethrough by shorting across said armature when the actual speed is below said predetermined speed.

244. The method as set forth in claim 238 wherein said step (e) includes: e-1) varying the ratio of on-time to off-time of said first silicon-controlled rectifier as a function of the demanded speed when the actual speed is below a predetermined speed which is substantially below the maximum speed of said motor, e-2) maintaining the first silicon-controlled rectifier in continuous conduction when the actual speed is greater than said predetermined speed, and wherein step (f) includes controlling the cohduction of said second silicon-controlled rectifier as an inverse function of the demanded and actual speeds both when said actual speed is below said predetermined speed and when it is greater than said predetermined speed, and wherein said step (h) includes: h-1) connecting said armature to said source of direct current for flow of brake current from said armature to said source when the actual speed is greater than said predetermined speed, h-2) connecting said armature for flow of brake current therethrough by shorting across said armature when the actual speed is below said predetermined speed.

245. The method as set forth in claim 244 and further including: k) generating an acceleration signal when the demanded speed is greater than the actual speed by a predetermined degree, and wherein step (f) includes: f1) controlling the conduction of said second silicon-controlled rectifier, when said acceleration signal is present, as an inverse function of the demanded and actual speeds which are present during the time said acceleration signal is present, f2) maintaining the conduction of said second silicon-controlled rectifier, when neither said acceleration signal nor said deceleration signal is present, as an inverse function of the demanded and actual speeds which were present at the time said acceleration signal was last present.

246. The method as set forth In claim 245 and further including: l) carrying out at least one of the following functions when said acceleration signal is present:

(1-1) increasing the conduction of said first silicon-controlled rectifier beyond that called for in step (e), (1-2) decreasing the conduction of said second silicon-controlled rectifier below that called for In step (f).

247. The method as set forth in claim 244 and further including: k) generating an acceleration signal when the demand speed is greater than the actual speed by a predetermined degree, l) carrying out at least one of the following functions when said acceleration signal is present:

(1-1 ) increasing the conduction of said f irst silicon-controlled rectifier beyond that called for in step (e) ,

(1-2) decreasing the conduction of said second silicon-controlled rectifier below that called for in step (f ) .

248. A method of controlling the operation of a direct-current motor having an armature and a separately excited field, said armature and field being separately connectable to a source of direct current, the method comprising: a) connecting said field to said current source for current flow in one direction through said field from said source, b) connecting said armature to said current source for flow of power current from said current source to and through said armature, c) controlling the levels of armature power current and field current to power said motor from said current source and drive said motor at a desired speed, d) disconnecting the power flow connection of said armature and current source effected in step (b) while maintaining the connection of said field and current source effected in step (a), e) connecting said armature for opposite flow of brake current therethrough, f) continuously monitoring the level of brake current flowing through said armature, g) regulating the field current to increase the field excitation when the level of armature brake current is below a predetermined maximum allowable level and to decrease the field excitation when the level of armature brake current is above said predetermined level.

249. The method as set forth in claim 248 wherein said armature is connected in step (e) for flow of brake current therethrough by: shorting said armature across the terminals thereof.

250. The method as set forth in claim 249 and further including: reducing the level of field current prior to step (e) and thereafter increasing the level of field current after step (e).

251. The method as set forth in claim 249 and further including: reducing the level of field current prior to step (e) and thereafter increasing the level of field current after step (e) while preventing said field current from increasing more rapidly than a predetermined rate.

252. The method as set forth in claim 249 and further including: h) generating a speed-demand signal proportional to the desired speed to which the motor is to decelerate, i) generating an actual-speed signal proportional to the actual speed of said motor, j) comparing said speed-demand and actual-speed signals and determining the difference therebetween, k) setting said predetermined level of maximum allowable armature brake current in the beginning of step (g) in proportion to the degree of difference between said signals.

253. The method as set forth in claim 252 and further including: l) decreasing said predetermined level of maximum allowable armature brake current in step (g) as the difference between said speed-demand and actual-speed signals decreases.

254. The method as set forth in claim 253 and further including: m) disconnecting the shorting of said armature after the difference between said speed-demand and actual-speed signals is less than a predetermined amount, n) reconnecting said armature and said current source as in step (b) after the disconnection of step (m).

255. The method as set forth in claim 248, wherein said motor is capable of developing an emf greater than that of said current source when said motor is driven as a generator and at a speed greater than a predetermined base speed, and wherein said desired speed of step (c) is above said base speed, the method further being that step (e) includes connecting said armature to said current source, the method further including: h) increasing the level of field current after step (e).

256. The method as set forth in claim 255 and further including: i) preventing the level of field current from increasing more rapidly than a predetermined rate during step (h).

257. The method as set forth in claim 255 and further including: i) subsequently reducing the level of brake current flow through said armature and disconnecting the connection effected in step (e) when the level of armature brake current has reduced to a predetermined level.

258. The method as set forth in claim 255 and further including: i) subsequently reducing the level of brake current flow through said armature and disconnection effected in step (e) when the level of armature brake current has reduced to a predetermined level, j) continuously monitoring the level of field current during steps (g) and (i), k) preventing the field current from Increasing beyond a predetermined maximum allowable level during steps (g) and (i).

259. The method as set forth in claim 258 wherein the level of brake current flow through said armature is reduced in step (k) by: slowing said armature to a speed wherein said motor is incapable of generating sufficient counter emf to cause brake current to flow from said armature to said current source.

260. The method as set forth in claim 258 wherein the level of brake current flow through said armature is reduced in step (i) by: reducing the flow of field current to decrease the excitation of said field to a value and for a time sufficient to cause the counter emf of said motor to decrease to a value insufficient to cause brake current to flow from said armature to said current source.

261. A method of controlling the operation of a direct-current motor having an armature and a separately excited field, said armature and field being separately connectable to a source of direct current, said motor being capable of developing an emf greater than that of said current source when the motor is driven as a generator and at a speed greater than a predetermined base speed, the method comprising: a) connecting said field to said current source of current flow in one direction through said field from aid source, b) connecting said armature to said current source for flow of power current from said source to and through said armature, c) controlling the levels of armature power current and field current to power said motor from said current source and drive said motor at a speed greater than said base speed, d) disconnecting the power flow connection effected in step (b) of said armature and said current source while maintaining the connection of said field and current source effected in step (a), e) increasing the level of field current, f) connecting said armature to said current source for opposite, flow of brake current from said armature to said source, g) continuously monitoring the level of brake current flowing through said armature, h) regulating the field current to increase the field excitation when the level of armature brake current is below a predetermined maxjmum allowable level and to decrease the field excitation when the level of armature brake current is above said predetermined level, i) subsequently reducing the level of brake current flow through said armature and disconnecting the connection effected in step (f) of said armature to said source, j) connecting said armature for flow of brake current therethrough by shorting said armature after it has been disconnected in step (i), k) regulating the field current to increase the field excitation when the level of armature brake current is below a predetermined maximum allowable level and to decrease the field excitation when the level of armature brake current is above said predetermined level.

262. The method as set forth In claim 261 and further including: l) continuously monitoring the level of field current during steps (h) and (i), m) preventing the field current from increasing beyond a predetermined maximum allowable level during steps (h) and (i).

263. The method as set forth in claim 262 wherein the level of brake current flow through said armature is reduced In step (i) by; slowing said armature to a speed wherein said motor is Incapable of generating sufficient counter emf to cause brake current flow from said armature to said current source.

264. The method as set forth in claim 261 wherein the level of brake current flow through said armature is reduced in step (i) by: reducing the flow of field current to decrease the excitation of said field to a value and for a time sufficient to cause the counter emf of said motor to decrease to a value insufficient to cause brake current flow from said armature to said current source.

265. The method as set forth in claim 264 and further including: n) decreasing the level of field current after said armature has been disconnected from the current source in step (i) and then increasing said level of field current after said armature has been shorted in step (j).

266. The method as set forth in claim 265 and further including: o) preventing the level of field current from increasing in steps (e) and (n) more rapidly than a predetermined rate of increase.

267. The method as set forth in claim 261 and further including: l) continuously generating an actual-speed signal proportional to the actual speed of said motor, and wherein the level of brake current flow through said armature is reduced in step (i) by: reducing the level of field current, when the actual speed of said motor is approximately at said predetermined base speed, to a value and for a time sufficient to cause the counter emf of said motor to decrease to a value insufficient to cause current flow from said armature to said current source.

268. The method as set forth in claim 261 and further including: l) generating a speed-demand signal proportional to the desired speed to which the motor is to decelerate, m) generating an actual-speed signal proportional to the actual speed of said motor, n) comparing said speed-demand and actual-speed signals and determining the difference therebetween, o) setting said predetermined level of maximum allowable armature brake current In the beginning of step (k) in proportion to the degree of difference between said signals.

269. The method as set forth in claim 268 and further including: p) decreasing said predetermined level of maximum allowable armature brake current In step (k) as the difference between said speed-demand and actual-speed signals decreases.

270. The method as set forth in claim 269 and further including: q) disconnecting the shorting of said armature after the difference between said speed-demand and actual-speed signals has become less than a predetermined amount, r) reconnecting said armature and said current source as in step (b) after the disconnection of step (q).

271. The method as set forth in claim 261, wherein step (e) includes: preventing the level of field current from Increasing more rapidly than a predetermined rate of increase.

272. The method of controlling the operation of a direct-current motor having an armature and a separately, excited field, said armature being connectable to a source of direct current, said field being reversibly connectable to said source of direct current, said motor being provided with an operator-controlled member whereby the direction of connection of said field to said current source may be selected, the method comprising: a) actuating said operator-controlled member to select a direction of connection of said field to said source of direct current and connecting said field in that direction to said source, b) connecting said armature to said current source for flow of power current from said source to and through said armature, c) controlling the levels of armature power current and field current to power said motor from said source and drive said motor at a desired speed, d) actuating said operator-controlled member to select a reverse direction of connection of said field to said source of direct current, e) disconnecting the connection of said armature to said source effected in step (b) in response to the actuation of step (d) while maintaining the connection of said field to said current source as effected in step (a), f) reducing the level of field current, g) shorting across said armature, h) increasing the level of field current, i) continuously monitoring the level of brake current flowing through said shorted armature, j) regulating the field current to increase the field excitation when the level of armature brake current is below a predetermined maximum allowable level and to decrease the field excitation when the level of armature brake current is above said predetermined level, k) monitoring the actual speed of said motor, l) reducing the level of field current when the actual motor speed has reduced to a predetermined low speed, m) monitoring the level of field current, n) disconnecting the connection of the field to said current source effected in step (a) when the field current has been reduced in step (l) to a predetermined low level.

273. The method as set forth in claim 272 and further including: o) reconnecting said field to said source of direct current and in the direction selected in step (d) after the disconnection of step (n), p) removing the short across said armature.

274. The method as set forth in claim 273 and further including: q) initiating flow of current from said source to said field, r) increasing the level of field current, s) reconnecting said armature to said source for flow of power current from said source to and through said armature after the levelr of field current has risen above a predetermined low level.

275. The method as set forth in claim 272 and further including limiting the rate of increase of said level of field current in step (h) to a predetermined rate.

276. The method of controlling the operation of a direct-current motor having an armature and a separately excited field, said armature being connectable to a source of direct current, said field being reversibly connectable to said source of direct current, said motor being capable of developing an emf greater than that of said current source when said motor is driven as a generator and at a speed greater than a predetermined base speed, said motor being provided with an operator-controlled member whereby the direction of connection of said field to said current source may be selected, the method comprising: a) actuating said operator-controlled member to select a direction of connection of said field to said source of direct current and connecting said field in that direction to said source, b) connecting said armature to said current source for flow of power current from said source to and through said armature, c) controlling the levels of armature power current and field current to power said motor from said source and drive said motor at a speed greater than said base speed, d) actuating said operator-controlled member to select a reverse connection of said field to said source of direct current, e) disconnecting the connection of said armature to said source effected in step (b) In response to the actuation of step (d) while maintaining the connection of said field to said d.c. current source effected in step (a), f) Increasing the level of field current, g) connecting said armature to said current source for flow of brake current from said armature to said source, h) continuously monitoring the level of brake current flowing through said armature, j) continuously monitoring the actual speed of said motor, k) regulating the field current to increase the field excitation when the level of armature brake current is below a predetermined maximum allowable level and to decrease the field excitation when the level of armature brake current is above said predetermined level, l) subsequently reducing the level of brake current flow through said armature and disconnecting the connection effected in step (g) of said armature to said current source when the level of armature brake current has reduced to a predetermined amount, m) reducing the level of field current, n) shorting across said armature, o) increasing the level of field current, p) regulating the field current to Increase the field excitation when the level of armature brake current is below a predetermined level, q) reducing the level of field current when the actual motor speed has reduced to a predetermined low level, r) monitoring the level of field current, s) disconnecting the connection of the field to said current source effected in step (a) when the field current has been reduced in step (q) to a predetermined low level.

277. The method as set forth in claim 276 and further including: t) reconnecting said field to said source of direct current and In the direction selected in step (d) after the disconnection of step (s), u) removing the short across said armature, v) Initiating flow of current from said source to said field, w) increasing the level of field current, x) reconnecting said armature to said source for flow of power current from said source to and through said armature after the level of field current has risen above a predetermined low level.

278. The method as set forth in claim 276 and further including limiting the rate of increase of said level of field current to a predetermined rate in both steps (f) and (m).

279. The method as set forth in claim 276 and further including maintaining a substantially lower maximum allowable level of brake current In step (k) than in step (p).

280. The method of controlling the operation of a battery-powered direct-current motor having an armature and a separately excited field and having an adjustable operator-controlled speed-demand member, the method comprising: a) generating a first signal proportional to the actual speed of said motor, b) generating a second signal proportional to the setting of said speed-demand member, c) generating a third signal having a frequency Inversely proportional to one of said first and second signals, d) generating a fourth signal having a frequency proportional to the other of said first and second signals, e) continuously counting the number of cycles of said fourth signal per cycle of said third signal, f) regulating the average amount of field current as an inverse function of the count obtained in step (e), g) regulating the average amount of armature current as a direct function of said first signal.

281. The method of controlling the operation of a direct-current motor having an armature and a speparately excited field, wherein said armature is connected through a first silicon-controlled rectifier to a source of direct current, wherein said field is connected through a second silicon-controlled rectifier to said source of direct current, and wherein an adjustable, operator-controlled, speed-demand member is provided, the method comprising: a) continuously generating a first speed-demand signal proportional to the setting of said speed-demand member, b) varying the ratio of on-time to off-time of said first silicon-controlled rectifier as a direct function of the magnitude of said first speed-demand signal during operation of said motor below a predetermined speed, c) continuously generating a second speed-demand signal, said second speed-demand signal having a frequency which is inversely proportional to the setting of said speed-demand member, d) continuously generating an actual-speed signal having a frequency which is proportional to the actual speed-of said motor, e) continuously making a count of the number of cycles of said actual-speed signal per cycle of said second speed-demand signal, f) increasing the ratio of on-time to off-time of said second silicon-controlled rectifier as the count in step (e) decreases and decreasing the ratio of on-time to off-time of said second silicon-controlled rectifier as the count In step (f) decreases.

282. The method as set forth in claim 281 wherein the predetermined speed In step (b) is a speed substantially less than the maximum allowable speed of said motor, the method further including: g) maintaining the first silicon-controlled rectifier in continuous conduction during operation of said motor above said predetermined speed.

283. In a method of controlling the operation of a direct-current motor having a separately excited field and in which the level of armature current and the field excitation is normally controlled in response to the setting of an adjustable operator-controlled speed-demand member, the steps of: a) continuously generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, b) continuously generating an actual-speed signal having a frequency proportional to the actual speed of said motor, c) continuously counting the number of cycles of said speed-demand signal per cycle of said actual-speed signal, d) carrying out at least one of the following functions when and as long as the count in step (c) is greater than a predetermined number:

(d-1) increasing the level of armature power current from that normally called for by the setting of said speed-demand member, (d-2) decreasing the level of field current from that normally called for by the setting of said speed- demand member.

284. In a method as set forth in claim 283 and further including: e) carrying out at least one of the following functions when and for as long as the count in step (c) is greater than a second predetermined number, said second predetermined number being higher than said number of step (d):

(e-1) increasing the level of armature power current from that established in step (d),

(e-2) decreasing the level of field current from that established in step (d).

285. In a method as set forth in claim 283 and further including: e) discontinuing normal control of armature power current by said speed-demand member and operating said motor as a generator when and as long as the count in step (c) is less than a second predetermined number, which second number is less than said number of step (d).

286. In a method as set forth in claim 285 and further including the steps of: f) controlling the excitation of said field during the time that the count in step (c) is less than said second predetermined number to maintain the armature brake current at a maximum allowable brake current level.

287. In a method as set forth in claim 286 and further including the step of initially setting the maximum allowable level of armature brake current in step (f) in accordance with the count in step (c) and reducing said level as the count increases.

238. In a method of controlling the operation of a direct-current motor having a separately excited field and in which the level of armature power current and the field excitation is normally controlled In response to an adjustable operator-controlled speed-demand member, the steps of: a) continuously generating a speed-demand signal having a frequency proportional to the setting of said speed-demand member, b) continuously generating an actual-speed signal having a frequency proportional to the actual speed of said motor, c) continuously counting the number of cycles of said speed-demand signal per cycle of said actual-speed signal, d) discontinuing control of armature power current by said speed-demand member and operating said motor as a generator when and as long as the count In step (c) is less than a predetermined number.

239. In a method as set forth in claim 288 and further including the steps of: e) controlling the excitation of said field during the time that the count in step (c) is less than said predetermined number to maintain the armature brake current at a maximum allowable brake current level.

290. In a method as set forth in claim 289 and further including: f) setting said maximum allowable brake current level in step (e) in accordance with the count in step (c).

291. In a method of controlling the operation of a direct-current motor having an armature and a separately excited field and having an adjustable operator-controlled speed-demand member, the method comprising: a) continuously generating a first speed-demand signal having a frequency proportional to the setting of said speed-demand member, b) continuously generating a second speed-demand signal having a frequency inversely proportional to the setting of said speed-demand member, c) continuously generating an actual-speed signal having a frequency proportional to the actual speed of said motor, d) continuously counting the number of cycles of said first speed-demand signal per cycle of said actual-speed signal, e) continuously counting the number of cycles of said actual-speed signal per cycle of said second speed-demand signal, f) controlling the level of armature power current as a direct function of the setting of said speed-demand member when the count in step (d) is higher than a predetermined number, g) controlling the excitation of said field as an inverse function of the count in step (e) when the count in step (d) is higher than said predetermined number.

292. A method as set forth in claim 291, and further including: h) generating a reference signal having a frequency indicative of a motor speed substantially below maximum speed of said motor, i) continuously comparing the actual-speed signal and said reference signal and applying full armature current during the time that the frequency of said actual-speed signal is greater than the frequency of said reference signal.

293. A method as set forth in claim 291 and further including: increasing the excitation of said field when and during the time that the armature power current exceeds an allowable power current limit level, setting the allowable power current limit level as an inverse function of the count in step (e) to decrease said allowable power current limit level as said count increases.

294. A method as set forth in claim 291 and further including: h) carrying out at least one of the following functions when and during the time that the count in step (d) is greater than a second predetermined number, said second predetermined number being higher than said predetermined number of step (d):

(1) increasing the armature power current beyond that established in step (f); (2) decreasing the field excitation from that established in step (g).

295. A method as set forth in claim 294 and further including: i) further performing, and to a greater degree, the functions performed in step (h) when and during the time that the count in step (d) is greater than a third predetermined number, said third predetermined number being higher than said second predetermined number of step (h).

296; The method as set forth in claim 291 and further including: h) discontinuing control of the level of said armature power current by said speed-demand member, driving said motor as a generator and generating armature brake current when and during the time that the count in step (d) is less than said predetermined count of step (f).

297. The method as set forth in claim 296 and further including: i) controlling the excitation of said field to maintain the armature brake current at an allowable brake current limit level during the time that the count in step (d) is less than said predetermined count in step (f).

298. The method as set forth in claim 297 and further including: j) setting the level of the allowable brake current limit in step (i) in accordance with the count in step (d) and reducing said level as the count in step (d) increases.

299. A method as set forth in claim 291 and further including: h) increasing the armature power current beyond that established in step (f) and/or decreasing the field excitation from that established in step (g) when and during the time that the count in step (d) is greater than a second predetermined number, said second predetermined number being higher than said predetermined number of step (g).

300. The method as set forth in claim 299 and further including: j) controlling the excitation of said field to maintain the armature brake current at an allowable brake current limit level during the time that the count in step (d) is less than said predetermined count in step (f).

301. The method set forth in claim 300 and further including: k) setting the level of the allowable brake current limit in step (i) in accordance with, the count in step (d) and reducing said level as the count in step (d) increases.

302. A method as set forth in claim 301 and further including: increasing the excitation of said field when and during the time that the armature power current exceeds an allowable power current limit level, setting the allowable power current limit level as an inverse function of the count in step (e) to decrease said allowable power current limit level as said count increases.

303. A method as set forth in claim 299 wherein said step (g) includes: g1) controlling the excitation of said field, when the count in step (d) is greater than said second predetermined number, as an inverse function of the count in step (e), g2) maintaining the excitation of said field, when the count in step (d) is between said first and second predtermined numbers, at the level established in step (g1) when the count in step (d) was last greater than said second predetermined number.

304. The method of controlling the operation of a battery-powered direct-current motor having an armature and a separately excited field, and having an adjustable operator-controlled speed-demand member, the method comprising: a) continuously generating an armature-control signal having a frequency normally proportional to the setting of said speed-demand member, b) continuously generating a speed-demand signal having a frequency inversely proportional to the setting of said speed-demand member, c) continuously generating an actual-speed signal having a frequency proportional to the actual speed of said motor, d) repeatedly connecting said armature to said battery for flow of power current from said battery to said armature and at a rate equal to the frequency of said armature-control signal, e) disconnecting said armature from said battery at a predetermined time after each such connection, f) continuously counting the number of cycles of said actual-speed signal per cycle of said speed-demand signal, g) generating a field-control signal having a frequency inversely proportional to the count obtained in step (f), h) connecting and disconnecting said field to and from said battery to establish a level of field current therethrough which is proportional to the frequency of said field-control signal.

305. The method as set forth in claim 304 wherein step (h) comprises: h1) repeatedly connecting said field to said battery at a rate equal to the frequency of said field-control signal, h2) disconnecting said field from said battery at a predetermined time after each such connection.

306. The method as set forth in claim 305 and further including: i) decreasing the length of said predetermined time in step (h2) as the count obtained in step (f) increases.

307. The method as set forth in claim 304 wherein step (h) comprises : h1) generating a field-current signal having a frequency proportional to the level of field current, h2) connecting said field to said battery when the frequency of said field-current signal is lower than the frequency of said field-control signal, h3) disconnecting said field from said battery when the frequency of said field-current signal is higher than the frequency of said field-control signal.

308. The method as set forth in claim 307 wherein step (g) includes progressively increasing the inverse proportionality of the frequency of said field-control signal to the count obtained in step (f) as said count increases.

309. The method as set forth in claim 304 and further including: i) continuously monitoring the level of field current flow through said field, j) inhibiting the connection of said armature to said battery in step (d) during the time that the level of field current is below a predetermined minimum value.

310. The method as set forth in claim 304 and further including: i) increasing the frequency of said field-control signal beyond that called for in step (g) during initial operation of said motor at speeds less than a predetermined minimum speed.

311. The method as set forth in claim 304 and further including: i) continuously monitoring the level of armature power current flowing through said armature, j) increasing the frequency of said field-control signal beyond that as called for in step (g) in the event the level of armature power current exceeds a predetermined maximum allowable power current limit level.

312. The method as set forth in claim 311 and further including: h) inhibiting the connection of step (d) of said armature to said battery during the time that the level of armature power current exceeds said predetermined level.

313. The method as set forth in claim 312 and further including: l) decreasing the predetermined time of disconnection of step (e) immediately upon the event that the level of armature power current exceeds said predetermined level.

314. The method as set forth in claim 312 and further including: m) setting the maximum allowable power current limit level as an inverse function of the count obtained in step (f).

315. The method as set forth in claim 312 and further including: l) increasing said maximum allowable power current limit level during operation of said motor at speeds below a predetermined minimum speed.

316. The method as set forth in claim 315 and further including: m) increasing the frequency of said field-control signal beyond that called for In step (g) during operation of aid motor at speeds below said predetermined minimum speed.

317. The method as set forth in claim 304 and further including: i) carrying out steps (d) and (e) during operation of said motor at speeds less than a predetermined base speed which is substantially less than the maximum allowable speed of said motor, and leaving said armature connected to said battery at motor speeds above said predetermined speeds.

318. The method as set forth in claim 317 and further including: k) continuously monitoring the level of armature power current flowing through said armature, l) increasing the frequency of said field-control signal beyond that called for in step (g) in the event the level of armature power current exceeds a predetermined maximum allowable power current limit level.

319 The method as set forth in claim 318 and further including: m) leaving the armature connected to said battery in the event the level of armature current exceeds said maximum allowable power current limit level and the speed of said motor is above said predetermined base speed, n) disconnecting the armature from said battery and maintaining it disconnected therefrom in the event and during the time that the level of armature current exceeds said maximum allowable power current limit level and the speed of said motor is below said predetermined base speed.

320. The method as set forth in claim 304 and further including: i) limiting the rate at which the frequency of said armature-control signal may increase in response to an increase in setting of said speed-demand member.

321. The method as set forth in claim 320 and further including: j) continuously monitoring the level of armature power current flowing through said armature, k) inhibiting the connection of said armature to said battery in the event that the level of armature power current exceeds a predetermined maximum allowable power current limit level.

322. The method as set forth in claim 304 and further including: i) continuously generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) continuously counting the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) doing at least one of the following when and during the time that the count obtained in step (j) is above a predetermined number:

(1) increasing the frequency of said armature-control signal beyond that called for in step (a),

(2) increasing the predetermined time in step (e),

(3) decreasing the frequency of said field-control signal beyond that called for in step (g).

323. The method as set forth in claim 322 and further including: l) doing the same as is done in step (k) but to a greater degree when and during the time that the count obtained in step (j) is above a predetermined number which is higher than the predetermined number of step (k).

324. The method as set forth in claim 322 and further including doing all of the sub-steps of step (k).

325. The method as set forth in claim 324 and further including: l) doing the same as is done in step (k) but to a greater degree when and during the time that the count obtained in step (j) is above a predetermined number which is higher than the predetermined number of step (k).

326. The method as set forth in claim 304 wherein the connections of step (d) permit flow of current through said armature in one direction only, and further including: i) continuously generating a second speeddemand signal having a frequency proportional to the setting of said speed-demand member, j) continuously counting the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) inhibiting the performance of step (d) when the count obtained in step (k) is below a predetermined number and connecting said armature for flow of brake current therethrough.

327. The method as set forth in claim 326 and further including: l) continuously monitoring the level of armature brake current, m) allowing connecting of said field to said battery when the level of armature brake current is less than a predetermined maximum allowable brake current limit level and inhibiting connection of said field to said battery when the level of armature brake current exceeds said maximum allowable level.

328. The method as set forth in claim 327 and further including: n) decreasing the maximum allowable brake current limit level as the number of cycles of said second speed-demand signal per cycle of actual-speed signal increases.

329. The method as set forth in claim 326, wherein said step (k) includes: k1) connecting said armature for brake current flow therethrough when the speed of said motor is below said base speed.

330. The method as set forth in claim 329 and further including: l) continuously monitoring the level of armature brake current, m) allowing connecting of said field to said battery when the level of armature brake current is less than a predetermined maximum allowable brake current limit level and inhibiting connection of said field to said battery when the level of armature brake current exceeds said maximum allowable level.

331. The method as set forth in claim 330 and further including: n) setting the maximum allowable brake current limit level at a substantially lower level during step (k1) than during step (k2).

332. The method as set forth in claim 304 and further including: i) continuously generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) continuously counting the number of cycles of said second speed-demand signal per cycle of said actual-speed signal, k) doing at least one of the following when and during the time that the count obtained in step (j) is above a first predetermined number:

(1) increasing the frequency of said armature-control signal beyond that called for in step (a), (2) increasing the predetermined time in step (e),

(3) decreasing the frequency of said field-control signal beyond that called for in step (g). l) inhibiting the performance of step (d) when the count obtained in step (j) is below a second predetermined number, said second number being lesser than said first number of step (k), and connecting said armature for brake current flow therethrough,

333. The method as set forth in claim 332 and further including: m) continuously monitoring the level of armature brake current, n) allowing connection of said field to said battery when the level of armature brake current is less than a predetermined maximum allowable brake current limit level and inhibiting connection ef said field to said battery when the level of armature brake current exceeds said maximum allowable level.

334. The method as set forth in claim 333 and further including: o) decreasing the maximum allowable brake current limit level as the number of cycles of said second speed-demand signal per cycle of actual-speed signal increases.

335. The method as set forth in claim 332 and further including: m) doing the same as is done in step (k) but to a greater degree when and during the time that the count obtained in step (j) is above a predetermined number which is higher than the predetermined number of step (k).

336. The method as set forth in claim 335 and further including: o) continuously monitoring the level of armature brake current, p) allowing connection of said field to said battery when the level of armature brake current is less than a predetermined maximum allowable brake current limit level and inhibiting connection of said field to said battery when the level of armature brake current exceeds said maximum allowable level.

337. The method as set forth in claim 304 and further including: i) continuously generating a second speed-demand signal having a frequency proportional to the setting of said speed-demand member, j) continuously counting the number of cycles of said second speed-demand signal per cycle of said actual-demand signal, k) allowing step (d) to be carried out when the count obtained in step (j) is above a predetermined number, l) inhibiting step (d) from being carried out when the count obtained in step (j) is below said predetermined number, m) reducing the frequency of said field-control signal, connecting said armature for flow of brake current therethrough and then Increasing the frequency of said field-control signal, when the count obtained in step (j) first goes below said predetermined number.

338. The method as set forth in claim 337 and further including: n) limiting the rate at which the frequency of said armature-control signal may increase in response to an increase In setting of said speed-demand member, o) limiting the rate at which the frequency of said field-control signal may rise in step (m).

339. The method as set forth in claim 338 and further including: p) continuously monitoring the level and direction of armature current, q) increasing the frequency of said field-control signal In the event that the level of armature power current exceeds a maximum allowable power current limit level, r) Inhibiting the connection of said field to said battery in the event that the level of armature brake current exceeds a maximum allowable brake current limit level.

340. The method as set forth in claim 339 and further including: s) varying the maximum allowable power current limit level Independently of the maximum allowable brake current limit level, and vice versa.

341. The method as set forth in claim 339 and further including: s) setting the maximum allowable power current limit level in step (q), as an inverse function of the count obtained in step (f), t) setting the maximum allowable brake current limit level in step (r) as an inverse function of the count obtained in step (j).

342. A power control for use with a direct-current voltage source having first and second terminals of opposite polarity and an electrical load having first and second sides, the first side of said load being connected to the first terminal of said voltage source, said power control comprising: a) first and second silicon-controlled rectifiers, each having main anode and cathode electrodes, one of said main electrodes of said first silicon-controlled rectifier being connected to the corresponding main electrode of said second silicon-controlled rectifier and being connectable to said second terminal of said voltage source, the other of said main electrodes of said first silicon-controlled rectifier being connectable to said second side of said load, b) a series circuit means comprising a third silicon-controlled rectifier having main anode and cathode electrodes and an inductance connected to one of said main electrodes of said third silicon-controlled rectifier, one end of said series circuit means being connected to the other main electrode of said second silicon-controlled rectifier, the other end of said series circuit means being connectable to said first side of said load, c) a commutating capacitor connected between said other main electrodes of said first and second silicon-controlled rectifiers, d) first gating means for repeatedly gating said first and third silicon-controlled rectifiers into simultaneous conduction at a controlled rate, e) second gating means for gating said second silicon-controlled rectifier into conduction at a controlled time after each gating of said first silicon-controlled rectifier.

343. A power control as set forth in claim

342 wherein said first gating means (d) comprises: d1) a pulse generator means for generating a single pulse in response to each application of a trigger pulse thereto, d2) trigger means for generating a series of trigger pulses at a controlled rate and for applying said trigger pulses to said pulse generator means, d3) means responsive to the Initiation of each pulse of said pulse generator means for gating said first and third silicon-controlled rectifiers into conduction, and wherein said second gating means includes means responsive to the termination of each pulse of said pulse generator means for gating said second silicon-conttolled rectifier into conduction.

344. A power control as set forth in claim

343 and further including: f) an operator-controllable variable demand member, and wherein said first gating means (d) further comprises: d4) means for varying the rate of generation of said trigger pulses by said trigger means in accordance with the setting of said demand member.

345. A power control as set forth in claim

344 wherein said first gating means (d) further comprises: d5) means for adjusting the duration of the pulses generated by said pulse generator means.

346. A power control for use with a direct-current voltage source and a direct-current motor, said voltage source having first and second terminals of opposite polarity, said motor having an armature with first and second sides, the first side of said armature being connected to the first terminal of said voltage source, said armature being drivable at times as a generator, said power control comprising: a) first and second silicon-controlled rectifiers, each having main anode and cathode electrodes, one of said main electrodes of said first silicon-controlled rectifier being connected to the corresponding main electrode of said second silicon-controlled rectifier and being connectable to said second terminal of said voltage source, the other of said main electrodes of said first silicon-controlled rectifier being connectable to said second side of said armature, b) a series circuit means comprising a third silicon-controlled rectifier having main anode and cathode electrodes and an Inductance connected to one of said main electrodes of said third silicon-controlled rectifier, one end of said series circuit means being connected to the other main electrode of said second silicon-controlled rectifier, the other end of said series circuit means being connectable to said first side of said armature, c) a commutating capacitor connected between said other main electrodes of said first and second silicon-controlled rectifiers, d) a fourth silicon-controlled rectifier having main anode and cathode electrodes, said fourth and first silicon-controlled rectifiers being connected together with the anode of one of said fourth and first silicon-controlled rectifier being connected to the corresponding main electrode of said third silicon-controlled rectifier, e) first gating means operable at a controllable rate for repeatedly enabling said first and third silicon-controlled rectifiers to conduct simultaneously with said third silicon-controlled rectifier being enabled to conduct prior to enablement of said first silicon-controlled rectifier, f) second gating means for enabling said second silicon-controlled rectifier to conduct at a controlled time after each enablement of said first silicon-controlled rectifier, or during conduction of said fourth silicon-controlled rectifier, g) disabling means operable to prevent operation of said first gating means, h) third gating means for enabling said fourth silicon-controlled rectifier to conduct during operation of said disabling means.

317. A power control as set forth in claim 346 wherein said one end of said series circuit means which is connected to said other main electrode of said second silicon-controlled rectifier comprises the other main electrode of said third silicon-controlled rectifier.

348. A power control as set forth in claim 346 wherein said first gating means includes means for enabling said third silicon-controlled rectifier to conduct during conduction of said fourth silicon-controlled rectifier while preventing said first silicon-controlled rectifier from being enabled to conduct prior to commutation of said fourth silicon-controlled rectifier.

349. A power control as set forth in claim 346 wherein said first gating means comprises a pulse generator means for generating a single pulse In response to the application of a trigger pulse thereto, trigger means for generating a series of trigger pulses at a controlled rate and for applying said trigger pulses to said pulse generator, and means responsive to the initiation of each pulse of said pulse generator means for gating said first and third silicon-controlled rectifiers into conduction; and wherein said second gating means includes means responsive to the termination of each pulse of aid pulse generator means for gating said second silicon-controlled rectifier into conduction.

350. A power control as set forth in claim

346 and further including: i) a fifth silicon-controlled rectifier having main anode and cathode electrodes connected respectively to the main cathode and anode electrodes of said first silicon-controlled rectifier, j) fourth gating means for enabling said fifth silicon-controlled rectifier to conduct during operation of said disabling means, k) means for selectively allowing one of said third and fourth gating means to operate while inhibiting operation of the other thereof.

351. A top speed limiting control system for a direct-current motor having an armature, said control system including: an operator-controllable speed demand member settable to demand a motor speed ranging from minimum to maximum, armature control means responsive to the setting of said speed demand member for establishing a level of armature power current in accordance with the setting of said speed demand member, first signal generating means for generating a top speed limit signal Indicative of a speed lower than the maximum speed demandable by said speed demand member, second signal generating means for generating an actual speed signal indicative of the actual speed of said motor, means for continuously comparing said top speed limit signal and said actual speed signal and for generating a first control signal when the actual speed of said motor is less than the top speed limit and a second control signal when the actual speed of said motor is greater than said top speed limit, means for allowing said armature control means to respond to said speed demand member when said first control signal is present and for inhibiting such response when said second control signal is present.

352. A control system as set forth in claim 351 and wherein said motor has a separately excited field, said control system further including: field control means responsive to the setting of said speed demand member and to the actual speed of said motor for varying the level of field current as an inverse function of the demanded and actual speeds.

353. A control system as set forth in claim 352 wherein said armature control means includes: means for maintaining a continuous flow of armature current when said speed demand member is set to demand maximum speed and said first control signal is present; and, means for shutting off flow of armature current during the time said second control signal is present.

354. A control system as set forth in claim

351 and further including: third signal generating means for generating a demanded speed signal indicative of the speed demanded by the setting of said speed demand member, fourth signal generating means for comparing said actual speed signal with said demanded speed signal when said first control signal is present and for comparing said actual speed signal with said top speed limit signal when said second control signal is present, and for generating an acceleration signal when the speed signal with which said actual speed signal is compared is indicative of a speed greater than the actual speed of said motor, means responsive to the presence of said acceleration signal for increasing the rate of acceleration of said motor.

355. A control system as set forth in claim

354 and wherein said motor has a separately excited field, said control system further including: field control means responsive to the setting of said speed demand member and to the actual speed of said motor and to the presence of said acceleration signal for varying the level of field current as an inverse function of the demanded and actual speeds during the time that said acceleration signal is present.

356. A control system as set forth in claim

355 wherein said armature control means includes: means for maintaining a continuous flow of armature current when said speed demand member is set to demand maximum speed and said first control signal is present; and, means for shutting off flow of armature current during the time said second control signal is present.

357. A control system as set forth in claim

354 wherein said fourth signal generating means further includes means for generating a braking signal when the speed signal with which said actual speed signal is compared is indicative of a speed less than the actual speed of said motor, said control system further including means responsive to the presence of said braking signal for connecting said armature for flow of brake current therethrough.

358. A control system as set forth in claim 351 and further including: third signal generating means for generating a demanded speed signal having a frequency proportional to the speed demanded by the setting of the speed demand member wherein said first signal generating means includes means for generating said top speed limit signal with said top speed limit signal having a frequency less than the maximum frequency of said speed demand signal, wherein said second signal generating means Includes means for generating said actual speed signal with said actual speed signal having a frequency proportional to the actual speed of said motor, and wherein said means for continuously comparing said top speed limit signal and said actual speed signal Includes eans for generating said first control signal when the frequency of said actual speed signal is lower than the frequency of said top speed limit signal and for generating said second control signal when the frequency of said actual speed signal is higher than the frequency of said top speed limit signal.

359. A control system as set forth in claim

358 and wherein said motor has a separately excited field, said control system further including: fourth signal generating means for generating a second demanded speed signal having a frequency inversely proportional to the speed demanded by the setting of said speed demand member, counter means for counting the number of cycles of said actual speed signal per cycle of said second demanded speed signal, field control means for varying the level of field current as an Inverse function of the counter obtained by said counter means.

360. A control system as set forth in claim 359 wherein said armature control means Includes: means for maintaining a continuous flow of armature power current when said speed demand member is set to demand maximum speed and said first control signal is present; and, means for shutting off flow of armature power current during the time said second control signal is present.

361. A control system as set forth in claim

358 and further including: counter means for counting the number of cycles of said demanded speed signal per cycle of said actual speed signal when said first control signal is present and for counting the number of cycles of said top speed limit signal per cycle of said actual speed signal when said second control signal is present, means responsive to the count of said counter means being greater than a predetermined number for generating an acceleration signal, means responsive to the presence of said acceleration signal for increasing the rate of acceleration of said motor when said acceleration signal is present and for decreasing the rate of acceleration when said acceleration signal is not present.

362. A control system as set forth in claim 361, and wherein said motor has a separately excited field, said control system further including: fourth signal generating means for generating a second demanded speed signal having a frequency inversely proportional to the speed demanded by the setting of said speed demand member, second counter means for counting the number of cycles of said actual speed signal per cycle of said second demanded speed signal, field control means for varying the level of field current as an inverse function of the count obtained by said second counter means, during the time that said acceleration signal is present.

363. A control system as set forth in claim

362 wherein said armature control means includes : means for maintaining a continuous flow of armature power current when said speed demand member is set to demand maximum speed and said first control signal is present; and, means for shutting off flow of armature power current during the time said second control signal is present.

364. A control system as set forth in claim 361 and further including: means responsive to the count of said first mentioned counter means for generating a braking signal when the count of said counter means is less than a seeond predetermined number, said second predetermined number being less than said first mentioned predetermined number, means responsive to the presence of said braking signal for connecting said armature for flow of brake current therethrough.