WO1980000626A1

WO1980000626A1 - Data processing system having error detection and correction circuits

Info

Publication number: WO1980000626A1
Application number: PCT/US1979/000669
Authority: WO
Inventors: W Lewis; W Ward
Original assignee: Ncr Co
Priority date: 1978-09-01
Filing date: 1979-08-27
Publication date: 1980-04-03
Also published as: EP0016823A4; EP0016823A1; US4201337A; JPS55500610A

Abstract

A data processing system (10) implemented in LSI includes a plurality of identical error detection and correction (EDC) circuits (30a-f) operating either in an error correction code (ECC) mode by generating ECC parity bits, or a byte parity mode by generating or checking byte parity bits. In operation in an ECC mode, the EDC circuit (30a) generates ECC check bits for storage in association with a data word being stored in a memory (14). When a data word is fetched from the memory (14) the fetched check bits are compared with check bits generated by the EDC circuit (30a) in an error control circuit (36) to provide syndrome bits. For a single error the syndrome bits cause the provision of an enable signal to that one of a plurality of memory interface circuits (13a-d) containing the error, all the interface circuits (13a-d) being provided with identical syndrome bits identifying a bit position within the interface circuit. The EDC circuits (30) may be used individually with a 32 bit data bus or may be combined for use with a 64 bit data bus.

Description

DATA PROCESSING SYSTEM HAVING ERROR DETECTION AND CORRECTION CIRCUITS

Technical Field

This invention relates to data processing system of the kind including: a data bus arranged to carry a plurality of data bits from a first location to a second location in the system; error bit means adapted to logically combine said data bits to generate a plurality of error correction code check bits; and error control means adapted to compare the generated check bits with a plurality of error correction code check bits associated with the data bits from the first location and thereby generate a plurality of syndrome bits identifying the bit position of any error in the data bits.

Background Art

In designing a data processing system implemented in LSI (large scale integration), it has been found desirable to limit the number of different types of LSI chips within the system. The production of a mask to manufacture each LSI chip-type requires a large amount of design effort and expense in order to arrange the large number of components on the chip and to provide the connections on the chip between such components. Unless production costs are minimized by limiting the total number of different LSI chip-types, an LSI system is not cost competitive with systems implemented in MSI (medium scale integration) or SSI (small scale integration).

A problem associated with LSI chips is that a large number of input/output pins are often required because of the large number of circuit components and the input and output signals used in connection with such components. If the number of pins exceeds the maximum number which may be physically mounted on the chip, techniques are required for spreading functions or operations among several identical chips. Thus, in the case where several bytes of data are operated on at one time as a single data word, the data may be "sliced", for example in bytes, with an identical LSI data chip for receiving each byte in the data .word and operating on each byte individually.

A data processing system of the kind specified is known from U. S. Patent No. 3,568,153. According to the known system the error correction circuitry is adapted to be controlled by an error correction code wherein the syndrome bits form the binary number of the bit position where the error has occurred. The known system has the disadvantage of being unsuitable for utilization in a system wherein respective bytes of data are handled in identical LSI data chips.

Disclosure of the Invention

It is an object of the present invention to provide a data processing system of the kind specified wherein the aforementioned is alleviated. Therefore, according to the present invention there is provided a data processing system of the kind specified characterized in that the system includes a plurality of identical data receiving circuits at the second location arranged to receive respective groups at said data bits, said syndrome bits including a first group of syndrome bits identifying one of a plurality of said groups of data bits where the error has occurred and a second group of syndrome bits identifying the bit position within one group of data bits where the error has occurred, said error control, means being adapted to generate an enabling signal in response to said first group of syndrome bits, the enabling signal being applied in operation to one of said data receiving circuits, which include identical bit decoder means arranged to receive said second group of syndrome bits and thereby control the correction in the enabled data receiving circuit of the erroneous bit. It will be appreciated that a system according to the immediately preceding paragraph can be readily implemented as an LSI system having plural identical data sliced data chips since the control inputs and the control logic or circuiting of each of the data receiving circuits are identical.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings.

Brief Description of the Drawings

Fig. 1 is a simplified block diagram illustrating a data processing system and the manner in which an error detection and correction circuit may be used at various locations in the data processing system. Fig. 2 is a block diagram of the error detection and correction circuit illustrated in Fig. 1.

Fig. 3 is an H-parity check matrix illustrating the modified Hamming code used in the error detection and correction circuit of Fig. 2. Fig. 4 is a logic diagram illustrating the

EXCLUSIVE OR tree for generating C₇.

Fig. 5 is a block diagram illustrating the manner in which the error detection and correction circuit is connected when used in an ECC mode. Fig. 6 is a block diagram illustrating the manner in which the error detection and correction circuit is connected when used in a byte parity mode.

Figs. 7A and 7B are a circuit block diagram illustrating the use of the error detection and correction circuit of Fig. 2 in a system having a 64 bit data bus.

Figs. 8A arid 8B are an H-parity check matrix illustrating the modified Hamming code used in the circuit of Figs. 7A and 7B.

Best Mode for Carrying Out the Invention

Referring now to Fig. 1, a microprocessor based data processing system 10 is shown. The data processing system 10 includes an arithmetic-logic unit (ALU) 12 which is connected by control and data buses to a main memory 14 by way of a memory interface 16, to a control store 18, to a scratch pad memory 20 and to an input/output (I/O) processor 22.

During normal operation, the ALU 12, as part of a processor, receives instructions and data from the main memory 14. The instructions are decoded and cause a microprogram stored in control store 18 to be selected. The system operates in accordance with the selected microprogram in order to execute each instruction from main memory. The necessary signals to control the sequencing of each component of the system 10 during the execution of each instruction are provided by a processor timing and control circuit 24, and there may be access, through the I/O processor 22 and a bus 50, to peripheral units 26 such as card readers, disc memories, operator consoles, printers, or the like. The ALU performs any necessary arithmetic or logic operations on data and may temporarily store data in the scratch pad memory 20.

As is common in data processing systems implemented in LSI, the ALU 12 and memory interface 16 receive groups or byte-slices of data, with the illustrated ALU and memory interface each comprised of four identical integrated circuit chips, and with each chip receiving and operating on one byte of data.

Error detection and correction (EDC) circuits, designated 30a through 30f, are connected at various locations along the data buses that interconnect the components of the system 10. Each of the EDC circuits is implemented in LSI and is identical. As will be more fully described later, each of the EDC circuits is capable of receiving 32 bits of data, and in response generating byte parity bits for byte parity error detection or generating ECC parity bits for single error correction and double error detection (SEC/DED). It is an advantage of the present embodiment that identical EDC circuits can be utilized at various locations in the data processing system, to provide either byte parity error detection, or single error correction and double error detection.

In Fig. 1, EDC circuit 30a operates in an ECC mode and is connected to receive the 32 bits of data from a bus 32 that transfers data between a location at the memory interface 16 and a location at the main memory 14. The EDC circuit 30a generates seven ECC parity bits which are provided by way of a bus 34 to an error control circuit 36. The error control circuit 36 either passes the generated ECC parity bits onto main memory 14 by way of a bus 38 as check bits to be stored with the data, or compares the ECC parity bits with the check bits coming from main memory along bus 38 to determine if an error has occurred in the data fetched from memory. If a single error has been made in the data, the error control circuit 36 generates appropriate syndrome and enabling bits along a bus 40 to the memory interface to correct the bit in error before being passed along one of four busses 41a, 41b, 41c and 41d to ALU 12. If a double error has been made, a DOUBLE ERROR signal is generated by the error control circuit 36 which can, for example, be delivered to the processor timing and control circuit 24 to cause the data to be fetched again from memory. The EDC circuits 30b and 30c are each operated in a byte parity mode and are used tσ both generate and check byte parity bits. EDC circuit 30b generates byte parity bits on a bus 43 for data leaving the I/O processor 22 along a bus 42 and receives byte parity bits from bus 43 for checking the byte parity of the data carried on the bus 42 from the ALU 12 to the I/O processor 22. The EDC circuit 30c generates byte parity bits on the bus 43 for data carried on bus 42 from the ALU to the I/O processor and receives byte parity bits from EDC circuit 30b on bus 43 for checking the byte parity of data carried on bus 42 from the I/O processor to the ALU.

The EDC circuits 30d, 30e and 30f also operate in a byte parity mode. EDC circuit 30d generates byte parity bits on a bus 45 for data sent to the scratch pad memory 20 and control store 18 along a bus 44, and the EDC circuit 30e checks the byte parity of data on a bus 46 returning from the scratch pad memory 20. EDC circuit 30f checks the byte parity of data on a bus 48 returning from the control store 18. Each of the EDC circuits 30b, 30c, 30e, and 30f generate an error signal (BP ERROR) when a byte parity error is detected.

It should be understood that the manner in which the EDC circuits 30a through 30f are shown is only exemplary, and that a typical data processing system will normally have more EDC circuits than those shown. The actual operation of the EDC circuits 30a through 30f will be explained in more detail in connection with Figs. 2, 3, 4, 5 and 6.

Referring now to Fig. 2, there is shown a block diagram of an EDC circuit 30, which could be used for any one of the EDC circuits 30a through 30f illustrated in Fig. 1. The EDC circuit 30 has data input terminals for receiving 32 bits of data, designated D₀ through D₃₁. The EDC circuit 30 also has eight parity bit terminals, designated E₀ through E₇, and two control inputs, designated CK/GEN and ECC/BP.

The data bits D₀ through D₃₁ are received by a connection matrix 54 which, in turn, connects the data lines to a group of EXCLUSIVE OR trees, designated 56. The connection matrix 54 and the EXCLUSIVE OR trees 56 together cause the data bits D₀ through D₃₁ to be logically combined to generate ECC parity bits in accordance with the modified Hamming code illustrated by the H-parity check matrix of Fig. 3. Turning momentarily away from Fig. 2 and referring to Figs. 3 and 4, the H-matrix of Fig. 3 illustrates by its patterns of "ones" and "zeros" the particular data bits which will be combined to generate each error correction code (ECC) bit. A "one" indicates that the corresponding data bit is included in the combination of data bits to generate an ECC bit, and a "zero" indicates that the corresponding data bit is not included in the combination. It should be noted that the "ones" and "zeroes" in the H-matrix do not represent logic levels.

Table I below shows the logical equations represented by the rows of the H-matrix for generating each of the ECC parity bits C₁ through C₇.

The symbol

represents an EXCLUSIVE OR.

Thus, for example, to generate the ECC bit C₇, the equation for the ECC bit C₇ in Table 1 and the row corresponding to ECC bit C₇ in Fig. 3 show that the data bits D₀-D₁₆ (represented by "ones" in the matrix) are logically combined, and the data bits ^D17-^D31 (represented by "zeros" in the matrix) are not included in the combination.

From the above it can be seen that C₇ is at a "0" logic level when an even number of the data bits D₀-D₁₆ are at a "1" logic level, and is at a "1" logic level when an odd number of the data bits are at a "1" logic level. C₇ is thus said to have even parity. ECC bits C₄, C₅ and C₆ will also have even parity. C₁, C₂ and C₃, on the other hand, will have odd parity, and those ECC bits are at a "0" logic level when an odd number of the data bits used to generate the ECC bits are at a "1" logic level, and are at a "1" logic level when an even number of the data bits are at a "1" logic level.

In Fig. 4, there is shown an EXCLUSIVE OR tree 58 which could be used to generate C₇ in accordance with the logical equation for C₇ listed in Table I and discussed above. The group of EXCLUSIVE OR trees represented by the block 56 in Fig. 2 will comprise a plurality of such logic trees, one for generating each ECC bit

^Cl^-C7^.

A description of a connection matrix and a set of EXCLUSIVE OR trees which combine data bits in certain patterns so as to generate ECC bits can be found in a wealth of publications and patents, for example, U. S. Patent No. 3,648,239, entitled "System For Translating to and from Single Error Correction-Double Error Detection Hamming Code and Byte Parity Code", by William C. Carter et al., and U. S. Patent No. 3,836,957, entitled "Data Storage System with Deferred Error Detection", by Keith A. Duke, et aI. Reference can be had to these patents if a more detailed description is desired. The Duke et al. patent is also noteworthy because it discloses a common circuit generating both ECC parity bits and byte parity bits.

It can be seen from the H-matrix of Fig. 3 and the logic diagram of Fig. 4 that the ECC code can be conveniently used to provide byte parity bits in addition to the ECC bits C₁-C₇. In Fig. 4, the EXCLUSIVE OR tree 58 generates even byte parity for byte 0 (data bits D₀-D₇) and byte 1 (data bits D₈-D₁₅). This is also illustrated by the enclosed portions labeled B₀ and B₁ in Fig. 3. As also illustrated in Fig. 3, by the enclosed portions labeled B₂ and B₃, byte parity for bytes 2 and 3 can also be obtained during the generation of the ECC bits C₅ and C₄, respectively. Referring again to Fig. 2, the output of the

EXCLUSIVE OR trees 56 is shown as the ECC parity bits C₁-C₇, and the byte parity bits B₀-B₃. The bits C₁-C₇ are presented to a set of enabling gates 60, and the byte parity bits B₀-B₃ are presented to a set of enabling gates 62 and one set of inputs of an EXCLUSIVE OR circuit 64. The seven outputs of the enabling gates 60 are connected to the terminals E₁-E₇ of the EDC circuit 30. The terminals E₄-E₇ are bidirectional and are also connected to the outputs of the enabling gates 62 and to a second set of inputs to the EXCLUSIVE OR circuit 64. The output of EXCLUSIVE OR circuit 64 is connected to a set of enabling gates 66, whose four outputs are connected to the terminals E₀-E₃.

When the EDC circuit 30 is to operate in a byte parity mode, a "1" logic level is applied to the control input ECC/BP. The ECC/BP control output is connected to the control line 68 of the enabling gates 60 and the "1" on control line 68 causes gates 60 to become disabled. The "1" at the ECC/BP input is also applied to an OR gate 70 and causes the inverted outputs of the gate 70 to go to a "0".

When in the byte parity mode (ECC/BP at a "1"), the EDC circuit 30 can be selected either for checking or generating byte parity bits, depending on the signal at the control input CK/GEN, which is connected to the control lines 72 and 74 of the enabling gates 62 and 66 by an OR gate 76. If the signal at CK/GEN is at a "1", the circuit is selected for generating parity and such signal is passed by OR gate 76 to control line 74 to disable the enabling gates 66. Such signal also appears as a "0" at the inverted output of OR gate 76, and is applied to the control line 72 to cause the enabling gates 62 to pass the byte parity bits B₀-B₃ from the output of the EXCLUSIVE OR trees 56 to the terminals E₄-E₇.

If the signal at CK/GEN is at a "0", the circuit is selected for checking parity and gates 62 are disabled and gates 66 are enabled. A comparison is made by the EXCLUSIVE OR circuit 64 of each of the byte parity bits B₀-B₃ generated by the connection matrix 54 and EXCLUSIVE OR trees 56 to each of the corresponding byte parity check bits received on the terminals E₄- E₇. The result of each bit comparison appears at the four terminals E₀-E₃, with a "0" indicating a match and no byte parity error, and a "1" indicating a mismatch and a byte parity error in one of the bytes in the data bits D₀-D₃₁.

When the ECC parity bits are to be generated by the EDC circuit 30, control input ECC/BP is at a "0", and control input CK/GEN is at a "1". Control lines 72 and 74 are at a "1" and enabling gates 62 and 66 are disabled. Control line 68 is at a "0", and thus the ECC bits C₁-C₆ at the output of the EXCLUSIVE OR trees 56 are passed through enabling gates 60 to the terminals E₁-E₇.

It should be noted that the enabling gates 60, 62 and 66 are comprised of NOR gates in order to be enabled by a "0" on the control lines 68, 72 and 74. Accordingly, the C₁-C₇ and B₀-B₃ bits are inverted by the enabling gates and are thus inverted when they appear at the terminals E₀-E₇. From the above, it can be seen that the EDC circuit 30 can be selected, by the signals applied at the control inputs CK/GEN and ECC/BP, to generate ECC parity bits or byte parity bits for data bits D₀-D₃₁' ^or to perform a byte parity check of the data bits D₀-D₃₁ by comparing the byte parity check bits provided at terminals E₄-E₇ with generated byte parity bits B₀-B₃. Fig. 5 shows in greater detail the connection of the EDC circuit 30a in the data processing system 10 of Fig. 1. The EDC. circuit 30a operates in an ECC mode, i.e., generating ECC parity bits. The data bus 32 carrying bits D₀-D₃₁ is connected between the main memory 14 and the EDC circuit 30a, as well as being connected in a byte sliced fashion between the main memory and the memory interface 16. The memory interface 16 is comprised, as illustrated in Fig. 5, of four integrated circuit chips 13a, 13b, 13c and 13d, with only the memory interface chip 13a receiving data byte

0 (bits D₀-D₇) illustrated in detail. The memory interface chips 13b-13d are identical to 13a, but receive the bytes 1, 2 and 3 and are not illustrated in detail.

The terminals E₁-E₇ of the EDC circuit 30a provide the inverted ECC parity bits (terminal

E₀ is not used), and the bits are carried by bus

34 to the error control circuit 36. The error control circuit 36 is also connected to bus 38 for carrying the ECC check bits C₁-C₇ between the main memory and the error control circuit.

The memory interface chip 13a illustrated in Fig. 5 includes a bidirectional bit transfer circuit 82 for receiving each of the data bits D₀-D₇. Only the bit transfer circuit 82 for receiving the data bit D₀ is shown in detail, but it should be understood that in each of the four memory interface, chips 13a-I3d, there will be eight bit transfer circuits, one for each bit. Each bit transfer circuit 82 transfers its associated data bit between the bus 32 (from main memory) and one of the busses 41a-41d (from the ALU).

The illustrated bit transfer circuit 82 includes a flip-flop 84 having its input D connected for receiving the bit D₀ and its output Q connected to one input of an EXCLUSIVE OR gate 86. The input CLK of flip-flop 84 receives a clocking signal FETCH for latching the bit D₀ into the flip-flop when data is to be fetched from the main memory to the ALU. The circuit 82 also includes a second flip-flop 88 which has its input D connected to

eive the bit D₀ from bus 41a. The inverted output of the flip-flop 88 is connected to one input of a NOR gate 90 which in turn has its output connected for delivering bit D₀ to bus 32. When data is to be passed from the ALU for storage in the main memory, the flip-flop 88 receives a clocking signal STORE for latching the bit D_Q from bus 41a into the f and the NOR gate 90 receives an enabling signal

for passing the data bit through to bus 32.

A bit decoder 92 in each memory interface chip has eight outputs S_D0-S_D7, with one of the outputs, provided to the second input of the EXCLUSIVE OR gate 86 in each bit transfer circuit 82, and causing the bit transferred from bus 32 to busses 41a-41d to be inverted under circumstances to be described in detail later.

As illustrated in Fig. 5, the error control circuit 36 includes a bit comparison and transfer circuit, designated 96, for each of the seven inverted ECC parity bits

delivered by the EDC circuit 30a and each of the corresponding check bits C₁-C₇ delivered by bus 38. Although only the bit transfer circuit for receiving bit from bus 34 and bit C

₁ from bus 38 is illustrated in detail, it should be understood that six other identical bit transfer circuits 96 will also be located in error control circuit 36.

The illustrated bit transfer circuit 96 includes a NOR gate 98 and an EXCLUSIVE NOR gate 100, each having an input for receiving the bit from the EDC

circuit 30a. A second input of NOR gate 98 receives an enabling signal

for inverting and passing the ECC parity bit when the ECC parity bits generated by

the EDC circuit 30a are to be stored in memory with data as ECC check bits. The output of NOR gate 98 is connected to the bus 38. Bus 38 is also connected to the input D of a flip-flop 102. The flip-flop 102 receives a clocking signal FETCH at its input CLK when data is to be fetched from memory to the ALU, causing the check bit C₁ from bus 38 to be clocked into the flip-flop 102 and be presented to a second input of the EXCLUSIVE NOR gate 100. The EXCLUSIVE NOR gate 100 provides a comparison of the ECC parity bit generated by the EDC

circuit 30a and the ECC check bit C₁ carried on bus 38 when data is fetched from the main memory. The comparison of each ECC parity bit and ECC check bit by the EXCLUSIVE NOR gate 100 in each bit transfer circuit 96 will indicate if an error has been made in the transfer of the data from the main memory to the memory interface. The output of each EXCLUSIVE NOR gate 100 is referred to as a syndrome bit, and the error control circuit 36 will provide seven syndrome bits, designated S₁-S₇, one syndrome bit from each bit transfer circuit 96. If any one of the data bits which are used to generate each ECC parity bit has arrived at the memory interface chip from main memory and is in error, the syndrome bit associated with such ECC parity bit at the output of EXCLUSIVE NOR gate 100 will be at a "one". By examining all of the syndrome bits, the location of a single error, and the existence of a double error, can be determined in accordance with the following rules: 1. If an odd number of syndrome bits are at a "1" logic level, a single data bit error, has occurred.

2. If an even number of syndrome bits are at a "1" logic level, a double data bit error has occurred.

3. If all syndrome bits are at a "0" logic level, no error has occurred.

The location of any single bit in error is determined, by decoding the seven syndrome bits. If a single error has occurred, the syndrome bits indicate that one of the 32 data bits D₀-D₃₁ is in error so that it may be corrected in a manner to be described in greater detail later. The modified Hamming code chosen in the present embodiment and illustrated by the matrix in Fig. 3 is arranged such that a group comprised of the three syndrome bits S₁-S₃ will, when decoded for indicating a single bit in error, point to the same bit position in each of the four bytes of data received by memory interface chip 13a-13d. A group comprised of the remaining syndrome bits S₄-S₇ determine, along with bits S₁-S₃, which byte the single error has occurred in. This feature in correcting a single error can be seen by viewing the H-matrix in Fig. 3, where the patterns of "ones" and "zeros" in the first three rows for generating C₁, C₂ and C₃ are repetitive for byte 0 (D₀-D₇), byte 1 (D₈-D₁₅), byte 2 (D₁₆-D₂₃) and byte 3 (D₂₄-D₃₁). Thus, for each of the bytes 0, 1, 2 and 3, the syndrome bits S₁, S₂ and S₃, when indicating an error in a single bit location in any one of the bytes, will indicate the same bit location in each byte. As mentioned above, the actual byte where the error occurs is determined by also considering the remaining syndrome bits S₄-S₇. The above feature of the illustrated modified

Hamming code is particularly advantageous in providing single error correction in an LSI system, such as the preferred embodiment. This is illustrated by again referring to Fig. 5, where syndrome bits S₁, S₂ and S₃ are shown presented, to the decoder 92 in each of the memory interface chips 13a-13d. Since the decoder in each memory interface chip receives the same signal (syndrome bits S₁, S₂ and S₃) to indicate the bit position of a single bit error, each of the LSI memory interface chips will have the same decoder logic circuitry and may be constructed identically. The advantage achieved by permitting as many LSI chips to be constructed identically as is possible has been noted earlier.

With regard to the decoder 92 in memory interface chip 13a illustrated in Fig. 5, each one of the eight possible combinations of the bits S₁-S₃ causes one of its output lines S_D0-S_D7 to be enabled. In addition, the error control circuit 36 includes a byte decoder and logic circuit 106 for receiving all the syndrome bits S₁-S₇, and in response, providing an enabling signal on one of four enable outputs. Each of the enable outputs of decoder 106 enables one of the decoders 92 in the four memory interface chips 13a-13d. The decoder and logic circuit 106 has appropriate logic circuitry for determining the byte whose memory interface chip decoder 92 is to be enabled in accordance with the logic equations in Table II.

A "1" for any one of the equations for Byte 0, Byte 1, Byte 2 or Byte 3 will cause the decoder 92 associated with the memory interface chip of that byte to be enabled.

When a particular bit position is indicated by the syndrome bits as in error, the EXCLUSIVE OR gate 86 in the bit transfer circuit 82 associated with that data bit causes the bit to be inverted. For example, if data bit D₀ is in error, the syndrome bits S₁-S₇ will cause decoder and logic circuit 106 to enable only the decoder 92 in the memory interface chip 13a and the syndrome bits S₁-S₃ will cause the output S_D0 of the decoder 92 in memory interface chip 13a to go to a "1". The logic level of the bit D₀, when passed through flip-flop 84 to the EXCLUSIVE OR gate 86, will be inverted by gate 86 and be passed on to the bus 41a for transfer to the ALU. When an even number of the syndrome bits S₁-S₇ are at a "1", appropriate logic in the decoder and logic circuit 106 will cause a DOUBLE ERROR signal to be generated, indicating a double data bit error in the data fetched from main memory.

From the foregoing, it can be seen that the EDC circuit 30a can be made to generate ECC parity bits when data is passed along bus 32 from the memory interface 13 to the main memory, with the ECC parity bits passing through the NOR gate 98 in each of the seven transfer circuits 96 to bus 38 where the ECC bits are stored as check bits with data in the main memory. Furthermore, the EDC circuit 30a can be used with error control circuit 36 in performing an ECC parity check for single or double errors in data passing along bus 32 from the main memory to the memory interface, by generating ECC parity bits for the data so that a comparison can be made with the ECC check bits coming from the main memory on the bus 38. Such comparison is performed by the EXCLUSIVE NOR gate 100 in each of the seven transfer circuits 96, and the syndrome bits resulting from the comparison can be used to perform single error correction and double error detection.

In Fig. 6, there is illustrated in detail the connection of the EDC circuit 30b in the data processing system 10. The EDC circuit 30b operates in a byte parity mode, and in particular, provides byte parity bits for data on bus 42 leaving the I/O processor 22 for the ALU 12, and Byte parity checking for the data on bus 42 entering the I/O processor 22 from the ALU 12. The connection of EDC circuit 30b was previously shown in general form in Fig. 1. Fig. 6 shows a portion of the I/O processor

22, which includes a bidirectional bit transfer circuit 110 for each of the 32 data bits D₀-D₃₁ on bus 42. The illustrated transfer circuit 110 transfers the data bit D₀ and includes a flip-flop 112 for receiving at its input D the data bit D₀ from the bus 42. The output Q of the flip-flop 112 is connected to the bus 50, and when a clocking signal, designated DATA OUT, is received at the input CLK of the flip-flop, indicating data is being transferred out of the ALU to peripheral units, the data bit D₀ is clocked into the flip-flop and presented to bus 50. The transfer circuit 110 further includes a flip-flop 114 having its input D connected for receiving the bit D₀ from the bus 50, and its inverted output

connected to an input of a NOR gate 116. The output of gate 116 is connected to bus 42. When an enabling signal

is received at a second input of the NOR gate 116, and a clocking signal DATA IN is received at the clocking input CLK of flip-flop 114, indicating data is being transferred into the ALU from the peripheral units, the data bit D₀ on bus 50 is transferred through flip-flop 114 and gate 116 to bus 42.

The bit transfer circuit 110 associated with each of the other data bits D₁-D₃₁ operates in the same fashion.

The operation of EDC circuit 30b for byte parity generating and checking has been described earlier with reference to Fig. 2. Briefly, when data is transferred from the I/O processor 22 to the ALU 12, the EDC circuit 30b will generate four inverted byte parity bits on the bus 43 for transmission with the

data, which will be used for a parity check at EDC circuit 30c. When, data is transferred along bus 42 from the ALU 12 to the I/O processor 22, the EDC circuit 30b will receive the inverted byte parity check bits

from the EDC circuit 30c by way of the bus 43, and will perform an internal parity check by comparing the byte parity check bits on bus 43 with the byte parity bits generated internally in response to the received data bits D₀-D₃₁. A signal BP ERROR is generated on one of the terminals E₀-E₃ if the comparison indicates a byte parity error.

The above described error detection and correction circuit has a further advantage in that it can be used in a system having a data bus larger than the data bus in the previously illustrated 32 bit system. Figs. 7A and 7B show a 64 bit EDC circuit 130 operating in an ECC mode and having two EDC circuits 130a and 130b, each of the same construction and design as the

EDC circuit 30 illustrated in Fig. 2. The circuit 130 generates eight inverted ECC parity bits

and performs SEC/DED for 64 bits of data, D ₀-D₆₃ from a data bus 132. A bus 134 carries ECC check bits C'₁-C'₈ to or from main memory.

As illustrated, the terminals E₁-E₇ are used in each of the circuits 130a and 130b and the

bits on those terminals are presented, along with the D₃₂ and D₄₈ data bits, to a 64 bit connection logic and error control circuit 140. The circuit 140 includes a bit comparison and transfer circuit 142 for each of the eight pairs of corresponding ECC parity and check bits associated with the 64 bits of data. Each of the circuits 142 include a flip-flop 144, an EXCLUSIVE NOR gate 146, and a NOR gate 148.

In Figs. 7A and 7B, only one of the circuits 142 is illustrated in detail. The flip-flop 144 in the illustrated circuit 142 receives the ECC check bit C'₁ from bus 134 at its input D, and if its clocking input CLK receives a clocking signal FETCH, indicating that data is being fetched from main memory and a check for error in such data is to be made, the ECC check bit C'₁ is clocked into the flip-flop and appears at the output Q. The output Q is connected to one input of the EXCLUSIVE NOR gate 146. The other input of the EXCLUSIVE NOR gate 146 receives the inverted ECC parity bit generated within the circuit 140, and the gate 146 performs a comparison and generates a syndrome bit S'₁. If data is being transferred into main memory on bus 132, the ECC parity bits generated by circuit 140 are delivered to bus 134 to be transferred with the data as ECC check bits. In such case, the NOR gate 148 in each bit transfer circuit 142 receives an inverted ECC parity bit generated by circuit 140 at one of its inputs. When the other input of NOR gate 148 receives an. enabling signal

indicating that data and check bits are to be stored in memory, each of the inverted

ECC parity bits is inverted and passed by one of the gates 148 to the bus 134 as a check bit.

The connection logic and error control circuit 140 also includes three EXCLUSIVE OR gates 154 which

receive the pairs of corresponding outputs of the circuits 130a and 130b and three EXCLUSIVE NOR gates 155 which receive the pairs of corresponding

outputs of the circuits 130a and 130b. The outputs of the gates 154 provide the inverted ECC parity bits and the outputs of the

gates 155 provide the inverted ECC parity bits and

As seen in Fig. 7B, an EXCLUSIVE OR gate 156 receives the data bits D₃₂ and D₄₈ and an EXCLUSIVE OR gate 158 receives the

bits from the circuit 130b. The outputs of the gates 156 and 158 are received by an EXCLUSIVE OR gate 160, which provides the signal at its output. The

signal and the signal

from circuit 130b are provided to an EXCLUSIVE OR gate

164, and the output of gate 164 is provided, along with the signal from circuit 130a to an EXCLUSIVE NOR gate

166. The output of gate 166 provides the signal

Figs. 8A and 8B show an H parity check matrix illustrating the modified Hamming code used in the 64 bit EDC circuit 130 of Figs. 7A and 7B. It can be seen from Figs. 8A and 8B that, with the exception of the rows associated with C'₆ and C'₈, the pattern of "ones" and "zeros" for the data bits D₃₂-D₆₃ is substantially repetitive of the pattern for bits D₀-D₃₁' and that both are similar to the pattern of the 32 bit matrix of Fig. 3. As in Fig. 3, the "ones" indicate that the corresponding data bits are logically combined to generate each ECC parity bit, and "zeros" indicate that they are not.

The EX VE OR gates 156, 158 and 160 in

Fig. 7B generate by EXCLUSIVE ORing ata s D₃₂,

D₄₈ and all the data bits asso

d with and from EDC circuit 130b. The result, is an EXCLUSIVE ORing of all the data bits D₃₂-D₆₃. This is illustrated in the H-matrix in Figs. 8A and 8B by the "ones" in the row associated with ECC parity bit C'₈.

The gates 164 and 166 generate by EXCLU

SIVE ORing all the data bits associated with

all the data bits associated with

from EDC circuit 130b and all the data bits associated with from EDC cir

cuit 130a. The result is the EXCLUSIVE ORing of the data bits corresponding to the "ones" in the row associated with ECC parity bit C'₆ in the matrix of Figs. 8A and 8B.

The EDC circuit 130 works much like the circuit arrangement in Fig. 5. Eight syndrome bits (S'₁- S'₈) are generated by the gates 146 in the bit transfer circuits 142, and the syndrome bits S'₁-S'₈ are provided to a decoder and logic circuit 170. The decoder circuit 170 has eight enable signal outputs, each for enabling one of eight memory interface chips (not shown), and a ninth output for indicating a double error. The syndrome bits S'₁-S'₃ are provided to each memory interface chip, and if the memory interface chip is enabled, will cause correction of one of the eight data bits associated with that memory interface chip.

It should be noted that the syndrome bit S'₈ provides an indication of whether a bit error has occurred in either the data bits D₁-D₃₁ or the data bits

D₃₂-D₆₃. This occurs because, as illustrated by the matrix in Figs. 8A and 8B, all of the bits D₃₂-D₆₃ are used in generating C'₈. Thus, if an error occurs in any of the data bits D₃₂-D₆₃, S'₈ will be at a "1". If an error occurs in any of the data bits D₀-D₃₁, S'₈ will be at a "0". It can thus be seen from the foregoing that the EDC circuit 30 can be used in a 32 bit data bus system and can be combined for use in systems having larger data busses, such as the illustrated 64 bit data bus system.

Claims

WHAT IS CLAIMED IS:

1. A data processing system (10) including: a data bus arranged to carry a plurality of data bits (D₀-D₃₁) from a first location to a second location in the system; error bit means (30) adapted to logically combine said data bits (D₀-D₃₁) to generate a plurality of error correction code check bits; and error control means (36) adapted to compare the generated check bits with a plurality of error correction code check bits associated with the data bits from the first location and thereby generate a plurality of syndrome bits

(S₁-S₇) identifying the bit position of any error in the data bits, characterized in that the system includes a plurality of identical data receiving circuits (13a-d) at the second location arranged to receive respective groups of said data bits, said syndrome bits including a first group of syndrome bits (S₁-S₇) identifying one of a plurality of said groups of data bits where the error has occurred and a second group of syndrome bits (S₁-S₃) identifying the bit position within one group of data bits where the error has occurred, said error control means (36) being adapted to generate an enabling signal in response to said first group of syndrome bits (S₁-S₇), the enabling signal being applied in operation to one of said data receiving circuits (13a-d), which include identical bit decoder means (92) arranged to receive said second group of syndrome bits (S₁-S₃) and thereby control the correction in the enabled data receiving circuit (13a-d) of the erroneous bit.

2. A data processing system according to claim 1, characterized in that a memory device (14) is provided at said first location, said plurality of data receiving circuits being formed by respective memory interface circuits (13a-d) adapted to transfer data bits to and from said memory device (14) and formed by respective integrated circuit chips.

3. A data processing system according to claim 2, characterized in that said groups of data bits form respective bytes of a data word formed by said data bits, said error control means (36) including byte decoder means (106) adapted to receive said first group of syndrome bits (S₁-S₇) and provide said enabling signal in response thereto.

4. A data processing system according to claim 3, characterized in that said plurality of data bits is formed by thirty-two data bits (D₀-D₃₁), in that said error control means (36) receives seven generated check bits and seven check bits associated with the data bits from the second location and generates seven syndrome bits (S₁-S₇), in that each of said bytes is formed by eight data bits, and in that said second group of syndrome bits is formed by three syndrome bits (S₁-S₃).

5. A data processing system according to claim 4, characterized in that said memory interface circuits (13a-d) include respective inverting means (86) adapted to invert a data bit applied thereto in accordance with an output from the respective bit decoder means (92).

6. A data processing system according to claim 3, characterized in that said error bit means (30) is further adapted to logically combine the data bits in the respective bytes to form respective byte parity bits (B₀-B₃).

7. A data processing system according to claim 6, characterized in that said error bit means (30) includes selection means (70, 76) adapted to selectively control the production of said error correction code check bits and said byte parity bits (B₀-B₃).

8. A data processing system according to claim 7, characterized in that said bit error means (30) includes comparison means adapted to compare said byte parity bits with received byte parity bits whereby a byte including an erroneous bit may be identified.

9. A data processing system according to claim 1, characterized in that said error bit means (30) includes a pair of error bit circuits (130a, 130b), said data bits being arranged in a word of eight bytes, each of said error bit circuits (130a, 130b), being arranged to receive four bytes of data bits and to generate seven error correction code check bits.

10. A data processing system according to claim 9, characterized in that said error means (130) includes combining means (154, 155, 156, 158, 160, 164, 166) adapted to combine the seven error correction code bits generated by said pair of error bit circuits (130a, 130b) to provide eight error correction code check bits.