UST955008I4 - Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate - Google Patents
Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate Download PDFInfo
- Publication number
- UST955008I4 UST955008I4 US05/693,385 US69338576A UST955008I4 US T955008 I4 UST955008 I4 US T955008I4 US 69338576 A US69338576 A US 69338576A US T955008 I4 UST955008 I4 US T955008I4
- Authority
- US
- United States
- Prior art keywords
- semiconductor element
- base substrate
- structure including
- flip chip
- silicon semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
A semiconductor device and carrier assembly package having a silicon integrated circuit semiconductor device provided with at least three raised electrical contacts on a first surface, a device support substrate of Si3 N4 provided with a conductive metallurgy pattern on at least one surface, the conductive pattern including an electrical contact configuration matching the raised electrical contacts on the device, metallurgical bonds between the raised electrical contacts on the device and the electrical contact pattern on the support substrate, and an electrically conductive means for electrically connecting elements of the conductive metallurgy pattern to coacting elements off the support substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/693,385 UST955008I4 (en) | 1974-08-19 | 1976-06-07 | Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49848774A | 1974-08-19 | 1974-08-19 | |
US05/693,385 UST955008I4 (en) | 1974-08-19 | 1976-06-07 | Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US49848774A Continuation | 1974-08-19 | 1974-08-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
UST955008I4 true UST955008I4 (en) | 1977-02-01 |
Family
ID=27052844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US05/693,385 Pending UST955008I4 (en) | 1974-08-19 | 1976-06-07 | Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate |
Country Status (1)
Country | Link |
---|---|
US (1) | UST955008I4 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0218438A2 (en) * | 1985-09-30 | 1987-04-15 | Mcnc | Apparatus for mounting a semiconductor chip and making electrical connections thereto |
US5368217A (en) * | 1993-08-25 | 1994-11-29 | Microelectronics And Computer Technology Corporation | High force compression flip chip bonding method and system |
US5379191A (en) * | 1991-02-26 | 1995-01-03 | Microelectronics And Computer Technology Corporation | Compact adapter package providing peripheral to area translation for an integrated circuit chip |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5682061A (en) * | 1990-09-24 | 1997-10-28 | Tessera, Inc. | Component for connecting a semiconductor chip to a substrate |
US6133627A (en) * | 1990-09-24 | 2000-10-17 | Tessera, Inc. | Semiconductor chip package with center contacts |
US20010030370A1 (en) * | 1990-09-24 | 2001-10-18 | Khandros Igor Y. | Microelectronic assembly having encapsulated wire bonding leads |
US20020155728A1 (en) * | 1990-09-24 | 2002-10-24 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US20050045697A1 (en) * | 2003-08-26 | 2005-03-03 | Lacap Efren M. | Wafer-level chip scale package |
-
1976
- 1976-06-07 US US05/693,385 patent/UST955008I4/en active Pending
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0218438A2 (en) * | 1985-09-30 | 1987-04-15 | Mcnc | Apparatus for mounting a semiconductor chip and making electrical connections thereto |
US4774630A (en) * | 1985-09-30 | 1988-09-27 | Microelectronics Center Of North Carolina | Apparatus for mounting a semiconductor chip and making electrical connections thereto |
EP0218438A3 (en) * | 1985-09-30 | 1989-03-01 | Mcnc | Apparatus for mounting a semiconductor chip and making electrical connections thereto |
US20010030370A1 (en) * | 1990-09-24 | 2001-10-18 | Khandros Igor Y. | Microelectronic assembly having encapsulated wire bonding leads |
US6433419B2 (en) | 1990-09-24 | 2002-08-13 | Tessera, Inc. | Face-up semiconductor chip assemblies |
US7291910B2 (en) | 1990-09-24 | 2007-11-06 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5682061A (en) * | 1990-09-24 | 1997-10-28 | Tessera, Inc. | Component for connecting a semiconductor chip to a substrate |
US5685885A (en) * | 1990-09-24 | 1997-11-11 | Tessera, Inc. | Wafer-scale techniques for fabrication of semiconductor chip assemblies |
US5848467A (en) * | 1990-09-24 | 1998-12-15 | Tessera, Inc. | Methods of making semiconductor chip assemblies |
US5950304A (en) * | 1990-09-24 | 1999-09-14 | Tessera, Inc. | Methods of making semiconductor chip assemblies |
US6133627A (en) * | 1990-09-24 | 2000-10-17 | Tessera, Inc. | Semiconductor chip package with center contacts |
US7198969B1 (en) | 1990-09-24 | 2007-04-03 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US6372527B1 (en) | 1990-09-24 | 2002-04-16 | Tessera, Inc. | Methods of making semiconductor chip assemblies |
US20050218495A1 (en) * | 1990-09-24 | 2005-10-06 | Tessera, Inc. | Microelectronic assembly having encapsulated wire bonding leads |
US6465893B1 (en) | 1990-09-24 | 2002-10-15 | Tessera, Inc. | Stacked chip assembly |
US20020155728A1 (en) * | 1990-09-24 | 2002-10-24 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US20050087855A1 (en) * | 1990-09-24 | 2005-04-28 | Tessera, Inc. | Microelectronic component and assembly having leads with offset portions |
US5379191A (en) * | 1991-02-26 | 1995-01-03 | Microelectronics And Computer Technology Corporation | Compact adapter package providing peripheral to area translation for an integrated circuit chip |
US5368217A (en) * | 1993-08-25 | 1994-11-29 | Microelectronics And Computer Technology Corporation | High force compression flip chip bonding method and system |
US5462217A (en) * | 1993-08-25 | 1995-10-31 | Microelectronics And Computer Technology Corporation | High force compression flip chip bonding system |
US20050045697A1 (en) * | 2003-08-26 | 2005-03-03 | Lacap Efren M. | Wafer-level chip scale package |
US8106516B1 (en) | 2003-08-26 | 2012-01-31 | Volterra Semiconductor Corporation | Wafer-level chip scale package |
US8710664B2 (en) | 2003-08-26 | 2014-04-29 | Volterra Semiconductor Corporation | Wafer-level chip scale package |
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