USRE44365E1 - Method of self-synchronization of configurable elements of a programmable module - Google Patents

Method of self-synchronization of configurable elements of a programmable module Download PDF

Info

Publication number
USRE44365E1
USRE44365E1 US12/909,061 US90906110A USRE44365E US RE44365 E1 USRE44365 E1 US RE44365E1 US 90906110 A US90906110 A US 90906110A US RE44365 E USRE44365 E US RE44365E
Authority
US
United States
Prior art keywords
configuration
runtime
information signal
select information
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US12/909,061
Inventor
Martin Vorbach
Robert M. Münch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Scientia Sol Mentis AG
Original Assignee
Martin Vorbach
Robert M. Münch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=46279486&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=USRE44365(E1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from DE19704728A external-priority patent/DE19704728A1/en
Application filed by Martin Vorbach, Robert M. Münch filed Critical Martin Vorbach
Priority to US12/909,061 priority Critical patent/USRE44365E1/en
Application granted granted Critical
Publication of USRE44365E1 publication Critical patent/USRE44365E1/en
Assigned to PACT XPP TECHNOLOGIES AG reassignment PACT XPP TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KRASS, MAREN, RICHTER, THOMAS
Adjusted expiration legal-status Critical
Assigned to SCIENTIA SOL MENTIS AG reassignment SCIENTIA SOL MENTIS AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PACT XPP TECHNOLOGIES AG
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • Synchronization of configurable elements of today's modules e.g., field programmable gate arrays (“FPGAs”), dynamically progammable gate arrays (“DPGAs”), etc.
  • FPGAs field programmable gate arrays
  • DPGAs dynamically progammable gate arrays
  • This type of time-controlled synchronization poses many problems because it is often not known in advance how much time is needed for a task until a final result is available.
  • Another problem with time-controlled synchronization is that the event on which the synchronization is based is not triggered by the element to be synchronized itself but rather by an independent element. In this case, two different elements are involved in the synchronization. This leads to a considerably higher administrative complexity.
  • European Patent No. 0 726 532 describes a method of controlling data flow in SIMD machines composed of several processors arranged as an array.
  • An instruction is sent to all processors which dynamically, selects the target processor of a data transfer.
  • the instruction is sent by a higher-level instance to all processors (broadcast instruction) and includes a destination field and a target field.
  • the destination field controls a unit in the processor element to dynamically determine the neighboring processor element to which the result is to be sent.
  • the operand register of another processor element in which another result is to be stored is dynamically selected with the target field.
  • the present invention relates to a method which permits self-synchronization of elements to be synchronized. Synchronization is neither implemented nor managed by a central entity. By shifting synchronization into each element, more synchronization tasks can also be performed simultaneously, because independent elements no longer interfere with one another when accessing the central synchronization entity.
  • each configurable element in a module, e.g., a data flow processor (“DFP”) or a DPGA, with a two- or multi-dimensionally arranged programmable cell structure, each configurable element can access the configuration and status register of other configurable elements over an interconnecting structure and thus can have an active influence on their function and operation.
  • a matrix of such cells is referred to below as a processing array (PA).
  • PA processing array
  • FIG. 1 shows how a loop construct can be implemented by using triggers, in accordance with an example embodiment of the present invention.
  • FIG. 2 shows how a comparison construct can be implemented by using multiple triggers, according to an example embodiment of the present invention.
  • FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them, according to an example embodiment of the present invention.
  • FIG. 4 shows the required expansions, according to an example embodiment of the present invention, in comparison with conventional FPGAs and DFPs.
  • FIGS. 5a-5d show an example of the selection of different functions of the configurable elements by, triggers, according to the present invention.
  • FIGS. 6 and 6a show an implementation of multiple configuration registers controlled by triggers for executing different functions, according to an example embodiment of the present invention.
  • FIGS. 7a and 7b shows an implementation of the method from FIG. 6 in microprocessors, according to an example embodiment of the present invention.
  • the present invention provides a module which is freely programmable during the running time and can also be reconfigured during the running time.
  • Configurable elements on the chip have one or more configuration registers for different functions. Both read and write access to these configuration registers is permitted. In the method described here, it is assumed that a configuration can be set in an element to be configured for the following information.
  • a cell is configured by a command which determines the function of the cell to be executed.
  • configuration data is entered to set the interconnection with other cells and the contents of the status register. After this operation, the cell is ready for operation.
  • each cell can have read or write access to all the configuration registers of another cell. Which of the many configuration registers is accessed by reading or writing is specified by the type of command with which the cell has been configured. Each command that can be executed by the cell exists in as many different types of addressing as there are different independent configuration registers in an element to be configured.
  • each cell can generate a quantity of trigger signals.
  • the trigger signals need not necessarily be transferred to the same target cell as the result of processing the configured command.
  • One trigger signal or a combination of multiple trigger signals triggers a certain action in the target cell or puts the cell in a certain state.
  • a description of the states is also to be found in the text below. The following are examples of trigger signals:
  • management data Due to the possibility of indicating in the processing cell into which register of the target cell the result is to be entered and which type of trigger signal is to be generated, a quantity of management data can be generated from a data stream.
  • This management data is not a result of the actual task to be processed by the chip, but instead it serves only the functions of management, synchronization, optimization, etc. of the internal state.
  • Each cell can assume the following states which are represented by suitable coding in the status register, for example:
  • each cell can assume an active administrative role.
  • all existing modules of this type have a central management entity which must always know and handle the entire state of the module.
  • each element to be configured received a RECONFIG trigger from an external entity to enter the “reconfigurable” state.
  • All configurable elements which are related by the interconnecting information represent a directional graph. Such a graph may have multiple roots (sources) and multiple leaves (targets).
  • the configurable elements are expanded so that they propagate an incoming RECONFIG trigger in the direction of either their outgoing registers, their ingoing registers or a combination thereof. Due to this propagation, all the configurable elements that are directly connected to the configurable element also receive the RECONFIG trigger.
  • a configuration (graph) can be brought completely into the “reconfigurable” state by sending a RECONFIG trigger to all the roots and propagating the RECONFIG trigger in the direction of the output registers.
  • the quantity of roots in a graph to which a RECONFIG trigger must be sent is considerably smaller than the total quantity of nodes in the graph. This greatly minimizes the complexity.
  • a RECONFIG trigger may also be sent to all leaves. In this case, the RECONFIG trigger is propagated in the direction of the input registers.
  • the configurable elements can receive an addition record to their status register, indicating whether or not an incoming RECONFIG trigger is to be propagated. This information is needed when two or more different graphs are connected at one or more points (i.e., they have a transition) and it is not desirable for one of the other graphs to enter the “reconfigurable” state. One or more configurable elements thus behave like a lock.
  • the status register can be expanded so that an additional entry indicates the direction in which an incoming RECONFIG trigger is to be relayed.
  • the method described here can be applied to all types of triggers and/or data. In this way, it is possible to establish an automatic distribution hierarchy needing very few access opportunities from the outside to set it in operation.
  • Triggers An especially complex variant of calling up various macros by a condition is presented below: In execution of a condition (IF COMP THEN A ELSE B; where COMP is a comparison, and A and B are operations to be executed), no GO and STOP triggers are generated. Instead, a trigger vector (TRIGV) is generated, indicating to which result the comparison COMP has led. The trigger vector can therefore assume the states “equal,” “greater” or “less.”
  • the vector is sent to a following cell which selects exactly a certain configuration register (corresponding to A or B) from a plurality of configuration registers on the basis of the state of the vector. What this achieves is that, depending on the result of the preceding comparison, another function is performed over the data. States such as “greater-equal,” “less-equal” and “equal-not equal” are triggered by writing the same configuration data to two configuration registers. For example, with “greater-equal” the configuration register “greater” and the configuration register “equal” are written with the same configuration word, while the configuration register “less” contains another configuration word.
  • any number n representing the state of the CASE may be relayed as trigger vectors TRIGV-m to the downstream cell(s).
  • n indicates the comparison within the CASE which was correct in analysis of the applied data.
  • n is relayed to the executing cells to select the corresponding function.
  • the cells need at least three configuration registers in the “greater/less/equal” case, the number of configuration registers must correspond exactly to at least the maximum value of n (max (n)) when using TRIGV-m.
  • TRIGV/TRIGV-m are sent to the first cell processing the data. In this cell, TRIGV/TRIGV-M are analyzed and the data is processed accordingly. TRIGV/TRIGV-m are relayed (propagated) together with the data to the downstream cells. They are propagated to all cells executing a certain function on the basis of the analysis (IF or CASE). Propagation is linked directly to propagation of data packages, i.e., propagation is synchronous with the data. TRIGV/TRIGV-m generated at time t are linked to data present at time t at first processing cells CELLS1 (see FIG. 5 : 0502 , 0505 , 0507 ).
  • TRIG/TRIG-V are propagated so that the vectors are applied to the second processing cells with the data at time t+1, and at time t+2 they are applied to the third processing cells, etc., until TRIG/TRIG-V and the data are present at time t+m to the (m ⁇ 1) th cells and at the same time to the last cells which depend on the comparison IF/CASE triggered by TRIG/TRIG-V.
  • a link is by no means such that the TRIG/TRIG-V generated at time t are linked to data applied to CELLS 1 at time t old ⁇ t.
  • Triggers In special cases, it is necessary to react to the absence of a trigger, i.e., a trigger state occurs, but no change in trigger vector is initiated. Appropriate and important information can also be transferred to the downstream cells in this case. For example, in a comparison of “greater,” “less,” “equal,” the trigger signal “equal” is not present and does not change when switching from the state “less” to the state “greater.” Nevertheless, the absence of “equal” does contain information, namely “not equal.”
  • a signal TRIGRDY indicating the presence of a trigger is added to trigger vector TRIGV representing states “equal,” “greater” and “less.” This is necessary because the state “not present” on one of the vectors does not provide any more information regarding the presence of a trigger per se.
  • TRIGRDY can be used as a handshake protocol between the transmitting cell and the receiving cell by having the receiving cell generate a TRIGACK as soon as it has analyzed the trigger vectors. Only after arrival of TRIGACK does the transmitting cell cancel the trigger state.
  • conditional jumps are no longer executed by the known method of branch prediction, i.e., prediction of a jump.
  • Speculative prediction of jumps introduced to increase processor performance calculated jumps in advance on the basis of speculative algorithms and had to reload the entire processor pipeline if the calculations were faulty, which led to a considerable loss of power.
  • a status flag one bit wide is assigned to each command, indicating whether the command is to be executed—or not. There may be any desired quantity of status flags.
  • Commands are assigned to status flags by a compiler during the translation of the code. The status flags are managed by comparison operations assigned to them at the time of execution and indicate the result of the respective comparison.
  • the command is then executed by the processor (if the status flag indicates “execute”) or the command is not executed and is replaced by an NOP (if the status flag indicates “not execute”).
  • NOP stands for “No OPERATION,” which means that the processor does not execute any operation in this cycle. Therefore, the cycle is lost for meaningful operations.
  • a modern microprocessor has several relatively independent processors.
  • the individual processors are each equipped with several command registers, with a command register of a processor of a microprocessor being synonymous with a configuration register according to conventional FPGA, DFP, etc. modules.
  • the respective active command register is selected
  • status vectors multibit status flags allocated to compare commands according to today's related art method.
  • Revised VLIW Command Set One special embodiment is possible through VLIW command sets. Thus, several possible commands depending on one comparison can be combined to give one command within one command word.
  • a VLIW word of any width is subdivided into any desired quantity of commands (codes). Each individual one of these codes is referenced by a trigger vector or a status vector. This means that one of the existing codes is selected from the VLIW word and processed during the running time.
  • the table illustrates a possible VLIW word with four codes referenced by a 2-bit trigger vector or a 2-bit status flag:
  • a status register and a configuration register are added to the configuration registers conventionally used in DFPs. Both registers are controlled by the PLU bus and have a connection to the state machine of the sequence control system of the respective cell.
  • the only part of the system bus relevant for the registers is the part that is interconnected to the PAE over the BM UNIT, i.e., the interface between the system buses and the PAE. Therefore, the bus is relayed from the BM UNIT to the registers where upstream multiplexers or upstream gates are responsible for switching between the PLU bus and the system bus relevant for the PAE.
  • the multiplexers or gates are switched so that they always switch the system bus relevant for the PAE through, except after resetting the module (RESET) or when the RECONFIG trigger is active.
  • Trigger Sources A configurable element can receive triggers from several sources at the same time. Due to this possibility, flexible semantics of the triggers can be achieved with the help of masking registers.
  • a PAE has multiple (max(n)) configuration registers.
  • Configuration State Machine and Multiplexer Downstream from the configuration registers is a multiplexer which selects one of the possible configurations.
  • the multiplexer is controlled by a separate state machine or a state machine integrated into the PAE state machine, controlling the multiplexer on the basis of incoming trigger vectors.
  • a configurable element may contain a masking register in which it is possible to set the trigger inputs to which a trigger signal must be applied, so that the conditions for an action of the configurable element are met.
  • a configurable element reacts not only to a trigger, but also to a set combination of triggers.
  • a configurable element can perform prioritization of simultaneously incoming triggers.
  • Incoming triggers are recognized on the basis of the TRIGRDY signal.
  • the trigger vectors are analyzed here according to configuration data also present in the configuration registers.
  • Trigger Handshake As soon as the trigger vectors have been analyzed, a TRIGACK is generated for confirmation of the trigger vector.
  • BM UNIT The BM UNIT is expanded so that it relays triggers coming from the bus to the sync unit and SM unit according to the configuration in M-PLUREG. Triggers generated by the EALU (e.g., comparator values “greater,” “less,” “equal,” 0 detectors, plus and minus signs, carry-overs, error states (division by 0, etc.), etc.) are relayed from the BM UNIT to the bus according to the wiring information in M-PLUREG.
  • EALU e.g., comparator values “greater,” “less,” “equal,” 0 detectors, plus and minus signs, carry-overs, error states (division by 0, etc.), etc.
  • the system bus i.e., the bus system between the cells (PAEs)
  • PAEs bus system between the cells
  • the system bus is expanded by the independent transfer of trigger vectors and trigger handshakes.
  • FIG. 1 shows how a loop construct can be implemented by using triggers.
  • a macro 0103 is to be executed 70 times.
  • One execution of the macro takes 26 clock cycles.
  • counter 0101 may be decremented by one increment only once in every 26 clock cycles.
  • One problem with freely programmable modules is that it is not always possible to guarantee that processing of macro 0103 will actually be concluded after 26 clock cycles. For example, a delay may occur due to the fact that a macro which is to supply the input data for macro 0103 may suddenly require 10 more clock cycles. For this reason, the cell in macro 0103 sends a trigger signal to counter 0101 , causing the result of the calculation to be sent to another macro. At the same time, processing of macro 0103 by the same cell is stopped. This cell “knows” exactly that the condition for termination of a calculation has been reached.
  • the trigger signal sent is a STEP trigger, causing counter 0101 to execute its configured function once.
  • the counter decrements its count by one and compares whether it has reached a value of 0. If this is not the case, a GO trigger is sent to macro 0103 .
  • This GO trigger signal causes macro 0103 to resume its function.
  • a trigger signal is sent to macro 0102 , where it triggers a function.
  • a very fine synchronization can be achieved due to this interaction of triggers.
  • FIG. 2 shows how a comparison construct can be implemented by using multiple triggers.
  • FIG. 2 corresponds to the basic idea of FIG. 1 .
  • the function in element 0202 is not a counter but a comparator.
  • Macro 0201 also sends a comparison value to comparator 0202 after each processing run.
  • different triggers are again driven to prompt an action in macros 0203 , for example.
  • the construct implemented in FIG. 2 corresponds to that of an IF query in a programming language.
  • FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them.
  • comparators 0301 , 0302 are used here to implement construction of an IF-ELSE-ELSE construct (or multiple choice). Due to the use of a wide variety of types of triggers and connections of these triggers to macros 0303 , 0304 , very complex sequences can be implemented easily.
  • FIG. 4 shows an example of some of the differences between the present invention and, for example, conventional FPGAs and DFPs.
  • Additional configuration register 0401 and additional status register 0402 are connected to the SM UNIT over bus 0407 .
  • Registers 0401 , 0402 , F-PLUREG and M-PLUREG are connected to a gate 0403 by an internal bus 0206 .
  • this gate connects internal bus 0406 to PLU bus 0405 to permit configuration by the PLU or to the BM UNIT by a bus 0408 .
  • the BM UNIT relays the data to the O-REG or to addressed register 0401 , 0402 , F-PLUREG or M-PLUREG.
  • BM UNIT 0411 sends trigger signals over 0415 to SYNC UNIT 0412 .
  • states generated by the SYNC UNIT or the STATE MACHINE can be relayed to the BM UNIT over 0415 .
  • the trigger signals transmitted by the BM UNIT to bus 0404 can be used there as STEP/STOP/GO triggers, RECONFIG triggers or for selecting a configuration register, depending on the configuration of the configurable elements to be analyzed. Which function a generated trigger will execute in the configurable elements to be analyzed is determined by interconnection 0404 and the configuration of the respective configurable element. One and the same trigger may have different functions with different configurable elements.
  • 0416 is the result output of R-REGsft to bus system 0404 and the following configurable elements.
  • FIG. 5 shows the time response between generated triggers and the configuration registers selected by the triggers as an example.
  • 0501 generates by comparison a trigger vector TRIGV, which can assume values “equal,” “greater,” or “less.”
  • Configurable elements 0502 - 0504 process data independently of comparison 0501 . Processing depends on comparison values “equal,” “greater” and “less.” Processing is pipelined, i.e., a data word is modified first by 0502 , then by 0503 and finally by 0504 .
  • 0505 also processes data as a function of 0501 . However, this is limited to the dependence on the comparison values “less”; “greater” and “equal” cause the same function to be carried out.
  • 0506 is connected downstream in pipeline 0505 .
  • 0506 reacts differently to “equal,” “greater” and “less” (see 0503 ).
  • 0507 also depends on 0501 , but a distinction is made between the values “equal” and “not equal (less or greater).”
  • This embodiment begins at time t ( FIG. 5a ) and ends at time t+3. If the data passes through one of pipelines 0502 , 0503 , 0504 or 0505 , 0506 , it is delayed by one clock cycle in each execution in one of macros 0502 - 0506 . Longer and especially different delays may also occur. Since there is a handshake mechanism between the data and trigger signals for automatic synchronization (according to the related art or this application (TRIGACK/TRIGRDY)), this case need not be discussed separately.
  • FIGS. 5a through 5d show the sequence of three clock cycles t through t+2.
  • the trigger vectors (i.e., the results of the comparison) generated by 0501 look as follows over t:
  • FIG. 6 shows the integration of several configuration registers into one configurable element.
  • a control unit 0601 (which may also be designed as a state machine) receives signals TRIGV and TRIGRDY over bus system 0411 . Depending on TRIGV, the control unit switches one of the configuration registers over multiplexer 0602 to bus system 0401 leading to the control mechanisms of the configurable element.
  • 0601 For synchronization of the trigger signals with the internal sequences of the configurable element, 0601 has a synchronization output leading to synchronization unit 0412 or to state machine 0413 .
  • 0601 For synchronization of the trigger sources, 0601 generates handshake signal TRIGACK after processing the incoming trigger.
  • each configuration register 0409 is assigned to one TRIGV of the type “equal,” “greater,” “less.” If other operations are executed with each type of trigger, then each configuration register is occupied differently. For example, if a distinction is made only between “equal” and “not equal” then the configuration registers are occupied equally for the types “less” and “greater,” namely with the configuration for “not equal.” The configuration register for “equal” is occupied differently. This means that the comparison can be made more specific on the basis of the occupancy of the configuration registers, each configurable element being able to design this specification differently.
  • TRIGV is relayed together with the result over register 0603 to the downstream configurable elements to permit pipelining according to FIGS. 5a-d .
  • the register and the handshake signals are controlled by 0412 or 0413 .
  • Trigger information together with the result from R-REGsft or with a time offset, i.e., before the result, can be sent over interface 0416 to downstream configurable elements.
  • FIG. 6a shows a corresponding timing (based on sequences conventional for DFP).
  • Trigger vectors 0615 are generated at rising edge 0613 of module clock 0614 .
  • Triggers are analyzed in the configurable elements at trailing edge 0612 .
  • Data is phase shifted, i.e., released at 0612 and entered at 0613 .
  • the trigger vectors are transferred over the bus and data is calculated during 0610 .
  • Data is transferred over the bus and triggers are calculated during 0611 , or configuration registers of the configurable elements are selected according to data stored at 0613 and the configuration is set accordingly.
  • FIG. 7a shows the management of jumps according to the predicate/NOP method of the related art.
  • an entry is made in predicate register 0704 .
  • This entry is queried during the execution of commands, determining whether a command is being executed (the command is inside the code sequence addressed by the conditional jump) or is replaced by an NOP (the command is in a different code sequence from that addressed by the conditional jump).
  • the command is in command register 0701 .
  • the predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued at the compile time of the program of the compiler. Allocation information 0707 is allocated to the command entered into the command register, so that a unique entry is referenced by the respective command.
  • 0703 selects whether the command from 0701 or an NOP is to be executed. In execution of an NOP, one clock cycle is lost. 0703 has a symbolic character, because executing unit 0702 could also in principle be controlled directly by 0704 .
  • n command registers ( 0701 : Func 1 . . . Func n).
  • the command register to be addressed i.e., the result of the comparison
  • Respective entry 0708 in 0706 is so wide that all possible command registers of an executing unit 0702 can be addressed by it, which means that the width of an entry is log 2 (n) with n command registers.
  • the predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued by the compiler at the compile time of the program.
  • Allocation information 0707 is allocated to the quantity of commands entered into the command registers, so that an unambiguous entry is referenced by the respective commands.
  • the multiplexer selects which command register supplies the code for the instantaneous execution.
  • BM UNIT Unit for switching data to the bus systems outside the PAE. Switching is done over multiplexers for the data inputs and gates for the data outputs. OACK lines are implemented as open collector drivers.
  • the BM UNIT is controlled by the M-PLUREG.
  • Data receiver The unit(s) that process(es) the results of the PAE further.
  • Data transmitter The unit(s) that make(s) available the data for the PAE as operands.
  • a data word consists of a bit series of any desired length. This bit series represents a processing unit for a system. Commands for processors or similar modules as well as pure data can be coded in a data word.
  • DFP Data flow processor according to German Patent/Unexamined Patent No. 44 16 881.
  • DPGA Dynamically configurable FPGAs. Related art.
  • EALU Expanded arithmetic logic unit. ALU which has been expanded by special functions which are needed or appropriate for operation of a data processing system according to German Patent No. 441 16 881 A1. These are counters in particular.
  • Event An event can be analyzed by a hardware element of any type suitable for use and can prompt a conditional action as a reaction to this analysis. Events thus include, for example:
  • FPGA Programmable logic module. Related art.
  • F-PLUREG Register in which the function of the PAE is set. Likewise, the one shot and sleep mode are also set. The register is written by the PLU.
  • H level Logic 1 level, depending on the technology used.
  • Configurable element A configurable element is a unit of a logic module which can be set for a special function by a configuration word. Configurable elements are thus all types of RAM cells, multiplexers, arithmetic logic units, registers and all types of internal and external network writing, etc.
  • Configurable cell See logic cells.
  • Configuration data Any quantity of configuration words.
  • the configuration memory contains one or more configuration words.
  • Configuration word A configuration word consists of a bit series of any desired length. This bit series represents a valid setting for the element to be configured, so that a functional unit is obtained.
  • Load logic Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.
  • Logic cells Configurable cells used in DFPs, FPGAs, DPGAs, fulfilling simple logic or arithmetic functions according to their configuration.
  • L level Logic 0 level, depending on the technology used.
  • M-PLUREG Register in which the interconnection of the PAE is set. The register is written by the PLU.
  • O-REG Operand register for storing the operands of the EALU. Permits independence of the PAE of the data transmitters in time and function. This simplifies the transfer of data because it can take place in an asynchronous or package-oriented manner. At the same time, the possibility of reconfiguring the data transmitters independently of the PAE or reconfiguring the PAE independently of the data transmitters is created.
  • PLU Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.
  • Propagate Controlled relaying of a received signal.
  • RECONFIG Reconfigurable state of a PAE.
  • RECONFIG trigger Setting a PAE in the reconfigurable state.
  • SM UNIT State machine UNIT. State machine controlling the EALU.
  • a switching table is a ring memory which is addressed by a control.
  • the entries in a switching table may accommodate any desired configuration words.
  • the control can execute commands.
  • the switching table reacts to trigger signals and reconfigures configurable elements on the basis of an entry in a ring memory.
  • Synchronization signals Status signals generated by a configurable element or a processor and relayed to other configurable elements or processors to control and synchronize the data processing. It is also possible to return a synchronization signal with a time lag (stored) to one and the same configurable element or processor.
  • TRIGACK/TRIGRDY Handshake of the triggers.
  • Trigger Synonymous with synchronization signals.
  • a processing cycle describes the period of time needed by a unit to go from one defined and/or valid state into the next defined and/or valid state.
  • VLIW Very large instruction word. Coding of microprocessors, prior art method.

Abstract

A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional reissue of U.S. Reissue patent application Ser. No. 12/109,280, filed on Apr. 24, 2008, which is a reissue application of U.S. patent application Ser. No. 10/379,403, filed on Mar. 4, 2003, now U.S. Pat. No. 7,036,036, which is a continuation of U.S. patent application Ser. No. 09/369,653, filed Aug. 6, 1999, now U.S. Pat. No. 6,542,998, which is a continuation-in-part of PCT/DE98/00334, filed on Feb. 7, 1998 and is a continuation-in-part of U.S. patent application Ser. No. 08/946,812, filed on Oct. 8, 1997, now U.S. Pat. No. 6,081,903, and claims the benefit of the priority date dates of these cases under 35 U.S.C. §120, each of which is expressly incorporated herein by reference in its entirety. This application also claims the benefit, under 35 U.S.C. §119, of the priority date of German Application No. DE 19704728.9, filed on Feb. 8, 1997, under 35 U.S.C. §119, which is expressly incorporated herein by reference in its entirety. Further, more than one reissue application of U.S. Pat. No. 7,036,036 has been filed. Specifically, the reissue applications are application Ser. No. 12/109,280, application Ser. No. 12/909,061, application Ser. No. 12/909,150, and application Ser. No. 12/909,203, the latter three of which were all filed on Oct. 21, 2010 as divisional reissue applications of application Ser. No. 12/109,280.
BACKGROUND INFORMATION
Synchronization of configurable elements of today's modules, e.g., field programmable gate arrays (“FPGAs”), dynamically progammable gate arrays (“DPGAs”), etc., is usually accomplished using the clock of the module. This type of time-controlled synchronization poses many problems because it is often not known in advance how much time is needed for a task until a final result is available. Another problem with time-controlled synchronization is that the event on which the synchronization is based is not triggered by the element to be synchronized itself but rather by an independent element. In this case, two different elements are involved in the synchronization. This leads to a considerably higher administrative complexity.
European Patent No. 0 726 532 describes a method of controlling data flow in SIMD machines composed of several processors arranged as an array. An instruction is sent to all processors which dynamically, selects the target processor of a data transfer. The instruction is sent by a higher-level instance to all processors (broadcast instruction) and includes a destination field and a target field. The destination field controls a unit in the processor element to dynamically determine the neighboring processor element to which the result is to be sent. The operand register of another processor element in which another result is to be stored is dynamically selected with the target field.
SUMMARY
The present invention relates to a method which permits self-synchronization of elements to be synchronized. Synchronization is neither implemented nor managed by a central entity. By shifting synchronization into each element, more synchronization tasks can also be performed simultaneously, because independent elements no longer interfere with one another when accessing the central synchronization entity.
In accordance with an example embodiment of the present invention, in a module, e.g., a data flow processor (“DFP”) or a DPGA, with a two- or multi-dimensionally arranged programmable cell structure, each configurable element can access the configuration and status register of other configurable elements over an interconnecting structure and thus can have an active influence on their function and operation. A matrix of such cells is referred to below as a processing array (PA). The configuration can thus be accomplished by a load logic from the PA in addition to the usual method.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows how a loop construct can be implemented by using triggers, in accordance with an example embodiment of the present invention.
FIG. 2 shows how a comparison construct can be implemented by using multiple triggers, according to an example embodiment of the present invention.
FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them, according to an example embodiment of the present invention.
FIG. 4 shows the required expansions, according to an example embodiment of the present invention, in comparison with conventional FPGAs and DFPs.
FIGS. 5a-5d show an example of the selection of different functions of the configurable elements by, triggers, according to the present invention.
FIGS. 6 and 6a show an implementation of multiple configuration registers controlled by triggers for executing different functions, according to an example embodiment of the present invention.
FIGS. 7a and 7b shows an implementation of the method from FIG. 6 in microprocessors, according to an example embodiment of the present invention.
DETAILED DESCRIPTION
The present invention provides a module which is freely programmable during the running time and can also be reconfigured during the running time. Configurable elements on the chip have one or more configuration registers for different functions. Both read and write access to these configuration registers is permitted. In the method described here, it is assumed that a configuration can be set in an element to be configured for the following information.
    • Interconnection register. In this register, the type of connection to other cells is set.
    • Command register. The function of the configurable element to be executed is entered in this register.
    • Status register. The cell stores its instantaneous status in this register. This status provides other elements of the module with information regarding which processing cycle the cell is in.
A cell is configured by a command which determines the function of the cell to be executed. In addition, configuration data is entered to set the interconnection with other cells and the contents of the status register. After this operation, the cell is ready for operation.
To permit flexible and dynamic cooperation of many cells, each cell can have read or write access to all the configuration registers of another cell. Which of the many configuration registers is accessed by reading or writing is specified by the type of command with which the cell has been configured. Each command that can be executed by the cell exists in as many different types of addressing as there are different independent configuration registers in an element to be configured.
Example: A cell has the configuration register described above (interconnection, command and status) and is to execute the command ADD which performs an addition. It is then possible to select through the various types of ADD command where the result of this function is to be transferred.
  • ADD-A. The result is transferred to operand register A of the target cell.
  • ADD-B. The result is transferred to operand register B of the target cell.
  • ADD-V. The result is transferred to the interconnecting register of the target cell.
  • ADD-S. The result is transferred to the status register of the target cell.
  • ADD-C. The result is transferred to the command register of the target cell.
Control and Synchronization Trigger: In addition to the result, each cell can generate a quantity of trigger signals. The trigger signals need not necessarily be transferred to the same target cell as the result of processing the configured command. One trigger signal or a combination of multiple trigger signals triggers a certain action in the target cell or puts the cell in a certain state. A description of the states is also to be found in the text below. The following are examples of trigger signals:
    • GO trigger. The GO trigger puts the target cell in the READY state.
    • RECONFIG trigger. The RECONFIG trigger puts the target cell in the RECONFIG state, so the cell can be reprogrammed. This trigger is very useful, especially in conjunction with switching tables. If it is assumed that the data to be processed is loaded into the operand register at the rising edge of the clock pulse, processed in the period of the H level and written to the output register at the trailing edge, then the cell can be reconfigured at the trailing edge. The new configuration data is written to the command register at the trailing edge. The period of the L level is sufficient to conclude the reconfiguration successfully.
    • STEP trigger. The STEP trigger initiates unique execution of the configured command in the target cell in the WAIT state.
    • STOP trigger. The STOP trigger stops the target cell by putting the cell in the STOP state.
Due to the possibility of indicating in the processing cell into which register of the target cell the result is to be entered and which type of trigger signal is to be generated, a quantity of management data can be generated from a data stream. This management data is not a result of the actual task to be processed by the chip, but instead it serves only the functions of management, synchronization, optimization, etc. of the internal state.
Each cell can assume the following states which are represented by suitable coding in the status register, for example:
    • READY. The cell is configured with a valid command and can process data. Processing takes place with each clock cycle. The data is entered into the register of the target cell on the basis of the type of addressing of the cell sending the data.
    • WAIT. The cell has been configured with a valid command and can process data. Processing takes place on the basis of a trigger signal which can be generated by other elements of the module. The data is entered into the register of the target cell on the basis of the type of addressing of the cell sending the data.
    • CONFIG. This cell is not configured with a valid command. The data package sent to the cell with the next clock cycle is entered into the command register. The data package is entered into the command register in any case, regardless of which type of addressing was used by the cell sending the data.
    • CONFIG-WAIT. This cell is not configured with a valid command. A data package is entered with the next trigger signal which can be generated by other elements of the module and is written to the command register. The data package is entered into the command register in any case, regardless of which type of addressing was used by the cell sending the data.
    • RECONFIG. The cell is configured with a valid command, but it does not process any additional data, nor does it accept data. The cell can be reconfigured by another element of the module.
    • STOP. The cell is configured with a valid command, but it is not processing any data at the moment. The data is accepted by the cell (transferred to the input register) but is not processed further.
Due to these various states and the possibility of read and write access to the various registers of a cell, each cell can assume an active administrative role. In contrast with that, all existing modules of this type have a central management entity which must always know and handle the entire state of the module.
To achieve greater flexibility, there is another class of commands which change types after the first execution. Based on the example of the ADD command, a command is then as follows:
    • ADD-C-A. The result of the ADD function is written to the command register of the target cell with the first execution of the command. With each additional execution, the result is written to operand register A.
This possibility can be expanded as desired, so that even commands of the type ADD-C-V-A-C- . . . -B are conceivable. Each command can assume all permutated combinations of the various types of addressing and triggers.
Reconfiguration Control by RECONFIG Trigger: In the previous method, each element to be configured received a RECONFIG trigger from an external entity to enter the “reconfigurable” state. This had the disadvantage that distribution of the RECONFIG trigger necessitated a considerable interconnection and configuration expense: Due to the structure of the interconnection, this disadvantage can be eliminated. All configurable elements which are related by the interconnecting information represent a directional graph. Such a graph may have multiple roots (sources) and multiple leaves (targets). The configurable elements are expanded so that they propagate an incoming RECONFIG trigger in the direction of either their outgoing registers, their ingoing registers or a combination thereof. Due to this propagation, all the configurable elements that are directly connected to the configurable element also receive the RECONFIG trigger.
A configuration (graph) can be brought completely into the “reconfigurable” state by sending a RECONFIG trigger to all the roots and propagating the RECONFIG trigger in the direction of the output registers. The quantity of roots in a graph to which a RECONFIG trigger must be sent is considerably smaller than the total quantity of nodes in the graph. This greatly minimizes the complexity. Of course, a RECONFIG trigger may also be sent to all leaves. In this case, the RECONFIG trigger is propagated in the direction of the input registers.
Due to the use of both options or a combination of both methods, a minimum quantity of configurable elements to which a RECONFIG trigger must be sent can be calculated.
The configurable elements can receive an addition record to their status register, indicating whether or not an incoming RECONFIG trigger is to be propagated. This information is needed when two or more different graphs are connected at one or more points (i.e., they have a transition) and it is not desirable for one of the other graphs to enter the “reconfigurable” state. One or more configurable elements thus behave like a lock.
In addition, the status register can be expanded so that an additional entry indicates the direction in which an incoming RECONFIG trigger is to be relayed.
The method described here can be applied to all types of triggers and/or data. In this way, it is possible to establish an automatic distribution hierarchy needing very few access opportunities from the outside to set it in operation.
Implementation of Multiple Functions Simultaneously in the Same Configurable Elements
Basic Function and Required Triggers: An especially complex variant of calling up various macros by a condition is presented below: In execution of a condition (IF COMP THEN A ELSE B; where COMP is a comparison, and A and B are operations to be executed), no GO and STOP triggers are generated. Instead, a trigger vector (TRIGV) is generated, indicating to which result the comparison COMP has led. The trigger vector can therefore assume the states “equal,” “greater” or “less.”
The vector is sent to a following cell which selects exactly a certain configuration register (corresponding to A or B) from a plurality of configuration registers on the basis of the state of the vector. What this achieves is that, depending on the result of the preceding comparison, another function is performed over the data. States such as “greater-equal,” “less-equal” and “equal-not equal” are triggered by writing the same configuration data to two configuration registers. For example, with “greater-equal” the configuration register “greater” and the configuration register “equal” are written with the same configuration word, while the configuration register “less” contains another configuration word.
In implementating trigger vectors TRIGV, no restriction to the states “greater,” “less” and “equal” is necessary. To analyze large “CASE . . . OF” constructs, any number n representing the state of the CASE may be relayed as trigger vectors TRIGV-m to the downstream cell(s). In other words, n indicates the comparison within the CASE which was correct in analysis of the applied data. For implementation of the function assigned to the comparison within the CASE, n is relayed to the executing cells to select the corresponding function. Although the cells need at least three configuration registers in the “greater/less/equal” case, the number of configuration registers must correspond exactly to at least the maximum value of n (max (n)) when using TRIGV-m.
Propagation of the Required Function by Triggers: TRIGV/TRIGV-m are sent to the first cell processing the data. In this cell, TRIGV/TRIGV-M are analyzed and the data is processed accordingly. TRIGV/TRIGV-m are relayed (propagated) together with the data to the downstream cells. They are propagated to all cells executing a certain function on the basis of the analysis (IF or CASE). Propagation is linked directly to propagation of data packages, i.e., propagation is synchronous with the data. TRIGV/TRIGV-m generated at time t are linked to data present at time t at first processing cells CELLS1 (see FIG. 5: 0502, 0505, 0507). TRIG/TRIG-V are propagated so that the vectors are applied to the second processing cells with the data at time t+1, and at time t+2 they are applied to the third processing cells, etc., until TRIG/TRIG-V and the data are present at time t+m to the (m−1)th cells and at the same time to the last cells which depend on the comparison IF/CASE triggered by TRIG/TRIG-V.
A link is by no means such that the TRIG/TRIG-V generated at time t are linked to data applied to CELLS1 at time told<t.
Reacting to the Presence or Absence of Triggers: In special cases, it is necessary to react to the absence of a trigger, i.e., a trigger state occurs, but no change in trigger vector is initiated. Appropriate and important information can also be transferred to the downstream cells in this case. For example, in a comparison of “greater,” “less,” “equal,” the trigger signal “equal” is not present and does not change when switching from the state “less” to the state “greater.” Nevertheless, the absence of “equal” does contain information, namely “not equal.”
To be able to react to both states “present” and “not present,” an entry in the configuration register of the cell is added, indicating which of the states is to be reacted to.
Furthermore, a signal TRIGRDY indicating the presence of a trigger is added to trigger vector TRIGV representing states “equal,” “greater” and “less.” This is necessary because the state “not present” on one of the vectors does not provide any more information regarding the presence of a trigger per se.
TRIGRDY can be used as a handshake protocol between the transmitting cell and the receiving cell by having the receiving cell generate a TRIGACK as soon as it has analyzed the trigger vectors. Only after arrival of TRIGACK does the transmitting cell cancel the trigger state.
On the basis of an entry into the configuration register, a determination is made as to whether to wait for receipt of a TRIGACK or whether the trigger channel is to proceed unsynchronized when a trigger vector is sent out.
Use in Microprocessors
In microprocessors of the most recent architecture, conditional jumps are no longer executed by the known method of branch prediction, i.e., prediction of a jump. Speculative prediction of jumps introduced to increase processor performance calculated jumps in advance on the basis of speculative algorithms and had to reload the entire processor pipeline if the calculations were faulty, which led to a considerable loss of power.
To eliminate these losses, the new predicate/NOP method was introduced. A status flag one bit wide is assigned to each command, indicating whether the command is to be executed—or not. There may be any desired quantity of status flags. Commands are assigned to status flags by a compiler during the translation of the code. The status flags are managed by comparison operations assigned to them at the time of execution and indicate the result of the respective comparison.
Depending on the state of a status flag assigned to a command, the command is then executed by the processor (if the status flag indicates “execute”) or the command is not executed and is replaced by an NOP (if the status flag indicates “not execute”). NOP stands for “No OPERATION,” which means that the processor does not execute any operation in this cycle. Therefore, the cycle is lost for meaningful operations.
Two options are proposed for optimizing the cycle loss:
Multiple Command Registers per Computer Unit: A modern microprocessor has several relatively independent processors.
According to the trigger principle presented here, the individual processors are each equipped with several command registers, with a command register of a processor of a microprocessor being synonymous with a configuration register according to conventional FPGA, DFP, etc. modules. The respective active command register is selected
a) on the basis of trigger vectors generated by other processors on the basis of comparisons,
b) on the basis of multibit status flags (hereinafter referred to as status vectors) allocated to compare commands according to today's related art method.
Revised VLIW Command Set: One special embodiment is possible through VLIW command sets. Thus, several possible commands depending on one comparison can be combined to give one command within one command word. A VLIW word of any width is subdivided into any desired quantity of commands (codes). Each individual one of these codes is referenced by a trigger vector or a status vector. This means that one of the existing codes is selected from the VLIW word and processed during the running time.
The table illustrates a possible VLIW word with four codes referenced by a 2-bit trigger vector or a 2-bit status flag:
VLIW Command Word:
Code 0 Code 1 Code 2 Code 3
Assignment:
Trigger Vector/Status Flag:
00 01 10 11
Expansion of Hardware in Comparison with Conventional FPGAs and DFPs.
Additional Registers: A status register and a configuration register are added to the configuration registers conventionally used in DFPs. Both registers are controlled by the PLU bus and have a connection to the state machine of the sequence control system of the respective cell.
Change in PLU Bus: The configurable registers M-/F-PLUREG in FPGAs and DFPs are managed exclusively over the PLU bus, which represents the connection to the load logic. To guarantee the function according to the present invention, an additional access option must be possible through the normal system bus between the cells. The same thing is true for the new status register and configuration register.
The only part of the system bus relevant for the registers is the part that is interconnected to the PAE over the BM UNIT, i.e., the interface between the system buses and the PAE. Therefore, the bus is relayed from the BM UNIT to the registers where upstream multiplexers or upstream gates are responsible for switching between the PLU bus and the system bus relevant for the PAE. The multiplexers or gates are switched so that they always switch the system bus relevant for the PAE through, except after resetting the module (RESET) or when the RECONFIG trigger is active.
Expansions of Configurable Elements (PAEs) with Respect to Conventional FPGAs and DFPs: Trigger Sources: A configurable element can receive triggers from several sources at the same time. Due to this possibility, flexible semantics of the triggers can be achieved with the help of masking registers.
Multiple Configuration Registers: Instead of one configuration register, a PAE has multiple (max(n)) configuration registers.
Configuration State Machine and Multiplexer: Downstream from the configuration registers is a multiplexer which selects one of the possible configurations.
The multiplexer is controlled by a separate state machine or a state machine integrated into the PAE state machine, controlling the multiplexer on the basis of incoming trigger vectors.
Trigger Analysis and Configuration: A configurable element may contain a masking register in which it is possible to set the trigger inputs to which a trigger signal must be applied, so that the conditions for an action of the configurable element are met. A configurable element reacts not only to a trigger, but also to a set combination of triggers. In addition, a configurable element can perform prioritization of simultaneously incoming triggers.
Incoming triggers are recognized on the basis of the TRIGRDY signal. The trigger vectors are analyzed here according to configuration data also present in the configuration registers.
Trigger Handshake: As soon as the trigger vectors have been analyzed, a TRIGACK is generated for confirmation of the trigger vector.
BM UNIT: The BM UNIT is expanded so that it relays triggers coming from the bus to the sync unit and SM unit according to the configuration in M-PLUREG. Triggers generated by the EALU (e.g., comparator values “greater,” “less,” “equal,” 0 detectors, plus and minus signs, carry-overs, error states (division by 0, etc.), etc.) are relayed from the BM UNIT to the bus according to the wiring information in M-PLUREG.
Expansions of System Bus: The system bus, i.e., the bus system between the cells (PAEs), is expanded so that information is transferred together with the data over the target register. This means that an address which selects the desired register on receipt of the data is also sent. Likewise, the system bus is expanded by the independent transfer of trigger vectors and trigger handshakes.
DETAILED DESCRIPTION OF DIAGRAMS AND EMBODIMENTS
FIG. 1 shows how a loop construct can be implemented by using triggers. In this example, a macro 0103 is to be executed 70 times. One execution of the macro takes 26 clock cycles. This means that counter 0101 may be decremented by one increment only once in every 26 clock cycles. One problem with freely programmable modules is that it is not always possible to guarantee that processing of macro 0103 will actually be concluded after 26 clock cycles. For example, a delay may occur due to the fact that a macro which is to supply the input data for macro 0103 may suddenly require 10 more clock cycles. For this reason, the cell in macro 0103 sends a trigger signal to counter 0101, causing the result of the calculation to be sent to another macro. At the same time, processing of macro 0103 by the same cell is stopped. This cell “knows” exactly that the condition for termination of a calculation has been reached.
In this case the trigger signal sent is a STEP trigger, causing counter 0101 to execute its configured function once. The counter decrements its count by one and compares whether it has reached a value of 0. If this is not the case, a GO trigger is sent to macro 0103. This GO trigger signal causes macro 0103 to resume its function.
This process is repeated until counter 0101 has reached a value of 0. In this case, a trigger signal is sent to macro 0102, where it triggers a function.
A very fine synchronization can be achieved due to this interaction of triggers.
FIG. 2 shows how a comparison construct can be implemented by using multiple triggers. FIG. 2 corresponds to the basic idea of FIG. 1. However, in this case the function in element 0202 is not a counter but a comparator. Macro 0201 also sends a comparison value to comparator 0202 after each processing run. Depending on the output of the comparison, different triggers are again driven to prompt an action in macros 0203, for example. The construct implemented in FIG. 2 corresponds to that of an IF query in a programming language.
FIG. 3 shows how a comparison construct with multiple outputs can be implemented by using multiple triggers and interleaving them. Here, as in FIG. 2, several comparators 0301, 0302 are used here to implement construction of an IF-ELSE-ELSE construct (or multiple choice). Due to the use of a wide variety of types of triggers and connections of these triggers to macros 0303, 0304, very complex sequences can be implemented easily.
FIG. 4 shows an example of some of the differences between the present invention and, for example, conventional FPGAs and DFPs. Additional configuration register 0401 and additional status register 0402 are connected to the SM UNIT over bus 0407. Registers 0401, 0402, F-PLUREG and M-PLUREG are connected to a gate 0403 by an internal bus 0206. Depending on position, this gate connects internal bus 0406 to PLU bus 0405 to permit configuration by the PLU or to the BM UNIT by a bus 0408. Depending on the address on data bus 0404, the BM UNIT relays the data to the O-REG or to addressed register 0401, 0402, F-PLUREG or M-PLUREG.
BM UNIT 0411 sends trigger signals over 0415 to SYNC UNIT 0412. 0411 receives results from the EALU over 0414 (“equal,” “greater,” “less,” “result=0,” “result positive,” “result negative,” carry-over (positive and negative), etc.) to convert the results into trigger vectors. As an alternative, states generated by the SYNC UNIT or the STATE MACHINE can be relayed to the BM UNIT over 0415.
The trigger signals transmitted by the BM UNIT to bus 0404 can be used there as STEP/STOP/GO triggers, RECONFIG triggers or for selecting a configuration register, depending on the configuration of the configurable elements to be analyzed. Which function a generated trigger will execute in the configurable elements to be analyzed is determined by interconnection 0404 and the configuration of the respective configurable element. One and the same trigger may have different functions with different configurable elements. 0416 is the result output of R-REGsft to bus system 0404 and the following configurable elements.
FIG. 5 shows the time response between generated triggers and the configuration registers selected by the triggers as an example. 0501 generates by comparison a trigger vector TRIGV, which can assume values “equal,” “greater,” or “less.” Configurable elements 0502-0504 process data independently of comparison 0501. Processing depends on comparison values “equal,” “greater” and “less.” Processing is pipelined, i.e., a data word is modified first by 0502, then by 0503 and finally by 0504. 0505 also processes data as a function of 0501. However, this is limited to the dependence on the comparison values “less”; “greater” and “equal” cause the same function to be carried out. Thus, a distinction is made between the values “less” and “greater than or equal to.” 0506 is connected downstream in pipeline 0505. 0506 reacts differently to “equal,” “greater” and “less” (see 0503). 0507 also depends on 0501, but a distinction is made between the values “equal” and “not equal (less or greater).” This embodiment begins at time t (FIG. 5a) and ends at time t+3. If the data passes through one of pipelines 0502, 0503, 0504 or 0505, 0506, it is delayed by one clock cycle in each execution in one of macros 0502-0506. Longer and especially different delays may also occur. Since there is a handshake mechanism between the data and trigger signals for automatic synchronization (according to the related art or this application (TRIGACK/TRIGRDY)), this case need not be discussed separately.
Due to the delays, data and trigger signals of the earlier time t−2 are available at time t between the second and third pipeline steps, for example.
FIGS. 5a through 5d show the sequence of three clock cycles t through t+2.
The trigger vectors (i.e., the results of the comparison) generated by 0501 look as follows over t:
Time t Result of comparison
t − 2 less
t − 1 greater
t equal
t + 1 greater
t + 2 equal
FIG. 6 shows the integration of several configuration registers into one configurable element. In this embodiment there are three configuration registers 0409 according to FIG. 4. These are configured over bus 0406. A control unit 0601 (which may also be designed as a state machine) receives signals TRIGV and TRIGRDY over bus system 0411. Depending on TRIGV, the control unit switches one of the configuration registers over multiplexer 0602 to bus system 0401 leading to the control mechanisms of the configurable element. For synchronization of the trigger signals with the internal sequences of the configurable element, 0601 has a synchronization output leading to synchronization unit 0412 or to state machine 0413. For synchronization of the trigger sources, 0601 generates handshake signal TRIGACK after processing the incoming trigger. In this embodiment, each configuration register 0409 is assigned to one TRIGV of the type “equal,” “greater,” “less.” If other operations are executed with each type of trigger, then each configuration register is occupied differently. For example, if a distinction is made only between “equal” and “not equal” then the configuration registers are occupied equally for the types “less” and “greater,” namely with the configuration for “not equal.” The configuration register for “equal” is occupied differently. This means that the comparison can be made more specific on the basis of the occupancy of the configuration registers, each configurable element being able to design this specification differently.
TRIGV is relayed together with the result over register 0603 to the downstream configurable elements to permit pipelining according to FIGS. 5a-d. The register and the handshake signals are controlled by 0412 or 0413. Trigger information together with the result from R-REGsft or with a time offset, i.e., before the result, can be sent over interface 0416 to downstream configurable elements.
A time-offset transfer offers the advantage that no additional time is necessary for setting the configuration registers in the downstream configurable elements, because the setting is made before receiving the data (simultaneously with the release of the result). FIG. 6a shows a corresponding timing (based on sequences conventional for DFP). Trigger vectors 0615 are generated at rising edge 0613 of module clock 0614. Triggers are analyzed in the configurable elements at trailing edge 0612. Data is phase shifted, i.e., released at 0612 and entered at 0613. The trigger vectors are transferred over the bus and data is calculated during 0610. Data is transferred over the bus and triggers are calculated during 0611, or configuration registers of the configurable elements are selected according to data stored at 0613 and the configuration is set accordingly.
FIG. 7a shows the management of jumps according to the predicate/NOP method of the related art. In execution of a comparison, an entry is made in predicate register 0704. This entry is queried during the execution of commands, determining whether a command is being executed (the command is inside the code sequence addressed by the conditional jump) or is replaced by an NOP (the command is in a different code sequence from that addressed by the conditional jump). The command is in command register 0701. The predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued at the compile time of the program of the compiler. Allocation information 0707 is allocated to the command entered into the command register, so that a unique entry is referenced by the respective command.
0703 selects whether the command from 0701 or an NOP is to be executed. In execution of an NOP, one clock cycle is lost. 0703 has a symbolic character, because executing unit 0702 could also in principle be controlled directly by 0704.
In FIG. 7b there are n command registers (0701: Func 1 . . . Func n). In executing a comparison/conditional jump, the command register to be addressed, i.e., the result of the comparison, is deposited as an entry 0708 in predicate register 0706, where 0706 has a plurality of such entries. Respective entry 0708 in 0706 is so wide that all possible command registers of an executing unit 0702 can be addressed by it, which means that the width of an entry is log2(n) with n command registers. The predicate register contains a plurality of entries allocated to a plurality of operations and/or a plurality of processors. This allocation is issued by the compiler at the compile time of the program. Allocation information 0707 is allocated to the quantity of commands entered into the command registers, so that an unambiguous entry is referenced by the respective commands.
The multiplexer selects which command register supplies the code for the instantaneous execution.
Due to this technology, a valid command is executed instead of an NOP even in the worst case with conditional jumps, so no clock cycle is wasted.
The following provides an explanation of various names, functions and terms described above.
Name Convention
Assembly group UNIT
Type of operation MODE
Multiplexer MUX
Negated signal not
Register for PLU visible PLUREG
Register internal REG
Shift register sft
Function Convention
NOT Function!
I Q
0 1
1 0
AND Function &
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
OR Function #
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
GATE Function G
EN B Q
0 0
0 1
1 0 0
1 1 1
DEFINITION OF TERMS
BM UNIT: Unit for switching data to the bus systems outside the PAE. Switching is done over multiplexers for the data inputs and gates for the data outputs. OACK lines are implemented as open collector drivers. The BM UNIT is controlled by the M-PLUREG.
Data receiver: The unit(s) that process(es) the results of the PAE further.
Data transmitter: The unit(s) that make(s) available the data for the PAE as operands.
Data word: A data word consists of a bit series of any desired length. This bit series represents a processing unit for a system. Commands for processors or similar modules as well as pure data can be coded in a data word.
DFP: Data flow processor according to German Patent/Unexamined Patent No. 44 16 881.
DPGA: Dynamically configurable FPGAs. Related art.
EALU: Expanded arithmetic logic unit. ALU which has been expanded by special functions which are needed or appropriate for operation of a data processing system according to German Patent No. 441 16 881 A1. These are counters in particular.
Elements: Collective term for all types of self-contained units which can be used as part of an electronic module.
Elements thus include:
    • configurable cells of all types
    • clusters
    • blocks of RAM
    • logic
    • processors
    • registers
    • multiplexers
    • I/O pins of a chip
Event: An event can be analyzed by a hardware element of any type suitable for use and can prompt a conditional action as a reaction to this analysis. Events thus include, for example:
    • clock cycle of a computer
    • internal or external interrupt signal
    • trigger signal from other elements within the module
    • comparison of a data stream and/or a command stream with a value
    • input/output events
    • sequencing, carry-over, reset, etc. of a counter
    • analysis of a comparison
FPGA: Programmable logic module. Related art.
F-PLUREG: Register in which the function of the PAE is set. Likewise, the one shot and sleep mode are also set. The register is written by the PLU.
H level: Logic 1 level, depending on the technology used.
Configurable element: A configurable element is a unit of a logic module which can be set for a special function by a configuration word. Configurable elements are thus all types of RAM cells, multiplexers, arithmetic logic units, registers and all types of internal and external network writing, etc.
Configurable cell: See logic cells.
Configure: Setting the function and interconnecting a logic unit, an (FPGA) cell or a PAE (see: Reconfigure).
Configuration data: Any quantity of configuration words.
Configuration memory: The configuration memory contains one or more configuration words.
Configuration word: A configuration word consists of a bit series of any desired length. This bit series represents a valid setting for the element to be configured, so that a functional unit is obtained.
Load logic: Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.
Logic cells: Configurable cells used in DFPs, FPGAs, DPGAs, fulfilling simple logic or arithmetic functions according to their configuration.
L level: Logic 0 level, depending on the technology used.
M-PLUREG: Register in which the interconnection of the PAE is set. The register is written by the PLU.
O-REG: Operand register for storing the operands of the EALU. Permits independence of the PAE of the data transmitters in time and function. This simplifies the transfer of data because it can take place in an asynchronous or package-oriented manner. At the same time, the possibility of reconfiguring the data transmitters independently of the PAE or reconfiguring the PAE independently of the data transmitters is created.
PLU: Unit for configuring and reconfiguring the PAE. Embodied by a microcontroller specifically adapted to its function.
Propagate: Controlled relaying of a received signal.
RECONFIG: Reconfigurable state of a PAE.
RECONFIG trigger. Setting a PAE in the reconfigurable state.
SM UNIT: State machine UNIT. State machine controlling the EALU.
Switching table: A switching table is a ring memory which is addressed by a control. The entries in a switching table may accommodate any desired configuration words. The control can execute commands. The switching table reacts to trigger signals and reconfigures configurable elements on the basis of an entry in a ring memory.
Synchronization signals: Status signals generated by a configurable element or a processor and relayed to other configurable elements or processors to control and synchronize the data processing. It is also possible to return a synchronization signal with a time lag (stored) to one and the same configurable element or processor.
TRIGACK/TRIGRDY: Handshake of the triggers.
Trigger: Synonymous with synchronization signals.
Reconfigure: Configuring any desired quantity of PAEs again while any desired remaining quantity of PAEs continue their own function (see: Configure).
Processing cycle: A processing cycle describes the period of time needed by a unit to go from one defined and/or valid state into the next defined and/or valid state.
VLIW: Very large instruction word. Coding of microprocessors, prior art method.
Cells: Synonymous with configurable elements.

Claims (81)

What is claimed is:
1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising:
for each of a plurality of the processing elements that each include at least one corresponding register:
predefining at least one corresponding configuration command; and
storing each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element;
processing data in at least one first processing element;
obtaining at least one of a comparison, a sign, a carry-over, and an error state during the processing of the data in the at least one first processing element;
in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime;
processing data in at least one second processing element in a stream-like manner; and
in response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence.
2. A runtime configurable processor comprising:
a plurality of configurable elements arranged in an array of more than one dimension, at least some of the plurality of configurable elements including an arithmetic logic unit, a configuration with respect to at least one of a function and an interconnection of at least one of the at least some configurable elements being reconfigurable at runtime in response to configuration data;
at least one multiplexer adapted to determine the at least one of the function and the interconnection in response to a state machine, which is adapted to control the at least one multiplexer; and
at least one storage component adapted for storing said configuration data;
wherein the at least one storage component:
is provided in the array; and
is selectively connectable to at least one of the at least some configurable elements via the at least one multiplexer so as to allow for the runtime reconfiguration.
3. The runtime configurable processor of claim 2, wherein the state machine is adapted to control the at least one multiplexer in response to received trigger signals.
4. The runtime configurable processor of claim 3, wherein the received trigger signals are generated in the array.
5. The runtime configurable processor of claim 3, wherein the received trigger signals are generated in the array by at least one of a counter and a comparator implemented in at least one of the configurable elements.
6. The runtime configurable processor of claim 4, wherein the received trigger signals are generated in the array by a counter implemented in at least one of the configurable elements.
7. The runtime configurable processor of claim 6, wherein the received trigger signals are multibit trigger signals generated by at least one of the configurable elements.
8. A runtime configurable processor comprising:
a plurality of configurable elements arranged in an array of more than one dimension, at least some of the plurality of configurable elements including an arithmetic logic unit, a configuration of at least one of a function and an interconnection of at least one of the at least some configurable elements being redeterminable at runtime in response to configuration select information;
a multiplexer arrangement adapted for determining said at least one of the function and the interconnection in response to said configuration select information;
at least one storage component adapted to store configuration data and provided in the array, wherein:
the at least one storage component is selectively connectable to at least one of the at least some configurable elements via at least one multiplexer of said multiplexer arrangement so as to allow for the runtime configuration redetermination, configuration select information being pipelined through said array; and
the at least one multiplexer receives configuration select information from said pipeline; and
a state machine being provided to control the at least one multiplexer.
9. The runtime configurable processor of claim 8, wherein the configuration select information is pipelined along with the data to be processed via a configurable interconnection system.
10. The runtime configurable processor of claim 9, wherein the pipeline is adapted to transfer trigger signals as configuration select information via the configurable interconnection system.
11. The runtime configurable processor of claim 9, wherein the pipeline is adapted to transfer one bit trigger signals as configuration select information via the configurable interconnection system.
12. The runtime configurable processor of any of claims 8 to 11, wherein the state machine is adapted to control the at least one multiplexer in response to received trigger signals.
13. The runtime configurable processor of claim 12, wherein the received trigger signals are generated in the array.
14. The runtime configurable processor of claim 12, wherein the received trigger signals are generated in the array by at least one of a counter and a comparator.
15. The runtime configurable processor of claim 12, wherein the received trigger signals are generated in the array by a counter.
16. The runtime configurable processor of claim 15, wherein the received trigger signals are multibit trigger signals.
17. A method for synchronizing data processing in a runtime configurable processor, the runtime reconfigurable processor comprising: a plurality of configurable elements arranged in an array of more than one dimension, at least some of the plurality of configurable elements including an arithmetic logic unit, a configuration of at least one of a function and an interconnection of at least one of the at least some configurable elements being redeterminable at runtime in response to configuration data; and at least one storage component for the configuration data, the at least one storage component being provided in the array, the method comprising the steps of:
processing data by the configurable elements;
propagating processed data through the array;
generating, by at least one of the configurble elements, at least one configuration select information signal in the array according to data being processed;
propagating the at least one configuration select information signal in a pipelined manner, the propagation of the configuration select information signal being synchronous to the propagation of the processed data; and
using the propagated configuration select information signal to one of trigger a certain action in data processing and put the at least one of the configurable elements in a certain state.
18. The method of claim 17, wherein the propagated configuration select information signal is used to determine that at least one of: data is to be processed in continuous manner; data is to be processed in a single step manner; data is not to be processed; and a configuration is to be changed.
19. The method of claim 17 or claim 18, wherein at least one configuration select information signal is pipelined downstream together with at least some of the data being processed.
20. The method of claim 17 or claim 18, wherein the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data.
21. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed; and
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data.
22. The method of claim 17 or claim 18, wherein a configuration select information signal is generated in the array by a counter.
23. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed; and
a configuration select information signal is generated in the array by a counter.
24. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a counter.
25. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a counter.
26. The method of claim 17 or claim 18, wherein a configuration select information signal is generated in the array by a comparator.
27. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed; and
a configuration select information signal is generated in the array by a comparator.
28. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a comparator.
29. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a comparator.
30. The method of claim 17 or claim 18, wherein a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator.
31. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed; and
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator.
32. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator.
33. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data; and
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator.
34. The method of claim 17 or claim 18, wherein:
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
35. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
36. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
37. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
38. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
39. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
40. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
41. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data is are selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
42. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
43. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
44. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
45. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
46. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
47. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
48. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
49. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals.
50. The method of claim 17 or claim 18, wherein:
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
51. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
52. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
53. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
54. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
55. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
56. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
57. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
58. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
59. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
60. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
61. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
62. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
63. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
64. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
65. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received trigger signals which were generated in the array.
66. The method of claim 17 or claim 18, wherein:
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
67. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
68. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
69. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
70. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
71. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
72. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
73. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
74. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
75. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
76. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
77. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
78. The method of claim 17 or claim 18, wherein:
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
79. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
80. The method of claim 17 or claim 18, wherein:
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
81. The method of claim 17 or claim 18, wherein:
at least one configuration select information signal is pipelined downstream together with at least some of the data being processed;
the propagated configuration select information signal is used to change a configuration during runtime of the processor and while at least another element of the configurable elements processes data;
a configuration select information signal is generated in the array by a counter and a configuration select information signal is generated in the array by a comparator;
the at least one storage component stores configuration data and is selectively connected to at least one of the at least some configurable elements via at least one multiplexer in a manner to allow for the runtime configuration redetermination; and
a state machine is provided to control the at least one multiplexer used to allow for the runtime configuration redetermination, the control being in response to received multibit trigger signals which were generated in the array.
US12/909,061 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module Expired - Lifetime USRE44365E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/909,061 USRE44365E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
DE19704728 1997-02-08
DE19704728A DE19704728A1 (en) 1997-02-08 1997-02-08 Method for self-synchronization of configurable elements of a programmable module
US08/946,812 US6081903A (en) 1997-02-08 1997-10-08 Method of the self-synchronization of configurable elements of a programmable unit
PCT/DE1998/000334 WO1998035299A2 (en) 1997-02-08 1998-02-07 Method for self-synchronization of configurable elements of a programmable component
US09/369,653 US6542998B1 (en) 1997-02-08 1999-08-06 Method of self-synchronization of configurable elements of a programmable module
US10/379,403 US7036036B2 (en) 1997-02-08 2003-03-04 Method of self-synchronization of configurable elements of a programmable module
US12/109,280 USRE44383E1 (en) 1997-02-08 2008-04-24 Method of self-synchronization of configurable elements of a programmable module
US12/909,061 USRE44365E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/379,403 Reissue US7036036B2 (en) 1997-02-08 2003-03-04 Method of self-synchronization of configurable elements of a programmable module

Publications (1)

Publication Number Publication Date
USRE44365E1 true USRE44365E1 (en) 2013-07-09

Family

ID=46279486

Family Applications (6)

Application Number Title Priority Date Filing Date
US09/369,653 Expired - Lifetime US6542998B1 (en) 1997-02-08 1999-08-06 Method of self-synchronization of configurable elements of a programmable module
US10/379,403 Ceased US7036036B2 (en) 1997-02-08 2003-03-04 Method of self-synchronization of configurable elements of a programmable module
US12/109,280 Expired - Lifetime USRE44383E1 (en) 1997-02-08 2008-04-24 Method of self-synchronization of configurable elements of a programmable module
US12/909,203 Expired - Lifetime USRE45109E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module
US12/909,061 Expired - Lifetime USRE44365E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module
US12/909,150 Expired - Lifetime USRE45223E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Family Applications Before (4)

Application Number Title Priority Date Filing Date
US09/369,653 Expired - Lifetime US6542998B1 (en) 1997-02-08 1999-08-06 Method of self-synchronization of configurable elements of a programmable module
US10/379,403 Ceased US7036036B2 (en) 1997-02-08 2003-03-04 Method of self-synchronization of configurable elements of a programmable module
US12/109,280 Expired - Lifetime USRE44383E1 (en) 1997-02-08 2008-04-24 Method of self-synchronization of configurable elements of a programmable module
US12/909,203 Expired - Lifetime USRE45109E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/909,150 Expired - Lifetime USRE45223E1 (en) 1997-02-08 2010-10-21 Method of self-synchronization of configurable elements of a programmable module

Country Status (1)

Country Link
US (6) US6542998B1 (en)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19654846A1 (en) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE59710317D1 (en) 1996-12-27 2003-07-24 Pact Inf Tech Gmbh METHOD FOR THE INDEPENDENT DYNAMIC RE-LOADING OF DATA FLOW PROCESSORS (DFPs) AND MODULES WITH TWO OR MORE-DIMENSIONAL PROGRAMMABLE CELL STRUCTURES (FPGAs, DPGAs, or the like)
US6542998B1 (en) * 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (en) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (en) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
WO2000077652A2 (en) 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
DE50115584D1 (en) 2000-06-13 2010-09-16 Krass Maren PIPELINE CT PROTOCOLS AND COMMUNICATION
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7624204B2 (en) * 2001-03-22 2009-11-24 Nvidia Corporation Input/output controller node in an adaptable computing environment
US7155602B2 (en) * 2001-04-30 2006-12-26 Src Computers, Inc. Interface for integrating reconfigurable processors into a general purpose computing system
ATE557344T1 (en) 2001-06-20 2012-05-15 Krass Maren METHOD AND DEVICE FOR PARTITIONING LARGE COMPUTER PROGRAMS
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7594229B2 (en) * 2001-10-09 2009-09-22 Nvidia Corp. Predictive resource allocation in computing systems
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US7644279B2 (en) * 2001-12-05 2010-01-05 Nvidia Corporation Consumer product distribution in the embedded system market
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
EP2043000B1 (en) 2002-02-18 2011-12-21 Richter, Thomas Bus systems and reconfiguration method
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7093255B1 (en) * 2002-05-31 2006-08-15 Quicksilver Technology, Inc. Method for estimating cost when placing operations within a modulo scheduler when scheduling for processors with a large number of function units or reconfigurable data paths
US7620678B1 (en) 2002-06-12 2009-11-17 Nvidia Corporation Method and system for reducing the time-to-market concerns for embedded system design
US7802108B1 (en) 2002-07-18 2010-09-21 Nvidia Corporation Secure storage of program code for an embedded system
WO2004010286A2 (en) * 2002-07-23 2004-01-29 Gatechange Technologies, Inc. Self-configuring processing element
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7502915B2 (en) * 2002-09-30 2009-03-10 Nvidia Corporation System and method using embedded microprocessor as a node in an adaptable computing machine
US8949576B2 (en) * 2002-11-01 2015-02-03 Nvidia Corporation Arithmetic node including general digital signal processing functions for an adaptive computing machine
US7617100B1 (en) 2003-01-10 2009-11-10 Nvidia Corporation Method and system for providing an excitation-pattern based audio coding scheme
US8296764B2 (en) * 2003-08-14 2012-10-23 Nvidia Corporation Internal synchronization control for adaptive integrated circuitry
JP4700611B2 (en) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Data processing apparatus and data processing method
DE102004001669B4 (en) * 2004-01-12 2008-06-05 Infineon Technologies Ag Configurable logic device without local configuration memory with parallel configuration bus
US8130825B2 (en) * 2004-05-10 2012-03-06 Nvidia Corporation Processor for video data encoding/decoding
US8018463B2 (en) * 2004-05-10 2011-09-13 Nvidia Corporation Processor for video data
JP4120631B2 (en) * 2004-10-05 2008-07-16 株式会社日立製作所 Semiconductor integrated circuit
TWI256013B (en) * 2004-10-12 2006-06-01 Uli Electronics Inc Sound-effect processing circuit
US7765250B2 (en) * 2004-11-15 2010-07-27 Renesas Technology Corp. Data processor with internal memory structure for processing stream data
JP2009524134A (en) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Hardware definition method
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US7832008B1 (en) * 2006-10-11 2010-11-09 Cisco Technology, Inc. Protection of computer resources
US7999820B1 (en) 2006-10-23 2011-08-16 Nvidia Corporation Methods and systems for reusing memory addresses in a graphics system
US20080111923A1 (en) * 2006-11-09 2008-05-15 Scheuermann W James Processor for video data
US8169789B1 (en) 2007-04-10 2012-05-01 Nvidia Corporation Graphics processing unit stiffening frame
US7987065B1 (en) 2007-04-17 2011-07-26 Nvidia Corporation Automatic quality testing of multimedia rendering by software drivers
US8572598B1 (en) 2007-04-18 2013-10-29 Nvidia Corporation Method and system for upgrading software in a computing device
US8726283B1 (en) 2007-06-04 2014-05-13 Nvidia Corporation Deadlock avoidance skid buffer
US7948500B2 (en) * 2007-06-07 2011-05-24 Nvidia Corporation Extrapolation of nonresident mipmap data using resident mipmap data
US7944453B1 (en) 2007-06-07 2011-05-17 Nvidia Corporation Extrapolation texture filtering for nonresident mipmaps
US8180997B2 (en) * 2007-07-05 2012-05-15 Board Of Regents, University Of Texas System Dynamically composing processor cores to form logical processors
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
EP2718859A1 (en) 2011-06-08 2014-04-16 Hyperion Core, Inc. Tool-level and hardware-level code optimization and respective hardware modification
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US11531552B2 (en) 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication

Citations (675)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2067477A (en) 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
US3242998A (en) 1962-05-28 1966-03-29 Wolf Electric Tools Ltd Electrically driven equipment
US3564506A (en) 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US3681578A (en) 1969-11-21 1972-08-01 Marconi Co Ltd Fault location and reconfiguration in redundant data processors
US3753008A (en) 1970-06-20 1973-08-14 Honeywell Inf Systems Memory pre-driver circuit
US3754211A (en) 1971-12-30 1973-08-21 Ibm Fast error recovery communication controller
US3757608A (en) 1970-11-21 1973-09-11 Bhs Bayerische Berg Solar and planetary gear system with load pressure compensation
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US3956589A (en) 1973-11-26 1976-05-11 Paradyne Corporation Data telecommunication system
US4151611A (en) 1976-03-26 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Power supply control system for memory systems
US4233667A (en) 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4414547A (en) 1981-08-05 1983-11-08 General Instrument Corporation Storage logic array having two conductor data column
JPS5858672B2 (en) 1976-10-20 1983-12-26 東ソー株式会社 electroluminescent display board
US4498172A (en) 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4498134A (en) 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4566102A (en) 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4590583A (en) 1982-07-16 1986-05-20 At&T Bell Laboratories Coin telephone measurement circuitry
US4591979A (en) 1982-08-25 1986-05-27 Nec Corporation Data-flow-type digital processing apparatus
US4594682A (en) 1982-12-22 1986-06-10 Ibm Corporation Vector processing
US4623997A (en) 1984-12-13 1986-11-18 United Technologies Corporation Coherent interface with wraparound receive and transmit memories
US4646300A (en) 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
EP0221350A1 (en) 1985-11-01 1987-05-13 Energy Conversion Devices, Inc. Electrolevelled substrate for electrophotographic photoreceptors and method of fabricating same
US4667190A (en) 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4686386A (en) 1984-03-21 1987-08-11 Oki Electric Industry Co., Ltd. Power-down circuits for dynamic MOS integrated circuits
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US4720780A (en) 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4720778A (en) 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US4739474A (en) 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4748580A (en) 1985-08-30 1988-05-31 Advanced Micro Devices, Inc. Multi-precision fixed/floating-point processor
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4761755A (en) 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
EP0208457A3 (en) 1985-07-09 1988-11-02 National Research Development Corporation A processor array
US4791603A (en) 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US4811214A (en) 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4852043A (en) 1986-05-21 1989-07-25 Hewlett-Packard Company Daisy-chain bus system with truncation circuitry for failsoft bypass of defective sub-bus subsystem
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
JPH01229378A (en) 1988-03-09 1989-09-13 Fujitsu Ltd Picture data storage device
US4870302A (en) 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4873666A (en) 1987-10-14 1989-10-10 Northern Telecom Limited Message FIFO buffer controller
US4882687A (en) 1986-03-31 1989-11-21 Schlumberger Technology Corporation Pixel processor
US4884231A (en) 1986-09-26 1989-11-28 Performance Semiconductor Corporation Microprocessor system with extended arithmetic logic unit
US4891810A (en) 1986-10-31 1990-01-02 Thomson-Csf Reconfigurable computing device
US4901268A (en) 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US4910665A (en) 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US4918440A (en) 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
WO1990004835A1 (en) 1988-10-19 1990-05-03 Wendt Hans J Digital computer with multiprocessor arrangement
JPH02130023A (en) 1988-11-10 1990-05-18 Fujitsu Ltd Multifunction programmable logic device
US4939641A (en) 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
JPH02226423A (en) 1989-01-12 1990-09-10 Internatl Business Mach Corp <Ibm> Microcode controller
US4959781A (en) 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
WO1990011648A1 (en) 1989-03-17 1990-10-04 Algotronix Limited Configurable cellular array
US4967340A (en) 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
US4972314A (en) 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4992933A (en) 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5010401A (en) 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US5014193A (en) 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5015884A (en) 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
EP0428327A1 (en) 1989-11-14 1991-05-22 Amt(Holdings) Limited Processor array system
US5021947A (en) 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5031179A (en) 1987-11-10 1991-07-09 Canon Kabushiki Kaisha Data communication apparatus
US5034914A (en) 1986-05-15 1991-07-23 Aquidneck Systems International, Inc. Optical disk data storage method and apparatus with buffered interface
US5036493A (en) 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5036473A (en) 1988-10-05 1991-07-30 Mentor Graphics Corporation Method of using electronically reconfigurable logic circuits
US5041924A (en) 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
US5043978A (en) 1988-09-22 1991-08-27 Siemens Aktiengesellschaft Circuit arrangement for telecommunications exchanges
US5047924A (en) 1988-06-30 1991-09-10 Mitsubishi Denki Kabushiki Kaisha Microcomputer
US5055997A (en) 1988-01-13 1991-10-08 U.S. Philips Corporation System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch
US5065308A (en) 1985-01-29 1991-11-12 The Secretary Of State For Defence In Her Britannic Magesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Processing cell for fault tolerant arrays
US5070475A (en) 1985-11-14 1991-12-03 Data General Corporation Floating point unit interface
US5072178A (en) 1989-06-09 1991-12-10 Hitachi, Ltd. Method and apparatus for testing logic circuitry by applying a logical test pattern
US5076482A (en) 1990-10-05 1991-12-31 The Fletcher Terry Company Pneumatic point driver
US5081375A (en) 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5081575A (en) 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
WO1992001987A1 (en) 1990-07-16 1992-02-06 Tekstar Systems Corporation Interface system for data transfer with remote peripheral independently of host processor backplane
US5099447A (en) 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5103311A (en) 1988-01-11 1992-04-07 U.S. Philips Corporation Data processing module and video processing system incorporating same
US5109503A (en) 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5119290A (en) 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US5123109A (en) 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US5125801A (en) 1990-02-02 1992-06-30 Isco, Inc. Pumping system
US5128559A (en) 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
EP0497029A2 (en) 1991-01-29 1992-08-05 Analogic Corporation Reconfigurable sequential processor
US5142469A (en) 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
EP0221360B1 (en) 1985-11-04 1992-12-30 International Business Machines Corporation Digital data message transmission networks and the establishing of communication paths therein
US5193202A (en) 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5203005A (en) 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5204935A (en) 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
EP0539595A1 (en) 1991-04-09 1993-05-05 Fujitsu Limited Data processor and data processing method
US5212777A (en) 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5212716A (en) 1991-02-05 1993-05-18 International Business Machines Corporation Data edge phase sorting circuits
US5218302A (en) 1991-02-06 1993-06-08 Sun Electric Corporation Interface for coupling an analyzer to a distributorless ignition system
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
EP0463721A3 (en) 1990-04-30 1993-06-16 Gennum Corporation Digital signal processing device
US5226122A (en) 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5237686A (en) 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5245616A (en) 1989-02-24 1993-09-14 Rosemount Inc. Technique for acknowledging packets
US5247689A (en) 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
JPH05265705A (en) 1992-03-23 1993-10-15 Nippon Telegr & Teleph Corp <Ntt> Digital processing circuit
JPH05276007A (en) 1991-11-27 1993-10-22 Philips Gloeilampenfab:Nv Integrated circuit device
USRE34444E (en) 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5276836A (en) 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5287511A (en) 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5287532A (en) 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5294119A (en) 1991-09-27 1994-03-15 Taylor Made Golf Company, Inc. Vibration-damping device for a golf club
WO1994006077A1 (en) 1992-08-28 1994-03-17 Siemens Aktiengesellschaft Computer system with at least one microprocessor and at least one coprocessor, and a method of operating the system
US5301284A (en) 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5303172A (en) 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
WO1994008399A1 (en) 1992-10-05 1994-04-14 Lattice Semiconductor Corporation Arrangement for parallel programming of in-system programmable ic logic devices
US5311079A (en) 1992-12-17 1994-05-10 Ditlow Gary S Low power, high performance PLA
US5327125A (en) 1992-07-13 1994-07-05 Sharp Kabushiki Kaisha Apparatus for and method of converting a sampling frequency according to a data driven type processing
US5336950A (en) 1991-08-29 1994-08-09 National Semiconductor Corporation Configuration features in a configurable logic array
US5343406A (en) 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
JPH06266605A (en) 1993-03-16 1994-09-22 Yokogawa Medical Syst Ltd Storage device
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
US5355508A (en) 1990-05-07 1994-10-11 Mitsubishi Denki Kabushiki Kaisha Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5365125A (en) 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5379444A (en) 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
WO1995000161A1 (en) 1993-06-18 1995-01-05 University Of Cincinnati Neuropeptide y antagonists and agonists
US5386154A (en) 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5386518A (en) 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
EP0638867A2 (en) 1993-08-12 1995-02-15 Hughes Aircraft Company Dynamically reconfigurable interprocessor communication network for SIMD multi-processors and apparatus implementing same
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5408643A (en) 1991-02-01 1995-04-18 Nec Corporation Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared
US5410723A (en) 1989-11-21 1995-04-25 Deutsche Itt Industries Gmbh Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell
US5412795A (en) 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US5418953A (en) 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US5418952A (en) 1988-11-23 1995-05-23 Flavors Technology Inc. Parallel processor cell computer system
US5421019A (en) 1988-10-07 1995-05-30 Martin Marietta Corporation Parallel data processor
US5422823A (en) 1989-08-15 1995-06-06 Advanced Micro Devices, Inc. Programmable gate array device having cascaded means for function definition
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
JPH07154242A (en) 1993-05-13 1995-06-16 Texas Instr Inc <Ti> Programmable logic array circuit
US5426378A (en) 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
US5430687A (en) 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5435000A (en) 1993-05-19 1995-07-18 Bull Hn Information Systems Inc. Central processing unit using dual basic processing units and combined result bus
JPH07182160A (en) 1993-10-29 1995-07-21 Advanced Micro Devicds Inc Superscalar microprocessor
JPH07182167A (en) 1993-10-29 1995-07-21 Advanced Micro Devicds Inc Loading/storing function unit of microprocessor and apparatus for information processing
US5440245A (en) 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5442790A (en) 1991-05-24 1995-08-15 The Trustees Of Princeton University Optimizing compiler for computers
US5444394A (en) 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
US5448186A (en) 1993-03-18 1995-09-05 Fuji Xerox Co., Ltd. Field-programmable gate array
US5450022A (en) 1994-10-07 1995-09-12 Xilinx Inc. Structure and method for configuration of a field programmable gate array
JPH0786921B2 (en) 1989-04-20 1995-09-20 富士写真フイルム株式会社 Method and apparatus for energy subtraction of radiation image
WO1995026001A1 (en) 1994-03-22 1995-09-28 Norman Richard S Efficient direct cell replacement fault tolerant architecture supporting completely integrated systems with means for direct communication with system operator
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5465375A (en) 1992-01-14 1995-11-07 France Telecom Multiprocessor system with cascaded modules combining processors through a programmable logic cell array
US5469003A (en) 1992-11-05 1995-11-21 Xilinx, Inc. Hierarchically connectable configurable cellular array
US5473266A (en) 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
US5473267A (en) 1993-02-16 1995-12-05 Sgs-Thomson Microelectronics Limited Programmable logic device with memory that can store routing data of logic data
US5475803A (en) 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
US5475583A (en) 1991-02-22 1995-12-12 Siemens Aktiengesellschaft Programmable control system including a logic module and a method for programming
US5475856A (en) 1991-11-27 1995-12-12 International Business Machines Corporation Dynamic multi-mode parallel processing array
US5477525A (en) 1992-09-03 1995-12-19 Sony Corporation Data destruction preventing method, recording apparatus provided with data destruction preventing capability, and disc recorded with guard band
US5483620A (en) 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5485104A (en) 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US5485103A (en) 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5489857A (en) 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
JPH0844581A (en) 1994-07-29 1996-02-16 Fujitsu Ltd Information processor with self-repairing function
US5493663A (en) 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5493239A (en) 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
DE4221278C2 (en) 1992-06-29 1996-02-29 Martin Vorbach Bus-linked multi-computer system
US5497498A (en) 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
JPH0869447A (en) 1994-08-31 1996-03-12 Toshiba Corp Data processor
US5502838A (en) 1994-04-28 1996-03-26 Consilium Overseas Limited Temperature management for integrated circuits
US5504439A (en) 1994-04-01 1996-04-02 Xilinx, Inc. I/O interface cell for use with optional pad
US5506998A (en) 1991-03-20 1996-04-09 Fujitsu Limited Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data
JPH08102492A (en) 1994-08-02 1996-04-16 Toshiba Corp Programmable wiring circuit and test board device
JPH08101761A (en) 1994-02-17 1996-04-16 Pilkington Germany Number 2 Ltd Reconstitutable application-specific device
EP0707269A1 (en) 1994-10-11 1996-04-17 International Business Machines Corporation Cache coherence network for a multiprocessor data processing system
JPH08106443A (en) 1994-10-05 1996-04-23 Hitachi Ltd Data processing system and parallel computer
US5511173A (en) 1989-11-08 1996-04-23 Ricoh Co., Ltd. Programmable logic array and data processing unit using the same
US5510730A (en) 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US5513366A (en) 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5521837A (en) 1992-06-04 1996-05-28 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
JPH08148989A (en) 1994-11-18 1996-06-07 Hitachi Ltd Superconducting fpga device
US5525971A (en) 1993-09-23 1996-06-11 Advanced Risc Machines Limited Integrated circuit
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5530873A (en) 1992-10-02 1996-06-25 Hudson Soft Co. Ltd. Method and apparatus for processing interruption
US5532693A (en) 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
US5532957A (en) 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
US5535406A (en) 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5537601A (en) 1993-07-21 1996-07-16 Hitachi, Ltd. Programmable digital signal processor for performing a plurality of signal processings
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5541530A (en) 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5544336A (en) 1991-03-19 1996-08-06 Fujitsu Limited Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US5548773A (en) 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
JPH08221164A (en) 1995-02-14 1996-08-30 Kumamoto Techno Porisu Zaidan Trial manufacture supporting device, substrate for ic mounting, and bus device
US5555434A (en) 1990-08-02 1996-09-10 Carlstedt Elektronik Ab Computing device employing a reduction processor and implementing a declarative language
US5559450A (en) 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
JPH08250685A (en) 1995-03-08 1996-09-27 Nippon Telegr & Teleph Corp <Ntt> Programmable gate array
US5561738A (en) 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5568624A (en) 1990-06-29 1996-10-22 Digital Equipment Corporation Byte-compare operation for high-performance processor
US5570040A (en) 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5572710A (en) 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5574927A (en) 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
EP0735685A3 (en) 1990-06-29 1996-11-13 STMicroelectronics, Inc. Programmable power reduction circuit for programmable logic device
US5581734A (en) 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5581731A (en) 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
US5584013A (en) 1994-12-09 1996-12-10 International Business Machines Corporation Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
US5583450A (en) 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
EP0748051A2 (en) 1995-06-05 1996-12-11 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5588152A (en) 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5590345A (en) 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5596742A (en) 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
JPH0927745A (en) 1995-06-02 1997-01-28 Internatl Business Mach Corp <Ibm> Programmable array clock/reset
US5600845A (en) 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5600597A (en) 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
US5603005A (en) 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5602999A (en) 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US5606698A (en) 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5608342A (en) 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5611049A (en) 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
GB2304438A (en) 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
US5617577A (en) 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5617547A (en) 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
US5619720A (en) 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5625806A (en) 1994-12-12 1997-04-29 Advanced Micro Devices, Inc. Self configuring speed path in a microprocessor with multiple clock option
US5627992A (en) 1988-01-20 1997-05-06 Advanced Micro Devices Organization of an integrated cache unit for flexible usage in supporting microprocessor operations
DE3855673T2 (en) 1987-08-28 1997-05-07 Ibm System part reconfiguration triggered by peripheral devices
US5635851A (en) 1996-02-02 1997-06-03 Xilinx, Inc. Read and writable data bus particularly for programmable logic devices
US5642058A (en) 1995-10-16 1997-06-24 Xilinx , Inc. Periphery input/output interconnect structure
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5649179A (en) 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5655124A (en) 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5657330A (en) 1994-11-15 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Single-chip microprocessor with built-in self-testing function
US5656950A (en) 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5659797A (en) 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
JPH09237284A (en) 1996-02-29 1997-09-09 Nec Corp Logic circuit division system
US5675262A (en) 1995-10-26 1997-10-07 Xilinx, Inc. Fast carry-out scheme in a field programmable gate array
US5675777A (en) 1990-01-29 1997-10-07 Hipercore, Inc. Architecture for minimal instruction set computing system
US5675757A (en) 1988-07-22 1997-10-07 Davidson; George S. Direct match data flow memory for data driven computing
US5675743A (en) 1995-02-22 1997-10-07 Callisto Media Systems Inc. Multi-media server
US5677909A (en) 1994-05-11 1997-10-14 Spectrix Corporation Apparatus for exchanging data between a central station and a plurality of wireless remote stations on a time divided commnication channel
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5682544A (en) 1992-05-12 1997-10-28 International Business Machines Corporation Massively parallel diagonal-fold tree array processor
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
JPH09294069A (en) 1996-03-01 1997-11-11 Agency Of Ind Science & Technol Programmable lsi and its arithmetic method
US5687325A (en) 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
EP0746106A3 (en) 1995-06-02 1997-11-19 International Business Machines Corporation Programmable array I/O - routing resource
US5694602A (en) 1996-10-01 1997-12-02 The United States Of America As Represented By The Secretary Of The Air Force Weighted system and method for spatial allocation of a parallel load
US5696976A (en) 1990-12-21 1997-12-09 Intel Corporation Protocol for interrupt bus arbitration in a multi-processor system
US5696791A (en) 1995-01-17 1997-12-09 Vtech Industries, Inc. Apparatus and method for decoding a sequence of digitally encoded data
US5701091A (en) 1995-05-02 1997-12-23 Xilinx, Inc. Routing resources for hierarchical FPGA
US5706482A (en) 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5705938A (en) 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5713037A (en) 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5717890A (en) 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5727229A (en) 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
WO1998010517A1 (en) 1996-09-03 1998-03-12 Xilinx, Inc. Fpga architecture having ram blocks with programmable word length and width and dedicated address and data lines
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Method for operating a data processing device
US5732209A (en) 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5734869A (en) 1995-09-06 1998-03-31 Chen; Duan-Ping High speed logic circuit simulator
US5737516A (en) 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
US5737565A (en) 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US5742180A (en) * 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5745734A (en) 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5754820A (en) 1991-07-09 1998-05-19 Kabushiki Kaisha Toshiba Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data
US5754871A (en) 1990-11-13 1998-05-19 International Business Machines Corporation Parallel processing system having asynchronous SIMD processing
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
US5754876A (en) 1994-12-28 1998-05-19 Hitachi, Ltd. Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner
US5754827A (en) 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5760602A (en) 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
US5768629A (en) 1993-06-24 1998-06-16 Discovision Associates Token-based adaptive video processing arrangement
US5773994A (en) 1995-12-15 1998-06-30 Cypress Semiconductor Corp. Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
WO1998028697A1 (en) 1996-12-20 1998-07-02 Pact Informationstechnologie Gmbh IO- AND MEMORY BUS SYSTEM FOR DFPs AS UNITS WITH TWO- OR MULTI-DIMENSIONALLY PROGRAMMABLE CELL STRUCTURES
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
US5778237A (en) 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5778439A (en) 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
US5781756A (en) 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5784313A (en) 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5784630A (en) 1990-09-07 1998-07-21 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5784636A (en) 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5794062A (en) 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5794059A (en) 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US5802290A (en) 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5801547A (en) 1996-03-01 1998-09-01 Xilinx, Inc. Embedded memory for field programmable gate array
US5801958A (en) 1990-04-06 1998-09-01 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5804986A (en) 1995-12-29 1998-09-08 Cypress Semiconductor Corp. Memory in a programmable logic device
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
US5815726A (en) 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US5815004A (en) 1995-10-16 1998-09-29 Xilinx, Inc. Multi-buffered configurable logic block output lines in a field programmable gate array
US5815715A (en) 1995-06-05 1998-09-29 Motorola, Inc. Method for designing a product having hardware and software components and product therefor
US5821774A (en) 1995-05-26 1998-10-13 Xilinx, Inc. Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
US5828229A (en) 1991-09-03 1998-10-27 Altera Corporation Programmable logic array integrated circuits
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US5832288A (en) 1996-10-18 1998-11-03 Samsung Electronics Co., Ltd. Element-select mechanism for a vector processor
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5838988A (en) 1997-06-25 1998-11-17 Sun Microsystems, Inc. Computer product for precise architectural update in an out-of-order processor
US5841973A (en) 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US5844888A (en) 1987-11-10 1998-12-01 Echelon Corporation Network and intelligent cell for providing sensing, bidirectional communications and control
US5844422A (en) 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US5848238A (en) 1996-01-12 1998-12-08 Hitachi, Ltd. Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them
US5854918A (en) 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5857109A (en) 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5857097A (en) 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
WO1999000739A1 (en) 1997-06-27 1999-01-07 Chameleon Systems, Inc. An integrated processor and programmable data path chip for reconfigurable computing
WO1999000731A1 (en) 1997-06-27 1999-01-07 Chameleon Systems, Inc. Method for compiling high level programming languages
US5859544A (en) 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US5860119A (en) 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US5862403A (en) 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5865239A (en) 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
US5867691A (en) 1992-03-13 1999-02-02 Kabushiki Kaisha Toshiba Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
US5867723A (en) 1992-08-05 1999-02-02 Sarnoff Corporation Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
US5870620A (en) 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
JPH1146187A (en) 1997-05-27 1999-02-16 Uniden Corp Data transmission method and data transmission device
US5884075A (en) 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US5887165A (en) 1996-06-21 1999-03-23 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US5887162A (en) 1994-04-15 1999-03-23 Micron Technology, Inc. Memory device having circuitry for initializing and reprogramming a control operation feature
DE19822776A1 (en) 1997-09-19 1999-03-25 Mitsubishi Electric Corp Data processing arrangement
US5889982A (en) 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5889533A (en) 1996-02-17 1999-03-30 Samsung Electronics Co., Ltd. First-in-first-out device for graphic drawing engine
US5892962A (en) 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5892370A (en) 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
US5894565A (en) 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
WO1999012111B1 (en) 1997-08-28 1999-04-15 Xilinx Inc A method of designing fpgas for dynamically reconfigurable computing
US5895487A (en) 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US5898602A (en) 1996-01-25 1999-04-27 Xilinx, Inc. Carry chain circuit with flexible carry function for implementing arithmetic and logical functions
US5901279A (en) 1996-10-18 1999-05-04 Hughes Electronics Corporation Connection of spares between multiple programmable devices
EP0485690B1 (en) 1990-11-13 1999-05-26 International Business Machines Corporation Parallel associative processor system
US5915099A (en) 1996-09-13 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Bus interface unit in a microprocessor for facilitating internal and external memory accesses
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US5913925A (en) 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
WO1999032975A1 (en) 1997-12-22 1999-07-01 Pact Informationstechnologie Gmbh Process for repairing integrated circuits
JPH11184718A (en) 1997-12-19 1999-07-09 Matsushita Electric Ind Co Ltd Programmable data processor
US5924119A (en) 1990-11-30 1999-07-13 Xerox Corporation Consistent packet switched memory bus for shared memory multiprocessors
US5926638A (en) 1996-01-17 1999-07-20 Nec Corporation Program debugging system for debugging a program having graphical user interface
US5927423A (en) 1997-03-05 1999-07-27 Massachusetts Institute Of Technology Reconfigurable footprint mechanism for omnidirectional vehicles
US5933642A (en) 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US5936424A (en) 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5960193A (en) 1993-11-30 1999-09-28 Texas Instruments Incorporated Apparatus and system for sum of plural absolute differences
US5960200A (en) 1996-05-03 1999-09-28 I-Cube System to transition an enterprise to a distributed infrastructure
US5966143A (en) 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
WO1999040522A3 (en) 1998-02-05 1999-10-14 Sheng George S Digital signal processor using a reconfigurable array of macrocells
US5978583A (en) 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
JPH11307725A (en) 1998-04-21 1999-11-05 Mitsubishi Electric Corp Semiconductor integrated circuit
US5996048A (en) 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6003143A (en) 1994-06-30 1999-12-14 Compaq Computer Corporation Tool and method for diagnosing and correcting errors in a computer program
US6011407A (en) 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US6020758A (en) 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US6020760A (en) 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6023742A (en) 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US6026478A (en) 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6026481A (en) 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US6035371A (en) 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6034538A (en) 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
JP2000076066A (en) 1998-09-02 2000-03-14 Fujitsu Ltd Signal processing circuit
US6038656A (en) 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6044030A (en) 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6045585A (en) 1995-12-29 2000-04-04 International Business Machines Corporation Method and system for determining inter-compilation unit alias information
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6049222A (en) 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6049866A (en) 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US6052524A (en) 1998-05-14 2000-04-18 Software Development Systems, Inc. System and method for simulation of integrated hardware and software components
US6055619A (en) 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6054873A (en) 1996-12-05 2000-04-25 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
US6058266A (en) 1997-06-24 2000-05-02 International Business Machines Corporation Method of, system for, and computer program product for performing weighted loop fusion by an optimizing compiler
EP0628917B1 (en) 1993-06-11 2000-05-03 Elsag Spa Multiprocessor system
US6064819A (en) 1993-12-08 2000-05-16 Imec Control flow and memory management optimization
US6072348A (en) 1997-07-09 2000-06-06 Xilinx, Inc. Programmable power reduction in a clock-distribution circuit
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6075935A (en) 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
US6077315A (en) 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
WO2000038087A1 (en) 1998-12-22 2000-06-29 Celoxica Limited Hardware/software codesign system
JP2000181566A (en) 1998-12-14 2000-06-30 Mitsubishi Electric Corp Multiclock parallel processor
US6085317A (en) 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US6084429A (en) 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6086628A (en) 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6092174A (en) 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
JP2000201066A (en) 1998-11-18 2000-07-18 Altera Corp Programmable logic device structure
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
WO2000045282A1 (en) 1999-01-28 2000-08-03 Bops Incorporated Methods and apparatus to support conditional execution in a vliw-based array processor with subword execution
US6105106A (en) 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
WO2000017771A3 (en) 1998-09-23 2000-08-17 Siemens Ag Method for configuring configurable hardware blocks
US6108760A (en) 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
WO2000049496A1 (en) 1999-02-15 2000-08-24 Koninklijke Philips Electronics N.V. Data processor with a configurable functional unit and method using such a data processor
USRE36839E (en) 1995-02-14 2000-08-29 Philips Semiconductor, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US6118724A (en) 1997-04-30 2000-09-12 Canon Kabushiki Kaisha Memory controller architecture
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US6125408A (en) 1997-03-10 2000-09-26 Compaq Computer Corporation Resource type prioritization in generating a device configuration
US6125072A (en) 1998-07-21 2000-09-26 Seagate Technology, Inc. Method and apparatus for contiguously addressing a memory system having vertically expanded multiple memory arrays
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
US6134166A (en) 1995-03-22 2000-10-17 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
JP2000311156A (en) 1999-04-27 2000-11-07 Mitsubishi Electric Corp Reconfigurable parallel computer
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US6150839A (en) 1997-12-12 2000-11-21 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6154826A (en) 1994-11-16 2000-11-28 University Of Virginia Patent Foundation Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order
US6154049A (en) 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
US6157214A (en) 1998-07-06 2000-12-05 Hewlett-Packard Company Wiring of cells in logic arrays
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6170051B1 (en) 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6173434B1 (en) 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US6173419B1 (en) 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6178494B1 (en) 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US6185256B1 (en) 1997-11-19 2001-02-06 Fujitsu Limited Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
US6185731B1 (en) 1995-04-14 2001-02-06 Mitsubishi Electric Semiconductor Software Co., Ltd. Real time debugger for a microcomputer
US6188650B1 (en) 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6188240B1 (en) 1998-06-04 2001-02-13 Nec Corporation Programmable function block
US6191614B1 (en) 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6198304B1 (en) 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
US6202163B1 (en) 1997-03-14 2001-03-13 Nokia Mobile Phones Limited Data processing circuit with gating of clocking signals to various elements of the circuit
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
US6204687B1 (en) 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6211697B1 (en) 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6212650B1 (en) 1997-11-24 2001-04-03 Xilinx, Inc. Interactive dubug tool for programmable circuits
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6219833B1 (en) 1997-12-17 2001-04-17 Hewlett-Packard Company Method of using primary and secondary processors
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US20010001860A1 (en) 1998-09-21 2001-05-24 Valeriu Beiu Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
US6240502B1 (en) 1997-06-25 2001-05-29 Sun Microsystems, Inc. Apparatus for dynamically reconfiguring a processor
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6247147B1 (en) 1997-10-27 2001-06-12 Altera Corporation Enhanced embedded logic analyzer
US20010003834A1 (en) 1999-12-08 2001-06-14 Nec Corporation Interprocessor communication method and multiprocessor
US6249756B1 (en) 1998-12-07 2001-06-19 Compaq Computer Corp. Hybrid flow control
US6252792B1 (en) 1997-01-29 2001-06-26 Elixent Limited Field programmable processor arrays
US6256724B1 (en) 1998-02-04 2001-07-03 Texas Instruments Incorporated Digital signal processor with efficiently connectable hardware co-processor
US6260114B1 (en) 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6260179B1 (en) 1997-10-23 2001-07-10 Fujitsu Limited Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US6262908B1 (en) 1997-01-29 2001-07-17 Elixent Limited Field programmable processor devices
US20010010074A1 (en) 2000-01-20 2001-07-26 Fuji Xerox Co., Ltd. Data processing method by programmable logic device, programmable logic device, information processing system and method of reconfiguring circuit in programmable logic
JP2001510650A (en) 1996-12-27 2001-07-31 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング Automatic dynamic unloading of a data flow processor (DFP) and a module with a two- or three-dimensional programmable cell structure (FPGA, DPGA, etc.)
WO2001055917A1 (en) 2000-01-27 2001-08-02 Morphics Technology Inc. Improved apparatus and method for multi-threaded signal processing
EP0686915B1 (en) 1994-05-27 2001-08-08 Nec Corporation Hierarchical resource management method
US6279077B1 (en) 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6282701B1 (en) 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US20010018733A1 (en) 2000-02-25 2001-08-30 Taro Fujii Array-type processor
JP2001236221A (en) 2000-02-21 2001-08-31 Keisuke Shindo Pipe line parallel processor using multi-thread
US6285624B1 (en) 2000-07-08 2001-09-04 Han-Ping Chen Multilevel memory access method
US6286134B1 (en) 1999-04-23 2001-09-04 Sun Microsystems, Inc. Instruction selection in a multi-platform environment
US6289369B1 (en) 1998-08-25 2001-09-11 International Business Machines Corporation Affinity, locality, and load balancing in scheduling user program-level threads for execution by a computer system
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6298472B1 (en) 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US6298396B1 (en) 1998-06-01 2001-10-02 Advanced Micro Devices, Inc. System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again
US6298043B1 (en) 1998-03-28 2001-10-02 Nortel Networks Limited Communication system architecture and a connection verification mechanism therefor
US6301706B1 (en) 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6311265B1 (en) 1996-03-25 2001-10-30 Torrent Systems, Inc. Apparatuses and methods for programming parallel computers
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6321298B1 (en) 1999-01-25 2001-11-20 International Business Machines Corporation Full cache coherency across multiple raid controllers
EP0696001B1 (en) 1994-07-22 2001-12-05 Mitsubishi Denki Kabushiki Kaisha Information processing system and method of computation performed by using an information processing system
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US20020004916A1 (en) 2000-05-12 2002-01-10 Marchand Patrick R. Methods and apparatus for power control in a scalable array of processor elements
US6339840B1 (en) 1997-06-02 2002-01-15 Iowa State University Research Foundation, Inc. Apparatus and method for parallelizing legacy computer code
US6339424B1 (en) 1997-11-18 2002-01-15 Fuji Xerox Co., Ltd Drawing processor
US6341318B1 (en) 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US20020013861A1 (en) 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US6347346B1 (en) 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US6349346B1 (en) 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6353841B1 (en) 1997-12-17 2002-03-05 Elixent, Ltd. Reconfigurable processor devices
US20020032305A1 (en) 1999-03-22 2002-03-14 Dsm N.V. Process for the preparation of polyamide granules
US6362650B1 (en) 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
WO2002029600A2 (en) 2000-10-06 2002-04-11 Pact Informationstechnologie Gmbh Cell system with segmented intermediate cell structure
US6373779B1 (en) 2000-05-19 2002-04-16 Xilinx, Inc. Block RAM having multiple configurable write modes for use in a field programmable gate array
US6374286B1 (en) 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US20020045952A1 (en) 2000-10-12 2002-04-18 Blemel Kenneth G. High performance hybrid micro-computer
DE10129237A1 (en) 2000-10-09 2002-04-18 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US6378068B1 (en) 1991-05-17 2002-04-23 Nec Corporation Suspend/resume capability for a protected mode microprocesser
US6381624B1 (en) 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
US20020051482A1 (en) 1995-06-30 2002-05-02 Lomp Gary R. Median weighted tracking for spread-spectrum communications
US6389579B1 (en) 1998-01-26 2002-05-14 Chameleon Systems Reconfigurable logic for table lookup
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US6400601B1 (en) 1999-06-30 2002-06-04 Nec Corporation Nonvolatile semiconductor memory device
WO2002021010A3 (en) 2000-09-04 2002-06-06 Continental Teves Ag & Co Ohg Operating device for an electromechanically actuated disk brake
US6404224B1 (en) 1995-12-19 2002-06-11 Fujitsu Limited Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time
US6405185B1 (en) 1992-04-06 2002-06-11 International Business Machines Corporation Massively parallel array processor
US20020073282A1 (en) 2000-08-21 2002-06-13 Gerard Chauvel Multiple microprocessors with a shared cache
EP1102674B1 (en) 1998-08-04 2002-06-19 UNICOR GmbH Rahn Plastmaschinen Device for continuously producing seamless plastic tubes
US20020083308A1 (en) 2000-12-20 2002-06-27 Bernardo De Oliveira Kastrup Pereira Data processing device with a configurable functional unit
US6421808B1 (en) 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6421809B1 (en) 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6425054B1 (en) 1996-08-19 2002-07-23 Samsung Electronics Co., Ltd. Multiprocessor operation in a multimedia signal processor
US20020099759A1 (en) 2001-01-24 2002-07-25 Gootherts Paul David Load balancer with starvation avoidance
WO2002013000A8 (en) 2000-06-13 2002-07-25 Pact Inf Tech Gmbh Pipeline configuration unit protocols and communication
US6426649B1 (en) 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US6427156B1 (en) 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US20020103839A1 (en) 2001-01-19 2002-08-01 Kunihiko Ozawa Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US6430309B1 (en) 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US6434642B1 (en) 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US6434695B1 (en) 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6434699B1 (en) 1998-02-27 2002-08-13 Mosaid Technologies Inc. Encryption processor with shared memory interconnect
US6434672B1 (en) 2000-02-29 2002-08-13 Hewlett-Packard Company Methods and apparatus for improving system performance with a shared cache memory
US6438747B1 (en) 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6437441B1 (en) 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US20020124238A1 (en) 2000-08-07 2002-09-05 Paul Metzgen Software-to-hardware compiler
US6449283B1 (en) 1998-05-15 2002-09-10 Polytechnic University Methods and apparatus for providing a fast ring reservation arbitration
EP0835685B1 (en) 1996-10-14 2002-09-18 Mitsubishi Gas Chemical Company, Inc. Oxygen absorption composition
US6456628B1 (en) 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US20020138716A1 (en) 2001-03-22 2002-09-26 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US20020143505A1 (en) 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US20020144229A1 (en) 2001-04-02 2002-10-03 Shaila Hanrahan Faster scalable floorplan which enables easier data control flow
US20020147932A1 (en) 2001-04-05 2002-10-10 International Business Machines Corporation Controlling power and performance in a multiprocessing system
US20020152060A1 (en) 1998-08-31 2002-10-17 Tseng Ping-Sheng Inter-chip communication system
US20020156962A1 (en) 1999-10-01 2002-10-24 Rajesh Chopra Microprocessor having improved memory management unit and cache memory
US20020162097A1 (en) 2000-10-13 2002-10-31 Mahmoud Meribout Compiling method, synthesizing system and recording medium
US6476634B1 (en) 2002-02-01 2002-11-05 Xilinx, Inc. ALU implementation in single PLD logic cell
US20020165886A1 (en) 2001-05-02 2002-11-07 Lam Peter Shing Fai Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US6483343B1 (en) 2000-12-29 2002-11-19 Quicklogic Corporation Configurable computational unit embedded in a programmable device
US6487709B1 (en) 2000-02-09 2002-11-26 Xilinx, Inc. Run-time routing for programmable logic devices
US6490695B1 (en) 1999-01-22 2002-12-03 Sun Microsystems, Inc. Platform independent memory image analysis architecture for debugging a computer program
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6496740B1 (en) 1999-04-21 2002-12-17 Texas Instruments Incorporated Transfer controller with hub and ports architecture
US6496902B1 (en) 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
US20030001615A1 (en) 2001-06-29 2003-01-02 Semiconductor Technology Academic Research Center Programmable logic circuit device having look up table enabling to reduce implementation area
US6507898B1 (en) 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6507947B1 (en) 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US6519674B1 (en) 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US6523107B1 (en) 1997-12-17 2003-02-18 Elixent Limited Method and apparatus for providing instruction streams to a processing device
US6525678B1 (en) 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US20030046607A1 (en) 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
US20030055861A1 (en) 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030056091A1 (en) 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US20030056202A1 (en) 2001-08-16 2003-03-20 Frank May Method for translating programs for reconfigurable architectures
US20030056062A1 (en) 2001-09-14 2003-03-20 Prabhu Manohar K. Preemptive write back controller
US20030052711A1 (en) 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
US6539477B1 (en) 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
US6539415B1 (en) 1997-09-24 2003-03-25 Sony Corporation Method and apparatus for the allocation of audio/video tasks in a network system
US6539438B1 (en) 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6538470B1 (en) 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6538468B1 (en) 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US20030061542A1 (en) 2001-09-25 2003-03-27 International Business Machines Corporation Debugger program time monitor
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US6542844B1 (en) 2000-08-02 2003-04-01 International Business Machines Corporation Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits
US20030062922A1 (en) 2001-09-28 2003-04-03 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US20030070059A1 (en) 2001-05-30 2003-04-10 Dally William J. System and method for performing efficient conditional vector operations for data parallel architectures
WO2002071249A9 (en) 2001-03-05 2003-04-10 Pact Inf Tech Gmbh Method and devices for treating and/or processing data
WO2003032975A1 (en) 2001-10-16 2003-04-24 The Trustees Of The University Of Pennsylvania Modulation of ocular growth and myopia by gaba drugs
US20030086300A1 (en) 2001-04-06 2003-05-08 Gareth Noyes FPGA coprocessing system
US6567834B1 (en) 1997-12-17 2003-05-20 Elixent Limited Implementation of multipliers in programmable arrays
US6587939B1 (en) 1999-01-13 2003-07-01 Kabushiki Kaisha Toshiba Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US20030123579A1 (en) 2001-11-16 2003-07-03 Saeid Safavi Viterbi convolutional coding method and apparatus
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6606704B1 (en) 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US20030154349A1 (en) 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
DE10204044A1 (en) 2002-02-01 2003-08-14 Tridonicatco Gmbh & Co Kg Electronic ballast for gas discharge lamp
WO2003023616A8 (en) 2001-09-03 2003-08-21 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US6625631B2 (en) 2001-09-28 2003-09-23 Intel Corporation Component reduction in montgomery multiplier processing element
US6624819B1 (en) 2000-05-01 2003-09-23 Broadcom Corporation Method and system for providing a flexible and efficient processor for use in a graphics processing system
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
US20030192032A1 (en) 1998-02-17 2003-10-09 National Instruments Corporation System and method for debugging a software program
US6633181B1 (en) 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
WO2002071196A8 (en) 2001-03-05 2003-10-30 Pact Inf Tech Gmbh Methods and devices for treating and processing data
WO2003091875A1 (en) 2002-04-23 2003-11-06 Quicksilver Techonology, Inc. Method, system and language structure for programming reconfigurable hardware
US6658564B1 (en) 1998-11-20 2003-12-02 Altera Corporation Reconfigurable programmable logic device computer system
US6657457B1 (en) 2000-03-15 2003-12-02 Intel Corporation Data transfer on reconfigurable chip
US20030226056A1 (en) 2002-05-28 2003-12-04 Michael Yip Method and system for a process manager
WO2002103532A3 (en) 2001-06-20 2003-12-11 Pact Xpp Technologies Ag Data processing method
US6665758B1 (en) 1999-10-04 2003-12-16 Ncr Corporation Software sanity monitor
US6668237B1 (en) 2002-01-17 2003-12-23 Xilinx, Inc. Run-time reconfigurable testing of programmable logic devices
US6681388B1 (en) 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US20040015899A1 (en) 2000-10-06 2004-01-22 Frank May Method for processing data
US6694434B1 (en) 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US20040039880A1 (en) 2002-08-23 2004-02-26 Vladimir Pentkovski Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US6704816B1 (en) 1999-07-26 2004-03-09 Sun Microsystems, Inc. Method and apparatus for executing standard functions in a computer system using a field programmable gate array
US6708223B1 (en) 1998-12-11 2004-03-16 Microsoft Corporation Accelerating a distributed component architecture over a network using a modified RPC communication
WO2000077652A9 (en) 1999-06-10 2004-03-25 Pact Inf Tech Gmbh Sequence partitioning in cell structures
US6717436B2 (en) 1999-09-29 2004-04-06 Infineon Technologies Ag Reconfigurable gate array
US6725334B2 (en) 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US20040078548A1 (en) 2000-12-19 2004-04-22 Claydon Anthony Peter John Processor architecture
US20040088691A1 (en) 2002-10-31 2004-05-06 Jeffrey Hammes Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
US20040088689A1 (en) 2002-10-31 2004-05-06 Jeffrey Hammes System and method for converting control flow graph representations to control-dataflow graph representations
WO2003025781A3 (en) 2001-09-19 2004-05-27 Pact Xpp Technologies Ag Router
US6745317B1 (en) 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
US6748440B1 (en) 1999-05-12 2004-06-08 Microsoft Corporation Flow of streaming data through multiple processing modules
US6754805B1 (en) 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
WO2004053718A1 (en) 2002-12-05 2004-06-24 Gemicer, Inc. Cellular engine for a data processing system
US6757892B1 (en) 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
US6757847B1 (en) 1998-12-29 2004-06-29 International Business Machines Corporation Synchronization for system analysis
WO2003036507A3 (en) 2001-09-19 2004-08-12 Pact Xpp Technologies Ag Reconfigurable elements
US6785826B1 (en) 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6802026B1 (en) 2001-05-15 2004-10-05 Xilinx, Inc. Parameterizable and reconfigurable debugger core generators
US6803787B1 (en) 2002-09-25 2004-10-12 Lattice Semiconductor Corp. State machine in a programmable logic device
WO2003017095A3 (en) 2001-08-16 2004-10-28 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US6829697B1 (en) 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US6836842B1 (en) 2001-04-24 2004-12-28 Xilinx, Inc. Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD
US6847370B2 (en) 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6871341B1 (en) 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US20050066213A1 (en) 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US6874108B1 (en) 2001-08-27 2005-03-29 Agere Systems Inc. Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US20050091468A1 (en) 2003-10-28 2005-04-28 Renesas Technology America, Inc. Processor for virtual machines and method therefor
US6901502B2 (en) 2000-12-06 2005-05-31 Matsushita Electric Industrial Co., Ltd. Integrated circuit with CPU and FPGA for reserved instructions execution with configuration diagnosis
US20050144215A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Applications of cascading DSP slices
US20050144210A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Programmable logic device with dynamic DSP architecture
US20050144212A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US6928523B2 (en) 2000-07-25 2005-08-09 Renesas Technology Corp. Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
US6957306B2 (en) 2002-09-09 2005-10-18 Broadcom Corporation System and method for controlling prefetching
US6961924B2 (en) 2002-05-21 2005-11-01 International Business Machines Corporation Displaying variable usage while debugging
US6975138B2 (en) 1996-09-04 2005-12-13 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US6977649B1 (en) 1998-11-23 2005-12-20 3Dlabs, Inc. Ltd 3D graphics rendering with selective read suspend
US7000161B1 (en) 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US20060036988A1 (en) 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7007096B1 (en) 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
WO2005045692A3 (en) 2003-08-28 2006-03-02 Pact Xpp Technologies Ag Data processing device and method
US7010687B2 (en) 2000-03-14 2006-03-07 Sony Corporation Transmission apparatus, reception apparatus, transmission method, reception method and recording medium
WO2004114128A3 (en) 2003-06-25 2006-03-09 Koninkl Philips Electronics Nv Instruction controlled data processing device
US7036114B2 (en) 2001-08-17 2006-04-25 Sun Microsystems, Inc. Method and apparatus for cycle-based computation
US7038952B1 (en) 2004-05-04 2006-05-02 Xilinx, Inc. Block RAM with embedded FIFO buffer
US20060095716A1 (en) 2004-08-30 2006-05-04 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
US7043416B1 (en) 2001-07-27 2006-05-09 Lsi Logic Corporation System and method for state restoration in a diagnostic module for a high-speed microprocessor
US20060230096A1 (en) 2003-12-29 2006-10-12 Xilinx, Inc. Digital signal processing circuit having an adder circuit with carry-outs
US20060230094A1 (en) 2003-12-29 2006-10-12 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7144152B2 (en) 2002-08-23 2006-12-05 Intel Corporation Apparatus for thermal management of multiple core microprocessors
US7164422B1 (en) 2000-07-28 2007-01-16 Ab Initio Software Corporation Parameterized graphs with conditional components
US20070050603A1 (en) 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device
US20070083730A1 (en) 2003-06-17 2007-04-12 Martin Vorbach Data processing device and method
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
WO2007030395A3 (en) 2005-09-07 2007-05-10 Internat Securities Exchange L Midpoint matching system
US20070143577A1 (en) 2002-10-16 2007-06-21 Akya (Holdings) Limited Reconfigurable integrated circuit
WO2007007269A3 (en) 2005-07-08 2007-07-05 Ioto Internat Ind E Com De Pro Agglutinant compound and agglutinated product for reconstituting powders of vegetal origin
US7249351B1 (en) 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
US7254649B2 (en) 2000-01-28 2007-08-07 Infineon Technologies Ag Wireless spread spectrum communication platform using dynamically reconfigurable logic
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US7455450B2 (en) 2005-10-07 2008-11-25 Advanced Micro Devices, Inc. Method and apparatus for temperature sensing in integrated circuits
US20090085603A1 (en) 2007-09-27 2009-04-02 Fujitsu Network Communications, Inc. FPGA configuration protection and control using hardware watchdog timer
EP1115204B1 (en) 2000-01-07 2009-04-22 Nippon Telegraph and Telephone Corporation Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
US7759968B1 (en) 2006-09-27 2010-07-20 Xilinx, Inc. Method of and system for verifying configuration data
US20100306602A1 (en) 2009-05-28 2010-12-02 Nec Electronics Corporation Semiconductor device and abnormality detecting method
US7873811B1 (en) 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US574827A (en) * 1897-01-05 Cask-pitching apparatus
US5512366A (en) * 1989-11-14 1996-04-30 Mitsubishi Denki Kabushiki Kaisha Magneto-optic recording medium and apparatus
US6865663B2 (en) 2000-02-24 2005-03-08 Pts Corporation Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
US6802206B2 (en) 2002-10-11 2004-10-12 American Axle & Manufacturing, Inc. Torsional actuation NVH test method

Patent Citations (780)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2067477A (en) 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
US3242998A (en) 1962-05-28 1966-03-29 Wolf Electric Tools Ltd Electrically driven equipment
US3564506A (en) 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US3681578A (en) 1969-11-21 1972-08-01 Marconi Co Ltd Fault location and reconfiguration in redundant data processors
US3753008A (en) 1970-06-20 1973-08-14 Honeywell Inf Systems Memory pre-driver circuit
US3757608A (en) 1970-11-21 1973-09-11 Bhs Bayerische Berg Solar and planetary gear system with load pressure compensation
US5602999A (en) 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US3754211A (en) 1971-12-30 1973-08-21 Ibm Fast error recovery communication controller
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US3956589A (en) 1973-11-26 1976-05-11 Paradyne Corporation Data telecommunication system
US4151611A (en) 1976-03-26 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Power supply control system for memory systems
JPS5858672B2 (en) 1976-10-20 1983-12-26 東ソー株式会社 electroluminescent display board
US4233667A (en) 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4414547A (en) 1981-08-05 1983-11-08 General Instrument Corporation Storage logic array having two conductor data column
US4498134A (en) 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4590583A (en) 1982-07-16 1986-05-20 At&T Bell Laboratories Coin telephone measurement circuitry
US4498172A (en) 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4667190A (en) 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
US4591979A (en) 1982-08-25 1986-05-27 Nec Corporation Data-flow-type digital processing apparatus
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4594682A (en) 1982-12-22 1986-06-10 Ibm Corporation Vector processing
US4739474A (en) 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4566102A (en) 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US5123109A (en) 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US4571736A (en) 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4646300A (en) 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4870302A (en) 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4686386A (en) 1984-03-21 1987-08-11 Oki Electric Industry Co., Ltd. Power-down circuits for dynamic MOS integrated circuits
US4761755A (en) 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4623997A (en) 1984-12-13 1986-11-18 United Technologies Corporation Coherent interface with wraparound receive and transmit memories
US5065308A (en) 1985-01-29 1991-11-12 The Secretary Of State For Defence In Her Britannic Magesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Processing cell for fault tolerant arrays
US4720778A (en) 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5247689A (en) 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5485104A (en) 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US5015884A (en) 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4972314A (en) 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4967340A (en) 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
EP0208457A3 (en) 1985-07-09 1988-11-02 National Research Development Corporation A processor array
US4748580A (en) 1985-08-30 1988-05-31 Advanced Micro Devices, Inc. Multi-precision fixed/floating-point processor
US4720780A (en) 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
EP0221350A1 (en) 1985-11-01 1987-05-13 Energy Conversion Devices, Inc. Electrolevelled substrate for electrophotographic photoreceptors and method of fabricating same
EP0221360B1 (en) 1985-11-04 1992-12-30 International Business Machines Corporation Digital data message transmission networks and the establishing of communication paths therein
US5070475A (en) 1985-11-14 1991-12-03 Data General Corporation Floating point unit interface
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US5021947A (en) 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US4882687A (en) 1986-03-31 1989-11-21 Schlumberger Technology Corporation Pixel processor
US5034914A (en) 1986-05-15 1991-07-23 Aquidneck Systems International, Inc. Optical disk data storage method and apparatus with buffered interface
US4852043A (en) 1986-05-21 1989-07-25 Hewlett-Packard Company Daisy-chain bus system with truncation circuitry for failsoft bypass of defective sub-bus subsystem
US4760525A (en) * 1986-06-10 1988-07-26 The United States Of America As Represented By The Secretary Of The Air Force Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4791603A (en) 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US4910665A (en) 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US5510730A (en) 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US5600265A (en) 1986-09-19 1997-02-04 Actel Corporation Programmable interconnect architecture
US4884231A (en) 1986-09-26 1989-11-28 Performance Semiconductor Corporation Microprocessor system with extended arithmetic logic unit
US4992933A (en) 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US4891810A (en) 1986-10-31 1990-01-02 Thomson-Csf Reconfigurable computing device
US4918440A (en) 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4811214A (en) 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5226122A (en) 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
DE3855673T2 (en) 1987-08-28 1997-05-07 Ibm System part reconfiguration triggered by peripheral devices
US5119290A (en) 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US4873666A (en) 1987-10-14 1989-10-10 Northern Telecom Limited Message FIFO buffer controller
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5081575A (en) 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5031179A (en) 1987-11-10 1991-07-09 Canon Kabushiki Kaisha Data communication apparatus
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
US5844888A (en) 1987-11-10 1998-12-01 Echelon Corporation Network and intelligent cell for providing sensing, bidirectional communications and control
US5103311A (en) 1988-01-11 1992-04-07 U.S. Philips Corporation Data processing module and video processing system incorporating same
USRE34444E (en) 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
US5055997A (en) 1988-01-13 1991-10-08 U.S. Philips Corporation System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch
US5627992A (en) 1988-01-20 1997-05-06 Advanced Micro Devices Organization of an integrated cache unit for flexible usage in supporting microprocessor operations
US5303172A (en) 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
JPH01229378A (en) 1988-03-09 1989-09-13 Fujitsu Ltd Picture data storage device
US4959781A (en) 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US5047924A (en) 1988-06-30 1991-09-10 Mitsubishi Denki Kabushiki Kaisha Microcomputer
US4939641A (en) 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
US5287511A (en) 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5675757A (en) 1988-07-22 1997-10-07 Davidson; George S. Direct match data flow memory for data driven computing
US5010401A (en) 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US5204935A (en) 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US4901268A (en) 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
US5043978A (en) 1988-09-22 1991-08-27 Siemens Aktiengesellschaft Circuit arrangement for telecommunications exchanges
US5036473A (en) 1988-10-05 1991-07-30 Mentor Graphics Corporation Method of using electronically reconfigurable logic circuits
US5421019A (en) 1988-10-07 1995-05-30 Martin Marietta Corporation Parallel data processor
US5014193A (en) 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
WO1990004835A1 (en) 1988-10-19 1990-05-03 Wendt Hans J Digital computer with multiprocessor arrangement
JPH02130023A (en) 1988-11-10 1990-05-18 Fujitsu Ltd Multifunction programmable logic device
US5418952A (en) 1988-11-23 1995-05-23 Flavors Technology Inc. Parallel processor cell computer system
US5041924A (en) 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
JPH02226423A (en) 1989-01-12 1990-09-10 Internatl Business Mach Corp <Ibm> Microcode controller
US5081375A (en) 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5245616A (en) 1989-02-24 1993-09-14 Rosemount Inc. Technique for acknowledging packets
US5243238A (en) 1989-03-17 1993-09-07 Algotronix Limited Configurable cellular array
WO1990011648A1 (en) 1989-03-17 1990-10-04 Algotronix Limited Configurable cellular array
US5491353A (en) 1989-03-17 1996-02-13 Xilinx, Inc. Configurable cellular array
JPH0786921B2 (en) 1989-04-20 1995-09-20 富士写真フイルム株式会社 Method and apparatus for energy subtraction of radiation image
US5287472A (en) 1989-05-02 1994-02-15 Tandem Computers Incorporated Memory system using linear array wafer scale integration architecture
US5203005A (en) 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
EP0398552B1 (en) 1989-05-02 1996-03-13 Tandem Computers Incorporated Linear array wafer scale integration architecture
US5237686A (en) 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
US5109503A (en) 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
US5072178A (en) 1989-06-09 1991-12-10 Hitachi, Ltd. Method and apparatus for testing logic circuitry by applying a logical test pattern
US5379444A (en) 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
US5343406A (en) 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5422823A (en) 1989-08-15 1995-06-06 Advanced Micro Devices, Inc. Programmable gate array device having cascaded means for function definition
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5586044A (en) 1989-08-15 1996-12-17 Advanced Micro Devices, Inc. Array of configurable logic blocks including cascadable lookup tables
US5587921A (en) 1989-08-15 1996-12-24 Advanced Micro Devices, Inc. Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer
US5128559A (en) 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
US5511173A (en) 1989-11-08 1996-04-23 Ricoh Co., Ltd. Programmable logic array and data processing unit using the same
EP0428327A1 (en) 1989-11-14 1991-05-22 Amt(Holdings) Limited Processor array system
US5287532A (en) 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
US5212777A (en) 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5410723A (en) 1989-11-21 1995-04-25 Deutsche Itt Industries Gmbh Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell
US5099447A (en) 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5675777A (en) 1990-01-29 1997-10-07 Hipercore, Inc. Architecture for minimal instruction set computing system
US5125801A (en) 1990-02-02 1992-06-30 Isco, Inc. Pumping system
US5036493A (en) 1990-03-15 1991-07-30 Digital Equipment Corporation System and method for reducing power usage by multiple memory modules
US5142469A (en) 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5801958A (en) 1990-04-06 1998-09-01 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
EP0463721A3 (en) 1990-04-30 1993-06-16 Gennum Corporation Digital signal processing device
US5355508A (en) 1990-05-07 1994-10-11 Mitsubishi Denki Kabushiki Kaisha Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller
US5440245A (en) 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5483620A (en) 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
JPH05509184A (en) 1990-05-29 1993-12-16 ウエーブトレーサー インコーポレイテッド Virtual processing address and instruction generator for parallel processor arrays
US5193202A (en) 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
EP0735685A3 (en) 1990-06-29 1996-11-13 STMicroelectronics, Inc. Programmable power reduction circuit for programmable logic device
US5568624A (en) 1990-06-29 1996-10-22 Digital Equipment Corporation Byte-compare operation for high-performance processor
WO1992001987A1 (en) 1990-07-16 1992-02-06 Tekstar Systems Corporation Interface system for data transfer with remote peripheral independently of host processor backplane
US5555434A (en) 1990-08-02 1996-09-10 Carlstedt Elektronik Ab Computing device employing a reduction processor and implementing a declarative language
US5784630A (en) 1990-09-07 1998-07-21 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
EP0477809B1 (en) 1990-09-28 1997-12-17 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5076482A (en) 1990-10-05 1991-12-31 The Fletcher Terry Company Pneumatic point driver
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5717943A (en) 1990-11-13 1998-02-10 International Business Machines Corporation Advanced parallel array processor (APAP)
US5713037A (en) 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5754871A (en) 1990-11-13 1998-05-19 International Business Machines Corporation Parallel processing system having asynchronous SIMD processing
US5617577A (en) 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5794059A (en) 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5590345A (en) 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5588152A (en) 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
EP0485690B1 (en) 1990-11-13 1999-05-26 International Business Machines Corporation Parallel associative processor system
US5924119A (en) 1990-11-30 1999-07-13 Xerox Corporation Consistent packet switched memory bus for shared memory multiprocessors
US5696976A (en) 1990-12-21 1997-12-09 Intel Corporation Protocol for interrupt bus arbitration in a multi-processor system
US5276836A (en) 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5301284A (en) 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
EP0497029A2 (en) 1991-01-29 1992-08-05 Analogic Corporation Reconfigurable sequential processor
US5301344A (en) 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US5408643A (en) 1991-02-01 1995-04-18 Nec Corporation Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared
US5212716A (en) 1991-02-05 1993-05-18 International Business Machines Corporation Data edge phase sorting circuits
US5218302A (en) 1991-02-06 1993-06-08 Sun Electric Corporation Interface for coupling an analyzer to a distributorless ignition system
US5475583A (en) 1991-02-22 1995-12-12 Siemens Aktiengesellschaft Programmable control system including a logic module and a method for programming
US5544336A (en) 1991-03-19 1996-08-06 Fujitsu Limited Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US5506998A (en) 1991-03-20 1996-04-09 Fujitsu Limited Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data
US5617547A (en) 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
EP0539595A1 (en) 1991-04-09 1993-05-05 Fujitsu Limited Data processor and data processing method
EP0539595A4 (en) 1991-04-09 1994-07-20 Fujitsu Ltd Data processor and data processing method
US5717890A (en) 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US6378068B1 (en) 1991-05-17 2002-04-23 Nec Corporation Suspend/resume capability for a protected mode microprocesser
US5442790A (en) 1991-05-24 1995-08-15 The Trustees Of Princeton University Optimizing compiler for computers
US5659797A (en) 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US5754820A (en) 1991-07-09 1998-05-19 Kabushiki Kaisha Toshiba Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5336950A (en) 1991-08-29 1994-08-09 National Semiconductor Corporation Configuration features in a configurable logic array
US5581731A (en) 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5828229A (en) 1991-09-03 1998-10-27 Altera Corporation Programmable logic array integrated circuits
US5485103A (en) 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5294119A (en) 1991-09-27 1994-03-15 Taylor Made Golf Company, Inc. Vibration-damping device for a golf club
US5475856A (en) 1991-11-27 1995-12-12 International Business Machines Corporation Dynamic multi-mode parallel processing array
JPH05276007A (en) 1991-11-27 1993-10-22 Philips Gloeilampenfab:Nv Integrated circuit device
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
US5801715A (en) 1991-12-06 1998-09-01 Norman; Richard S. Massively-parallel processor array with outputs from individual processors directly to an external device without involving other processors or a common physical carrier
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5465375A (en) 1992-01-14 1995-11-07 France Telecom Multiprocessor system with cascaded modules combining processors through a programmable logic cell array
US5412795A (en) 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US5867691A (en) 1992-03-13 1999-02-02 Kabushiki Kaisha Toshiba Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
JPH05265705A (en) 1992-03-23 1993-10-15 Nippon Telegr & Teleph Corp <Ntt> Digital processing circuit
US5655124A (en) 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US6405185B1 (en) 1992-04-06 2002-06-11 International Business Machines Corporation Massively parallel array processor
US5493663A (en) 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5682544A (en) 1992-05-12 1997-10-28 International Business Machines Corporation Massively parallel diagonal-fold tree array processor
US5611049A (en) 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
US5521837A (en) 1992-06-04 1996-05-28 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
DE4221278C2 (en) 1992-06-29 1996-02-29 Martin Vorbach Bus-linked multi-computer system
US5475803A (en) 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
US5327125A (en) 1992-07-13 1994-07-05 Sharp Kabushiki Kaisha Apparatus for and method of converting a sampling frequency according to a data driven type processing
US5365125A (en) 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5386154A (en) 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5802290A (en) 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US6289440B1 (en) 1992-07-29 2001-09-11 Virtual Computer Corporation Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs
US5489857A (en) 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5867723A (en) 1992-08-05 1999-02-02 Sarnoff Corporation Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
WO1994006077A1 (en) 1992-08-28 1994-03-17 Siemens Aktiengesellschaft Computer system with at least one microprocessor and at least one coprocessor, and a method of operating the system
US5477525A (en) 1992-09-03 1995-12-19 Sony Corporation Data destruction preventing method, recording apparatus provided with data destruction preventing capability, and disc recorded with guard band
US5572710A (en) 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5530873A (en) 1992-10-02 1996-06-25 Hudson Soft Co. Ltd. Method and apparatus for processing interruption
WO1994008399A1 (en) 1992-10-05 1994-04-14 Lattice Semiconductor Corporation Arrangement for parallel programming of in-system programmable ic logic devices
US5857109A (en) 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5831448A (en) 1992-11-05 1998-11-03 Xilinx, Inc. Function unit for fine-gained FPGA
US5497498A (en) 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5469003A (en) 1992-11-05 1995-11-21 Xilinx, Inc. Hierarchically connectable configurable cellular array
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5634131A (en) 1992-11-06 1997-05-27 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5311079A (en) 1992-12-17 1994-05-10 Ditlow Gary S Low power, high performance PLA
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
US5386518A (en) 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5473267A (en) 1993-02-16 1995-12-05 Sgs-Thomson Microelectronics Limited Programmable logic device with memory that can store routing data of logic data
JPH06266605A (en) 1993-03-16 1994-09-22 Yokogawa Medical Syst Ltd Storage device
US5448186A (en) 1993-03-18 1995-09-05 Fuji Xerox Co., Ltd. Field-programmable gate array
US5548773A (en) 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5596742A (en) 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5418953A (en) 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US5473266A (en) 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
US5606698A (en) 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
JPH07154242A (en) 1993-05-13 1995-06-16 Texas Instr Inc <Ti> Programmable logic array circuit
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Method for operating a data processing device
US5435000A (en) 1993-05-19 1995-07-18 Bull Hn Information Systems Inc. Central processing unit using dual basic processing units and combined result bus
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
EP0628917B1 (en) 1993-06-11 2000-05-03 Elsag Spa Multiprocessor system
WO1995000161A1 (en) 1993-06-18 1995-01-05 University Of Cincinnati Neuropeptide y antagonists and agonists
US5768629A (en) 1993-06-24 1998-06-16 Discovision Associates Token-based adaptive video processing arrangement
US5444394A (en) 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
US5537601A (en) 1993-07-21 1996-07-16 Hitachi, Ltd. Programmable digital signal processor for performing a plurality of signal processings
US5581734A (en) 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
EP0638867A2 (en) 1993-08-12 1995-02-15 Hughes Aircraft Company Dynamically reconfigurable interprocessor communication network for SIMD multi-processors and apparatus implementing same
US6145072A (en) 1993-08-12 2000-11-07 Hughes Electronics Corporation Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same
US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5525971A (en) 1993-09-23 1996-06-11 Advanced Risc Machines Limited Integrated circuit
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
JPH07182160A (en) 1993-10-29 1995-07-21 Advanced Micro Devicds Inc Superscalar microprocessor
JPH07182167A (en) 1993-10-29 1995-07-21 Advanced Micro Devicds Inc Loading/storing function unit of microprocessor and apparatus for information processing
US5960193A (en) 1993-11-30 1999-09-28 Texas Instruments Incorporated Apparatus and system for sum of plural absolute differences
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US6064819A (en) 1993-12-08 2000-05-16 Imec Control flow and memory management optimization
US5535406A (en) 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
JPH08101761A (en) 1994-02-17 1996-04-16 Pilkington Germany Number 2 Ltd Reconstitutable application-specific device
US5748872A (en) 1994-03-22 1998-05-05 Norman; Richard S. Direct replacement cell fault tolerant architecture
WO1995026001A1 (en) 1994-03-22 1995-09-28 Norman Richard S Efficient direct cell replacement fault tolerant architecture supporting completely integrated systems with means for direct communication with system operator
US5574927A (en) 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US5561738A (en) 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5504439A (en) 1994-04-01 1996-04-02 Xilinx, Inc. I/O interface cell for use with optional pad
US5430687A (en) 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5781756A (en) 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5887162A (en) 1994-04-15 1999-03-23 Micron Technology, Inc. Memory device having circuitry for initializing and reprogramming a control operation feature
US5426378A (en) 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
EP0678985B1 (en) 1994-04-20 2006-03-01 Xilinx, Inc. A programmable logic device which stores more than one configuration and means for switching configurations
US5502838A (en) 1994-04-28 1996-03-26 Consilium Overseas Limited Temperature management for integrated circuits
US5677909A (en) 1994-05-11 1997-10-14 Spectrix Corporation Apparatus for exchanging data between a central station and a plurality of wireless remote stations on a time divided commnication channel
EP0686915B1 (en) 1994-05-27 2001-08-08 Nec Corporation Hierarchical resource management method
US5532693A (en) 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
US6003143A (en) 1994-06-30 1999-12-14 Compaq Computer Corporation Tool and method for diagnosing and correcting errors in a computer program
EP0696001B1 (en) 1994-07-22 2001-12-05 Mitsubishi Denki Kabushiki Kaisha Information processing system and method of computation performed by using an information processing system
US5600845A (en) 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
JPH0844581A (en) 1994-07-29 1996-02-16 Fujitsu Ltd Information processor with self-repairing function
US5655069A (en) 1994-07-29 1997-08-05 Fujitsu Limited Apparatus having a plurality of programmable logic processing units for self-repair
JPH08102492A (en) 1994-08-02 1996-04-16 Toshiba Corp Programmable wiring circuit and test board device
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
JPH0869447A (en) 1994-08-31 1996-03-12 Toshiba Corp Data processor
US5513366A (en) 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5619720A (en) 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
JPH08106443A (en) 1994-10-05 1996-04-23 Hitachi Ltd Data processing system and parallel computer
US5450022A (en) 1994-10-07 1995-09-12 Xilinx Inc. Structure and method for configuration of a field programmable gate array
EP0707269A1 (en) 1994-10-11 1996-04-17 International Business Machines Corporation Cache coherence network for a multiprocessor data processing system
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5815726A (en) 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US5657330A (en) 1994-11-15 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Single-chip microprocessor with built-in self-testing function
US6154826A (en) 1994-11-16 2000-11-28 University Of Virginia Patent Foundation Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order
JPH08148989A (en) 1994-11-18 1996-06-07 Hitachi Ltd Superconducting fpga device
US5584013A (en) 1994-12-09 1996-12-10 International Business Machines Corporation Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
US5625806A (en) 1994-12-12 1997-04-29 Advanced Micro Devices, Inc. Self configuring speed path in a microprocessor with multiple clock option
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5603005A (en) 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5754876A (en) 1994-12-28 1998-05-19 Hitachi, Ltd. Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5778237A (en) 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5696791A (en) 1995-01-17 1997-12-09 Vtech Industries, Inc. Apparatus and method for decoding a sequence of digitally encoded data
US5493239A (en) 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5532957A (en) 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
EP0726532B1 (en) 1995-02-10 2000-07-26 International Business Machines Corporation Array processor communication architecture with broadcast instructions
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5742180A (en) * 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
JPH08221164A (en) 1995-02-14 1996-08-30 Kumamoto Techno Porisu Zaidan Trial manufacture supporting device, substrate for ic mounting, and bus device
USRE36839E (en) 1995-02-14 2000-08-29 Philips Semiconductor, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US5862403A (en) 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5675743A (en) 1995-02-22 1997-10-07 Callisto Media Systems Inc. Multi-media server
JPH08250685A (en) 1995-03-08 1996-09-27 Nippon Telegr & Teleph Corp <Ntt> Programmable gate array
US6134166A (en) 1995-03-22 2000-10-17 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5570040A (en) 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US6185731B1 (en) 1995-04-14 2001-02-06 Mitsubishi Electric Semiconductor Software Co., Ltd. Real time debugger for a microcomputer
US6077315A (en) 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
US6058469A (en) 1995-04-17 2000-05-02 Ricoh Corporation System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5794062A (en) 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5933642A (en) 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US6026481A (en) 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
USRE37195E1 (en) 1995-05-02 2001-05-29 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5701091A (en) 1995-05-02 1997-12-23 Xilinx, Inc. Routing resources for hierarchical FPGA
US5705938A (en) 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5600597A (en) 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
US5541530A (en) 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5649179A (en) 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5821774A (en) 1995-05-26 1998-10-13 Xilinx, Inc. Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
US5706482A (en) 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5870620A (en) 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
US5652529A (en) 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
JPH0927745A (en) 1995-06-02 1997-01-28 Internatl Business Mach Corp <Ibm> Programmable array clock/reset
EP0746106A3 (en) 1995-06-02 1997-11-19 International Business Machines Corporation Programmable array I/O - routing resource
EP0748051A2 (en) 1995-06-05 1996-12-11 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5646544A (en) 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
EP0748051A3 (en) 1995-06-05 1997-12-17 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5815715A (en) 1995-06-05 1998-09-29 Motorola, Inc. Method for designing a product having hardware and software components and product therefor
US20020051482A1 (en) 1995-06-30 2002-05-02 Lomp Gary R. Median weighted tracking for spread-spectrum communications
US5889982A (en) 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5559450A (en) 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
US5978583A (en) 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
US6321373B1 (en) 1995-08-07 2001-11-20 International Business Machines Corporation Method for resource control in parallel environments using program organization and run-time support
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
GB2304438A (en) 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
US6480954B2 (en) 1995-08-18 2002-11-12 Xilinx Inc. Method of time multiplexing a programmable logic device
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5978260A (en) 1995-08-18 1999-11-02 Xilinx, Inc. Method of time multiplexing a programmable logic device
US5583450A (en) 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
US6263430B1 (en) 1995-08-18 2001-07-17 Xilinx, Inc. Method of time multiplexing a programmable logic device
US5778439A (en) 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5784313A (en) 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US20020010853A1 (en) 1995-08-18 2002-01-24 Xilinx, Inc. Method of time multiplexing a programmable logic device
US5737565A (en) 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US5737516A (en) 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
US5734869A (en) 1995-09-06 1998-03-31 Chen; Duan-Ping High speed logic circuit simulator
US6430309B1 (en) 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5745734A (en) 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5754827A (en) 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5815004A (en) 1995-10-16 1998-09-29 Xilinx, Inc. Multi-buffered configurable logic block output lines in a field programmable gate array
US5642058A (en) 1995-10-16 1997-06-24 Xilinx , Inc. Periphery input/output interconnect structure
US5608342A (en) 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5675262A (en) 1995-10-26 1997-10-07 Xilinx, Inc. Fast carry-out scheme in a field programmable gate array
US5656950A (en) 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US6859869B1 (en) 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US5732209A (en) 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US5773994A (en) 1995-12-15 1998-06-30 Cypress Semiconductor Corp. Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
US6404224B1 (en) 1995-12-19 2002-06-11 Fujitsu Limited Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time
US6045585A (en) 1995-12-29 2000-04-04 International Business Machines Corporation Method and system for determining inter-compilation unit alias information
US5804986A (en) 1995-12-29 1998-09-08 Cypress Semiconductor Corp. Memory in a programmable logic device
US5848238A (en) 1996-01-12 1998-12-08 Hitachi, Ltd. Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them
US5760602A (en) 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
US5926638A (en) 1996-01-17 1999-07-20 Nec Corporation Program debugging system for debugging a program having graphical user interface
US5854918A (en) 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5898602A (en) 1996-01-25 1999-04-27 Xilinx, Inc. Carry chain circuit with flexible carry function for implementing arithmetic and logical functions
US5635851A (en) 1996-02-02 1997-06-03 Xilinx, Inc. Read and writable data bus particularly for programmable logic devices
US5936424A (en) 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5727229A (en) 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
US5889533A (en) 1996-02-17 1999-03-30 Samsung Electronics Co., Ltd. First-in-first-out device for graphic drawing engine
JPH09237284A (en) 1996-02-29 1997-09-09 Nec Corp Logic circuit division system
JPH09294069A (en) 1996-03-01 1997-11-11 Agency Of Ind Science & Technol Programmable lsi and its arithmetic method
US5801547A (en) 1996-03-01 1998-09-01 Xilinx, Inc. Embedded memory for field programmable gate array
US6020758A (en) 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US5841973A (en) 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US6279077B1 (en) 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6311265B1 (en) 1996-03-25 2001-10-30 Torrent Systems, Inc. Apparatuses and methods for programming parallel computers
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US6266760B1 (en) 1996-04-11 2001-07-24 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5687325A (en) 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US6173434B1 (en) 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5960200A (en) 1996-05-03 1999-09-28 I-Cube System to transition an enterprise to a distributed infrastructure
US6014509A (en) 1996-05-20 2000-01-11 Atmel Corporation Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US5894565A (en) 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5784636A (en) 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5892370A (en) 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
US5887165A (en) 1996-06-21 1999-03-23 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US6785826B1 (en) 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6023742A (en) 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6105105A (en) 1996-07-19 2000-08-15 Xilinx, Inc. Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
US6023564A (en) 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
FR2752466B1 (en) 1996-08-19 2005-01-07 Samsung Electronics Co Ltd INTEGRATED PROCESSOR DEVICE FOR DIGITAL SIGNALS
US6425054B1 (en) 1996-08-19 2002-07-23 Samsung Electronics Co., Ltd. Multiprocessor operation in a multimedia signal processor
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
WO1998010517A1 (en) 1996-09-03 1998-03-12 Xilinx, Inc. Fpga architecture having ram blocks with programmable word length and width and dedicated address and data lines
JP2001500682A (en) 1996-09-03 2001-01-16 ザイリンクス・インコーポレイテッド FPGA architecture with RAM blocks having programmable word length and width and dedicated address and data lines
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US7382156B2 (en) 1996-09-04 2008-06-03 Actel Corporation Method and apparatus for universal program controlled bus architecture
US6975138B2 (en) 1996-09-04 2005-12-13 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US5859544A (en) 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US6049866A (en) 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US5915099A (en) 1996-09-13 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Bus interface unit in a microprocessor for facilitating internal and external memory accesses
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US6178494B1 (en) 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US5694602A (en) 1996-10-01 1997-12-02 The United States Of America As Represented By The Secretary Of The Air Force Weighted system and method for spatial allocation of a parallel load
EP0835685B1 (en) 1996-10-14 2002-09-18 Mitsubishi Gas Chemical Company, Inc. Oxygen absorption composition
US5901279A (en) 1996-10-18 1999-05-04 Hughes Electronics Corporation Connection of spares between multiple programmable devices
US5832288A (en) 1996-10-18 1998-11-03 Samsung Electronics Co., Ltd. Element-select mechanism for a vector processor
US5892962A (en) 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US5895487A (en) 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US5844422A (en) 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US5860119A (en) 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US6054873A (en) 1996-12-05 2000-04-25 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
US20030056085A1 (en) 1996-12-09 2003-03-20 Entire Interest Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
US6728871B1 (en) 1996-12-09 2004-04-27 Pact Xpp Technologies Ag Runtime configurable arithmetic and logic cell
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
WO1998026356A1 (en) 1996-12-09 1998-06-18 Pact Informationstechnologie Gmbh Unit for processing numeric and logical operations, for use in processors (cpus) and in multicomputer systems
US6425068B1 (en) 1996-12-09 2002-07-23 Pact Gmbh Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US7237087B2 (en) 1996-12-09 2007-06-26 Pact Xpp Technologies Ag Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells
US20040168099A1 (en) 1996-12-09 2004-08-26 Martin Vorbach Unit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems
US5913925A (en) 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
WO1998028697A1 (en) 1996-12-20 1998-07-02 Pact Informationstechnologie Gmbh IO- AND MEMORY BUS SYSTEM FOR DFPs AS UNITS WITH TWO- OR MULTI-DIMENSIONALLY PROGRAMMABLE CELL STRUCTURES
US6721830B2 (en) 1996-12-20 2004-04-13 Pact Xpp Technologies Ag I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
WO1998031102A1 (en) 1996-12-20 1998-07-16 Pact Informationstechnologie Gmbh Reconfiguration method for programmable components during running time
US7650448B2 (en) 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US6513077B2 (en) 1996-12-20 2003-01-28 Pact Gmbh I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US6021490A (en) 1996-12-20 2000-02-01 Pact Gmbh Run-time reconfiguration method for programmable units
US6119181A (en) 1996-12-20 2000-09-12 Pact Gmbh I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US20030097513A1 (en) 1996-12-20 2003-05-22 Martin Vorbach l/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US20040199688A1 (en) 1996-12-20 2004-10-07 Martin Vorbach I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
EP1146432B1 (en) 1996-12-20 2010-06-09 Richter, Thomas Reconfiguration method for programmable components during runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
JP2001510650A (en) 1996-12-27 2001-07-31 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング Automatic dynamic unloading of a data flow processor (DFP) and a module with a two- or three-dimensional programmable cell structure (FPGA, DPGA, etc.)
US6477643B1 (en) 1996-12-27 2002-11-05 Pact Gmbh Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US20030093662A1 (en) 1996-12-27 2003-05-15 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US7028107B2 (en) 1996-12-27 2006-04-11 Pact Xpp Technologies Ag Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
WO1998029952A1 (en) 1996-12-27 1998-07-09 Pact Informationstechnologie Gmbh METHOD FOR AUTOMATIC DYNAMIC UNLOADING OF DATA FLOW PROCESSORS (DFP) AS WELL AS MODULES WITH BIDIMENSIONAL OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURES (EPGAs, DPGAs OR THE LIKE)
US6088795A (en) 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US6427156B1 (en) 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US6542394B2 (en) 1997-01-29 2003-04-01 Elixent Limited Field programmable processor arrays
US6252792B1 (en) 1997-01-29 2001-06-26 Elixent Limited Field programmable processor arrays
US6262908B1 (en) 1997-01-29 2001-07-17 Elixent Limited Field programmable processor devices
US6038650A (en) 1997-02-04 2000-03-14 Pactgmbh Method for the automatic address generation of modules within clusters comprised of a plurality of these modules
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US5865239A (en) 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
US6055619A (en) 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6526520B1 (en) 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
EP1669885A3 (en) 1997-02-08 2007-09-12 PACT XPP Technologies AG Method for self-synchronization of configurable elements of a programmable component
WO1998035299A3 (en) 1997-02-08 1998-09-17 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable component
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
US6081903A (en) 1997-02-08 2000-06-27 Pact Gmbh Method of the self-synchronization of configurable elements of a programmable unit
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
US20030135686A1 (en) 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US7010667B2 (en) 1997-02-11 2006-03-07 Pact Xpp Technologies Ag Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
WO1998035294A3 (en) 1997-02-11 1998-10-22 Pact Inf Tech Gmbh Internal bus system for dfps, building blocks with two dimensional or multidimensional programmable cell structures to handle large amounts of data involving high networking requirements
US6405299B1 (en) 1997-02-11 2002-06-11 Pact Gmbh Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5927423A (en) 1997-03-05 1999-07-27 Massachusetts Institute Of Technology Reconfigurable footprint mechanism for omnidirectional vehicles
US5884075A (en) 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US6125408A (en) 1997-03-10 2000-09-26 Compaq Computer Corporation Resource type prioritization in generating a device configuration
US5857097A (en) 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US6202163B1 (en) 1997-03-14 2001-03-13 Nokia Mobile Phones Limited Data processing circuit with gating of clocking signals to various elements of the circuit
US6507898B1 (en) 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6118724A (en) 1997-04-30 2000-09-12 Canon Kabushiki Kaisha Memory controller architecture
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
JPH1146187A (en) 1997-05-27 1999-02-16 Uniden Corp Data transmission method and data transmission device
US6035371A (en) 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6339840B1 (en) 1997-06-02 2002-01-15 Iowa State University Research Foundation, Inc. Apparatus and method for parallelizing legacy computer code
US6011407A (en) 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5996048A (en) 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6058266A (en) 1997-06-24 2000-05-02 International Business Machines Corporation Method of, system for, and computer program product for performing weighted loop fusion by an optimizing compiler
US6240502B1 (en) 1997-06-25 2001-05-29 Sun Microsystems, Inc. Apparatus for dynamically reconfiguring a processor
US5838988A (en) 1997-06-25 1998-11-17 Sun Microsystems, Inc. Computer product for precise architectural update in an out-of-order processor
WO1999000731A1 (en) 1997-06-27 1999-01-07 Chameleon Systems, Inc. Method for compiling high level programming languages
US6708325B2 (en) 1997-06-27 2004-03-16 Intel Corporation Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic
US5966534A (en) 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US20030014743A1 (en) 1997-06-27 2003-01-16 Cooke Laurence H. Method for compiling high level programming languages
WO1999000739A1 (en) 1997-06-27 1999-01-07 Chameleon Systems, Inc. An integrated processor and programmable data path chip for reconfigurable computing
US6072348A (en) 1997-07-09 2000-06-06 Xilinx, Inc. Programmable power reduction in a clock-distribution circuit
US6437441B1 (en) 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6020760A (en) 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6282701B1 (en) 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US6170051B1 (en) 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6026478A (en) 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6085317A (en) 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US6078736A (en) 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
WO1999012111B1 (en) 1997-08-28 1999-04-15 Xilinx Inc A method of designing fpgas for dynamically reconfigurable computing
US6038656A (en) 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
DE19822776A1 (en) 1997-09-19 1999-03-25 Mitsubishi Electric Corp Data processing arrangement
US6539415B1 (en) 1997-09-24 2003-03-25 Sony Corporation Method and apparatus for the allocation of audio/video tasks in a network system
US5966143A (en) 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
US6188650B1 (en) 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6260179B1 (en) 1997-10-23 2001-07-10 Fujitsu Limited Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US6247147B1 (en) 1997-10-27 2001-06-12 Altera Corporation Enhanced embedded logic analyzer
US6751722B2 (en) 1997-10-31 2004-06-15 Broadcom Corporation Local control of multiple context processing elements with configuration contexts
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6553479B2 (en) 1997-10-31 2003-04-22 Broadcom Corporation Local control of multiple context processing elements with major contexts and minor contexts
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US6457116B1 (en) 1997-10-31 2002-09-24 Broadcom Corporation Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements
US6108760A (en) 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
US6339424B1 (en) 1997-11-18 2002-01-15 Fuji Xerox Co., Ltd Drawing processor
US6185256B1 (en) 1997-11-19 2001-02-06 Fujitsu Limited Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
US6212650B1 (en) 1997-11-24 2001-04-03 Xilinx, Inc. Interactive dubug tool for programmable circuits
US6075935A (en) 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
US6150839A (en) 1997-12-12 2000-11-21 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6219833B1 (en) 1997-12-17 2001-04-17 Hewlett-Packard Company Method of using primary and secondary processors
US6567834B1 (en) 1997-12-17 2003-05-20 Elixent Limited Implementation of multipliers in programmable arrays
US6553395B2 (en) 1997-12-17 2003-04-22 Elixent, Ltd. Reconfigurable processor devices
US6523107B1 (en) 1997-12-17 2003-02-18 Elixent Limited Method and apparatus for providing instruction streams to a processing device
EP0926594B1 (en) 1997-12-17 2007-05-23 Hewlett-Packard Company, A Delaware Corporation Method of using primary and secondary processors
US6820188B2 (en) 1997-12-17 2004-11-16 Elixent Limited Method and apparatus for varying instruction streams provided to a processing device using masks
US6353841B1 (en) 1997-12-17 2002-03-05 Elixent, Ltd. Reconfigurable processor devices
JPH11184718A (en) 1997-12-19 1999-07-09 Matsushita Electric Ind Co Ltd Programmable data processor
WO1999032975A1 (en) 1997-12-22 1999-07-01 Pact Informationstechnologie Gmbh Process for repairing integrated circuits
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
US6697979B1 (en) 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6049222A (en) 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6260114B1 (en) 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6516382B2 (en) 1997-12-31 2003-02-04 Micron Technology, Inc. Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times
US6301706B1 (en) 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6105106A (en) 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6034538A (en) 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US6389579B1 (en) 1998-01-26 2002-05-14 Chameleon Systems Reconfigurable logic for table lookup
US6256724B1 (en) 1998-02-04 2001-07-03 Texas Instruments Incorporated Digital signal processor with efficiently connectable hardware co-processor
WO1999040522A3 (en) 1998-02-05 1999-10-14 Sheng George S Digital signal processor using a reconfigurable array of macrocells
US6086628A (en) 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US20030192032A1 (en) 1998-02-17 2003-10-09 National Instruments Corporation System and method for debugging a software program
US6198304B1 (en) 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6480937B1 (en) 1998-02-25 2002-11-12 Pact Informationstechnologie Gmbh Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
WO1999044147A3 (en) 1998-02-25 1999-10-28 Pact Inf Tech Gmbh METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
US6571381B1 (en) 1998-02-25 2003-05-27 Pact Xpp Technologies Ag Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
WO1999044120A3 (en) 1998-02-25 1999-11-11 Pact Inf Tech Gmbh METHOD FOR CONFIGURING DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) WITHOUT PRODUCING DEADLOCKS
US6687788B2 (en) 1998-02-25 2004-02-03 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US6434699B1 (en) 1998-02-27 2002-08-13 Mosaid Technologies Inc. Encryption processor with shared memory interconnect
US6154049A (en) 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
US6298043B1 (en) 1998-03-28 2001-10-02 Nortel Networks Limited Communication system architecture and a connection verification mechanism therefor
US6374286B1 (en) 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6456628B1 (en) 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
JPH11307725A (en) 1998-04-21 1999-11-05 Mitsubishi Electric Corp Semiconductor integrated circuit
US6084429A (en) 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6421808B1 (en) 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6052524A (en) 1998-05-14 2000-04-18 Software Development Systems, Inc. System and method for simulation of integrated hardware and software components
US6173419B1 (en) 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6449283B1 (en) 1998-05-15 2002-09-10 Polytechnic University Methods and apparatus for providing a fast ring reservation arbitration
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6092174A (en) 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
US6298396B1 (en) 1998-06-01 2001-10-02 Advanced Micro Devices, Inc. System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again
US6188240B1 (en) 1998-06-04 2001-02-13 Nec Corporation Programmable function block
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
US6157214A (en) 1998-07-06 2000-12-05 Hewlett-Packard Company Wiring of cells in logic arrays
US6125072A (en) 1998-07-21 2000-09-26 Seagate Technology, Inc. Method and apparatus for contiguously addressing a memory system having vertically expanded multiple memory arrays
US6421809B1 (en) 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
EP1102674B1 (en) 1998-08-04 2002-06-19 UNICOR GmbH Rahn Plastmaschinen Device for continuously producing seamless plastic tubes
US6201406B1 (en) 1998-08-04 2001-03-13 Xilinx, Inc. FPGA configurable by two types of bitstreams
US6154048A (en) 1998-08-04 2000-11-28 Xilinx, Inc. Structure and method for loading narrow frames of data from a wide input bus
US6289369B1 (en) 1998-08-25 2001-09-11 International Business Machines Corporation Affinity, locality, and load balancing in scheduling user program-level threads for execution by a computer system
US20020152060A1 (en) 1998-08-31 2002-10-17 Tseng Ping-Sheng Inter-chip communication system
JP2000076066A (en) 1998-09-02 2000-03-14 Fujitsu Ltd Signal processing circuit
US20010001860A1 (en) 1998-09-21 2001-05-24 Valeriu Beiu Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
WO2000017771A3 (en) 1998-09-23 2000-08-17 Siemens Ag Method for configuring configurable hardware blocks
US6681388B1 (en) 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
JP2000201066A (en) 1998-11-18 2000-07-18 Altera Corp Programmable logic device structure
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
US6658564B1 (en) 1998-11-20 2003-12-02 Altera Corporation Reconfigurable programmable logic device computer system
US6977649B1 (en) 1998-11-23 2005-12-20 3Dlabs, Inc. Ltd 3D graphics rendering with selective read suspend
US6249756B1 (en) 1998-12-07 2001-06-19 Compaq Computer Corp. Hybrid flow control
US6708223B1 (en) 1998-12-11 2004-03-16 Microsoft Corporation Accelerating a distributed component architecture over a network using a modified RPC communication
JP2000181566A (en) 1998-12-14 2000-06-30 Mitsubishi Electric Corp Multiclock parallel processor
US6044030A (en) 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
WO2000038087A1 (en) 1998-12-22 2000-06-29 Celoxica Limited Hardware/software codesign system
US6434695B1 (en) 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6694434B1 (en) 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US6757847B1 (en) 1998-12-29 2004-06-29 International Business Machines Corporation Synchronization for system analysis
US6496902B1 (en) 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
US6587939B1 (en) 1999-01-13 2003-07-01 Kabushiki Kaisha Toshiba Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US6539438B1 (en) 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6490695B1 (en) 1999-01-22 2002-12-03 Sun Microsystems, Inc. Platform independent memory image analysis architecture for debugging a computer program
US6321298B1 (en) 1999-01-25 2001-11-20 International Business Machines Corporation Full cache coherency across multiple raid controllers
WO2000045282A1 (en) 1999-01-28 2000-08-03 Bops Incorporated Methods and apparatus to support conditional execution in a vliw-based array processor with subword execution
WO2000049496A1 (en) 1999-02-15 2000-08-24 Koninklijke Philips Electronics N.V. Data processor with a configurable functional unit and method using such a data processor
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US20020032305A1 (en) 1999-03-22 2002-03-14 Dsm N.V. Process for the preparation of polyamide granules
US6191614B1 (en) 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6496740B1 (en) 1999-04-21 2002-12-17 Texas Instruments Incorporated Transfer controller with hub and ports architecture
US6286134B1 (en) 1999-04-23 2001-09-04 Sun Microsystems, Inc. Instruction selection in a multi-platform environment
JP2000311156A (en) 1999-04-27 2000-11-07 Mitsubishi Electric Corp Reconfigurable parallel computer
US6381624B1 (en) 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
US6298472B1 (en) 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US6748440B1 (en) 1999-05-12 2004-06-08 Microsoft Corporation Flow of streaming data through multiple processing modules
US7007096B1 (en) 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US6211697B1 (en) 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6504398B1 (en) 1999-05-25 2003-01-07 Actel Corporation Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
WO2000077652A9 (en) 1999-06-10 2004-03-25 Pact Inf Tech Gmbh Sequence partitioning in cell structures
US6782445B1 (en) 1999-06-15 2004-08-24 Hewlett-Packard Development Company, L.P. Memory and instructions in computer architecture containing processor and coprocessor
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6757892B1 (en) 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
US6400601B1 (en) 1999-06-30 2002-06-04 Nec Corporation Nonvolatile semiconductor memory device
US20020038414A1 (en) 1999-06-30 2002-03-28 Taylor Bradley L. Address generator for local system memory in reconfigurable logic chip
US6347346B1 (en) 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6704816B1 (en) 1999-07-26 2004-03-09 Sun Microsystems, Inc. Method and apparatus for executing standard functions in a computer system using a field programmable gate array
US6745317B1 (en) 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
US6341318B1 (en) 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6204687B1 (en) 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6438747B1 (en) 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6507947B1 (en) 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6606704B1 (en) 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6349346B1 (en) 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
US6717436B2 (en) 1999-09-29 2004-04-06 Infineon Technologies Ag Reconfigurable gate array
US20020156962A1 (en) 1999-10-01 2002-10-24 Rajesh Chopra Microprocessor having improved memory management unit and cache memory
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6665758B1 (en) 1999-10-04 2003-12-16 Ncr Corporation Software sanity monitor
US6434642B1 (en) 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
JP2001167066A (en) 1999-12-08 2001-06-22 Nec Corp Inter-processor communication method and multiprocessor system
US20010003834A1 (en) 1999-12-08 2001-06-14 Nec Corporation Interprocessor communication method and multiprocessor
US20020013861A1 (en) 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US6633181B1 (en) 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
EP1115204B1 (en) 2000-01-07 2009-04-22 Nippon Telegraph and Telephone Corporation Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
US20010010074A1 (en) 2000-01-20 2001-07-26 Fuji Xerox Co., Ltd. Data processing method by programmable logic device, programmable logic device, information processing system and method of reconfiguring circuit in programmable logic
WO2001055917A1 (en) 2000-01-27 2001-08-02 Morphics Technology Inc. Improved apparatus and method for multi-threaded signal processing
US7254649B2 (en) 2000-01-28 2007-08-07 Infineon Technologies Ag Wireless spread spectrum communication platform using dynamically reconfigurable logic
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6487709B1 (en) 2000-02-09 2002-11-26 Xilinx, Inc. Run-time routing for programmable logic devices
US6519674B1 (en) 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
JP2001236221A (en) 2000-02-21 2001-08-31 Keisuke Shindo Pipe line parallel processor using multi-thread
US20010018733A1 (en) 2000-02-25 2001-08-30 Taro Fujii Array-type processor
US6434672B1 (en) 2000-02-29 2002-08-13 Hewlett-Packard Company Methods and apparatus for improving system performance with a shared cache memory
US6539477B1 (en) 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
US7010687B2 (en) 2000-03-14 2006-03-07 Sony Corporation Transmission apparatus, reception apparatus, transmission method, reception method and recording medium
US6657457B1 (en) 2000-03-15 2003-12-02 Intel Corporation Data transfer on reconfigurable chip
US6871341B1 (en) 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US6624819B1 (en) 2000-05-01 2003-09-23 Broadcom Corporation Method and system for providing a flexible and efficient processor for use in a graphics processing system
US20020004916A1 (en) 2000-05-12 2002-01-10 Marchand Patrick R. Methods and apparatus for power control in a scalable array of processor elements
US6362650B1 (en) 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6373779B1 (en) 2000-05-19 2002-04-16 Xilinx, Inc. Block RAM having multiple configurable write modes for use in a field programmable gate array
US6725334B2 (en) 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US7350178B1 (en) 2000-06-12 2008-03-25 Altera Corporation Embedded processor with watchdog timer for programmable logic
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
US20040025005A1 (en) 2000-06-13 2004-02-05 Martin Vorbach Pipeline configuration unit protocols and communication
WO2002013000A8 (en) 2000-06-13 2002-07-25 Pact Inf Tech Gmbh Pipeline configuration unit protocols and communication
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
US6285624B1 (en) 2000-07-08 2001-09-04 Han-Ping Chen Multilevel memory access method
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US6928523B2 (en) 2000-07-25 2005-08-09 Renesas Technology Corp. Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
US7164422B1 (en) 2000-07-28 2007-01-16 Ab Initio Software Corporation Parameterized graphs with conditional components
US6538468B1 (en) 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US6542844B1 (en) 2000-08-02 2003-04-01 International Business Machines Corporation Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits
US6754805B1 (en) 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
US20020124238A1 (en) 2000-08-07 2002-09-05 Paul Metzgen Software-to-hardware compiler
US20020073282A1 (en) 2000-08-21 2002-06-13 Gerard Chauvel Multiple microprocessors with a shared cache
US7249351B1 (en) 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
WO2002021010A3 (en) 2000-09-04 2002-06-06 Continental Teves Ag & Co Ohg Operating device for an electromechanically actuated disk brake
US6829697B1 (en) 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6538470B1 (en) 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
WO2002029600A2 (en) 2000-10-06 2002-04-11 Pact Informationstechnologie Gmbh Cell system with segmented intermediate cell structure
US6525678B1 (en) 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US20040015899A1 (en) 2000-10-06 2004-01-22 Frank May Method for processing data
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
DE10129237A1 (en) 2000-10-09 2002-04-18 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US20020045952A1 (en) 2000-10-12 2002-04-18 Blemel Kenneth G. High performance hybrid micro-computer
US20020162097A1 (en) 2000-10-13 2002-10-31 Mahmoud Meribout Compiling method, synthesizing system and recording medium
US6901502B2 (en) 2000-12-06 2005-05-31 Matsushita Electric Industrial Co., Ltd. Integrated circuit with CPU and FPGA for reserved instructions execution with configuration diagnosis
US20040078548A1 (en) 2000-12-19 2004-04-22 Claydon Anthony Peter John Processor architecture
WO2002050665A1 (en) 2000-12-20 2002-06-27 Koninklijke Philips Electronics N.V. Data processing device with a configurable functional unit
US20020083308A1 (en) 2000-12-20 2002-06-27 Bernardo De Oliveira Kastrup Pereira Data processing device with a configurable functional unit
US6483343B1 (en) 2000-12-29 2002-11-19 Quicklogic Corporation Configurable computational unit embedded in a programmable device
US6426649B1 (en) 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US20020103839A1 (en) 2001-01-19 2002-08-01 Kunihiko Ozawa Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US20020099759A1 (en) 2001-01-24 2002-07-25 Gootherts Paul David Load balancer with starvation avoidance
US6847370B2 (en) 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
WO2002071248A8 (en) 2001-03-05 2004-01-29 Pact Inf Tech Gmbh Methods and devices for treating and/or processing data
WO2002071196A8 (en) 2001-03-05 2003-10-30 Pact Inf Tech Gmbh Methods and devices for treating and processing data
WO2002071249A9 (en) 2001-03-05 2003-04-10 Pact Inf Tech Gmbh Method and devices for treating and/or processing data
US20050066213A1 (en) 2001-03-05 2005-03-24 Martin Vorbach Methods and devices for treating and processing data
US20020138716A1 (en) 2001-03-22 2002-09-26 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US20020143505A1 (en) 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US20020144229A1 (en) 2001-04-02 2002-10-03 Shaila Hanrahan Faster scalable floorplan which enables easier data control flow
US20020147932A1 (en) 2001-04-05 2002-10-10 International Business Machines Corporation Controlling power and performance in a multiprocessing system
US20030086300A1 (en) 2001-04-06 2003-05-08 Gareth Noyes FPGA coprocessing system
US6836842B1 (en) 2001-04-24 2004-12-28 Xilinx, Inc. Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD
US20020165886A1 (en) 2001-05-02 2002-11-07 Lam Peter Shing Fai Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US6802026B1 (en) 2001-05-15 2004-10-05 Xilinx, Inc. Parameterizable and reconfigurable debugger core generators
US20030070059A1 (en) 2001-05-30 2003-04-10 Dally William J. System and method for performing efficient conditional vector operations for data parallel architectures
US20060036988A1 (en) 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
WO2002103532A3 (en) 2001-06-20 2003-12-11 Pact Xpp Technologies Ag Data processing method
US20030001615A1 (en) 2001-06-29 2003-01-02 Semiconductor Technology Academic Research Center Programmable logic circuit device having look up table enabling to reduce implementation area
US7043416B1 (en) 2001-07-27 2006-05-09 Lsi Logic Corporation System and method for state restoration in a diagnostic module for a high-speed microprocessor
US20030056202A1 (en) 2001-08-16 2003-03-20 Frank May Method for translating programs for reconfigurable architectures
WO2003017095A3 (en) 2001-08-16 2004-10-28 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7036114B2 (en) 2001-08-17 2006-04-25 Sun Microsystems, Inc. Method and apparatus for cycle-based computation
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US6874108B1 (en) 2001-08-27 2005-03-29 Agere Systems Inc. Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US20030046607A1 (en) 2001-09-03 2003-03-06 Frank May Method for debugging reconfigurable architectures
WO2003023616A8 (en) 2001-09-03 2003-08-21 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US20030056062A1 (en) 2001-09-14 2003-03-20 Prabhu Manohar K. Preemptive write back controller
US20030056091A1 (en) 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US20030055861A1 (en) 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
WO2003036507A3 (en) 2001-09-19 2004-08-12 Pact Xpp Technologies Ag Reconfigurable elements
WO2003025781A3 (en) 2001-09-19 2004-05-27 Pact Xpp Technologies Ag Router
US20030061542A1 (en) 2001-09-25 2003-03-27 International Business Machines Corporation Debugger program time monitor
US6625631B2 (en) 2001-09-28 2003-09-23 Intel Corporation Component reduction in montgomery multiplier processing element
US20030062922A1 (en) 2001-09-28 2003-04-03 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US7000161B1 (en) 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
WO2003032975A1 (en) 2001-10-16 2003-04-24 The Trustees Of The University Of Pennsylvania Modulation of ocular growth and myopia by gaba drugs
US20030123579A1 (en) 2001-11-16 2003-07-03 Saeid Safavi Viterbi convolutional coding method and apparatus
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6668237B1 (en) 2002-01-17 2003-12-23 Xilinx, Inc. Run-time reconfigurable testing of programmable logic devices
US20030154349A1 (en) 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
US6476634B1 (en) 2002-02-01 2002-11-05 Xilinx, Inc. ALU implementation in single PLD logic cell
DE10204044A1 (en) 2002-02-01 2003-08-14 Tridonicatco Gmbh & Co Kg Electronic ballast for gas discharge lamp
WO2003091875A1 (en) 2002-04-23 2003-11-06 Quicksilver Techonology, Inc. Method, system and language structure for programming reconfigurable hardware
US6961924B2 (en) 2002-05-21 2005-11-01 International Business Machines Corporation Displaying variable usage while debugging
US20030226056A1 (en) 2002-05-28 2003-12-04 Michael Yip Method and system for a process manager
US20070050603A1 (en) 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device
US20040039880A1 (en) 2002-08-23 2004-02-26 Vladimir Pentkovski Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US7144152B2 (en) 2002-08-23 2006-12-05 Intel Corporation Apparatus for thermal management of multiple core microprocessors
US6957306B2 (en) 2002-09-09 2005-10-18 Broadcom Corporation System and method for controlling prefetching
US6803787B1 (en) 2002-09-25 2004-10-12 Lattice Semiconductor Corp. State machine in a programmable logic device
US20070143577A1 (en) 2002-10-16 2007-06-21 Akya (Holdings) Limited Reconfigurable integrated circuit
US20040088691A1 (en) 2002-10-31 2004-05-06 Jeffrey Hammes Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
US20040088689A1 (en) 2002-10-31 2004-05-06 Jeffrey Hammes System and method for converting control flow graph representations to control-dataflow graph representations
US7155708B2 (en) 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
WO2004053718A1 (en) 2002-12-05 2004-06-24 Gemicer, Inc. Cellular engine for a data processing system
US7873811B1 (en) 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric
US20070083730A1 (en) 2003-06-17 2007-04-12 Martin Vorbach Data processing device and method
WO2004114128A3 (en) 2003-06-25 2006-03-09 Koninkl Philips Electronics Nv Instruction controlled data processing device
WO2005045692A3 (en) 2003-08-28 2006-03-02 Pact Xpp Technologies Ag Data processing device and method
US20080313383A1 (en) 2003-10-28 2008-12-18 Renesas Technology America, Inc. Processor for Virtual Machines and Method Therefor
US20050091468A1 (en) 2003-10-28 2005-04-28 Renesas Technology America, Inc. Processor for virtual machines and method therefor
US20060230094A1 (en) 2003-12-29 2006-10-12 Xilinx, Inc. Digital signal processing circuit having input register blocks
US20050144210A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Programmable logic device with dynamic DSP architecture
US20060230096A1 (en) 2003-12-29 2006-10-12 Xilinx, Inc. Digital signal processing circuit having an adder circuit with carry-outs
US20050144212A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US20050144215A1 (en) 2003-12-29 2005-06-30 Xilinx, Inc. Applications of cascading DSP slices
US7038952B1 (en) 2004-05-04 2006-05-02 Xilinx, Inc. Block RAM with embedded FIFO buffer
US20060095716A1 (en) 2004-08-30 2006-05-04 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
WO2007007269A3 (en) 2005-07-08 2007-07-05 Ioto Internat Ind E Com De Pro Agglutinant compound and agglutinated product for reconstituting powders of vegetal origin
WO2007030395A3 (en) 2005-09-07 2007-05-10 Internat Securities Exchange L Midpoint matching system
US7455450B2 (en) 2005-10-07 2008-11-25 Advanced Micro Devices, Inc. Method and apparatus for temperature sensing in integrated circuits
US7759968B1 (en) 2006-09-27 2010-07-20 Xilinx, Inc. Method of and system for verifying configuration data
US20090085603A1 (en) 2007-09-27 2009-04-02 Fujitsu Network Communications, Inc. FPGA configuration protection and control using hardware watchdog timer
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
US20100306602A1 (en) 2009-05-28 2010-12-02 Nec Electronics Corporation Semiconductor device and abnormality detecting method

Non-Patent Citations (456)

* Cited by examiner, † Cited by third party
Title
"BlueGene/L: the next generation of scalable supercomputer," Kissel et al., Lawrence Livermore National Laboratory, Livermore, California, Nov. 18, 2002, 29 pages.
"BlueGene/L—Hardware Architecture Overview," BlueGene/L design team, IBM Research, Oct. 17, 2003 slide presentation, pp. 1-23.
"IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Std. 1149.1-1990,1993, pp. 1-127.
A Dictionary of Computing, Fourth Edition, Oxford University Press, 1997, 4 pages.
Abnous et al., "Ultra-Low-Power Domain-Specific Multimedia Processors," U.C. Berkeley, 1996 IEEE, pp. 461-470.
Abnous, A., et al., "The Pleiades Architecture," Chapter 1 of The Application of Programmable DSPs in Mobile Communications, A. Gatherer and A. Auslander, Ed., Wiley, 2002, pp. 1-33.
Ade, et al., "Minimum Memory Buffers in DSP Applications," Electronics Letters, vol. 30, No. 6, Mar. 17, 1994, pp. 469-471.
Advanced RISC Machines Ltd (ARM), "AMBA-Advanced Microcontroller Bus Architecture Specification," (Document No. ARM IHI 0001C), Sep. 1995, 72 pages.
Advanced RISC Machines, "Introduction to AMBA," Oct. 1996, Section 1, pp. 1-7.
Agarwal, A., et al., "April: A Processor Architecture for Multiprocessing," Laboratory for Computer Science, MIT, Cambridge, MA, IEEE 1990, pp. 104-114.
Agreed and Disputed Terms, Exhibit 17 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-16.
Albaharna, O.T. et al., "On the Viability of FPGA-Based Integrated Coprocessors," Dept. of Electrical and Electronic Engineering, Imperial College of Science, London, 1999 IEEE, pp. 206-215.
Alfke, Peter, Xilinx Application Note, "Dynamic Reconfiguration," XAPP 093, Nov. 10, 1997, pp. 13-45 through 13-46.
Alfke, Peter, Xilinx Application Note, "Megabit FIFO in Two Chips: One LCA Device and One DRAM," XAPP 030.000, 1994, pp. 8-148 through 8-150.
Alfke, Peter; New, Bernie, Xilinx Application Note, "Adders, Subtracters and Accumulators in XC3000," XAPP 022.000, 1994, pp. 8-98 through 8-104.
Alfke, Peter; New, Bernie, Xilinx Application Note, "Additional XC3000 Data," XAPP 024.000, 1994, pp. 8-11 through 8-20.
Alfke, Peter; New, Bernie, Xilinx Application Note, "Implementing State Machines in LCA Devices," XAPP 027.001, 1994, pp. 8-169 through 8-172.
Algotronix, Ltd., CAL4096 Datasheet, 1992, pp. 1-53.
Algotronix, Ltd., CAL64K Preliminary Data Sheet, Apr. 1989, pp. 1-24.
Algotronix, Ltd., CHS2×4 User Manual, "CHA2×4 Custom Computer," 1991, pp. 1-38.
Alippi, C., et al., Determining the Optimum Extended Institution Set Architecture for Application Specific Reconfigurable VLIW CPUs, IEEE., 2001, pp. 50-56.
Alippi, et al., "Determining the Optimum Extended Instruction Set Architecture for Application Specific Reconfigurable VLIW CPUs," IEEE, 2001, pp. 50-56.
Allaire, Bill; Fischer, Bud, Xilinx Application Note, "Block Adaptive Filter," XAPP 055, Aug. 15, 1996 (Version 1.0), pp. 1-10.
Almasi and Gottlieb, Highly Parallel Computing, The Benjamin/Cummings Publishing Company, Inc., Redwood City, CA, 1989, 3 pages (Fig. 4.1).
Altera Application Note (73), "Implementing FIR Filters in FLEX Devices," Altera Corporation, Feb. 1998, ver. 1.01, pp. 1-23.
Altera, "2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices," Altera Corporation, Jul. 2005, 28 pages.
Altera, "APEX 20K Programmable Logic Device Family," Altera Corporation Data Sheet, Mar. 2004, ver. 5.1, pp. 1-117.
Altera, "APEX II Programmable Logic Device Family," Altera Corporation Data Sheet, Aug. 2002, Ver. 3.0, 99 pages.
Altera, "Flex 10K Embedded Programmable Logic Device Family," Altera Corporation Data Sheet, Jan. 2003, pp. 1-128.
Altera, "Flex 8000 Programmable Logic Device Family," Altera Corporation Data Sheet, Jan. 2003, pp. 1-62.
Altera, "Implementing High-Speed Search Applications with Altera CAM," Jul. 2001, Ver. 2.1, Application Note 119, 50 pages.
Amendment from File History of U.S. Appl. No. 10/156,397, filed May 28, 2002, Exhibit 25 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-12.
Amendment from File History of U.S. Appl. No. 10/265,846, filed Oct. 7, 2002, Exhibit 40 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas,'2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-12.
Amendment from File History of U.S. Appl. No. 10/791,501, filed Mar. 1, 2004, Exhibit 39 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-9.
Amendment from File History of U.S. Appl. No. 11/246,617, filed Oct. 7, 2005, Exhibit 26 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-9.
Amendment, Response from File History of U. S. Patent Application U.S. Appl. No. 10/156,397, filed May 28, 2002, Exhibit 15 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-137.
Application from File History of U.S. Appl. No. 08/544,435, filed Nov. 17, 1995, Exhibit 20 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-102.
Arabi et al., "PLD Integrates Dedicated High-speed Data Buffering, Complex State Machine, and Fast Decode Array," conference record on WESCON '93, Sep, 28, 1993, pp. 432-436.
Arabi, et al., "PLD Integrates Dedicated High-speed Data Buffering, Complex State machine, and Fast Decode Array," conference record on WESCON '93, Sep. 28, 1993, pp. 432-436.
Arm Limited, "ARM Architecture Reference Manual," Dec. 6, 2000, pp. A10-6-A10-7.
ARM, "The Architecture for the Digital World," http://www.arm.com/products/ Mar. 18,.2009, 3 pages.
ARM, "The Architecture for the Digital World; Milestones," http://www.arm.com/aboutarm/milestones.html Mar. 18, 2009, 5 pages.
Asari, K. et al., "FeRAM circuit technology for system on a chip," Proceedings First NASA/DoD Workshop on Evolvable Hardware (1999), pp. 193-197.
Athanas et al., "Processor Reconfiguration Through Instruction-Set Metamorphosis," 1993, IEEE Computers, pp. 11-18.
Athanas P. "A Functional Reconfigurable Architecture and Compiler for Adoptive Computing,", IEEE, pp. 49-55.
Athanas, "A Functional Reconfigurable Architecture and Compiler for Adoptive Computing," IEEE 1993, pp. 49-55.
Athanas, et al., "An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Recongifugation," IEEE, Laboratory for Engineering man/Machine Systems Division of Engineering, Box D, Brown University, Providence, Rhode Island, 1991, pp. 397-400.
Athanas, P. (Thesis), "An adaptive machine architecture and compiler for dynamic processor reconfiguration," Brown University 1992, pp. 1-157.
Athanas, P. et al., "An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration", IEEE, Laboratory for Engineering Man/Machine Systems Division of Engineering, Box D, Brown University Providence, Rhode Island, 1991, pp. 397-400.
Athanas, Peter, et al., "IEEE Symposium on FPGAs For Custom Computing Machines," IEEE Computer Society Press, Apr. 19-21, 1995, pp. i-vii, 1-222.
Atmel Corporation, Atmel 5-K- 50K Gates Coprocessor FPGA and FreeRAM, (www.atmel.com), Apr. 2002 , pp. 1-68.
Atmel, "An Introduction to DSP Applications using the AT4OK FPGA," FPGA Application Engineering, San Jose, CA, Apr. 2004, 15 pages.
Atmel, 5-K-50K Gates Coprocessor FPGA with Free Ram, Data Sheet, Jul. 2006, 55 pages.
Atmel, Configurable Logic Design & Application Book, Atmel Corporation, 1995, pp. 2-19 through 2-25.
Atmel, Field Programmable Gate Array Configuration Guide, AT6000 Series Configuration Data Sheet, Sep. 1999, pp. 1-20.
Atmel, FPGA-based FIR Filter Application Note, Sep. 1999, 10 pages.
Bacon, D. et al., "Compiler Transformations for High-Performance Computing," ACM Computing Surveys, 26(4):325-420 (1994).
Bakkes, P.J., et al., "Mixing Fixed and Reconfigurable Logic for Array Processing," Dept. of Electrical and Electronic Engineering, University of Stellenbosch, South Africa, 1996 IEEE, pp. 118-125.
Ballagh et al., "Java Debug Hardware Models Using JBits," 8th Reconfigurable Architectures Workshop, 2001, 8 pages.
Baumgarte, et al., PACT XPP "A Self-reconfigurable Data Processing Architecture," PACT Info. GmbH, Munchen Germany 2001.
Baumgarte, V. et al., "PACT XPP—A Self-reconfigurable Data Processing Architecture," PACT Info. GmbH, Munchen Germany, 2001, 7 pages.
Beck et al., "From control flow to data flow," TR 89-1050, Oct. 1989, Dept. of Computer Science, Cornell University, Ithaca, NY, pp. 1-25.
Becker et al., "Automatic Parallelism Exploitation for FPL—Based Accelerators," 1998, Proc. 31st Annual Hawaii International Conference on System Sciences, pp. 169-178.
Becker, et al., "Parallelization in Co-compilation for Configurable Accelerators—a Host/accelerator Partitioning Compilation Method," proceedings of Asia and South Pacific Desing Automation Conference, Yokohama, Japan, Feb. 10-13, 1998.
Becker, J. et al., "Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC)," IEEE Computer Society Annual Workshop on VLSI (WVLSI 2003) (Feb. 2003), 6 pages.
Becker, J. et al., "Parallelization in Co-compilation for Configurable Accelerators—a Host/accelerator Partitioning Compilation Method," Proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, Feb. 10-13, 1998, 11 pages.
Becker, J., "A Partitioning Compiler for Computers with Xputer-based Accelerators," 1997, Kaiserslautern University, 326 pp.
Becker, J., "Configurable Systems-on-Chip (CSoC)," (Invited Tutorial), Proc. of 9th Proc. of XV Brazilian Symposium on Integrated Circuit, Design (SBCCI 2002), (Sep. 2002), 6 pages.
Bellows et al., "Designing Run-Time Reconfigurable Systems with JHDL," Journal of VLSI Signal Processing 28, Kluwer Academic Publishers, The Netherlands, 2001, pp. 29-45.
Berkeley Design Technology, Inc., Buyer's Guide to DSP Processors, 1995, Fremont, CA., pp. 673-698.
Bittner, "Wormhole Run-time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System," Dissertation, Jan. 23, 1997, pp. I-XX, 1-415.
Bittner, R. et al., "Colt: An Experiment in Wormhole Run-Time Reconfiguration," Bradley Department of Electrical and Computer Engineering, Blacksburg, VA, SPIE-International Society for Optical Engineering, vol. 2914/187, Nov. 1996, Boston, MA, pp. 187-194.
Bittner, Ray, A., Jr., "Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing system," Disseratation, Jan. 23, 1997, pp. i-xx, 1-415.
BlueGene Project Update, Jan. 2002, IBM slide presentation, 20 pages.
BlueGene/L, "An Overview of the BlueGene/L Supercomputer," The BlueGene/L Team, IBM and Lawrence Livermore National Laboratory, 2002 IEEE. pp. 1-22.
Bolsens, Ivo (CTO Xilinx), "FPGA, a history of interconnect," Xilinx slide presentation, posted on the internet Oct. 30, 2008 at http://www.doestoc.com/docs/2198008/FPGA-a-historv-of-interconnect, 32 pages.
Bondalapati et al., "Reconfigurable Meshes: Theory and Practice," Dept. of Electrical Engineering-Systems, Univ. of Southern California, Apr. 1997, Reconfigurable Architectures Workshop, International Parallel Processing Symposium, 15 pages.
Bratt, A, "Motorola field programmable analogue arrays, present hardware and future trends," Motorola Programmable Technology Centre, Gadbrook Business Centre, Northwich, Cheshire, 1998, The Institute of Electrical Engineers, IEE. Savoy Place, London, pp. 1-5.
Cadambi, et al., "Management Pipeline-reconfigurable FPGAs," ACM, 1998, pp. 55-64.
Cadambi, et al., "Managing Pipeline-reconfigurable FPGAs," ACM, 1998, pp. 55-64.
Callahan, et al., "The Garp Architecture and C Compiler," Computer, Apr. 2000, pp. 62-69.
Callahan, T. et al. "The Garp Architecture and C Copiler," Computer, Apr. 2000, pp. 62-69.
Camilleri, Nick; Lockhard, Chris, Xilinx Application Note, "Improving XC4000 Design Performance," XAPP 043.000, 1994, pp. 8-21 through 8-35.
Cardoso, "Compilation Systems of Java™ Algorithms onto Reconfigurable Computing Systems with Exploitation of Operation-Level Parallelism," Ph.D. Thesis, Universidade Technica de Lisboa (UTL), Lisbon, Portugal Oct. 2000 (English Abstract included).
Cardoso, J.M.P., "Compilation of Java™ Algorithms onto Reconfigurable Computing Systems with Exploitation of Operation-Level Parallelism," Ph.D. Thesis, Universidade Tecnica de Lisboa (UTL), Lisbon, Portugal Oct. 2000.
Cardoso, J.M.P., et al., "A novel algorithm combining temporal partitioning and sharing of functional units," University of Algarve, Faro, Portugal, 2001 IEEE, pp. 1-10.
Cardoso, J.M.P., et al., "Compilation and Temporal Partitioning for a Coarse-Grain Reconfigurable Architecture," New Algorithms, Architectures and Applications for Reconfigurable Computing, Lysacht, P. & Rosentiel, W. eds., (2005) pp. 105-115.
Cardoso, J.M.P., et al., "Macro-Based Hardware Compilation of Java™0 Bytecodes into a Dynamic Reconfigurable Computing System," IEEE, Apr. 21, 1999, pp. 2-11.
Cardoso, Joao M.P., and Markus Weinhardt, "XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture," Field-Programmable Logic and Applications. Reconfigurable Computing is Going Mainstream, 12th International Conference FPL 2002, Proceedings (Lecture Notes in Computer Science, vol. 2438) Springer-Verlag Berlin, Germany, 2002, pp. 864-874.
Cartier, Lois, Xilinx Application Note, "System Design with New XC4000EX I/O Features," Feb. 21, 1996, pp. 1-8.
Chaudhry, G.M. et al., "Separated caches and buses for multiprocessor system," Circuits and Systems, 1993; Proceedings of the 36th Midwest Symposium on Detroit, MI, USA, Aug. 16-18, 1993, New York, NY IEEE, Aug. 16, 1993, pp. 1113-1116, XP010119918 ISBN: 0-7803-1760-2.
Chen et al., "A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths," IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1895-1904.
Chen, D., (Thesis) "Programmable arithmetic devices for high speed digital signal processing," U. California Berkeley 1992, pp. 1-175.
Cherbaka, Mark F., "Verification and Configuration of a Run-time Reconfigurable Custom Computing Integrated Circuit for DSP Applications," Thesis: Virginia Polytechnic Institute and State University, Jul. 8, 1996, 106 pages.
Churcher, S., et al., "The XC6200 FastMap TM Processor Interface," Xilinx, Inc., Aug. 1995, pp. 1-8.
Clearspeed, CSX Processor Architecture, Whitepaper, PN-1110-0306, 2006, pp. 1-14, www.clearspeed.com.
Clearspeed, CSX Processor Architecture, Whitepaper, PN-1110-0702, 2007, pp. 1-15, www.clearspeed.com.
Coelho, F., "Compiling dynamic mappings with array copies," Jul. 1997, 12 pages, http://delivery.acm.org/10.1145/270000/263786/p168-coelho.pdf.
Communications Standard Dictionary, Third Edition, Martin Weik (Ed.), Chapman & Hall, 1996, 3 pages.
Compton, K., et al., "Configurable Computing: A Survey of Systems and Software," Northwestern University, Dept. of ECE, Technical Report, 1999, (XP-002315148), 39 pages.
Cong at al., "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-Based FPGA Designs," Univ. of California, ACM Transactions on Design Automation of Electronic Systems, vol. 5, No. 2, Apr. 2000, pp. 193-225.
Cook, Jeffrey J., "The Amalgam Compiler Infrastructure," Thesis at the University of Illinois at Urbana-Champaign (2004) Chapter 7 & Appendix G.
Cowie, Beth, Xilinx Application Note, "High Performance, Low Area, Interpolator Design for the XC6200," XAPP 081, May 7, 1997 (Version 1.0), pp. 1-10.
Cronquist, D., et al., "Architecture Design of Reconfigurable Pipelined Datapaths," Department of Computer Science and Engineering, University of Washington, Seattle, WA, Proceedings of the 20th Anniversary Conference on Advanced Research in VSLI, 1999, pp. 1-15.
Culler, D.E; Singh, J.P., "Parallel Computer Architecture," p. 17, 1999, Morgan Kaufmann, San Francisco, CA USA, XP002477559.
Culler, D.E; Singh, J.P., "Parallel Computer Architecture," pp. 434-437, 1999, Morgan Kaufmann, San Francisco, CA USA, XP002477559.
Declaration of Aaron Taggart in Support of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief (Exhibit A), PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-5.
Declaration of Harry L. (Nick) Tredennick in Support of Pact's Claim Constructions, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-87.
Defendant's Claim Construction Chart for P.R. 4-2 Constructions and Extrinsic Evidence for Terms Proposed by Defendants, PACT XPP Technologies, AG. V. Xilinx, Inc. and AVNET, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-19.
Defendants' Invalidity Contentions in PACT XPP Technologies, AG v. Xilinx, Inc et al., (E.D. Texas Dec. 28, 2007) (No. 2:07cv563)., including Exhibits A through K in separate PDF files.
Defendants Xilinx, Inc. and Avnet, Inc.'s Claim Construction Surreply Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Jan. 18, 2011, 142 pages.
Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-55.
DeHon, A., "DPGA Utilization and Application," MIT Artificial Intelligence Laboratory, Proceedings of the Fourth International ACM Symposium on Field-Programmable Gate Arrays (FPGA 1996), IEEE Computer Society, pp. 1-7.
DeHon, Andre, "Reconfigurable Architectures for General-Purpose Computing," Massachusetts Institute of Technology, Technical Report AITR-1586, Oct. 1996 (1996-10), XP002445054, Cambridge, MA, pp. 1-353.
Del Corso at al., "Microcomputer Buses and Links," Academic Press Inc. Ltd., 1986, pp. 138-143, 277-285.
Dictionary of Communications Technology, Terms Definitions and Abbreviations, Second Edition, Gilbert Held (Ed.), John Wiley & Sons, England, 1995, 5 pages.
Dictionary.com, "address," at http://dictionary.reference.com/browse/address, Jun. 18, 2010, 4 pages.
Diniz et al., "Automatic Synthesis of Data Storage and Control Structures for FPGA—based Computing Engines", 2000, IEEE, pp. 91-100.
Diniz, P., et al., "A behavioral synthesis estimation interface for configurable computing," University of Southern California, Marina Del Rey, CA, 2001 IEEE, pp. 1-2.
Diniz, P., et al., "Automatic Synthesis of Data Storage and Control Structures for FPGA—based Computing Engines," 2000, IEEE, pp. 91-100.
Documents from File History of U.S. Appl. No. 08/947,254, filed Oct. 8, 1997, Exhibit 27 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-38.
Documents from File History of U.S. Appl. No. 08/947,254, filed Oct. 8, 1997, specifically, German priority application specification [English translation provided], Exhibit 33 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, 54 pages [including English translation].
Documents from File History of U.S. Appl. No. 09/290,342, filed Apr. 12, 1999, Exhibit 20 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1- 37.
Documents from File History of U.S. Appl. No. 09/329,132, filed Jun. 9, 1999, Exhibit 24 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al, E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-13.
Documents from File History of U.S. Appl. No. 09/335,974, filed Jun. 18, 1999, Exhibit 28 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-32.
Documents from File History of U.S. Appl. No. 10/265,846, filed Oct. 7, 2002, Exhibit 32 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-23.
Documents from File History of U.S. Appl. No. 10/791,501, filed Mar. 1, 2004, Exhibit 25 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-14.
Documents from File History of U.S. Patent Reexamination Control No. 90/010,450, filed Mar. 27, 2009, Exhibit 30 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-71.
Documents from File History U.S. Appl. No. 09/329,132, filed Jun. 9, 1999, Exhibit 27 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1- 36.
Donandt, "Improving Response Time of Programmable Logic Controllers by use of a Boolean Coprocessor," AEG Research Institute Berlin, IEEE, 1989, pp. 4-167-4-169.
Donandt, "Improving Response Time of Programmable Logic Controllers by Use of a Boolean Coprocessor", AEG Research Institute Berlin, IEEE, 1989, pp. 4-167-4-169.
Duncan, Ann, Xilinx Application Note, "A32x16 Reconfigurable Correlator for the XC6200," XAPP 084, Jul. 25, 1997 (Version 1.0), pp. 1-14.
Dutt, et al., "If Software is King for Systems-in-Silicon, What's New in Compilers?" IEEE, 1997, pp. 322-325.
Dutt, et al., "If Software is King for Systems-on-Silicon, What's New in Compiler," IEEE, 1997, pp. 322-325.
Ebeling, C., et al., "RaPiD-Reconfigurable Pipelined Datapath," Dept. of Computer Science and Engineering, U. Washington, 1996, pp. 126-135.
Ebeling, C., et al., "Mapping Applications to the RaPiD Configurable Architecture," Department of Computer Science and Engineering, University of Washington, Seattle, WA, FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium, Publication Date: Apr. 16-18, 1997, 10 pages.
Epstein, D., "IBM Extends DSP Performance with Mfast-Powerful Chip Uses Mesh Architecture to Accelerate Graphics, Video," 1995 MicroDesign Resources, vol. 9, No. 16, Dec. 4, 1995, pp. 231-236.
Equator, Pixels to Packets, Enabling Multi-Format High Definition Video, Equator Technologies BSP-15 Product Brief, www.equator.com, 2001, 4 pages.
Exhibit A—P.R. 4-3 Amended Joint Claim Constructions Statement, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Aug. 2, 2010, pp. 1-66.
Expert Report of Joe McAlexander Re Claim Construction dated Sep. 27, 2010, Exhibit 19 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-112.
Expert Report of Joe McAlexander re Claim Construction, Exhibit 2 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-137.
Fawcett, B., "New SRAM-Based FPGA Architectures Address New Applications," Xilinx, Inc. San Jose, CA, Nov. 1995, pp. 231-236.
Fawcett, B.K., "Map, Place and Route: The Key to High-Density PLD Implementation," Wescon Conference, IEEE Center (Nov. 7, 1995) pp. 292-297.
Ferrante, et al., "The Program Dependence Graph and its Use in Optimization ACM Transactions on Programming Languages and Systems," Jul. 1987, USA, [online] Bd. 9, Nr., 3, pp. 319-349, XP002156651 ISSN: 0164-0935 ACM Digital Library.
Ferrante, J., et al., "The Program Dependence Graph and its Use in Optimization ACM Transactions on Programming Languages and Systems," Jul. 1987, USA, [online] Bd. 9, Nr., 3, pp. 319-349, XP002156651 ISSN: 0164-0935 ACM Digital Library.
Fineberg, et al., "Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting", vol. 11. No. 3, Mar. 1991, pp. 239-251.
Fineberg, S, et al., "Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting," Journal of Parallel and Distributed Computing, vol. 11, No. 3, Mar. 1991, pp. 239-251.
Foldoc, The Free On-Line Dictionary of Computing, "handshaking," online Jan. 13, 1995, retrieved from Internet Jan. 23, 2011 at http://foldoc.oru/handshake.
Fornaciari, et al., System-level power evaluation metrics, 1997 Proceedings of the 2nd Annual IEEE International Conference on Innovative Systems in Silicon, New York, NY, Oct. 1997, pp. 323-330.
Forstner, "Wer Zuerst Kommt, Mahlt Zuerst!: Teil 3: Einsatzgebiete and Anwendungbeispiele von FIFO-Speichern," Elektronik, Aug. 2000, pp. 104-109.
Forstner, "Wer Zuerst Kommt, Mahlt Zuerst!: Teil 3: Einsatzgebiete und Anwendungsbeispiele von FIFO-Speichern", Electronik, Aug. 2000, pp. 104-109.
Franklin, Manoj, et al., "A Fill-Unit Approach to Multiple Instruction Issue," Proceedings of the Annual International Symposium on Microarchitecture, Nov. 1994, pp. 162-171.
Freescale Slide Presentation, An Introduction to Motorola's RCF (Reconfigurable Compute Fabric) Technology, Presented by Frank David, Launched by Freescale Semiconductor, Inc., 2004, 39 pages.
Galanis, M.D. et al., "Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems," Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2005, 2 pages.
Garner's Modern American Usage, Bryan A. Garner (Ed.), Oxford University Press, 2003, 3 pages.
Genius, D., et al., "A Case for Array Merging in Memory Hierarchies," Proceedings of the 9th International Workshop on Compilers for Parallel Computers, CPC'01 (Jun. 2001), 10 pages.
Glaskowsky, Peter N., "Analysis' Choice Nominees Named; Our Picks for 2002's Most Important Products and Technologies," Microprocessor, The Insider's Guide to Microprocessor Hardware, MicroDesign Resources—Microprocessor Report, Dec. 9, 2002 (www.MPRonline.com), 4 pages.
Glaskowsky, Peter N., "PACT Debuts Extreme Processor; Reconfigurable ALU Array Is Very Powerful—and Very Complex," Microprocessor, The Insider's Guide to Microprocessor Hardware, MicroDesign Resources —Microprocessor Report, Oct. 9, 2000 (www.MPRonline.com), 6 pages.
Gokhale, et al., "Automatic Allocation of Arrays to Memories in FPGA processors with Multiple Memory Banks", Field-Programmable Custom Computing Machines, 1999, IEEE, pp. 63-67.
Gokhale, M.B., et al., "Automatic Allocation of Arrays to Memories in FPGA processors with Multiple Memory Banks," Field-Programmable Custom Computing Machines, 1999, IEEE, pp. 63-69.
Goslin, G; Newgard, B, Xilinx Application Note, "16-Tap, 8-Bit FIR Filter Applications Guide," Nov. 21, 1994, pp. 1-5.
Guccione et al., "JBits: Java based interface for reconfigurable computing," Xilinx, Inc., San Jose, CA, 1999, 9 pages.
Guo, Z. et al., "A Compiler Intermediate Representation for Reconfigurable Fabrics," University of California, Riverside, Dept. of Electrical Engineering, IEEE 2006, 4 pages.
Gwennap, Linley, "Intel's P6 Bus Designed for Multiprocessing," Microprocessor Report, vol. 9, No. 7 (MicroDesign Resources), May 30, 1995, p. 1 and pp. 6-10.
Gwennap, Linley, "P6 Underscores Intel's Lead," Microprocessor Report, vol. 9., No. 2, Feb. 16 1995 (MicroDesign Resources), p. 1 and pp. 6-15.
Hammes, et al., "Cameron: High Level Language Compilation for Reconfigurable Systems," Department of Computer Science, Colorado State University, Conference on Parallel Architectures and Compilation Techniques, Oct. 12-16, 1999.
Hammes, Jeff, et al., "Cameron: High Level Language Compilation for Reconfigurable Systems," Department of Computer Science, Colorado State University, Conference on Parallel Architectures and Compilation Techniques, Oct. 12-16, 1999, 9 pages.
Hartenstein et al., "A Two-Level Co-Design Framework for Xputer-based Data-driven Reconfigurable Accelerators," 1997, Proceedings of the Thirtieth Annual Hawaii International Conference on System Sciences, 10 pp.
Hartenstein et al., "Parallelizing Compilation for a Novel Data-Parallel Architecture," 1995, PCAT-94, Parallel Computing: Technology and Practice, 13 pp.
Hartenstein, R. et al., "A new FPGA architecture for word-oriented datapaths," Proc. FPL'94, Springer LNCS, Sep. 1994, pp. 144-155.
Hartenstein, R., "Coarse grain reconfigurable architectures," Design Automation Conference, 2001, Proceedings of the ASP-DAC 2001 Asia and South Pacific, Jan. 30-Feb. 2, 2001, IEEE Jan. 30, 2001, pp. 564-569.
Hastie et al., "The implementation of hardware subroutines on field programmable gate arrays," Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990, May 16, 1990, pp. 31.3.1-31.4.3 (3 pages).
Hauck, "The Roles of FPGA's in Reconfigurable Systems," IEEE, Apr. 1998, pp. 615-638.
Hauck, "The Roles of FPGAs in Reprogrammable Systems," IEEE, Apr. 1998, pp. 615-638.
Hauser, et al., "Garp: A MIPS Processor with a Reconfigurable Coprocessor", University of California, Berkeley, IEEE, 1997, pp. 12-21.
Hauser, J.R., et al., "Garp: A MIPS Processor with a Reconfigurable Coprocessor," University of California, Berkeley, IEEE, Apr. 1997, pp. 12-23.
Hauser, John R., "The Garp Architecture," University of California at Berkeley, Computer Science Division, Oct. 1997, pp. 1-55.
Hauser, John Reid, (Dissertation) "Augmenting a Microprocessor with Reconfigurable Hardware," University of California, Berkeley, Fall 2000, 255 pages. (submitted in 3 PDFs, Parts 1-3).
Hedge, 3D WASP Devices for On-line Signal and Data Processing, 1994, International Conference on Wafer Sale Integration, pp. 11-21.
Hedge, S.J., "3D WASP Devices for On-line Signal and Data Processing," 1994, International Conference on Wafer Scale Integration, pp. 11-21.
Hendrich, N., et al., "Silicon Compilation and Rapid Prototyping of Microprogrammed VLSI—Circuits with MIMOLA and SOLO 1400," Microprocessing & Microprogramming (Sep. 1992) vol. 35(1-5), pp. 287-294.
Huang, Libo et al., "A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design," School of Computer National University of Defense Technology, China, IEEE 2007, 8 pages.
Hwang, K., "Advanced Computer Architecture—Parallelism, Scalability, Programmability," 1993, McGraw-Hill, Inc., pp. 348-355.
Hwang, K., "Computer Architecture and Parallel Processing," Data Flow Computers and VLSI Computations, XP-002418655, 1985 McGraw-Hill, Chapter 10, pp. 732-807.
Hwang, L., et al., "Min-cut Replication in Partitioned Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, [online] Bd. 14, Nr. 1, Jan. 1995, pp. 96-106, XP00053228 USA ISSN: 0278-0070 IEEE Xplore.
Hwang,—et al., "Min-cut Replication in Partitioned Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, [online] Bd. 14, Nr. 1, Jan. 1995, pp. 96-106, XP00053228 USA ISSN: 0278-00700 IEEE Xplore.
IBM Technical Disclosure Bulletin, IBM Corp., New York, XP000424878, Bd. 36, Nr. 11, Nov. 1, 1993, pp. 335-336.
IMEC, "ADRES multimedia processor & 3MF multimedia platform," Transferable IP, IMEC Technology Description, (Applicants believe the date to be Oct. 2005), 3 pages.
Inside DSP, "Ambric Discloses Massively Parallel Architecture," Aug. 23, 2006, http://www.insidedsp.com/Articles/tabid/64/articleType/ArticleView/articleId/155/Default.aspx, 2 pages.
Intel, "Pentium Pro Family Developer's Manual, vol. 3: Operating System Writer's Guide," Intel Corporation, Dec. 1995, [submitted in 4 PDF files: Part I, Part II, Part III and Part IV], 458 pages.
Intel, Intel MXP5800/MXP5400 Digital Media Processors, Architecture Overview, Jun. 2004, Revision 2.4, pp. 1-24.
Iseli, C., et al. "A C++ Compiler for FPGA Custom Execution Units Synthesis," IEEE, 1995, pp. 173-179.
Iseli, et al. "A C++ Compiler for FPGA Custom Execution Units Synthesis," IEEE. 1995, pp. 173-179.
Isshiki, et al., "Bit-Serial Pipeline Synthesis for Multi-FPGA Systems with C++ Design Capture," 1996 IEEE, pp. 38-47.
Isshiki, Tsuyoshi, et al., "Bit-Serial Pipeline Synthesis for Multi-FPGA Systems with C++ Design Capture," 1996 IEEE, pp. 38-47.
Iwanczuk, Roman, Xilinx Application Note, "Using the XC4000 RAM Capability," XAPP 031.000, 1994, pp. 8-127 through 8-138.
Jacob, et al., "Memory Interfacing and Instruction Specification for Reconfigurable Processors", ACM 1999, pp. 145-154.
Jacob, J., et al., "Memory Interfacing and Instruction Specification for Reconfigurable Processors," ACM Feb. 1999, pp. 145-154.
Janssen et al., "A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters," Mar. 1996, 6 pages, http://delivery.acm.org/10.1145/790000/787534/74230138.pdf.
Jantsch, Axel et al., "A Case Study on Hardware/Software Partitioning," Royal Institute of Technology, Kista, Sweden, Apr. 10, 1994, IEEE, pp. 111-118.
Jantsch, Axel et al., "Hardware/Software Partitioning and Minimizing Memory Interface Traffic," Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden (Apr. 1994), pp. 226-231.
Jantsch, et al., "A Case Study on Hardware/software Partitioning," Royal Institute of Technology, Kista, Sweden, Apr. 10, 1994 IEEE, pp. 111-118.
Jo, Manhwee et al., "Implementation of Floating-Point Operations for 3D Graphics on a Coarse-Grained Reconfigurable Architecture," Design Automation Laboratory, School of EE/CS, Seoul National University, Korea, IEEE 2007, pp. 127-130.
John, et al., "A Dynamically Reconfigurable Interconnect for Array Processors", vol. 6, No. 1, Mar. 1998, IEEE, pp. 150-157.
John, L., et al., "A Dynamically Reconfigurable Interconnect for Array Processors," vol. 6, No. 1, Mar. 1998, IEEE, pp. 150-157.
Kanter, David, "NVIDIA's GT200: Inside a Parallel Processor," http://www.realworldtech.com/page.cfm?ArticleID=RWT090989195242&p=1, Sep. 8, 2008, 27 pages.
Kastrup, B., "Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs," Proceedings of the PACT Workshop on Reconfigurable Computing, 1998, pp. 5-10.
Kaul, M., et al., "An automated temporal partitioning and loop fission approach of FPGA based reconfigurable synthesis of DSP applications," University of Cincinnati, Cincinnati, OH, ACM 1999, pp. 616-622.
Kean, T., et al., "A Fast Constant Coefficient Multiplier for the XC6200," Xilinx, Inc., Lecture Notes in Computer Science, vol. 1142, Proceedings of the 6th International Workshop of Field-Programmable Logic, 1996, 7 pages.
Kean, T.A., "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation," University of Edinburgh (Dissertation) 1988, pp. 1-286. [in two PDFs, Pt. 1 and Pt.2.].
Kim et al., "A Reconfigurable Multifunction Computing Cache Architecture," IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 9, Issue 4, Aug. 2001 pp. 509-523.
Knapp, Steven, "Using Programmable Logic to Accelerate DSP Functions," Xilinx, Inc., 1995, pp. 1-8.
Knittel, Gunter, "A PCI—compatible FPGA—Coprocessor for 2D/3D Image Processing," University of Turgingen, Germany, 1996 IEEE, pp. 136-145.
Koch, A., et al., "Practical Experiences with the SPARXIL Co-Processor," 1998, IEEE, pp. 394-398.
Koch, Andreas et al., "High-Level-Language Compilation for Reconfigurable Computers," Proceedings of European Workshop on Reconfigurable Communication-Centric SOCS (Jun. 2005) 8 pages.
Koch, et al, "Practical Experiences with the SPARXIL Co-Processor", 1998, IEEE, pp. 394-398.
Koren et al., "A data-driven VLSI array for arbitrary algorithms," IEEE Computer Society, Long Beach, CA vol. 21, No. 10, Oct. 1, 1988, pp. 30-34.
Kung, "Deadlock Avoidance for Systolic Communication," 1988 Conference Proceedings of the 15th Annual International Symposium on Computer Architecture, May 30, 1998, pp. 252-260.
Kung, "Deadlock Avoidance for Systolic Communication", 1988 Conference Proceeding of 15th Annual International Symposium on Computer Architecture, May 30, 1988, pp. 252-260.
Lange, H. et al., "Memory access schemes for configurable processors," Field-Programmable Logic and Applications, International Workshop, FPL, Aug. 27, 2000, pp. 615-625, XP02283963.
Larsen, S., et al., "Increasing and Detecting Memory Address Congruence," Proceedings of the 2002 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'02), pp. 1-12 (Sep. 2002).
Lattice Semiconductor Corporation, "ispLSI 2000E, 2000VE and 2000 VL Family Architectural Description," Oct. 2001, pp. 1-88.
Lee et al., "A new distribution network based on controlled switching elements and its applications," IEEE/ACT Trans. of Networking, vol. 3, No. 1, pp. 70-81, Feb. 1995.
Lee, Jong-eun, et al., "Reconfigurable ALU Array Architecture with Conditional Execution," International Soc. Design Conference (ISOOC) [online] Oct. 25, 2004, Seoul, Korea, 5 pages.
Lee, Ming-Hau et al., "Design and Implementation of the MorphoSys Reconfigurable Computing Processors," The Journal of VLSI Signal Processing, Kluwer Academic Publishers, BO, vol. 24, No. 2-3, Mar. 2, 2000, pp. 1-29.
Lee, R. B., et al., "Multimedia extensions for general-purpose processors," IEEE Workshop on Signal Processing Systems, SIPS 97—Design and Implementation (1997), pp. 9-23.
Li et al., "Hardware-Software Co-Design of Embedded Reconfigurable Architectures," Los Angeles, CA, 2000, ACM, pp. 507-512.
Li, Zhiyuan, et al., "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation," International Symposium on Field Programmable Gate Arrays, Feb. 1, 2002, pp. 187-195.
Ling et al., "WASMII: A Multifunction Programmable Logic Device (MPLD) with Data Driven Control," The Transactions of the Institute of Electronics, Information and Communication Engineers, Apr. 25, 1994, vol. J77-D-1, Nr. 4, pp. 309-317. [This reference is in Chinese, but should be comparable in content to the Ling et al. reference above.]
Ling, "WASMII: An MPLD with Data-Driven Control on a Virtual Hardware," Journal of Supercomputing, Kluwer Acdemic Publishers, Dordrecht, Netherlands, 1995, pp. 253-276.
Ling, X., "WASMII: An MPLD with Data-Driven Control on a Virtual Hardware," Journal of Supercomputing, Kluwer Acdemic Publishers, Dordrecht, Netherlands, 1995, pp. 253-276.
M. Morris Mano, "Digital Design," by Prentice Hall, Inc., Englewood Cliffs, New Jersey 07632, 1984, pp. 119-125, 154-161.
M. Saleeba, "A Self-Contained Dynamically Reconfigurable Processor Architecture", Sixteenth Australian Computer Science Conference, ASCS-16, QLD, Australia, Feb. 1993.
Mano, M.M., "Digital Design," by Prentice Hall, Inc., Englewood Cliffs, New Jersey 07632, 1984, pp. 119-125, 154-161.
Margolus, N., "An FPGA architecture for DRAM-based systolic computations," Boston University Center for Computational Science and MIT Artificial Intelligence Laboratory, IEEE 1997, pp. 2-11.
Markman Hearing Minutes and Attorney Sign-In Sheet, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Feb. 22, 2011, 3 pages; and court transcript, 245 pages.
Marshall et al., "A Reconfigurable Arithmetic Array for Multimedia Applications," FPGA '99 Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 10 pages.
Maxfield, C. "Logic that Mutates While-U-Wait" EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA.
Maxfield,C., "Logic that Mutates While-U-Wait," EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA, pp. 137-140, 142.
McGraw-Hill Electronics Dictionary, Sixth Edition, Neil Sclater et al. (Ed.), McGraw-Hill, 1997, 3 pages.
Mei, Bingfeng et al., "Adres: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix," Proc. Field-Programmable Logic and Applications (FPL 03), Springer, 2003, pp. 61-70.
Mei, Bingfeng et al., "Design and Optimization of Dynamically Reconfigurable Embedded Systems," IMEC vzw, 2003, Belgium, 7 pages, http://www.imec.be/reconfigurable/pdf/ICERSA—01—design.pdf.
Mei, Bingfeng, "A Coarse-Grained Reconfigurable Architecture Template and Its Compilation Techniques," Katholeike Universiteit Leuven, PhD Thesis, Jan. 2005, IMEC vzw, Universitair Micro-Electronica Centrum, Belgium, pp. 1-195 (and Table of Contents).
Melvin, Stephen et al., "Hardware Support for Large Atomic Units in Dynamically Scheduled Machines," Computer Science Division, University of California, Berkeley, IEEE (1988), pp. 60-63.
Memorandum Opinion and Order, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Jun. 17, 2011, pp. 1-71.
Microsoft Press Computer Dictionary, Second Edition, 1994, Microsoft Press, ISBN 1-55615-597-2, p. 10.
Microsoft Press Computer Dictionary, Second Edition, Redmond, WA, 1994, 3 pages.
Microsoft Press Computer Dictionary, Third Edition, Redmond, WA, 1997, 3 pages.
Miller, et al., "High-Speed FIFOs Contend with Widely Differing Data Rates: Dual-port RAM Buffer and Dual-pointer System Provide Rapid, High-density Data Storage and Reduce Overhead", Computer Design, Sep. 1, 1985, pp. 83-86.
Miller, M.J., et al., "High-Speed FIFOs Contend with Widely Differing Data Rates: Dual-port RAM Buffer and Dual-pointer System Provide Rapid, High-density Data Storage and Reduce Overhead," Computer Design, Sep. 1, 1985, pp. 83-86.
Mirsky, "MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, 1996, pp. 157-1666.
Mirsky, E. DeHon, "Matrix: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, 1996, pp. 157-166.
Miyamori, T., et al., "REMARC: Reconfigurable Multimedia Array Coprocessor," Computer Systems Laboratory, Stanford University, IEICE Transactions on Information and Systems E Series D, 1999; (abstract): Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p. 261, Feb. 22-25, 1998, Monterey, California, United States, pp. 1-12.
Modern Dictionary of Electronics, Sixth Edition Revised and Updated, Rudolf F. Graf (Ed.), Butterworth-Heinemann, 1997, 5 pages.
Modern Dictionary of Electronics, Sixth Edition Revised and Updated, Rudolf F. Graf (Ed.), Butterworth-Heinemann, 1997, 7 pages.
Modern Dictionary of Electronics, Sixth Edition, Rudolf Graf (Ed.), Newnes (Butterwoth-Heinemann), 1997, 5 pages.
Moraes, F., et al., "A Physical Synthesis Design Flow Based on Virtual Components," XV Conference on Design of Circuits and Integrated Systems (Nov. 2000) 6 pages.
mPulse Living Language, "high-level," at http://www.macmillandictionary.com/dictionary/american/high-level, Jun. 18, 2010, 1 page.
MSN Encarta, "arrangement," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=arrangement , Jun. 17, 2010, 2 pages.
MSN Encarta, "communication," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=communication, Jun. 17, 2010, 2 pages.
MSN Encarta, "dimension," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=dimension, Jun. 17, 2010, 2 pages.
MSN Encarta, "pattern," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=pattern, Jun. 17, 2010, 2 pages.
MSN Encarta, "regroup," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=regroup, Jun. 17, 2010, 2 pages.
MSN Encarta, "synchronize," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=synchronize, Jun. 17, 2010, 2 pages.
MSN Encarta, "vector," at http://encarta.msn.com/encnet/features/dictionary/DictionaryResults.aspx?lextype=3&search=vector, Jul. 30, 2010, 2 pages.
Muchnick, S., "Advanced Compiler Design and Implementation," (Morgan Kaufmann 1997), Table of Contents, 11 pages.
Murphy, C., "Virtual Hardware Using Dynamic Reconfigurable Field Programmable Gate Arrays," Engineering Development Centre, Liverpool John Moores University, UK, GERI Annual Research Symposium 2005, 8 pages.
Myers, G. "Advances in Computer Architecture," Wiley-Interscience Publication, 2nd ed., John Wiley & Sons, Inc., 1978, pp. 463-494.
Myers, G., Advances in Computer Architecture, Wiley-Interscience Publication, 2nd ed., John Wiley & Sons, Inc. pp. 463-494, 1978.
Nageldinger, U., "Design-Space Exploration for Coarse Grained Reconfigurable Architectures," (Dissertation) Universitaet Kaiserslautern, 2000, Chapter 2, pp. 19-45.
Neumann, T., et al., "A Generic Library for Adaptive Computing Environments," Field Programmable Logic and Applications, 11th International Conference, FPL 2001, Proceedings (Lecture Notes in Computer Science, vol. 2147) (2001) pp. 503-512.
New, Bernie, Xilinx Application Note, "Accelerating Loadable Counters in SC4000," XAPP 023.001, 1994, pp. 8-82 through 8-85.
New, Bernie, Xilinx Application Note, "Boundary Scan Emulator for XC3000," XAPP 007.001, 1994, pp. 8-53 through 8-59.
New, Bernie, Xilinx Application Note, "Bus-Structured Serial Input-Output Device," XAPP 010.001, 1994, pp. 8-181 through 8-182.
New, Bernie, Xilinx Application Note, "Complex Digital Waveform Generator," XAPP 008.002, 1994, pp. 8-163 through 8-164.
New, Bernie, Xilinx Application Note, "Ultra-Fast Synchronous Counters," XAPP 014.001, 1994, pp. 8-78 through 8-81.
New, Bernie, Xilinx Application Note, "Using the Dedicated Carry Logic in XC4000," XAPP 013.001, 1994, pp. 8-105 through 8-115.
Newton, Harry, "Newton's Telecom Dictionary," Ninteenth Edition, 2003, CMP Books, p. 40.
Nilsson, et al., "The Scalable Tree Protocol—A Cache Coherence Approaches for Large-Scale Multiprocessors," IEEE, pp. 498-506, Dec. 1992.
Nilsson, et al., "The Scalable Tree Protocol—A Cache Coherence Approaches for Large-Scale Multiprocessors" IEEE, pp. 495-506 Dec. 1992.
Norman, R.S., "Hyperchip Business Summary, The Opportunity," Jan. 31, 2000, pp. 1-3.
Norman, Richard S., Hyperchip Business Summary, The Opportunity, Jan. 31, 2000, pp. 1-3.
Ohmsha, "Information Processing Handbook," edited by the Information Processing Society of Japan, pp. 376, Dec. 21, 1998.
Olukotun, K. et al., "Rationale, Design and Performance of the Hydra Multiprocessor," Computer Systems Laboratory, Stanford University, CA, Nov. 1994, pp. 1-19.
Olukotun, K., "The Case for a Single-Chip Microprocessor," ACM Sigplan Notices, ACM, Association for Computing Machinery, New York, vol. 31, No. 9, Sep. 1996 pp. 2-11.
Oral Videotaped Deposition Joseph McAlexander (Oct. 12, 2010), Exhibit 1 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-9.
Oral Videotaped Deposition—Joseph McAlexander dated Oct. 12, 2010, vol. 1, Exhibit 18 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-17.
Order Granting Joint Motion for Leave to File An Amended Joint Claim Construction and Prehearing Statement and Joint Motion to File an Amended Joint Claim Construction and Prehearing Statement Pursuant to Local Patent Rule 4-3, and Exhibit A: P.R. 4-3 Amended Joint Claim Constructions Statement, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Aug. 2, 2010, 72 pages.
Oxford Dictionary of Computing, Oxford University Press, 2008, 4 pages.
Ozawa, Motokazu et al., "A Cascade ALU Architecture for Asynchronous Super-Scalar Processors," IEICE Transactions on Electronics, Electronics Society, Tokyo, Japan, vol. E84-C, No. 2, Feb. 2001, pp. 229-237.
P.R . 4-3 Joint Claim Constructions Statement, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc at al., E.D. Texas, 2:07-cv00563-CE, Jul. 19, 2010, pp. 1-50.
P.R. 4-3 Amended Joint Claim Constructions Statement, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Aug. 3, 2010, pp. 1-65.
PACT Corporate Backgrounder, PACT company release, Oct. 2008, 4 pages.
PACT Corporation, "The XPP Communication System," Technical Report 15 (2000), pp. 1-16.
PACT's Claim Construction Reply Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Jan. 7, 2011, pp. 1-20.
PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-55.
PACT's P.R. 4-1 List of Claim Terms for Construction, PACT XPP Technologies, AG. V. Xilinx, Inc. and AVNET, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-7.
PACT's P.R. 4-2 Preliminary Claim Constructions and Extrinsic Evidence, PACT XPP Technologies, AG. V Xilinx, Inc. and AVNET, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, pp. 1-16, and Exhibits re Extrinsic Evidence Parts in seven (7) separate additional PDF files (Parts 1-7).
Page, Ian., "Reconfigurable processor architectures," Oxford University Computing Laboratory, Oxford UK, Elsevier Science B.V., Microprocessors an Microsystems 20 (1996) pp. 185-196.
Parhami, B., "Parallel Counters for Signed Binary Signals," Signals, Systems and Computers, 1989, Twenty-Third Asilomar Conference, vol. 1, pp. 513-516.
PCI Local Bus Specification, Production Version, Revision 2.1, Portland, OR, Jun. 1, 1995, pp. 1-281.
Piotrowski, "IEC-BUS, Die Funktionsweise des IEC-Bus und seine Anwendung in Geräten und Systemen", 1987, Franzis-Verlag GmbH, München, pp. 20-25.
Piotrowski, A., "IEC-BUS, Die Funktionsweise des IEC-Bus unde seine Anwendung in Geräten and Systemen," 1987, Franzis-Verlag GmbH, München, pp. 20-25. [English Abstract Provided].
Pirsch, P. et al., "VLSI implementations of image and video multimedia processing systems," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, No. 7, Nov. 1998, pp. 878-891.
Pistorius et al., "Generation of Very Large Circuits to Benchmark the Partitioning of FPGAs," Monterey, CA, 1999, ACM, pp. 67-73.
Price et al., "Debug of Reconfigurable Systems," Xilinx, Inc., San Jose, CA, Proceedings of SPIE, 2000, pp. 181-187.
Quenot, G.M., et al., "A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping," Laboratoire Systeme de Perception, DGA/Etablissement Technique Central de l'Armement, France, 1994 IEEE, pp. 91-100.
Ramanathan et al., "Reconfigurable Filter Coprocessor Architecture for DSP Applications," Journal of VLSI Signal Processing, 2000, vol. 26, pp. 333-359.
Random House Personal Computer Dictionary, Second Edition, Philip E. Margolis (Ed.), Random House, New York, 1996, 5 pages.
Random House Webster's College Dictionary with CD-ROM, Random House, 2001, 4 pages.
Random House Webster's College Dictionary with CD-ROM, Random House, 2001, 7 pages.
Razdan et al., A High-Performance Microarchitecture with Hardware-Programmable Functional Units, Micro-27, Proceedings of the 27th Annual International Symposium on Microarchitecture, IEEE Computer Society and Association for Computing Machinery, Nov. 30-Dec. 2, 1994, pp. 172-180.
Rehmouni et al., "Formulation and evaluation of scheduling techniques for control flow graphs," Dec. 1995, 6 pages, http://delivery.acm.org/10.1145/230000/224352/p386-rahmouni.pdf.
Ridgeway, David, Xilinx Application Note, "Designing Complex 2-Dimensional Convolution Filters," XAPP 037.000, 1994, pp. 8-175 through 8-177.
Roterberg, Eric., et al., "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," Proceedings of the 29th Annual International Symposium on Michoarchitecture, Paris, France, IEEE (1996), 12 pages.
Rowson, J., et al., "Second-generation compilers optimize semicustom circuits," Electronic Design Feb. 19, 1987, pp. 92-96.
Ryo, A., "Auszug aus Handbuch der Informationsverarbeitung," ed. Information Processing Society of Japan, Information Processing Handbook, New Edition, Software Information Center, Ohmsha, Dec. 1998, 4 pages. [Translation provided].
Saleeba, M. "A Self-Contained Dynamically Reconfigurable Processor Architecture," Sixteenth Australian Computer Science Conference, ASCS-16, QLD, Australia, Feb. 1993, pp. 59-70.
Saleeba, Z.M.G., "A Self-Reconfiguring Computer System," Department of Computer Science, Monash University (Dissertation) 1998, pp. 1-306.
Salefski, B. et al., "Re-configurable computing in wireless," Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation (2001) pp. 178-183.
Schewel, J., "A Hardware/Software Co-Design System using Configurable Computing Technology," Virtual Computer Corporation, Reseda, CA, IEEE 1998, pp. 620-625.
Schmidt, H. et al., "Behavioral synthesis for FGPA—based computing," Carnegie Mellon University, Pittsburgh, PA, 1994 IEEE, pp. 125-132.
Schmidt, U. et al., "Datawave: A Single-Chip Multiprocessor for Video Applications," IEEE Micro, vol. 11, No. 3, May/Jun. 1991, pp. 22-25, 88-94.
Schmit, et al., "Hidden Markov Modeling and Fuzzy Controllers in FPGAs, FPGAs for Custom Computing Machines," 1995; Proceedings, IEEE Symposium in Napa Valley, CA, Apr. 1995, pp. 214-221.
Schmit, et al., Hidden Markov Modeling and Fuzzy Controllers in FPGAs, FPGAs for Custom Computing Machined, 1995; Proceedings, IEEE Symposium on Napa Valley, CA, Apr. 1995, pp. 214-221.
Schöonfeld, M., et al., "The LISA Design Environment for the Synthesis of Array Processors Including Memories for the Data Transfer and Fault Tolerance by Reconfiguration and Coding Techniques," J. VLSI Signal Processing Systems for Signal, Image, and Video Technology, (Oct. 1, 1995) vol. 11(1/2), pp. 51-74.
Segers, Dennis, Xilinx Memorandum, "Mike-Product Description and MRD," Jun. 8, 1994, pp. 1-29.
Shanley, Tom, Pentium Pro and Pentium II System Architecture, MindShare, Inc., Addition Wesley, 1998, Second Edition, pp. 11-17; Chapter 7; Chapter 10; pp. 209-211, and p. 394.
Shin, D., et al., "C-based Interactive RTL Design Methodology," Technical Report CECS-03-42 (Dec. 2003) pp. 1-16.
Shirazi, et al., "Quantitative analysis. of floating point arithmetic on FPGA based custom computing machines," IEEE Symposium on FPGAs for Custom Computing Machines, IEEE Computer Society Press, Apr. 19-21, 1995, pp. 155-162.
Short, Kenneth L., Microprocessors and Programmed Logic, Prentice Hall, Inc., New Jersey 1981, p. 34.
Shoup, Richard, "Programmable Cellular Logic Arrays," Dissertation, Computer Science Department, Carnegie-Mellon University, Mar. 1970, 193 pages.
Siemers et al., "The .>S<puter: A Novel Micoarchitecture Model for Execution inside Superscalar and VLIW Processors Using Reconfigurable Hardware," Australian Computer Science Communications, vol. 20, No. 4, Computer Architecture, Proceedings of the 3rd Australian Computer Architecture Conference, Perth, John Morris, Ed., Feb. 2-3, 1998, pp. 169-178.
Siemers, "Rechenfabrik Ansaetze Fuer Extrem Parallele Prozessoren", Verlag Heinze Heise GmbH., Hannover, DE No. 15, Jul. 16, 2001, pp. 170-179.
Siemers, C., "Rechenfabrik Ansaetze Fuer Extrem Parallele Prozessoren," Verlag Heinze Heise GmbH., Hannover, DE No. 15, Jul. 16, 2001, pp. 170-179.
Simunic, et al., Source Code Optimization and Profiling of Energy Consumation in Embedded Systems, Proceedings of the 13th International Symposium on System Synthesis, Sep. 2000, pp. 193-198.
Singh, H. et al., "MorphoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications," University of California, Irvine, CA. and Federal University of Rio de Janeiro, Brazil, 2000, IEEE Transactions on Computers, pp. 1-35.
Singh, Hartej et al., "Morpho-Sys: A Reconfigurable Architecture for Multimedia Applications," Univ. of California, Irvine, CA and Federal University of Rio de Janiero, Brazil, at http://www.ena.uci.edu/morphosys/docs/sbcci98.html, Jun. 18, 2010, 10 pages.
Sinha et al., "System-dependence-graph-based slicing of programs with arbitrary interprocedural control flow," May 1999, 10 pages, http://delivery.ac.org/10.1145/310000/203675/032-sinha.pdf.
Skokan, Z.E., "Programmable logic machine (A programmable cell array)," IEEE Journal of Solid-State Circuits, vol. 18, Issue 5, Oct. 1983, pp. 572-578.
Sondervan, J., "Retiming and logic synthesis," Electronic Engineering (Jan. 1993) vol. 65(793), pp. 33, 35-36.
Soni, M., "VLSI Implementation of a Wormhole Run-time Reconfigurable Processor," Jun. 2001, (Masters Thesis)Virginia Polytechnic Institute and State University, 88 pages.
Stallings, William, "Data & Computer Communications," Sixth Edition, Jun. 2000, Prentice-Hall, Inc., ISBN 0-084370-9, pp. 195-196.
Sueyoshi, T, "Present Status and Problems of the Reconfigurable Computing Systems Toward the Computer Evolution," Department of Artificial Intelligence, Kyushi Institute of Technology, Fukuoka, Japan; Institute of Electronics, Information and Communication Engineers, vol. 96, No. 426, IEICE Technical Report (1996), pp. 111-119 [English Abstract Only].
Sundararajan et al., "Testing FPGA Devices Using JBits," Proc. MAPLD 2001, Maryland, USA, Katz (ed.), NASA, CA, 8 pages.
Sutton et al., "A Multiprocessor DSP System Using PADDI-2," U.C. Berkeley, 1998 ACM, pp. 62-65.
Tau, E., et al., "A First Generation DPGA Implementation," FPD'95, pp. 138-143.
Tau, Edward, et al., "A First Generation DPGA Implementation," FPD'95, pp. 138-143.
Tenca, A.F., et al., "A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures," University of California, Los Angeles, 1998, pp. 216-225.
Tenca, et al., "A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures", University of California, Los Angeles, 1998, pp. 216-225.
Texas Instruments, "TMS320C80 (MVP) Parallel Processor," User's Guide, Digital Signal Processing Products 1995, 73 pages.
Texas Instruments, "TMS320C80 Digital Signal Processor," Data Sheet, Digital Signal Processing Solutions 1997, 171 pages.
Texas Instruments, "TMS320C8x System-Level Synopsis," Sep. 1995, 75 pages.
The American Heritage Dictibnary, Fourth Edition, Dell (Houghton-Mifflin), 2001, 5 pages.
The American Heritage Dictionary, Fourth Edition, Dell/Houghton Mifflin 2001, 5 pages.
The American Heritage Dictionary, Second College Edition, Houghton Mifflin, 1982, 23 pages.
The American Heritage Dictionary, Second College Edition, Houghton Mifflin, 1982, 8 pages.
The American Heritage Dictionary, Third Edition, Dell Publishing (Bantam Doubleday Dell Publishing Group, Inc.), 1994, 4 pages.
The IEEE Standard Dictionary of Electrical and Electronics Terms, Sixth Edition, 1996, 36 pages.
The IEEE Standard Dictionary of Electrical and Electronics Terms, Sixth Edition, 1996, 8 pages.
The New Fowler's Modern English Usage, R.W. Burchfield (Ed.), Oxford University Press, 2000, 3 pages.
The Oxford American Dictionary and Language Guide, Oxford University Press, 1999, 5 pages.
The Oxford Duden German Dictionary, Edited by the Dudenredaktion and the German Section of the Oxford University Press, W. Scholze-Stubenrecht et al. (Eds), Clarendon Press, Oxford, 1990, 7 pages.
The Random House College Dictionary, Revised Edition, Random House, Inc., 1984, 14 pages.
The Random House College Dictionary, Revised Edition, Random House, Inc., 1984, 7 pages.
The XPP White Paper, Release 2.1, PACT—A Technical Perspective, Mar. 27, 2002, pp. 1-27.
Theodoridis, G. et al., "Chapter 2—A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools, Basic Definitions, Critical Design Issues and Existing Coarse-grain Reconfigurable Systems," from S. Vassiliadis, and D. Soudris (eds.) Fine- and Coarse-Grained Reconfigurable Computing, Springer 2007, pp. 89-149.
TMS320C54X DSP: CPU and Peripherals, Texas Instruments, 1996, 25 pages.
TMS320C54X DSP: CPU and Peripherals, Texas Instruments, 1996, pp. 6-26 to 6-46.
TMS320C54x DSP: Mnemonic Instruction Set, Texas Instruments, 1996, 342 pages.
TMS320C54x DSP: Mnemonic Instruction Set, Texas Instruments, 1996, p. 4-64.
Trainor, D.W., et al., "Implementation of the 2D DCT Using A Xilinx XC6264 FPGA," 1997, IEEE Workshop of Signal Processing Systems SiPS 97, pp. 541-550.
Transcript of Harry (Nick) L. Tredennick III, Ph.D., Oct. 11, 2010, vol. 1, Exhibit 16 of PACT's Opening Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Nov. 1, 2010, pp. 1-3.
Transcript of Harry (Nick) L. Tredennick III, Ph.D., Oct. 11, 2010, vol. 1, Exhibit 7 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. And Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-28.
Translation of DE 101 39 170 by examiner using Google Translate, 10 pages.
Trimberger, S, (Ed.) et al., "Field-Programmable Gate Array Technology," 1994, Kluwer Academic Press, pp. 1-258 (and the Title Page, Table of Contents, and Preface) [274 pages total].
Trimberger, S., "A Reprogrammable Gate Array and Applications," IEEE 1993, Proceedings of the IEEE, vol. 81, No. 7, Jul. 1993, pp. 1030-1041.
Trimberger, S., et al., "A Time-Multiplexed FPGA," Xilinx, Inc., 1997 IEEE, pp. 22-28.
Tsutsui, A., et al., "YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing," NTT Optical Network Systems Laboratories, Japan, 1997 ACM, pp. 93-99.
U.S. Appl. No. 60/109,417, Jefferson et al., filed Nov. 18, 1998.
U.S. Appl. No. 90/010,450, Vorbach et al. filed Mar. 27, 2009.
U.S. Appl. No. 90/010,979, Vorbach et al., filed May 4, 2010.
U.S. Appl. No. 90/011,087, Vorbach et al., filed Jul. 8, 2010.
Ujvari, Dan, Xilinx Application Note, "Digital Mixer in an XC7272," XAPP 035.002, 1994, p. 1.
Various Documents from File History of U.S. Appl. No. 09/290,342, filed Apr. 12, 1999, Exhibit 6 of Defendants Xilinx, Inc. and Avnet, Inc.'s Responsive Claim Construction Brief, PACT XPP Technologies, AG v. Xilinx, Inc. and Avnet, Inc. et al., E.D. Texas, 2:07-cv-00563-CE, Dec. 6, 2010, pp. 1-181.
Vasell et al., "The Function Processor: A Data-Driven Processor Array for Irregular Computations," Chalmers University of Technology, Sweden, 1992, pp. 1-21.
Veendrick, H., et al., "A 1.5 GIPS video signal processor (VSP)," Philips Research Laboratories, The Netherlands, IEEE 1994 Custom Integrated Circuits Conference, pp. 95-98.
Venkatachalam et al., "A highly flexible, distributed multiprocessor architecture for network processing," Computer Networks, The International Journal of Computer and Telecommunications Networking, vol. 41, No. 5, Apr. 5, 2003, pp. 563-568.
Villasenor, et al., "Express Letters Video Communications Using Rapidly Reconfigurable Hardware," IEEE Transactions on Circuits and Systems for Video Technology, IEEE, Inc., NY, Dec. 1995, pp. 565-567.
Villasenor, John, et al., "Configurable Computing." Scientific American, vol. 276, No. 6, Jun. 1997, pp. 66-71.
Villasensor, et al., "Express Letters Video Communications Using Rapidly Reconfigurable Hardware," IEEE Transactions on Circuits and Systems for Video Technology, IEEE, Inc. NY, Dec. 1995, pp. 565-567.
Wada, et al., "A Performance Evaluation of Tree-based Coherent Distributed Shared Memory," Proceedings of the Pacific RIM Conference on Communications, Comput and Signal Processing, Victoria, May 19-21, 1993, pp. 390-393.
Wada, et al., "A Performance Evaluation of Tree-based Coherent Distributed Shared Memory" Proceedings of the Pacific RIM Conference on Communications, Comput and Signal Processing, Victoria, May 19-21, 1993.
Waingold, E., et al., "Baring it all to software: Raw machines," IEEE Computer, Sep. 1997, at 86-93.
Webster's New Collegiate Dictionary, Merriam Co., 1981, 4 pages.
Webster's New Collegiate Dictionary, Merriam Co., 1981, 5 pages.
Webster's Ninth New Collegiate Dictionary, Merriam-Webster, Inc., 1990, p. 332 (definition of "dedicated").
Weinhardt, "Compilation Methods for Structure-programmable Computers", dissertation, ISBN 3-89722-011-3, 1997.
Weinhardt, "Ubersetzingsmethoden fur strukturprogrammierbare rechner," Dissertation for Doktors der Ingenieurwissenchaffen der Universitat Karlsruhe: Jul. 1, 1997.
Weinhardt, et al., "Pipeline Vectorization for Reconfigurable Systems", 1999, IEEE, pp. 52-60.
Weinhardt, M., "Compilation Methods for Structure-programmable Computers," dissertation, ISBN 3-89722-011-3, 1997. [Table of Contents and English Abstract Provided].
Weinhardt, Markus et al., "Memory Access Optimization for Reconfigurable Systems," IEEE Proceedings Computers and Digital Techniques, 48(3)(May 2001) pp. 1-16.
Weinhardt, Markus et al., "Pipeline Vectorization for Reconfigurable Systems," 1999, IEEE, pp. 52-62.
Weinhardt, Markus et al., "Pipeline Vectorization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 2, Feb. 2001, pp. 234-248.
Weinhardt, Markus et al., "Using Function Folding to Improve Silicon Efficiency of Reconfigurable Arithmetic Arrays," PACT XPP Technologies AG, Munich, Germany, IEEE 2004, pp. 239-245.
Wikipedia, the free encyclopedia, "Granularity," at http://en.wikipedia.org/wiki/Granularity, Jun. 18, 2010, 4 pages.
Wilkie, Bill, Xilinx Application Note, "Interfacing XC6200 to Microprocessors (MC68020 Example)," XAPP 063, Oct. 9, 1996 (Version 1.1), pp. 1-8.
Wilkie, Bill, Xilinx Application Note, "Interfacing XC6200 to Microprocessors (TMS320C50 Example)," XAPP 064, Oct. 9, 1996 (Version 1.1), pp. 1-9.
Witig,et al., "OneChip: An FPGA Processor with Reconfigurable Logic" IEEE, 1996 pp. 126-135.
Wittig, et al., "OneChip: An FPGA Processor with Reconfigurable Logic," IEEE, 1996, pp. 126-135.
Wolfe, M. et al., "High Performance Compilers for Parallel Computing," (Addison-Wesley 1996) Table of Contents, 11 pages.
Wordsmyth, The Premier Educational Dictionary—Thesaurus, at http://www.wordsmyth.net, "communication," Jun. 18, 2010, 1 page.
Wu, et al., "A New Cache Directory Scheme," IEEE, pp. 466-472, Jun. 1996.
Wu, et al., "A New Cache Directory Scheme", IEEE, pp. 466-472, Jun. 1996.
XCELL, Issue 18, Third Quarter 1995, "Introducing three new FPGA Families!"; "Introducing the XC6200 FPGA Architecture: The First FPGA Architecture Optimized for Coprocessing in Embedded System Applications," 40 pages.
Xilinx Application Note, "A Fast Constant Coefficient Multiplier for the XC6200," XAPP 082, Aug. 24, 1997 (Version 1.0), pp. 1-5.
Xilinx Application Note, Advanced Product Specification, "XC6200 Field Programmable Gate Arrays," Jun. 1, 1996 (Version 1.0), pp. 4-253-4-286.
Xilinx Data Book, "The Programmable Logic Data Book," 1996, 909 pages.
Xilinx Technical Data, "XC5200 Logic Cell Array Family," Preliminary (v1.0), Apr. 1995, pp. 1-43.
Xilinx, "Logic Cell Array Families: XC4000, XC4000A and XC4000H," 1994, product description, pp. 2-7, 2-9, 2-14, 2-15, 8-16, and 9-14.
Xilinx, "Spartan and SpartanXL Families Field Programmable Gate Arrays," Jan. 1999, Xilinx, pp. 4-3 through 4-70.
Xilinx, "The Programmable Logic Data Book," 1994, Section 2, pp. 1-231, Section 8, pp. 1, 23-25, 29, 45-52, 169-172.
Xilinx, "Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays," (v1.5) Jul. 17, 2002, Xilinx Production Product Specification, pp. 1-118.
Xilinx, "Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays," (v2.2) Sep. 10, 2002, Xilinx Production Product Specification, pp. 1-52.
Xilinx, "Virtex-II and Virtex-II Pro X FPGA Platform FPGAs: Complete Data Sheet," (v4.6) Mar. 5, 2007, pp. 1-302.
Xilinx, "Virtex-II and Virtex-II Pro X FPGA User Guide," Mar. 28, 2007, Xilinx user • aide, pp. 1-559.
Xilinx, "Virtex-II Platform FPGAs: Complete Data Sheet," (v3.5) Nov. 5, 2007, pp. 1-226.
Xilinx, "XC3000 Series Field Programmable Gate Arrays," Nov. 6, 1998, Xilinx product description, pp. 1-76.
Xilinx, "XC4000E and XC4000X Series Field Programmable Gate Arrays," May 14, 1999, Xilinx product description, pp. 1-68.
Xilinx, "XC6200 Field Programmable Gate Arrays," Apr. 24, 1997, Xilinx product description, pp. 1-73.
Xilinx, Inc.'s and Avnet, Inc.'s Disclosure Pursuant to P.R. 4-1; PACT XPP Technologies, AG. V Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, 9 pages.
Xilinx, Inc.'s and Avnet, Inc.'s Disclosure Pursuant to P.R. 4-2; PACT XPP Technologies, AG. V. Xilinx, Inc. and Avnet, Inc., Case No. 2:07-cv-00563-TJW-CE, U.S. District Court for the Eastern District of Texas, Dec. 28, 2007, 4 pages.
Xilinx, Series 6000 User's Guide, Jun. 26, 1997, 223 pages.
Xilinx, Virtex-II Platform FPGA User Guide, UG002 (V2.1) Mar. 28, 2007, pp. 1-502 [Parts 1-3].
Xilinx, White Paper 298: (Spartan-6 and Virtex-6 Devices) "Power Consumption at 40 and 50 nm," Matt Klein, Apr. 13, 2009, pp. 1-21.
Xilinx, White Paper 370: (Virtex-6 and Spartan-6 FPGA Families) "Reducing Switching Power with Intelligent Clock Gating," Frederic Rivoallon, May 3, 2010, pp. 1-5.
Xilinx, XC4000E and SC4000X Serial Field Programmable Gate Arrays, Product Specification (Version 1.6), May 14, 1999, pp. 1-107.
Xilinx, XC6200 Field Programmable Gate Arrays, Advance Product Specification, Jun. 1, 1996 (Version 1.0), pp. 4-255 through 4-286.
XLINX, "Logic Cell Array Families: XC4000, XC4000A and XC4000H", product description, pp. 2-7 to 2-15, Additional XC3000, XC31000 and XC3100A Data, pp. 8-16 and 9-14.
Xu, et al., "Parallel QR Factorization on a Block Data Flow Architecture" Conference Proceeding Article, Mar. 1, 1992, pp. 332-336 XPO10255276, p. 333, Abstract 2.2, 2.3, 2.4-p.334.
Xu, H. et al., "Parallel QR Factorization on a Block Data Flow Architecture," Conference Proceeding Article, Mar. 1, 1992, pp. 332-336.
Yahoo! Education, "affect," at http://education.yahoo.com/reference/dictionary/entry/affect, Jun. 18, 2010, 2 pages.
Ye, et al., "A Compiler for a Processor With A Reconfigurable Functional Unit," FPGA 2000 ACM/SIGNA International Symposium on Field Programmable Gate Arrays, Monterey, CA Feb. 9-11, 2000, pp. 95-100.
Ye, Z.A. et al., "A C-Compiler for a Processor With a Reconfigurable Functional Unit," FPGA 2000 ACM/SIGNA International Symposium on Field Programmable Gate Arrays, Monterey, CA Feb 9-11, 2000, pp. 95-100.
Yeung, A. et al., "A data-driven architecture for rapid prototyping of high throughput DSP algorithms," Dept. of Electrical Engineering and Computer Sciences, Univ. of California, Berkeley, USA, Proceedings VLSI Signal Processing Workshop, IEEE Press, pp. 225-234, Napa, Oct. 1992.
Yeung, A. et al., "A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms," Dept. of Electrical Engineering and Computer Sciences, Univ. of California, Berkeley, USA, pp. 169-178, IEEE 1993.
Yeung, K., (Thesis) "A Data-Driven Multiprocessor Architecture for High Throughput Digital Signal Processing," Electronics Research Laboratory, U. California Berkeley, Jul. 10, 1995, pp. 1-153.
Yeung, L., et al., "A 2.4GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP," Dept. of EECS, U. California Berkeley, 1995 IEEE International Solid State Circuits Conference, pp. 108-110.
Zhang et al., "Abstract: Low-Power Heterogeneous Reconfigurable Digital Signal Processors with Energy-Efficient Interconnect Network," U.C. Berkeley (2004), pp. 1-120.
Zhang, et al., "A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing," IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1697-1704.
Zhang, et al., "Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers, Signals, Systems and Computers," 2000; Conference Record of the Thirty-Fourth Asilomar Conference, Bd. 1, Oct. 29, 2000, pp. 78-83.
Zhang, et al., Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers, Signals, Systems and Computers, 2000; Conference Record of the Thirty-Fourth Asilomar Conference, Bd. 1, Oct. 29, 2000, pp. 78-83.
Zilog Preliminary Product Specification, "Z86C95 CMOS Z8 Digital Signal Processor," 1992, pp. 1-82.
Zilog Preliminary Product Specification, "Z89120 Z89920 (ROMless) 16-Bit Mixed Signal Processor," 1992, pp. 1-82.
Zima, H. et al., "Supercompilers for parallel and vector computers," (Addison-Wesley 1991) Table of Contents, 5 pages.
Zucker, Daniel F., "A Comparison of Hardware Prefetching Techniques for Multimedia Benchmarks," Technical Report: CSL-TR-95-683, Dec. 1995, 26 pages.

Also Published As

Publication number Publication date
US7036036B2 (en) 2006-04-25
USRE45109E1 (en) 2014-09-02
US20040083399A1 (en) 2004-04-29
USRE44383E1 (en) 2013-07-16
US6542998B1 (en) 2003-04-01
USRE45223E1 (en) 2014-10-28

Similar Documents

Publication Publication Date Title
USRE44365E1 (en) Method of self-synchronization of configurable elements of a programmable module
AU740243B2 (en) Method of self-synchronization of configurable elements of a programmable component
US7822968B2 (en) Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US5828858A (en) Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US7028107B2 (en) Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
JP2647315B2 (en) Arrays that dynamically process in multiple modes in parallel
US20090144485A1 (en) Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
GB2471067A (en) Shared resource multi-thread array processor with heterogeneous function blocks
JPH0764788A (en) Microcomputer
US7716458B2 (en) Reconfigurable integrated circuit, system development method and data processing method
US6694385B1 (en) Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
US5890009A (en) VLIW architecture and method for expanding a parcel
US7194609B2 (en) Branch reconfigurable systems and methods
US8171259B2 (en) Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal
US20030172248A1 (en) Synergetic computing system
David et al. Self-timed architecture of a reduced instruction set computer
US9081901B2 (en) Means of control for reconfigurable computers

Legal Events

Date Code Title Description
AS Assignment

Owner name: PACT XPP TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RICHTER, THOMAS;KRASS, MAREN;REEL/FRAME:032225/0089

Effective date: 20140117

AS Assignment

Owner name: SCIENTIA SOL MENTIS AG, SWITZERLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACT XPP TECHNOLOGIES AG;REEL/FRAME:045532/0745

Effective date: 20180315