USRE42658E1 - Gate driver multi-chip module - Google Patents

Gate driver multi-chip module Download PDF

Info

Publication number
USRE42658E1
USRE42658E1 US11/787,234 US78723407A USRE42658E US RE42658 E1 USRE42658 E1 US RE42658E1 US 78723407 A US78723407 A US 78723407A US RE42658 E USRE42658 E US RE42658E
Authority
US
United States
Prior art keywords
power
substrate
mosfets
disposed
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US11/787,234
Inventor
David Jauregui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to US11/787,234 priority Critical patent/USRE42658E1/en
Application granted granted Critical
Publication of USRE42658E1 publication Critical patent/USRE42658E1/en
Assigned to Infineon Technologies Americas Corp. reassignment Infineon Technologies Americas Corp. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL RECTIFIER CORPORATION
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01021—Scandium [Sc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a multi-chip module (MCM). More specifically, the present invention relates to an MCM power circuit for a computer motherboard.
  • MCM multi-chip module
  • Power supply circuitry typically occupies a substantial area on a computer motherboard. It would be desirable to reduce the size of the power circuitry on a computer motherboard without sacrificing performance.
  • the present invention provides an MCM which includes a MOSFET gate driver, two power MOSFETs, and associated passive elements including an input capacitor all mounted on a ball grid array (BGA) substrate and packaged in a single chip.
  • BGA ball grid array
  • the power MOSFETs of the MCM of the present invention are connected in a half-bridge arrangement between an input voltage and ground.
  • the MOSFET gate driver is connected to respective gate inputs of the two power MOSFETs, and alternately switches the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs.
  • At least one Schottky diode is disposed on the BGA substrate and connected between a common output node and ground to minimize losses during deadtime conduction periods.
  • the passive circuit components include an input capacitor connected between the input voltage and ground which provides input capacitance for the converter.
  • the input capacitor is physically close to all other components. Additional components provide appropriate biasing for the gate driver. All components are encased in a molding compound to form the MCM package.
  • the location of the input capacitor within the MCM package provides layout independence for the mother board, which no longer needs to contain that capacitor (at a distance from the MOSFETs in the MCM package).
  • the capacitor acts as a bypass to conduction of unintended current (with a high di/dt) through the body diode of one of the MOSFETs in the package and acts to help clamp the Q RR (reverse recovery charge) of the MOSFET.
  • the module preferably is enclosed in a package that has side dimensions of about 11 mm ⁇ 11 mm (i.e., about 1 cm ⁇ 1 cm) or less. Accordingly, the input capacitor is located less than 1 cm from the MOSFET.
  • the MCM of the present invention advantageously results in a 50% reduction in size with no performance trade off and is printed circuit board (PCB) independent.
  • PCB printed circuit board
  • the package advantageously provides a performance increase over the discrete solution.
  • FIG. 1 is a plan view drawing of the co-packaged active and passive components in the MCM of the present invention.
  • FIG. 2 is an elevation view drawing of an MCM according to the present invention.
  • FIG. 3 is a circuit schematic of an MCM according to the present invention.
  • FIG. 3A is an equivalent circuit diagram of a portion of FIG. 3 .
  • FIG. 4 is a timing diagram for an MCM according to the present invention.
  • MCM 2 includes six die mounted on a BGA substrate 4 .
  • a plurality of bonding pads 6 are disposed on the upper surface of substrate 4 .
  • Die 8 and 10 are power MOSFETs, preferably IRFC7811A and IRFC7809A power MOSFETs, respectively, mounted in a half-bridge configuration.
  • Die 12 is a MOSFET gate driver, preferably a Semtech SC1405 High Speed Synchronous Power MOSFET Smart Driver.
  • Die 14 , 16 , and 18 are Schottky diodes, preferably SKM863 diodes, connected as shown in the circuit schematic of FIG. 3 .
  • the active components mounted on the upper surface of substrate 4 are connected electrically to corresponding bonding pads 6 using wire bonds 20 .
  • the passive components shown in FIG. 1 include resistor R 1 , and capacitors C 1 , C 2 , C 3 , and C 4 , also connected as shown in the circuit schematic of FIG. 3 .
  • the passive components are shown bonded directly to corresponding pads 6 .
  • capacitor C 4 is mounted close to MOSFETs 8 and 10 .
  • MCM 2 of the present invention is shown in elevation.
  • a plurality of solder balls 22 are arranged on the lower surface of substrate 4 .
  • the components on the upper surface of substrate 4 are encapsulated in a mold compound 24 such as Nitto HC 100.
  • the dimension of housing 2 is about 1 cm ⁇ 1 cm so it will take very little space on a mother board.
  • FIG. 3 a circuit schematic of power supply MCM 2 is shown.
  • Power MOSFETs 8 and 10 are mounted in a half-bridge configuration, connected in series between an input voltage V IN and ground P GND .
  • External circuit capacitance C EXT is connected to V IN .
  • a high-side output gate drive TG of MOSFET gate driver 12 is connected to a gate input 20 of high-side power MOSFET 8 .
  • a low-side output gate drive BG of MOSFET gate driver 12 is connected to a gate input 22 of low-side power MOSFET 10 .
  • Gate driver 12 alternately switches the power MOSFETs to generate an alternating output voltage at a common output node SW NODE between the power MOSFETs.
  • Schottky diodes 16 and 18 are connected between common output node SW NODE and ground to minimize losses during dead time conduction periods.
  • An input capacitor C 4 is connected between the input voltage V IN and ground P GND .
  • the use of two parallel diodes 16 and 18 helps in keeping a symmetrical layout of components.
  • An output inductor 30 generally will be connected to the SW NODE and to the output voltage terminal V OUT .
  • An output capacitor C OUT is also in the output circuit.
  • a supply voltage V DD is provided to MOSFET gate driver 12 on pin V CC .
  • a bootstrap circuit consisting of Schottky diode 14 , and resistor R 1 /capacitor C 2 connected between the bootstrap pin BST and the DRN pin, is provided to develop a floating bootstrap voltage for high-side MOSFET 8 .
  • a TTL-level input signal is provided on line DRV_IN to MOSFET driver pin CO. Operation of the device is enabled by providing a minimum of 2.0 volts on enable pin EN of MOSFET driver 12 .
  • Status pin P RDY indicates the status of the +5V supply voltage. When the supply voltage is less than 4.4V, this output is driven low. When the supply voltage is greater than 4.4V, this output is driven high. This output has a 10 mA source and 10 ⁇ A capability. When P RDY is low, undervoltage circuitry built into driver 12 guarantees that both driver outputs TG and BG are low.
  • a timing diagram for MCM 2 is shown.
  • a turn on delay t D(ON) of typically 63 ns exists between the signal input DRV_IN and output SW NODE of MCM 2 .
  • a turn off delay t D(OFF) of typically 26 ns exists between the signal input DRV_IN and output SW NODE of MCM 2 .
  • a portion of the delay is inherent in driver 12 .
  • the supply voltage can range between 4.2 and 6.0 V. Input voltages of between 5 and 12 volts can be used, providing an output voltage range of 0.9-2.0 V. Output current is typically 15A.
  • the device operates at frequencies from 300-1,000 kHz.
  • MOSFET 10 has a parasitic capacitance C OSS .
  • the circuit including the stray inductance L and C OSS tends to ring at its resonant frequency. By reducing L, the ring is also reduced.
  • FIG. 3A is an equivalent circuit of portions of FIG. 3 showing in particular the body diode of MOSFET 10 .
  • FIG. 3A shows in particular the body diode of MOSFET 10 .
  • the dead time during which both MOSFETs 8 and 10 are off, conduction takes place through Schottky diodes 16 and 18 of FIG. 3 , but some “residual” current also is conducted through the body diode of MOSFET 10 .
  • MOSFET 8 turns on while the body diode of MOSFET 10 is conducting, a reverse recovery current will be fed from the external capacitor C EXT with very high di/dt.
  • Capacitor C 4 will act as a bypass to this high di/dt.
  • the capacitor C 4 of FIG. 3 serves similar purposes.

Abstract

A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This is a continuation of U.S. patent application Ser. No. 09/813,011, filed Mar. 21, 2001 abandoned, which is based upon and claims priority of U.S. Provisional Application Ser. No. 60/191,125, filed Mar. 22, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-chip module (MCM). More specifically, the present invention relates to an MCM power circuit for a computer motherboard.
2. Description of the Related Art
Power supply circuitry typically occupies a substantial area on a computer motherboard. It would be desirable to reduce the size of the power circuitry on a computer motherboard without sacrificing performance.
SUMMARY OF THE INVENTION
The present invention provides an MCM which includes a MOSFET gate driver, two power MOSFETs, and associated passive elements including an input capacitor all mounted on a ball grid array (BGA) substrate and packaged in a single chip.
The power MOSFETs of the MCM of the present invention are connected in a half-bridge arrangement between an input voltage and ground. The MOSFET gate driver is connected to respective gate inputs of the two power MOSFETs, and alternately switches the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between a common output node and ground to minimize losses during deadtime conduction periods.
The passive circuit components include an input capacitor connected between the input voltage and ground which provides input capacitance for the converter. Advantageously, the input capacitor is physically close to all other components. Additional components provide appropriate biasing for the gate driver. All components are encased in a molding compound to form the MCM package.
By mounting the input capacitor very close to other components and within the very small package, a number of advantages are realized, as follows:
First, there is a very low stray inductance between the input capacitor and the MOSFETs which reduces the “ring” that would be caused in the circuit including the MOSFET parasitic capacitance COSS and the stray inductance L. Reducing the inductance reduces the circuit ring.
Second, the location of the input capacitor within the MCM package provides layout independence for the mother board, which no longer needs to contain that capacitor (at a distance from the MOSFETs in the MCM package).
Third, the capacitor acts as a bypass to conduction of unintended current (with a high di/dt) through the body diode of one of the MOSFETs in the package and acts to help clamp the QRR (reverse recovery charge) of the MOSFET.
The module preferably is enclosed in a package that has side dimensions of about 11 mm×11 mm (i.e., about 1 cm×1 cm) or less. Accordingly, the input capacitor is located less than 1 cm from the MOSFET.
The MCM of the present invention advantageously results in a 50% reduction in size with no performance trade off and is printed circuit board (PCB) independent. The package advantageously provides a performance increase over the discrete solution.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view drawing of the co-packaged active and passive components in the MCM of the present invention.
FIG. 2 is an elevation view drawing of an MCM according to the present invention.
FIG. 3 is a circuit schematic of an MCM according to the present invention.
FIG. 3A is an equivalent circuit diagram of a portion of FIG. 3.
FIG. 4 is a timing diagram for an MCM according to the present invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, a diagram of a preferred layout for MCM 2 of the present invention is shown. MCM 2 includes six die mounted on a BGA substrate 4. A plurality of bonding pads 6 are disposed on the upper surface of substrate 4.
Die 8 and 10 are power MOSFETs, preferably IRFC7811A and IRFC7809A power MOSFETs, respectively, mounted in a half-bridge configuration. Die 12 is a MOSFET gate driver, preferably a Semtech SC1405 High Speed Synchronous Power MOSFET Smart Driver. Die 14, 16, and 18 are Schottky diodes, preferably SKM863 diodes, connected as shown in the circuit schematic of FIG. 3. The active components mounted on the upper surface of substrate 4 are connected electrically to corresponding bonding pads 6 using wire bonds 20.
The passive components shown in FIG. 1 include resistor R1, and capacitors C1, C2, C3, and C4, also connected as shown in the circuit schematic of FIG. 3. The passive components are shown bonded directly to corresponding pads 6. Significantly, capacitor C4 is mounted close to MOSFETs 8 and 10.
Referring to FIG. 2, MCM 2 of the present invention is shown in elevation. A plurality of solder balls 22 are arranged on the lower surface of substrate 4. In the finished package, the components on the upper surface of substrate 4 are encapsulated in a mold compound 24 such as Nitto HC 100. The dimension of housing 2 is about 1 cm×1 cm so it will take very little space on a mother board.
Referring to FIG. 3, a circuit schematic of power supply MCM 2 is shown. Power MOSFETs 8 and 10 are mounted in a half-bridge configuration, connected in series between an input voltage VIN and ground PGND. External circuit capacitance CEXT is connected to VIN. A high-side output gate drive TG of MOSFET gate driver 12 is connected to a gate input 20 of high-side power MOSFET 8. A low-side output gate drive BG of MOSFET gate driver 12 is connected to a gate input 22 of low-side power MOSFET 10. Gate driver 12 alternately switches the power MOSFETs to generate an alternating output voltage at a common output node SW NODE between the power MOSFETs.
Schottky diodes 16 and 18 are connected between common output node SW NODE and ground to minimize losses during dead time conduction periods. An input capacitor C4 is connected between the input voltage VIN and ground PGND. The use of two parallel diodes 16 and 18 helps in keeping a symmetrical layout of components. An output inductor 30 generally will be connected to the SW NODE and to the output voltage terminal VOUT. An output capacitor COUT is also in the output circuit.
A supply voltage VDD is provided to MOSFET gate driver 12 on pin VCC. A bootstrap circuit, consisting of Schottky diode 14, and resistor R1/capacitor C2 connected between the bootstrap pin BST and the DRN pin, is provided to develop a floating bootstrap voltage for high-side MOSFET 8.
A TTL-level input signal is provided on line DRV_IN to MOSFET driver pin CO. Operation of the device is enabled by providing a minimum of 2.0 volts on enable pin EN of MOSFET driver 12. Status pin PRDY indicates the status of the +5V supply voltage. When the supply voltage is less than 4.4V, this output is driven low. When the supply voltage is greater than 4.4V, this output is driven high. This output has a 10 mA source and 10 μA capability. When PRDY is low, undervoltage circuitry built into driver 12 guarantees that both driver outputs TG and BG are low.
Referring to FIG. 4, a timing diagram for MCM 2 is shown. A turn on delay tD(ON) of typically 63 ns exists between the signal input DRV_IN and output SW NODE of MCM 2. A turn off delay tD(OFF) of typically 26 ns exists between the signal input DRV_IN and output SW NODE of MCM 2. A portion of the delay is inherent in driver 12.
The supply voltage can range between 4.2 and 6.0 V. Input voltages of between 5 and 12 volts can be used, providing an output voltage range of 0.9-2.0 V. Output current is typically 15A. The device operates at frequencies from 300-1,000 kHz.
The operation of the circuit of FIG. 3 is considerably enhanced by the inherently close spacing between input capacitor C4 and MOSFET 10.
First, the removal of capacitor C4 from the mother board increases layout flexibility for the mother board.
Second, since the capacitor C4 is very close to MOSFETs 8 and 10, the stray inductance in the circuit is reduced in comparison to that which would be produced with C4 located outside the chip, on the mother board. This close location (about one centimeter or less) substantially reduces the “ring” in the circuit. More specifically, as shown in FIG. 3, MOSFET 10 has a parasitic capacitance COSS. The circuit including the stray inductance L and COSS tends to ring at its resonant frequency. By reducing L, the ring is also reduced.
A third benefit of capacitor C4 is that it clamps QRR (reverse recovery charge) of MOSFET 10 and keeps high di/dt from flowing out of module 2 and into the mother board. More specifically, FIG. 3A is an equivalent circuit of portions of FIG. 3 showing in particular the body diode of MOSFET 10. During the dead time, during which both MOSFETs 8 and 10 are off, conduction takes place through Schottky diodes 16 and 18 of FIG. 3, but some “residual” current also is conducted through the body diode of MOSFET 10. When MOSFET 8 turns on while the body diode of MOSFET 10 is conducting, a reverse recovery current will be fed from the external capacitor CEXT with very high di/dt. Capacitor C4, however, will act as a bypass to this high di/dt. The capacitor C4 of FIG. 3 serves similar purposes.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art.

Claims (13)

1. A multi-chip module (MCM) for providing power circuitry on a computer motherboard, comprising:
a ball grid array (BGA) substrate having a first surface and a second opposing surface;
two power MOSFETs disposed on the first surface of the BGA substrate and connected in a half-bridge arrangement between an input voltage and ground;
a MOSFET gate driver disposed on the first surface of the BGA substrate and electrically connected to respective gate inputs of the two power MOSFETs for alternatively switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs; and
at least one diode disposed on the first surface of the BGA substrate and connected between the common output node and ground to minimize losses during deadtime connection periods; and
an input capacitor disposed on the first surface of the BGA and connected between the input voltage and ground;
wherein the input capacitor is located adjacent to, and spaced less than 1 cm from the first and second MOSFETs, and wherein the input capacitor and the first and second MOSFETs are positioned side-by-side.
2. The module of claim 1, further comprising another diode connected in parallel with the diode connected between the common output node and between the common output node and ground.
3. The module of claim 1, wherein the substrate has an area of about 1 cm by 1 cm or less.
4. The module of claim 1, which further includes an insulation housing enclosing the substrate, the MOSFETs, the gate driver and the at least one diode, the ball grid array being exposed through the bottom of the housing for mounting to a mother board.
5. A multichip module comprising:
a substrate having a first surface and an opposing second surface;
a power input connection;
a ground connection;
two power switching devices disposed on said first surface of said substrate and connected in series according to a half-bridge arrangement between said power input connection and said ground connection, a terminal of one of said two power switching devices directly connected to said power input connection and a terminal of another of said two power switching devices directly connected to said ground connection; and
an input capacitor connected between said power input connection and said ground connection, wherein said input capacitor is disposed on said first surface of said substrate and spaced no more than one centimeter from said two either power switching devices device, and wherein said input capacitor and said power switching devices are positioned side-by-side.
6. A The multichip module according to claim 5, wherein said power switching devices are MOSFETs.
7. A The multichip module according to claim 5, wherein said substrate is a ball grid array.
8. A The multichip module according to claim 5, wherein said half-bridge connection includes an output node located between said two power switching devices, and further comprising at least one Schottky diode connected between said output node and said ground connection.
9. A The multichip module according to claim 8, further comprising another Schottky diode connected between said output node and said ground connection.
10. A The multichip module according to claim 5, further comprising a controller disposed on said substrate for selective control of the operation of said two power switching devices.
11. A The multichip module according to claim 5, wherein said multichip module is 1 cm by 1 cm or less.
12. A The multichip module according to claim 5, wherein said input capacitor reduces the stray inductance to reduce the ringing due to resonance in said at least one of said two power switching devices.
13. A The multichip module according to claim 5, wherein said input capacitor is disposed on said substrate and spaced no more than one centimeter from the low side power switching device in said half-bridge arrangement.
US11/787,234 2000-03-22 2007-04-12 Gate driver multi-chip module Expired - Lifetime USRE42658E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/787,234 USRE42658E1 (en) 2000-03-22 2007-04-12 Gate driver multi-chip module

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19112500P 2000-03-22 2000-03-22
US09/813,011 US20020021560A1 (en) 2000-03-22 2001-03-21 Gate driver multi-chip module
US10/252,988 US6879491B2 (en) 2000-03-22 2002-09-23 Gate driver multi-chip module
US11/787,234 USRE42658E1 (en) 2000-03-22 2007-04-12 Gate driver multi-chip module

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/252,988 Reissue US6879491B2 (en) 2000-03-22 2002-09-23 Gate driver multi-chip module

Publications (1)

Publication Number Publication Date
USRE42658E1 true USRE42658E1 (en) 2011-08-30

Family

ID=22704238

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/813,011 Abandoned US20020021560A1 (en) 2000-03-22 2001-03-21 Gate driver multi-chip module
US10/252,988 Ceased US6879491B2 (en) 2000-03-22 2002-09-23 Gate driver multi-chip module
US11/787,234 Expired - Lifetime USRE42658E1 (en) 2000-03-22 2007-04-12 Gate driver multi-chip module

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/813,011 Abandoned US20020021560A1 (en) 2000-03-22 2001-03-21 Gate driver multi-chip module
US10/252,988 Ceased US6879491B2 (en) 2000-03-22 2002-09-23 Gate driver multi-chip module

Country Status (6)

Country Link
US (3) US20020021560A1 (en)
JP (1) JP3943395B2 (en)
CN (1) CN1284421C (en)
AU (1) AU2001247631A1 (en)
TW (1) TWI250406B (en)
WO (1) WO2001072092A1 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247932B1 (en) 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
GB0128351D0 (en) * 2001-11-27 2002-01-16 Koninkl Philips Electronics Nv Multi-chip module semiconductor devices
US6940724B2 (en) * 2003-04-24 2005-09-06 Power-One Limited DC-DC converter implemented in a land grid array package
JP4489485B2 (en) 2004-03-31 2010-06-23 株式会社ルネサステクノロジ Semiconductor device
US7274243B2 (en) * 2004-04-26 2007-09-25 Gary Pace Adaptive gate drive for switching devices of inverter
JP2006049341A (en) * 2004-07-30 2006-02-16 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP2006073655A (en) * 2004-08-31 2006-03-16 Toshiba Corp Semiconductor module
JP4426955B2 (en) 2004-11-30 2010-03-03 株式会社ルネサステクノロジ Semiconductor device
US7504733B2 (en) 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
JP4875380B2 (en) 2006-02-24 2012-02-15 ルネサスエレクトロニクス株式会社 Semiconductor device
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7710702B2 (en) * 2006-05-18 2010-05-04 Global Power Technologies, Inc. Primary side control module and method for protection of MOSFET against burnout
US7687885B2 (en) 2006-05-30 2010-03-30 Renesas Technology Corp. Semiconductor device with reduced parasitic inductance
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
US20090085552A1 (en) * 2007-09-29 2009-04-02 Olivier Franza Power management using dynamic embedded power gate domains
DE102008049231A1 (en) * 2008-09-27 2010-04-01 Bayerische Motoren Werke Aktiengesellschaft Circuit and method for its production
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
EP2453476A1 (en) * 2010-11-12 2012-05-16 Nxp B.V. Semiconductor device packaging method and semiconductor device package
US9209766B1 (en) 2012-09-11 2015-12-08 Sandia Corporation High temperature charge amplifier for geothermal applications
US20160149380A1 (en) * 2014-11-20 2016-05-26 Hamilton Sundstrand Corporation Power control assembly with vertically mounted power devices
EP3065172A1 (en) 2015-03-06 2016-09-07 Nxp B.V. Semiconductor device
US10256168B2 (en) 2016-06-12 2019-04-09 Nexperia B.V. Semiconductor device and lead frame therefor
CN108847770B (en) * 2018-05-21 2020-09-04 威创集团股份有限公司 Dual-voltage output mainboard
JP2019213399A (en) * 2018-06-07 2019-12-12 株式会社村田製作所 Power module
EP3790043A4 (en) * 2018-07-10 2021-07-14 Aisin Aw Co., Ltd. Circuit module and power supply chip module
WO2020179161A1 (en) * 2019-03-05 2020-09-10 アイシン・エィ・ダブリュ株式会社 Semiconductor device
US10784854B1 (en) 2019-09-12 2020-09-22 Inno-Tech Co., Ltd. Power control device
CN110752192B (en) * 2019-10-12 2021-05-14 安徽鸿创新能源动力有限公司 Motor controller drive circuit structure
JP6954413B1 (en) * 2020-06-29 2021-10-27 ダイキン工業株式会社 Inverter device
EP4250347A1 (en) 2022-03-24 2023-09-27 Infineon Technologies Austria AG Semiconductor device and method of fabricating a semiconductor device
EP4250359A1 (en) 2022-03-24 2023-09-27 Infineon Technologies Austria AG Semiconductor device and method of fabricating a semiconductor device

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967332A (en) 1990-02-26 1990-10-30 General Electric Company HVIC primary side power supply controller including full-bridge/half-bridge driver
US5331253A (en) * 1992-08-24 1994-07-19 Usi Lighting, Inc. Electronic ballast for gaseous discharge lamp operation
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
JPH08130282A (en) 1994-10-31 1996-05-21 Fuji Electric Co Ltd Semiconductor device
US5629563A (en) 1994-08-25 1997-05-13 National Semiconductor Corporation Component stacking in multi-chip semiconductor packages
US5642262A (en) 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US5747982A (en) 1996-12-05 1998-05-05 Lucent Technologies Inc. Multi-chip modules with isolated coupling between modules
US5818669A (en) * 1996-07-30 1998-10-06 Micro Linear Corporation Zener diode power dissipation limiting circuit
JPH1167947A (en) 1997-08-20 1999-03-09 Sony Corp Surface mounting method of hybrid integrated circuit device, hybrid integrated circuit device and hybrid integrated circuit device package
US6002213A (en) * 1995-10-05 1999-12-14 International Rectifier Corporation MOS gate driver circuit with analog input and variable dead time band
US6031338A (en) 1997-03-17 2000-02-29 Lumatronix Manufacturing, Inc. Ballast method and apparatus and coupling therefor
US6058012A (en) 1996-08-26 2000-05-02 Compaq Computer Corporation Apparatus, method and system for thermal management of an electronic system having semiconductor devices
US6137167A (en) * 1998-11-24 2000-10-24 Micron Technology, Inc. Multichip module with built in repeaters and method
US20020163322A1 (en) * 2000-02-08 2002-11-07 Vlt Corporation, A Texas Corporation Active rectifier

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967332A (en) 1990-02-26 1990-10-30 General Electric Company HVIC primary side power supply controller including full-bridge/half-bridge driver
US5331253A (en) * 1992-08-24 1994-07-19 Usi Lighting, Inc. Electronic ballast for gaseous discharge lamp operation
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US5629563A (en) 1994-08-25 1997-05-13 National Semiconductor Corporation Component stacking in multi-chip semiconductor packages
JPH08130282A (en) 1994-10-31 1996-05-21 Fuji Electric Co Ltd Semiconductor device
US5642262A (en) 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US6002213A (en) * 1995-10-05 1999-12-14 International Rectifier Corporation MOS gate driver circuit with analog input and variable dead time band
US5818669A (en) * 1996-07-30 1998-10-06 Micro Linear Corporation Zener diode power dissipation limiting circuit
US6058012A (en) 1996-08-26 2000-05-02 Compaq Computer Corporation Apparatus, method and system for thermal management of an electronic system having semiconductor devices
US5747982A (en) 1996-12-05 1998-05-05 Lucent Technologies Inc. Multi-chip modules with isolated coupling between modules
US6031338A (en) 1997-03-17 2000-02-29 Lumatronix Manufacturing, Inc. Ballast method and apparatus and coupling therefor
JPH1167947A (en) 1997-08-20 1999-03-09 Sony Corp Surface mounting method of hybrid integrated circuit device, hybrid integrated circuit device and hybrid integrated circuit device package
US6137167A (en) * 1998-11-24 2000-10-24 Micron Technology, Inc. Multichip module with built in repeaters and method
US20020163322A1 (en) * 2000-02-08 2002-11-07 Vlt Corporation, A Texas Corporation Active rectifier
US7015561B2 (en) * 2000-02-08 2006-03-21 Vlt, Inc. Active rectifier

Also Published As

Publication number Publication date
CN1284421C (en) 2006-11-08
US20020021560A1 (en) 2002-02-21
TWI250406B (en) 2006-03-01
WO2001072092A1 (en) 2001-09-27
US6879491B2 (en) 2005-04-12
CN1419798A (en) 2003-05-21
JP2003528449A (en) 2003-09-24
AU2001247631A1 (en) 2001-10-03
US20030016505A1 (en) 2003-01-23
JP3943395B2 (en) 2007-07-11

Similar Documents

Publication Publication Date Title
USRE42658E1 (en) Gate driver multi-chip module
JP4010792B2 (en) Semiconductor device
KR101086751B1 (en) Semiconductor device and power supply system
US7071550B2 (en) Semiconductor module having heat sink serving as wiring line
USRE41869E1 (en) Semiconductor device
US6448643B2 (en) Three commonly housed diverse semiconductor dice
US8044520B2 (en) Semiconductor device
US6603291B2 (en) Integrated FET and driver for use in a synchronous dc-dc conversion circuit
US6133632A (en) Commonly housed diverse semiconductor die
US8148815B2 (en) Stacked field effect transistor configurations
US8422261B2 (en) Semiconductor device and power supply device using the same
US6919643B2 (en) Multi-chip module semiconductor devices
US20110227169A1 (en) Semiconductor device
US20020096748A1 (en) Back-to -back connected power semiconductor device package
JP4344776B2 (en) Semiconductor device
KR20010070032A (en) Semiconductor device
US20190287885A1 (en) Power converter having a conductive clip
JP4709349B2 (en) Semiconductor die housing equipment
JP2006253734A (en) Semiconductor device
JP3583382B2 (en) Semiconductor die mounting structure
TWI430409B (en) Lead frame substrate for manufacturing flip chip device

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: INFINEON TECHNOLOGIES AMERICAS CORP., CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:INTERNATIONAL RECTIFIER CORPORATION;REEL/FRAME:046612/0968

Effective date: 20151001