|Publication number||USRE42423 E1|
|Application number||US 12/266,739|
|Publication date||7 Jun 2011|
|Filing date||7 Nov 2008|
|Priority date||27 Jul 2001|
|Also published as||EP1412985A1, EP1412985A4, EP1412985B1, US7132701, US7638820, US20070117366, WO2003023860A1|
|Publication number||12266739, 266739, US RE42423 E1, US RE42423E1, US-E1-RE42423, USRE42423 E1, USRE42423E1|
|Inventors||Martin E. Kordesch, Howard D. Bartlow, Richard L. Woodin|
|Original Assignee||Fairchild Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (32), Non-Patent Citations (7), Referenced by (2), Classifications (25), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided by the terms of F33615-01-C-1602 awarded by the Air Force Research Laboratory.
1. Field of the Invention
The present invention relates to methods of making semiconductor devices and in particular to methods of providing ohmic contacts to compound semiconductor layers utilized in semiconductor devices.
2. Description of the Related Art
The fabrication and operation of basic transistor devices is well known. New technologies have developed needs for higher speed and power transistors capable of withstanding extreme operating conditions such as high temperatures, current, and radiation. Silicon carbide devices have the potential to fulfill these needs but have yet to achieve commercial success. One obstacle to using silicon carbide in electronic devices is the difficulty in providing electrical contacts to the device.
Electrical contacts to silicon carbide may be formed by reacting a contact metal with silicon carbide. One such method involves melting an alloy on the surface of silicon carbide. When the alloy melts, it dissolves and reacts with a small portion of the silicon carbide to form a contact. A second method of creating a contact involves laminating the surface of the silicon carbide with a contact metal. When annealed, this metal reacts with the silicon carbide to form an ohmic contact. The first method results in a contact that is too large for use in miniature devices. Annealing temperatures in the second method would be destructive to insulating layers. Both methods are incompatible with semiconductor devices having thin silicon carbide layers because of problems with metal spiking.
In order to prevent metal spiking, barrier layers between the contact metal and silicon carbide may be used. In one method a portion of doped silicon carbide is bombarded with ions to produce a heavily doped barrier region to which contact is made. Alternatively, a silicide barrier layer may be formed during annealing. Both of these methods are impractical for forming contacts to thin silicon carbide layers. Ion bombardment is not feasible for thin silicon carbide layers because the highly doped region is likely to extend through the entire layer and into an underlying layer. Similarly, the formation of a silicide barrier layer may electrically short a thin silicon carbide layer to an underlying layer because the reaction can consume the entire thickness of the thin silicon carbide layer and a portion of the underlying layer.
In embodiments described below, the process overcomes the problems above to enable the creation of microscopic contacts and is thus compatible with modern, miniature devices. Another benefit of the described embodiments is that insulating layers created during the process are preserved because of lower process temperatures. Finally, the embodiments described may be used with thin silicon carbide layers without causing electrical shorts through the layer.
In one set of embodiments, a process for forming a contact to a compound semiconductor layer can comprise forming a first compound semiconductor layer over a substrate. The first compound semiconductor layer may have a first conductivity type. The process can also comprise forming a second compound semiconductor layer. The second compound semiconductor layer may have a second conductivity type that is opposite the first conductivity type. The process can further comprise forming a third compound semiconductor layer. The third compound semiconductor layer may have the first conductivity type. The process can still further comprise patterning the third compound semiconductor layer to define an opening with a wall. The process can also comprise forming an insulating material along the wall, and forming a fourth compound semiconductor layer at least partially within the opening. The fourth compound semiconductor layer may have the second conductivity type and a dopant concentration that is higher than a dopant concentration of the second compound semiconductor layer. The fourth compound semiconductor layer may also be electrically connected to the second compound semiconductor layer and may be insulated from the third compound semiconductor layer.
In another set of embodiments, a semiconductor device can comprise a first active layer including a first compound semiconductor material and having a first conductivity type. The semiconductor device may also comprise a second active layer including a second compound semiconductor material and having a second conductivity type opposite the first conductivity type. The second active layer can contact the first active layer. The semiconductor device may further comprise a third active layer that includes a third compound semiconductor material having the first conductivity type. The third active layer can contact the second active layer, and a combination of the first, second, and third active layers can be at least part of a transistor. An opening may extend through the third active layer and contact the second active layer. The semiconductor device can still further comprise a fourth compound semiconductor material at least partially within the opening. The fourth compound semiconductor material may have the second conductivity type and a dopant concentration higher than a dopant concentration of the second active layer and may be electrically connected to the second active layer. The semiconductor device can also comprise a first insulating layer at least partially within opening. The first insulating layer may lie between the third active layer and the fourth compound semiconductor layer.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The present invention is illustrated by way of example and not limitation in the accompanying figures.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Reference is now made in detail to the exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts (elements).
Described generally below is a process for fabricating an electrical connection between a metal contact and a thin layer of silicon carbide while reducing the likelihood of spiking of the silicon carbide layer. The contact process is described in the context of fabricating a planar, multilayered silicon carbide device, but as one skilled in the art may surmise, it may be used for forming connections between any applicable metal and silicon carbide layer.
Layer 12 can have a thickness in a range of approximately 2-20 microns, can be n-type doped with nitrogen, phosphorus, or the like, and can have a dopant concentration in a range of approximately 1E15 to 1E18 atoms per cubic centimeter. Layer 14 can have a thickness in a range of approximately 0.1-2.0 microns, can be p-type doped with aluminum, boron, or the like, and have a dopant concentration in a range of approximately 1E15 to 1E17 atoms per cubic centimeters. Layer 16 can have a thickness in a range of approximately 0.5-2.0 microns, can be n-type doped with nitrogen, phosphorus, or the like, and have a dopant concentration in a range of approximately 1E17 to 1E19 per cubic centimeters. Layer 12 may be a collector, layer 14 may be a base, and layer 16 may be an emitter of a transistor.
Next, openings 20 can be formed by masking layer 16 with aluminum, nickel, or the like (not shown) and etching layer 16. The openings 20 extend through layer 16 and expose a portion of layer 14. A reactive ion etch (RIE) in an ionized CF4/O2/H2 atmosphere may be used.
An insulating layer 30, capable of being anisotropically etched, is then deposited on the exposed surfaces of layer 16 and at least partially within the openings 20 as shown in
As shown in
The desired dopant concentration for the SiC layer 50 is in the range of approximately 1E19-1E20 atoms per cubic centimeter. Dopants can be incorporated by simultaneously co-sputtering, DC sputtering, or by sputtering in the presence of a gas. For example, aluminum may be incorporated by simultaneously co-sputtering, DC sputtering from an aluminum target, or by sputtering in the presence of gaseous trimethyl aluminum (Al(CH3)3). Aluminum may be sputtered with a power in the range of approximately 10-50 watts of DC power. An alternative p-dopant may be boron, which can be added as gaseous diborane (B2H6). Alternatively, the dopants can be alloyed with the silicon carbide target.
Portions of SiC layer 50 overlying the third active layer 16 may be mechanically or chemically removed to expose portions of layer 16, leaving SiC material 50 at least partially within openings 20, as illustrated in
The metal layers 70 and 72 can be annealed to form an ohmic electrical connection or contact with the underlying silicon carbide. Depending upon the metal, the annealing temperature may be in a range of approximately 600° C. 1100° C., which is below the melting temperature of the insulating layer 30. Due to the thickness of the heavily doped silicon carbide layer 50, the reaction region 74 between the metal contact 70 and the heavily doped silicon carbide 50 that occurs when the metal is annealed should not extend through the thin layer 14. In this particular embodiment, region 74 does not physically contact layer 14.
Insulating layer 80 can be deposited on layer 16 and metal layers 70 and 72 as shown in
Additional compound semiconductor layers having appropriate contacts and conductivity types may be incorporated to create devices such as thyristors.
Accordingly, devices produced can exhibit faster performance because the active layer 14 can be thin and not exhibit high contact resistance or junction spiking. Further, high temperature anneals are not required at stages where insulating material may be damaged, thus processing is simplified and reduced. Also, as shown in
Because of these benefits, transistors produced according to the process described herein may operate in any standard transistor application and are particularly suited for wireless communication base amplifiers or high power switching devices where these devices may be smaller and faster than existing devices. In RF applications such as amplification, the devices may handle approximately 120 volts and up to approximately 5 watts per millimeter perimeter at roughly 3 gigahertz. Power switching devices may handle approximately 2000 volts and may have a switching frequency around 1 megahertz. Devices can be scalable so that greater power levels may be utilized.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
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|U.S. Classification||257/198, 257/E21.371, 438/318, 257/E21.541, 257/E29.188|
|International Classification||H01L29/737, H01L21/203, H01L29/24, H01L21/331, H01L21/04, H01L29/732|
|Cooperative Classification||H01L21/0485, H01L29/45, H01L29/66068, H01L29/0649, H01L29/1608, H01L29/1004, H01L29/732, H01L29/74|
|European Classification||H01L29/732, H01L21/04H10A, H01L29/66M4T, H01L29/06B3C, H01L29/45, H01L29/10B|
|28 Apr 2014||FPAY||Fee payment|
Year of fee payment: 8
|19 Sep 2016||AS||Assignment|
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:FAIRCHILD SEMICONDUCTOR CORPORATION;REEL/FRAME:040075/0644
Effective date: 20160916