USRE41764E1 - Semiconductor device with compensated threshold voltage and method for making same - Google Patents

Semiconductor device with compensated threshold voltage and method for making same Download PDF

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USRE41764E1
USRE41764E1 US11/318,397 US31839700A USRE41764E US RE41764 E1 USRE41764 E1 US RE41764E1 US 31839700 A US31839700 A US 31839700A US RE41764 E USRE41764 E US RE41764E
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pockets
dopant
conductivity type
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semiconductor device
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Thomas Skotnicki
Romain Gwoziecki
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Liberty Patents LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface

Definitions

  • the present invention relates in general to a semiconductor device, such as an MOS transistor, in which there is compensation for the drop in the threshold voltage (V th ) due to the short-channel effects, and to a process for fabrication of such a semiconductor device.
  • a semiconductor device such as an MOS transistor
  • V th the threshold voltage (V th ) drops suddenly, in particular for short-channel transistors (i.e., those having a channel length of less than 0.25 ⁇ m and typically a channel length, L, of about 0.18 ⁇ m).
  • the threshold voltage of a semiconductor device such as an MOS transistor, in particular a short-channel device, is a critical parameter of the device. This is because the leakage current of the device (for example, of the transistor) depends strongly on the threshold voltage. Taking into consideration current supply voltages and those envisaged in the future (from 0.9 to 1.8 volts) for such devices and the permitted leakage currents (I off of approximately 1 nA/ ⁇ m), the threshold voltage V th must have values of approximately 0.2 to 0.25 volts.
  • the sudden voltage drop (or roll-off) in the zones of the channel region of the semiconductor device results in dispersion of the electrical characteristics of the device and makes it difficult to obtain the desired threshold voltages.
  • a semiconductor device such as an MOS transistor, whose voltage threshold roll-off due to the short-channel effects is almost fully compensated for may be desired. This makes it possible to achieve channel lengths which are arbitrarily small but non-zero.
  • a semiconductor device such as an MOS transistor, may have a constant threshold voltage, V th , when the channel length, L, decreases down to very small effective channel lengths, for example, 0.025 ⁇ m or less.
  • a process for fabricating a semiconductor device may apply to devices having channels of arbitrarily small length, these being, moreover, technologically realizable.
  • a semiconductor device may have a semiconductor substrate with a predetermined concentration, Ns, of a dopant of a first conductivity type.
  • the device may have source and drain regions which are doped with a dopant of a second conductivity type, which is opposite of the first conductivity type.
  • Junctions delimiting a channel region of predetermined nominal length, L N may be defined in the substrate.
  • a first pocket adjacent to each of the junctions and having a predetermined length, Lp may be defined.
  • the first pockets may be doped with a dopant of the first conductivity type but with a local concentration, Np, which locally increases the net concentration in the substrate.
  • the device may include at least one second pocket located adjacent to each of the junctions and stacked against each of the first pockets.
  • These second pockets may have a length, Ln, such that Ln>Lp.
  • the second pockets may be doped with a dopant of the second conductivity type and have a concentration, Nn, such that Nn ⁇ Np. This may locally decrease the net concentration of the substrate without changing the conductivity type.
  • the second pockets include a plurality of elementary pockets stacked against one another.
  • Each elementary pocket of a given rank, i may have a predetermined length, Ln i , and a predetermined concentration, Nn i , of a dopant of the second conductivity type satisfying the following relationships:
  • the second pockets decrease the net concentration of dopant of the first conductivity type both in the first pockets and in the channel region. However, they do not change the conductivity type of the first pockets nor of the channel region.
  • a process for fabricating a semiconductor device as defined above may include the formation of a source region and of a drain region in a semiconductor substrate having a predetermined concentration, Ns, of a dopant of a first conductivity type.
  • the source region and the drain region may be doped with a dopant of a second conductivity type, which is opposite of the first conductivity type.
  • the source and drain regions may form one or more junctions in the substrate such that the junctions delimit between them a channel region.
  • the channel region may have a predetermined nominal length, L N .
  • one or more first pockets may be formed having a predetermined length, Lp, and a predetermined concentration, Np.
  • the process may furthermore include the implantation, in the channel region, of a dopant of the second conductivity type, which is opposite of the first conductivity type. This may be done under a set of conditions such that at least one second pocket is formed in the channel region. Each second pocket may be stacked against each of the first pockets, respectively.
  • the second pocket may have a length, Ln, such that Ln>Lp, and a concentration, Nn, of a dopant of the first type such that Nn ⁇ Np. This may locally decrease the net concentration in the substrate, without changing the conductivity type.
  • the implantation of the dopant of the second conductivity type consists of a series of successive implantations under a set of conditions such that the second pockets formed each consist of a plurality of elementary pockets stacked against one another.
  • Each elementary pocket of a given rank, i may have a length, Ln i , and a concentration, Nn i , of a dopant of the second conductivity type satisfying the relationships:
  • the lengths Lp and Ln of the pockets are taken from the junctions.
  • Implantation of a dopant in a semiconductor substrate is a known process and it is possible, in the present process, to use any implantation process conventionally used in the technology of semiconductors.
  • the formation of doped pockets in a semiconductor substrate depends on the angle of incidence of the implantation with respect to the normal to the substrate, on the implantation dose, and on the implantation energy of the dopant.
  • the angle of incidence and the dopant dose it is possible to increase the length of the implanted pocket and to vary the dopant concentration.
  • successive implantation steps may be carried out with the same angle of incidence with respect to the normal, the same dose, and the same implantation energy.
  • subjecting the device to a different annealing heat treatment step after each successive implantation step may make the dopant implanted in the substrate diffuse differently for each implanted pocket.
  • FIG. 1 a first embodiment of a semiconductor device, such as an MOS transistor;
  • FIG. 2 a second embodiment of a semiconductor device
  • FIG. 3 a graph of the threshold voltage (V th ) for various semiconductor devices as a function of the effective channel length.
  • FIG. 1 shows a first embodiment of a semiconductor device, such as an MOS transistor.
  • the semiconductor device may include a semiconductor substrate 1 , which may be, for example, a silicon substrate doped with a dopant of a first conductivity type (for example, p-type conductivity).
  • Source 2 and drain 3 regions may be formed in the substrate 1 and doped with a dopant of a second conductivity type, which is opposite of the first conductivity type (for example, an n-type dopant).
  • the source and drain regions may, in the substrate, define junctions 4 , 5 delimiting between them a channel region 6 .
  • the channel region 6 may be covered with a gate oxide layer 11 (for example, a thin silicon oxide layer), which is itself surmounted by a gate 12 (for example, a gate made of silicon).
  • the gate 12 may be flanked on two opposed sides by spacers 13 , 14 made of a suitable dielectric.
  • each pocket may be adjacent to one of the junctions 4 , 5 , respectively.
  • These pockets are doped by means of a dopant of the first conductivity type, p, but with a concentration, Np, of dopant which locally increases the concentration in the substrate to above Ns and has a length, Lp, as short as possible.
  • Two second pockets 9 , 10 are formed in the channel region 6 .
  • the second pockets are each stacked against one of the first pockets, but with a length, Ln, greater than the length, Lp, of the first pockets.
  • the second pockets are doped with a dopant of the second conductivity type.
  • the dopant may be an n-type dopant with a concentration, Nn, such that Nn is less than the concentration Np of dopant of the first conductivity type in the substrate.
  • the net concentration of dopant of the first conductivity type (for example, the p-type dopant) is decreased but the nature of the conductivity in the channel region is not changed.
  • the channel may still remain a region of p-type conductivity.
  • FIG. 2 shows another embodiment of a semiconductor device.
  • the second pockets 9 , 10 may include pluralities of elementary pockets stacked against one another.
  • pluralities of elementary pockets may include three elementary pockets as shown in the embodiment of FIG. 2 .
  • Each elementary pocket of a given rank, i has a length, Ln i , and a concentration, Nni, of dopant of the second conductivity type which satisfy the following relationships:
  • the elementary pockets stacked against the first pockets 7 and 8 are also stacked against one another. However, they have increasing lengths and, concurrently, concentrations of dopant of the first conductivity type which decrease as their lengths increase.
  • the sum of the concentrations, ⁇ Nn i , of the stacked elementary pockets is such that it remains less than the concentration, Ns, of dopant of the first conductivity type in the substrate so that the conductivity type of the channel region 6 is not modified.
  • the second pockets consist of three elementary pockets.
  • the lengths and dopant concentrations of the elementary pockets satisfy the relationships:
  • FIG. 3 shows simulated graphs of the threshold voltage, V th , for transistors having a gate oxide layer 4 nm in thickness and for a drain/source voltage of 1.5 volts as a function of the effective channel length.
  • the lengths, Lp, and the concentrations, Np, of the first pockets doped with a dopant of the same type as the substrate correspond to the minimum channel length to be obtained and the highest doping.
  • Curve A corresponds to the stacking of a single second pocket and shows that a flat V th is obtained for a channel length down to 0.15 ⁇ m.
  • Curve B corresponds to the stacking of two second pockets and shows that a flat V th is obtained for a channel length down to 0.07 ⁇ m.
  • curve C corresponds to the stacking of seven second pockets and shows that a flat V th can be obtained for a channel length down to 0.025 ⁇ m.

Abstract

A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device, such as an MOS transistor, in which there is compensation for the drop in the threshold voltage (Vth) due to the short-channel effects, and to a process for fabrication of such a semiconductor device.
2. Description of the Related Art
For a given nominal channel length (L) of a transistor, the threshold voltage (Vth) drops suddenly, in particular for short-channel transistors (i.e., those having a channel length of less than 0.25 μm and typically a channel length, L, of about 0.18 μm).
The threshold voltage of a semiconductor device such as an MOS transistor, in particular a short-channel device, is a critical parameter of the device. This is because the leakage current of the device (for example, of the transistor) depends strongly on the threshold voltage. Taking into consideration current supply voltages and those envisaged in the future (from 0.9 to 1.8 volts) for such devices and the permitted leakage currents (Ioff of approximately 1 nA/μm), the threshold voltage Vth must have values of approximately 0.2 to 0.25 volts.
The sudden voltage drop (or roll-off) in the zones of the channel region of the semiconductor device results in dispersion of the electrical characteristics of the device and makes it difficult to obtain the desired threshold voltages.
To remedy this threshold voltage roll-off in semiconductor devices such as MOS transistors, it has been proposed, as described in the article “Self-Aligned Control of Threshold Voltages in Sub-0.02-μm MOSFETs” by Hajima Kurata and Toshihiro Sugii, IEEE Transactions on Electron Devices, Vol. 45, No. Oct. 10, 1998, to form, in the channel region, pockets adjacent to the source and drain region junctions that have a conductivity of the same type as the substrate; but in which, the dopant concentration is greater than that of the substrate.
Although this solution reduces the threshold voltage roll-off gradient in the channel region, the short-channel effects lead to a more rapid roll-off of the threshold voltage, Vth, than the increase in the threshold voltage that can be obtained by incorporating the compensation pockets of the prior art.
Consequently, although these compensation pockets allow partial local compensation for the roll-off of the threshold voltage, Vth, it is not possible to obtain complete compensation for the roll-off over the entire channel region range desired.
Therefore a semiconductor device, such as an MOS transistor, that remedies the drawbacks of the devices of the prior art may be desired.
More particularly, a semiconductor device, such as an MOS transistor, whose voltage threshold roll-off due to the short-channel effects is almost fully compensated for may be desired. This makes it possible to achieve channel lengths which are arbitrarily small but non-zero.
Also a semiconductor device, such as an MOS transistor, may have a constant threshold voltage, Vth, when the channel length, L, decreases down to very small effective channel lengths, for example, 0.025 μm or less.
A process for fabricating a semiconductor device may apply to devices having channels of arbitrarily small length, these being, moreover, technologically realizable.
DESCRIPTION OF THE INVENTION
A semiconductor device is described that may have a semiconductor substrate with a predetermined concentration, Ns, of a dopant of a first conductivity type. The device may have source and drain regions which are doped with a dopant of a second conductivity type, which is opposite of the first conductivity type. Junctions delimiting a channel region of predetermined nominal length, LN, may be defined in the substrate. A first pocket adjacent to each of the junctions and having a predetermined length, Lp, may be defined. The first pockets may be doped with a dopant of the first conductivity type but with a local concentration, Np, which locally increases the net concentration in the substrate. The device may include at least one second pocket located adjacent to each of the junctions and stacked against each of the first pockets. These second pockets may have a length, Ln, such that Ln>Lp. The second pockets may be doped with a dopant of the second conductivity type and have a concentration, Nn, such that Nn<Np. This may locally decrease the net concentration of the substrate without changing the conductivity type.
In an embodiment, the second pockets include a plurality of elementary pockets stacked against one another. Each elementary pocket of a given rank, i, may have a predetermined length, Lni, and a predetermined concentration, Nni, of a dopant of the second conductivity type satisfying the following relationships:
    • Ln1>Lp,
    • Lni−1<Lni<Lni+1,
    • Nni−1>Nni>Nni+1, and
    • the sum, ΣNni, of the concentrations of the dopant of the second conductivity type in the elementary pockets may be such that:
    • ΣNni<Ns.
In other words, the second pockets decrease the net concentration of dopant of the first conductivity type both in the first pockets and in the channel region. However, they do not change the conductivity type of the first pockets nor of the channel region.
A process for fabricating a semiconductor device as defined above is described. The process may include the formation of a source region and of a drain region in a semiconductor substrate having a predetermined concentration, Ns, of a dopant of a first conductivity type. The source region and the drain region may be doped with a dopant of a second conductivity type, which is opposite of the first conductivity type. The source and drain regions may form one or more junctions in the substrate such that the junctions delimit between them a channel region. The channel region may have a predetermined nominal length, LN. In the channel region in a zone adjacent to each of the junctions, one or more first pockets may be formed having a predetermined length, Lp, and a predetermined concentration, Np. This may locally increase the net concentration in the substrate above Ns. The process may furthermore include the implantation, in the channel region, of a dopant of the second conductivity type, which is opposite of the first conductivity type. This may be done under a set of conditions such that at least one second pocket is formed in the channel region. Each second pocket may be stacked against each of the first pockets, respectively. The second pocket may have a length, Ln, such that Ln>Lp, and a concentration, Nn, of a dopant of the first type such that Nn<Np. This may locally decrease the net concentration in the substrate, without changing the conductivity type.
In a preferred embodiment, the implantation of the dopant of the second conductivity type consists of a series of successive implantations under a set of conditions such that the second pockets formed each consist of a plurality of elementary pockets stacked against one another. Each elementary pocket of a given rank, i, may have a length, Lni, and a concentration, Nni, of a dopant of the second conductivity type satisfying the relationships:
    • Ln1>Lp,
    • Lni−1<Lni<Lni+1,
    • Nni−1>Nni>Nni+1, and
    • the sun sum, ΣNni, of the concentrations of the dopant of the second conductivity type in the elementary pockets being such that:
    • ΣNni<Ns.
The lengths Lp and Ln of the pockets are taken from the junctions.
Implantation of a dopant in a semiconductor substrate is a known process and it is possible, in the present process, to use any implantation process conventionally used in the technology of semiconductors.
As is known, the formation of doped pockets in a semiconductor substrate depends on the angle of incidence of the implantation with respect to the normal to the substrate, on the implantation dose, and on the implantation energy of the dopant. Thus, by varying the angle of incidence and the dopant dose, it is possible to increase the length of the implanted pocket and to vary the dopant concentration.
As a variant, in order to vary the length of the second implanted pockets and their dopant concentration, successive implantation steps may be carried out with the same angle of incidence with respect to the normal, the same dose, and the same implantation energy. However, subjecting the device to a different annealing heat treatment step after each successive implantation step may make the dopant implanted in the substrate diffuse differently for each implanted pocket.
BRIEF DESCRIPTION OF THE DRAWINGS
The remainder of the description refers to the appended figures, which show respectively:
FIG. 1, a first embodiment of a semiconductor device, such as an MOS transistor;
FIG. 2, a second embodiment of a semiconductor device; and
FIG. 3, a graph of the threshold voltage (Vth) for various semiconductor devices as a function of the effective channel length.
 DETAILED DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a first embodiment of a semiconductor device, such as an MOS transistor. The semiconductor device may include a semiconductor substrate 1, which may be, for example, a silicon substrate doped with a dopant of a first conductivity type (for example, p-type conductivity). Source 2 and drain 3 regions may be formed in the substrate 1 and doped with a dopant of a second conductivity type, which is opposite of the first conductivity type (for example, an n-type dopant). The source and drain regions may, in the substrate, define junctions 4, 5 delimiting between them a channel region 6.
The channel region 6 may be covered with a gate oxide layer 11 (for example, a thin silicon oxide layer), which is itself surmounted by a gate 12 (for example, a gate made of silicon). The gate 12 may be flanked on two opposed sides by spacers 13, 14 made of a suitable dielectric.
To reduce the rate of roll-off of the threshold voltage, Vth, in the channel region 6, two first pockets 7, 8 are formed in the channel region. Each pocket may be adjacent to one of the junctions 4, 5, respectively. These pockets are doped by means of a dopant of the first conductivity type, p, but with a concentration, Np, of dopant which locally increases the concentration in the substrate to above Ns and has a length, Lp, as short as possible.
Two second pockets 9, 10 are formed in the channel region 6. The second pockets are each stacked against one of the first pockets, but with a length, Ln, greater than the length, Lp, of the first pockets. The second pockets are doped with a dopant of the second conductivity type. For example, the dopant may be an n-type dopant with a concentration, Nn, such that Nn is less than the concentration Np of dopant of the first conductivity type in the substrate.
Thus, in the zones of the second pockets, the net concentration of dopant of the first conductivity type (for example, the p-type dopant) is decreased but the nature of the conductivity in the channel region is not changed. The channel may still remain a region of p-type conductivity.
FIG. 2, in which the same reference numbers denote the same elements as previously, shows another embodiment of a semiconductor device. FIG. 2 shows that the second pockets 9, 10 may include pluralities of elementary pockets stacked against one another. For example, pluralities of elementary pockets may include three elementary pockets as shown in the embodiment of FIG. 2.
Each elementary pocket of a given rank, i, has a length, Lni, and a concentration, Nni, of dopant of the second conductivity type which satisfy the following relationships:
    • Lp<Lni,
    • Lni−1<Lni<Lni+1,
    • Nni−1<Nni<Nni+1, and
    • the sum ΣNni of the concentrations of the dopant of the second conductivity type in the elementary pockets being such that:
    • ΣNni<Ns.
In other words, the elementary pockets stacked against the first pockets 7 and 8 are also stacked against one another. However, they have increasing lengths and, concurrently, concentrations of dopant of the first conductivity type which decrease as their lengths increase.
Moreover, the sum of the concentrations, ΣNni, of the stacked elementary pockets is such that it remains less than the concentration, Ns, of dopant of the first conductivity type in the substrate so that the conductivity type of the channel region 6 is not modified.
Thus, in the case shown in FIG. 2, in which the second pockets consist of three elementary pockets. The lengths and dopant concentrations of the elementary pockets satisfy the relationships:
    • Lp<Ln1,
    • Ln1<Ln2<Ln3,
    • Nn1>Nn2>Nn3, and
    • Nn1+Nn2+Nn3<Ns.
FIG. 3 shows simulated graphs of the threshold voltage, Vth, for transistors having a gate oxide layer 4 nm in thickness and for a drain/source voltage of 1.5 volts as a function of the effective channel length. The lengths, Lp, and the concentrations, Np, of the first pockets doped with a dopant of the same type as the substrate correspond to the minimum channel length to be obtained and the highest doping.
Curve A corresponds to the stacking of a single second pocket and shows that a flat Vth is obtained for a channel length down to 0.15 μm.
Curve B corresponds to the stacking of two second pockets and shows that a flat Vth is obtained for a channel length down to 0.07 μm.
Finally, curve C corresponds to the stacking of seven second pockets and shows that a flat Vth can be obtained for a channel length down to 0.025 μm.
Thus, the above curves show that the necessary doping levels remain reasonable and make it possible to obtain flat curves of Vth as a function of the effective channel length down to effective lengths of 25 nm. This may be so even with gate oxide thicknesses of 4 nm.

Claims (49)

1. A semiconductor device, comprising:
a semiconductor substrate having a predetermined concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions, wherein the junctions delimit a channel region of a predetermined length, LN, in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets located adjacent to each of the junctions, wherein the pockets have a predetermined length, Lp, wherein the first pockets are doped with a dopant of the first conductivity type with a dopant concentration, Np, which locally increases a net concentration in the substrate above Ns;
second pockets located adjacent to each of the junctions and stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, and wherein the second pockets are doped with a dopant of the second conductivity type with a dopant concentration, Nn, such that Nn is less than Np, which locally decreases a net concentration without changing a conductivity type, and wherein Nn is less than Ns; and
wherein an overall length of the first pockets and the second pockets is less than the length, LN, of the channel region.
2. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other.
3. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other, wherein each elementary pocket comprises a rank, i, and a predetermined length, Lni, wherein a predetermined concentration, Nni, of a dopant of the second conductivity type satisfies the relationships:
Ln1>Lp;
Lni−1<Lni<Lni+1;
Nni−1>Nni>Nni+1; and
wherein the sum, ΣNni, of the concentrations of the dopant in the elementary pockets satisfies the relationship, ΣNni<Ns.
4. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other, and wherein the plurality of elementary pockets comprises three elementary pockets.
5. The semiconductor device of claim 1, wherein the semiconductor device comprises an MOS transistor.
6. The semiconductor device of claim 1, wherein the first conductivity type comprises p-type conductivity.
7. The semiconductor device of claim 1, wherein the second conductivity type comprises n-type conductivity.
8. A method for fabricating a semiconductor device, comprising:
forming a semiconductor substrate with a predetermined concentration, Ns, of a dopant of a first conductivity type;
forming a source region and a drain region by doping the source and drain regions with a dopant of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, wherein the source and drain regions form junctions that delimit a channel region between them, and wherein the channel region comprises a predetermined length, LN;
forming first pockets adjacent to each of the junctions in the channel region, wherein the first pockets are formed by doping each of the first pockets with a predetermined concentration, Np, of a dopant of the first conductivity type, which locally increases a net concentration in the substrate above Ns, and wherein each of the first pockets comprises a predetermined length, Lp; and
implanting in the channel region a dopant of the second conductivity type under a set of conditions such that second pockets are formed in the channel region, wherein the second pockets are stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, wherein the second pockets have a concentration, Nn, of the dopant of the second conductivity type such that Nn is less than Np, which locally decreases a net concentration without changing a conductivity type, wherein Nn is less than Ns, and wherein the overall length of the first pockets and the second pockets is less than the nominal length, LN, of the channel region.
9. The method of claim 8, wherein implanting in the channel region comprises a series of successive implanting steps such that the second pockets comprise a plurality of elementary pockets.
10. The method of claim 8, wherein implanting in the channel region comprises a series of successive implantion implantation steps such that the second pockets comprise comprises a plurality of elementary pockets, wherein each elementary pocket comprises a rank, i, and a predetermined length, Lni, and wherein a predetermined concentration, Nni, of a dopant of the second conductivity type satisfies the relationships:
Ln1>Lp;
Lni−1<Lni<Lni+1;
Nni−1>Nni>Nni+1; and
wherein the sum, ΣNni of the concentrations of the dopant in the elementary pockets satisfies the relationship, ΣNni<Ns.
11. The method of claim 10, further comprising increasing an implantation angle of incidence with respect to the normal angle to the substrate with each successive implantion implantation step and decreasing an implantation dose with each successive implantion implantation step.
12. The method of claim 10, wherein the successive implanting steps comprise implanting the dopant of the second conductivity type using a same angle of incidence with respect to the normal angle to the substrate, a same implantation dose, and a same implantation energy in each successive implantion implantation step, the method further comprising annealing the device in an annealing step after each successive implantion implantation step, wherein each annealing step is different.
13. The method of claim 8, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate, an implantation dose, and an implantation energy.
14. The method of claim 8, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate.
15. The method of claim 8, wherein the set of conditions comprises an implantation dose.
16. The method of claim 8, wherein the set of conditions comprises an implantation energy.
17. The method of claim 8, further comprising forming an MOS transistor with the semiconductor device.
18. The method of claim 8, wherein the first conductivity type comprises p-type conductivity.
19. The method of claim 8, wherein the second conductivity type comprises n-type conductivity.
20. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions that define a channel region of a length, LN, in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets located adjacent to each of the junctions, wherein the first pockets have a length, Lp, and wherein the first pockets are doped with a dopant of the first conductivity type with a dopant concentration, Np;
second pockets stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, wherein the second pockets are doped with a dopant of the second conductivity type with a dopant concentration, Nn, such that Nn is less than Np; and
wherein an overall length of the first pockets and the second pockets is less than the length, LN, of the channel region.
21. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions that define a channel region of a length, L N , in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets including a pocket located adjacent to each of the junctions, wherein each of the first pockets is doped with a dopant of the first conductivity type with a dopant concentration, Np;
second pockets including one pocket stacked against each of the first pockets, wherein each of the second pockets is doped with a dopant of the second conductivity type with a dopant concentration, Nn; and
wherein an overall length of the first pockets and the second pockets is less than the length, L N , of the channel region.
22. The semiconductor device of claim 21, wherein the first pockets each have a length, Lp, and the second pockets each have a length, Ln, and wherein Ln is greater than Lp.
23. The semiconductor device of claim 21, wherein Nn is less than Np.
24. The semiconductor device of claim 21, wherein each of the second pockets comprise a plurality of elementary pockets stacked against each other.
25. The semiconductor device of claim 21, wherein each of the second pockets comprises a plurality of elementary pockets stacked against each other, wherein each elementary pocket in one of the second pockets has a rank, i, a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type satisfying the relationships:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the elementary pockets in one of the second pockets satisfies the relationship, ΣNn i <Ns.
26. The semiconductor device of claim 21, wherein each of the second pockets comprises a plurality of elementary pockets stacked against each other, and wherein the plurality of elementary pockets comprises three elementary pockets.
27. The semiconductor device of claim 21, wherein the semiconductor device comprises an MOS transistor.
28. The semiconductor device of claim 21, wherein the first conductivity type is p-type conductivity.
29. The semiconductor device of claim 21, wherein the second conductivity type is n-type conductivity.
30. A method for fabricating a semiconductor device, comprising:
forming a semiconductor substrate with a concentration, Ns, of a dopant of a first conductivity type;
forming a source region and a drain region by doping the source and drain regions with a dopant of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, wherein the source and drain regions form junctions that delimit a channel region between them, and wherein the channel region comprises a length, L N;
forming first pockets including a pocket adjacent to each of the junctions in the channel region, wherein each of the first pockets is formed by doping each of the first pockets with a concentration, Np, of a dopant of the first conductivity type; and
implanting in the channel region a dopant of the second conductivity type under a set of conditions such that second pockets are formed in the channel region, wherein the second pockets include a pocket stacked against each of the first pockets, wherein the second pockets have a concentration, Nn, of the dopant of the second conductivity type, and wherein the overall length of the first pockets and the second pockets is less than the length, L N , of the channel region.
31. The method of claim 30, wherein forming the first pockets with the concentration, Np, locally increases a net concentration in the substrate above Ns.
32. The method of claim 30, wherein each of the first pockets has a length, Lp, and each of the second pockets have a length, Ln, and wherein Ln is greater than Lp.
33. The method of claim 30, wherein Nn is less than Np which locally decreases a net concentration without changing a conductivity type.
34. The method of claim 30, wherein Nn is less than Ns.
35. The method of claim 30, wherein implanting in the channel region comprises a series of successive implanting steps such that each of the second pockets comprises a plurality of elementary pockets.
36. The method of claim 30, wherein implanting in the channel region comprises a series of successive implantation steps such that each of the second pockets comprises a plurality of elementary pockets, wherein each elementary pocket has a rank, i, a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type satisfying the relationships:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the elementary pockets in each of the second pockets satisfies the relationship, ΣNn i <Ns.
37. The method of claim 36, further comprising increasing an implantation angle of incidence with respect to the normal angle to the substrate with each successive implantation step and decreasing an implantation dose with each successive implantation step.
38. The method of claim 36, wherein the successive implanting steps comprise implanting the dopant of the second conductivity type using a same angle of incidence with respect to the normal angle to the substrate, a same implantation dose, and a same implantation energy in each successive implantation step, the method further comprising annealing the device in an annealing step after each successive implantation step, wherein each annealing step is different.
39. The method of claim 30, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate.
40. The method of claim 30, wherein the set of conditions relates to an implantation dose.
41. The method of claim 30, wherein the set of conditions relates to an implantation energy.
42. The method of claim 30, further comprising forming a MOS transistor with the semiconductor device.
43. The method of claim 30, wherein the first conductivity type is p-type conductivity.
44. The method of claim 43, wherein the second conductivity type is n-type conductivity.
45. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
first and second junctions that define a channel region of a length, L N , in the substrate, wherein the first and seocnd junctions are defined by the source region and the drain region, respectively;
a first set of pockets that includes a first pocket and a second pocket, wherein the first and second pockets are located adjacent to the first and second junctions, respectively, and wherein each of the first set of pockets is doped with a dopant of the first conductivity type with a dopant concentration, Np;
a second set of pockets that includes at least one pocket in the channel region adjacent to the first pocket, and at least one pocket in the channel region adjacent to the second pocket, wherein each of the second set of pockets is doped with a dopant of the second conductivity type with a dopant concentration, Nn; and
wherein an overall length of the first set of pockets and the second set of pockets is less than the length, L N , of the channel region.
46. The semiconductor device of claim 45, wherein each of the first set of pockets has a length, Lp, and each of the second set of pockets has a length, Ln, and wherein Ln is greater than Lp.
47. The semiconductor device of claim 45, wherein Nn is less than Np.
48. The semiconductor device of claim 45, wherein the second set of pockets includes:
a first group of at least two pockets located adjacent to the first pocket in the channel region, wherein the first group of at least two pockets are stacked against one another;
a second group of at least two pockets located adjacent to the second pocket in the channel region, wherein the second group of at least two pockets are stacked against one andother;
49. The semiconductor device of claim 45, wherein the second set of pockets includes at least two pockets stacked against each of the first set of pockets, wherein each of the at least two pockets stacked against each of the first set of pockets has a rank, i, and a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type that satisfy the relationship:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1 ;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the second set of pockets satisfies the relationship, ΣNn i <Ns.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9548401B2 (en) * 2014-11-20 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2794898B1 (en) 1999-06-11 2001-09-14 France Telecom SEMICONDUCTOR DEVICE WITH COMPENSATED THRESHOLD VOLTAGE AND MANUFACTURING METHOD
JP2005116891A (en) * 2003-10-09 2005-04-28 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
CN100373621C (en) * 2004-10-28 2008-03-05 电子科技大学 CMOS device with longitudinal ring grating non-homogeneous germanium silicon doped channel
US8134142B2 (en) * 2006-01-25 2012-03-13 Nxp B.V. Tunneling transistor with barrier
SG136058A1 (en) * 2006-03-10 2007-10-29 Chartered Semiconductor Mfg Integrated circuit system with double doped drain transistor
US7855110B2 (en) * 2008-07-08 2010-12-21 International Business Machines Corporation Field effect transistor and method of fabricating same

Citations (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4154626A (en) 1975-09-22 1979-05-15 International Business Machines Corporation Process of making field effect transistor having improved threshold stability by ion-implantation
US4276095A (en) 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4636822A (en) 1984-08-27 1987-01-13 International Business Machines Corporation GaAs short channel lightly doped drain MESFET structure and fabrication
US4683485A (en) 1985-12-27 1987-07-28 Harris Corporation Technique for increasing gate-drain breakdown voltage of ion-implanted JFET
US4801555A (en) 1987-01-14 1989-01-31 Motorola, Inc. Double-implant process for forming graded source/drain regions
US4851360A (en) 1986-09-29 1989-07-25 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US4966859A (en) 1982-03-09 1990-10-30 Siemens Aktiengesellschaft Voltage-stable sub-μm MOS transistor for VLSI circuits
US4968639A (en) 1987-12-21 1990-11-06 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing CMOS integrated devices with reduced gate lengths
US4987088A (en) 1988-07-29 1991-01-22 Sgs-Thomson Microelectronics S.R.L. Fabrication of CMOS devices with reduced gate length
US5006477A (en) 1988-11-25 1991-04-09 Hughes Aircraft Company Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
US5021851A (en) 1988-05-03 1991-06-04 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US5045898A (en) 1988-08-30 1991-09-03 At&T Bell Laboratories CMOS integrated circuit having improved isolation
US5132753A (en) 1990-03-23 1992-07-21 Siliconix Incorporated Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
US5143857A (en) 1988-11-07 1992-09-01 Triquint Semiconductor, Inc. Method of fabricating an electronic device with reduced susceptiblity to backgating effects
US5270235A (en) 1988-01-06 1993-12-14 Seiko Epson Corporation Semiconductor device fabrication
JPH06318698A (en) 1993-05-06 1994-11-15 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5371394A (en) 1993-11-15 1994-12-06 Motorola, Inc. Double implanted laterally diffused MOS device and method thereof
US5409848A (en) 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US5422510A (en) 1992-10-30 1995-06-06 Analog Devices, Incorporated MOS transistor with non-uniform channel dopant profile
US5449937A (en) 1993-03-19 1995-09-12 Sharp Kabushiki Kaisha Field effect transistor with short channel and manufacturing method therefor
US5548148A (en) 1994-04-15 1996-08-20 International Business Machines Corporation MOS channel device with counterdoping of ion implant for reduced substrate sensitivity
EP0763855A2 (en) 1995-09-18 1997-03-19 Texas Instruments Incorporated Asymmetrical FET and method of fabrication
US5675166A (en) 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US5716861A (en) 1991-06-26 1998-02-10 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5731611A (en) 1996-01-30 1998-03-24 Megamos Corporation MOSFET transistor cell manufactured with selectively implanted punch through prevent and threshold reductoin zones
US5759901A (en) 1995-04-06 1998-06-02 Vlsi Technology, Inc. Fabrication method for sub-half micron CMOS transistor
US5767557A (en) 1994-12-01 1998-06-16 Lucent Technologies Inc. PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom
US5770880A (en) 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
US5827763A (en) 1997-01-30 1998-10-27 Advanced Micro Devices, Inc. Method of forming a multiple transistor channel doping using a dual resist fabrication sequence
US5858827A (en) 1994-09-29 1999-01-12 Sony Corporation Method of manufacturing MOS transistor device with improved threshold value control and reduced reverse short channel effect
US5874329A (en) 1996-12-05 1999-02-23 Lsi Logic Corporation Method for artificially-inducing reverse short-channel effects in deep sub-micron CMOS devices
US6020244A (en) 1996-12-30 2000-02-01 Intel Corporation Channel dopant implantation with automatic compensation for variations in critical dimension
US6091111A (en) 1995-01-17 2000-07-18 National Semiconductor Corporation High voltage mos device having an extended drain region with different dopant species
US6150200A (en) 1998-04-03 2000-11-21 Motorola, Inc. Semiconductor device and method of making
US6172406B1 (en) 1997-08-26 2001-01-09 Texas Instruments Incorporated Breakdown drain extended NMOS
US6284579B1 (en) 1999-10-14 2001-09-04 Taiwan Semiconductor Manufacturing Company Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications
US6352912B1 (en) 2000-03-30 2002-03-05 International Business Machines Corporation Reduction of reverse short channel effects by deep implantation of neutral dopants
US20020039819A1 (en) 2000-06-16 2002-04-04 Guiseppe Curello Method for manufacturing a field effect transistor
US6387763B1 (en) 1998-11-19 2002-05-14 Stmicroelectronics S.R.L. Field-effect transistor and corresponding manufacturing method
US6410393B1 (en) 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Semiconductor device with asymmetric channel dopant profile
US6465332B1 (en) 1997-04-11 2002-10-15 Stmicroelectronics S.A. Method of making MOS transistor with high doping gradient under the gate
US6507058B1 (en) 2000-10-17 2003-01-14 Semiconductor Components Industries Llc Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same
US6559019B1 (en) 1998-08-26 2003-05-06 Texas Instruments Incorporated Breakdown drain extended NMOS
US6593623B1 (en) * 1998-03-30 2003-07-15 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6667513B1 (en) 1999-06-11 2003-12-23 FRANCE TéLéCOM Semiconductor device with compensated threshold voltage and method for making same
US6700160B1 (en) 2000-10-17 2004-03-02 Texas Instruments Incorporated Double-diffused MOS (DMOS) power transistor with a channel compensating implant
US20040061187A1 (en) 2002-09-30 2004-04-01 Weber Cory E. Indium-boron dual halo MOSFET
US20040132260A1 (en) 2002-11-14 2004-07-08 Stmicroelectronics Sa Process for fabricating a short-gate-length MOS transistor and integrated circuit comprising such a transistor
US20050151174A1 (en) 2003-12-31 2005-07-14 Kim Tae W. Semiconductor device and fabricating method thereof
US6960499B2 (en) 1998-02-24 2005-11-01 Texas Instruments Incorporated Dual-counterdoped channel field effect transistor and method
US7112501B2 (en) 2003-10-20 2006-09-26 Oki Electric Industry Co., Ltd. Method of fabrication a silicon-on-insulator device with a channel stop

Patent Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4154626A (en) 1975-09-22 1979-05-15 International Business Machines Corporation Process of making field effect transistor having improved threshold stability by ion-implantation
US4276095A (en) 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4966859A (en) 1982-03-09 1990-10-30 Siemens Aktiengesellschaft Voltage-stable sub-μm MOS transistor for VLSI circuits
US4636822A (en) 1984-08-27 1987-01-13 International Business Machines Corporation GaAs short channel lightly doped drain MESFET structure and fabrication
US4683485A (en) 1985-12-27 1987-07-28 Harris Corporation Technique for increasing gate-drain breakdown voltage of ion-implanted JFET
US4851360A (en) 1986-09-29 1989-07-25 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US4801555A (en) 1987-01-14 1989-01-31 Motorola, Inc. Double-implant process for forming graded source/drain regions
US4968639A (en) 1987-12-21 1990-11-06 Sgs-Thomson Microelectronics S.R.L. Process for manufacturing CMOS integrated devices with reduced gate lengths
US5270235A (en) 1988-01-06 1993-12-14 Seiko Epson Corporation Semiconductor device fabrication
US5021851A (en) 1988-05-03 1991-06-04 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US4987088A (en) 1988-07-29 1991-01-22 Sgs-Thomson Microelectronics S.R.L. Fabrication of CMOS devices with reduced gate length
US5045898A (en) 1988-08-30 1991-09-03 At&T Bell Laboratories CMOS integrated circuit having improved isolation
US5143857A (en) 1988-11-07 1992-09-01 Triquint Semiconductor, Inc. Method of fabricating an electronic device with reduced susceptiblity to backgating effects
US5006477A (en) 1988-11-25 1991-04-09 Hughes Aircraft Company Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
US5132753A (en) 1990-03-23 1992-07-21 Siliconix Incorporated Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
US5949105A (en) * 1991-06-26 1999-09-07 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5716861A (en) 1991-06-26 1998-02-10 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5422510A (en) 1992-10-30 1995-06-06 Analog Devices, Incorporated MOS transistor with non-uniform channel dopant profile
US5449937A (en) 1993-03-19 1995-09-12 Sharp Kabushiki Kaisha Field effect transistor with short channel and manufacturing method therefor
JPH06318698A (en) 1993-05-06 1994-11-15 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5371394A (en) 1993-11-15 1994-12-06 Motorola, Inc. Double implanted laterally diffused MOS device and method thereof
US5409848A (en) 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US5548148A (en) 1994-04-15 1996-08-20 International Business Machines Corporation MOS channel device with counterdoping of ion implant for reduced substrate sensitivity
US5858827A (en) 1994-09-29 1999-01-12 Sony Corporation Method of manufacturing MOS transistor device with improved threshold value control and reduced reverse short channel effect
US5767557A (en) 1994-12-01 1998-06-16 Lucent Technologies Inc. PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom
US6091111A (en) 1995-01-17 2000-07-18 National Semiconductor Corporation High voltage mos device having an extended drain region with different dopant species
US5759901A (en) 1995-04-06 1998-06-02 Vlsi Technology, Inc. Fabrication method for sub-half micron CMOS transistor
US5675166A (en) 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US6017798A (en) 1995-07-07 2000-01-25 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
EP0763855A2 (en) 1995-09-18 1997-03-19 Texas Instruments Incorporated Asymmetrical FET and method of fabrication
US5731611A (en) 1996-01-30 1998-03-24 Megamos Corporation MOSFET transistor cell manufactured with selectively implanted punch through prevent and threshold reductoin zones
US5770880A (en) 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
US5874329A (en) 1996-12-05 1999-02-23 Lsi Logic Corporation Method for artificially-inducing reverse short-channel effects in deep sub-micron CMOS devices
US6020244A (en) 1996-12-30 2000-02-01 Intel Corporation Channel dopant implantation with automatic compensation for variations in critical dimension
US5827763A (en) 1997-01-30 1998-10-27 Advanced Micro Devices, Inc. Method of forming a multiple transistor channel doping using a dual resist fabrication sequence
US6465332B1 (en) 1997-04-11 2002-10-15 Stmicroelectronics S.A. Method of making MOS transistor with high doping gradient under the gate
US6172406B1 (en) 1997-08-26 2001-01-09 Texas Instruments Incorporated Breakdown drain extended NMOS
US6960499B2 (en) 1998-02-24 2005-11-01 Texas Instruments Incorporated Dual-counterdoped channel field effect transistor and method
US6593623B1 (en) * 1998-03-30 2003-07-15 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6150200A (en) 1998-04-03 2000-11-21 Motorola, Inc. Semiconductor device and method of making
US6559019B1 (en) 1998-08-26 2003-05-06 Texas Instruments Incorporated Breakdown drain extended NMOS
US6387763B1 (en) 1998-11-19 2002-05-14 Stmicroelectronics S.R.L. Field-effect transistor and corresponding manufacturing method
US6737715B2 (en) 1998-11-19 2004-05-18 Stmicroelectronics S.R.L. Field-effect transistor and corresponding manufacturing method
US6667513B1 (en) 1999-06-11 2003-12-23 FRANCE TéLéCOM Semiconductor device with compensated threshold voltage and method for making same
US6410393B1 (en) 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Semiconductor device with asymmetric channel dopant profile
US6284579B1 (en) 1999-10-14 2001-09-04 Taiwan Semiconductor Manufacturing Company Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications
US6486510B2 (en) 2000-03-30 2002-11-26 International Business Machines Corporation Reduction of reverse short channel effects by implantation of neutral dopants
US6352912B1 (en) 2000-03-30 2002-03-05 International Business Machines Corporation Reduction of reverse short channel effects by deep implantation of neutral dopants
US20020039819A1 (en) 2000-06-16 2002-04-04 Guiseppe Curello Method for manufacturing a field effect transistor
US6507058B1 (en) 2000-10-17 2003-01-14 Semiconductor Components Industries Llc Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same
US6700160B1 (en) 2000-10-17 2004-03-02 Texas Instruments Incorporated Double-diffused MOS (DMOS) power transistor with a channel compensating implant
US20040061187A1 (en) 2002-09-30 2004-04-01 Weber Cory E. Indium-boron dual halo MOSFET
US20040132260A1 (en) 2002-11-14 2004-07-08 Stmicroelectronics Sa Process for fabricating a short-gate-length MOS transistor and integrated circuit comprising such a transistor
US7112501B2 (en) 2003-10-20 2006-09-26 Oki Electric Industry Co., Ltd. Method of fabrication a silicon-on-insulator device with a channel stop
US20050151174A1 (en) 2003-12-31 2005-07-14 Kim Tae W. Semiconductor device and fabricating method thereof

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Hajime Kurata et al: "Self-Aligned Control of Threshold Voltages in Sub-0.2-mum MOSFET's" IEEE Transactions on Electron Devices, vol. 45, No. 10, US, New-York, NY: Oct. 1998, pp. 2161-2166, XP000786856 ISBN: 0018-9383.
Hajime Kurata et al: "Self-Aligned Control of Threshold Voltages in Sub-0.2-μm MOSFET's" IEEE Transactions on Electron Devices, vol. 45, No. 10, US, New-York, NY: Oct. 1998, pp. 2161-2166, XP000786856 ISBN: 0018-9383.
Yoshinori Okumura et al.: "Source-to Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Controllability" IEEE Transactions on Electron Devices, vol. 39, No. 11, US, New-York, NY: IEEE, Nov. 1992, pp. 2541-2552, XP000321695 ISBN: 0018-9383.
Yoshinori Okumura et al.: "Source—to Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Controllability" IEEE Transactions on Electron Devices, vol. 39, No. 11, US, New-York, NY: IEEE, Nov. 1992, pp. 2541-2552, XP000321695 ISBN: 0018-9383.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9478615B2 (en) 2011-11-04 2016-10-25 Globalfoundries Inc. Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9548401B2 (en) * 2014-11-20 2017-01-17 Samsung Electronics Co., Ltd. Semiconductor device

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