USRE41719E1 - Power MOSFET with integrated drivers in a common package - Google Patents
Power MOSFET with integrated drivers in a common package Download PDFInfo
- Publication number
- USRE41719E1 USRE41719E1 US11/183,302 US18330205A USRE41719E US RE41719 E1 USRE41719 E1 US RE41719E1 US 18330205 A US18330205 A US 18330205A US RE41719 E USRE41719 E US RE41719E
- Authority
- US
- United States
- Prior art keywords
- channel driver
- fets
- power mosfet
- channel
- driver fets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Definitions
- This invention relates to semiconductor devices and more specifically relates to a power MOSFET device with driver FETs integrated into or copacked with the same package to provide drive current to the gate circuit of the power MOSFET.
- Power MOSFETs frequently require a high gate current pulse for their operation.
- circuits containing control or synchronous power MOSFETs frequently require a high gate pulse current for their operation.
- high frequency dc to dc converters such as synchronous buck converters are operated in the region of 3 MHz and above, at breakdown voltages of about 30 volts and below.
- the gate charge Q g required to turn on the MOSFET is in the region of 14nC. If the MOSFET turn on time t ON is limited to 10 ns, the switching current can therefore be of the order 1.4A. This poses a problem for control ICs where capability to deliver this current level is not economically viable, given manufacturing complexity versus chip area required.
- a driver stage is placed inside the MOSFET package, and the driver current requirement can therefore be reduced to that of two small driver FETs.
- the total active area of these devices is approximately 1 ⁇ 4 that of the main FET/switch.
- the input drive current will therefore, be reduced by similar proportions thereby enabling the driver devices to be driven directly by the control IC, removing the need for discrete driver ICs.
- the internal driver stage uses two separate MOSFET chips in a totem pole configuration. This minimizes the wafer level manufacturing complexity for providing the desired function.
- the small driver chips can also be integrated with one another, or into the main chip.
- the three devices, the main MOSFET and the two smaller driver MOSFETs, when discrete chips, may be copacked in standard small footprint plastic encapsulated packages, such as the well known TSSOP, SOIC, or MLP packages.
- FIG. 1 is a circuit diagram of a non-inverting configuration for an integrated driver and power MOSFET.
- FIG. 2 is a top view of a first embodiment of a dual pad lead frame and the three die forming the circuit of FIG. 1 .
- FIG. 2A is a cross-section of FIG. 2 , taken across section line 2 a— 2 a in FIG. 2 .
- FIG. 3 is a top view of a second package embodiment, using an internal isolating substrate on a common lead frame pad.
- FIG. 3A is a cross-section of FIG. 3 taken across section line 3 a— 3 a in FIG. 3 .
- FIG. 4 is a top view of a third embodiment for the three die and a lead frame.
- FIG. 5 is a top view of a fourth embodiment for the package.
- FIG. 6 is a top view of a fifth embodiment in which the two driver FETS are integrated into a common integrated circuit.
- FIG. 7 is a circuit diagram of an inverting driver circuit configuration for the device of the invention.
- FIG. 8 is a top view of a lead frame and die for implementing the circuit of FIG. 7 with the driver FET insulated from the lead pad by a passivation layer as in FIG. 3 .
- FIG. 9 is a top view of a further embodiment of lead frame and die to implement the circuit of FIG. 7 with the two driver FETS integrated into a single die, as in FIG. 6 .
- FIG. 1 shows a circuit in which two small MOSFETs, P channel MOSFET 2 and N channel MOSFET 3 act as drivers for a main N channel MOSFET 1 . All MOSFETs are vertical conduction devices, although other structures could be used. Further, the MOSFETs 1 , 2 and 3 could be replaced by other types of transistors, as desired.
- a single input line 23 from a suitable driver integrated circuit is connected to gates G 2 and G 3 of MOSFETs 2 and 3 respectively.
- the sources S 2 and S 3 of FETS 2 and 3 respectively are connected to a common node and to G 1 of MOSFET 1 .
- Input power terminal I/P and output power terminal O/P are connected as shown with respect to ground GND.
- An optional resistor 24 may be connected as shown.
- the N channel power switch or MOSFET 1 may be a die having an area of 70 ⁇ 102 mils with an R DSON less than about 14 mohm.
- the P channel gate driver FET 2 may also have a dimension of about 31 ⁇ 29 mils and an R DSON of less about 140 mohm.
- the N-channel driver MOSFET may have a dimension of 29 ⁇ 31 mils or less and an R DSON of 140 mohm Resistor 24 may be about 50 ohm and acts to ensure that the gate of MOSFET 1 is pulled down to ground when the driver I/P reaches ground. Without this, an offset voltage equivilent roughly to that of the P-channel driver FET threshold voltage may appear at G 1 . This could trigger a false switching of MOSFET 1 .
- the threshold voltage of FETs 1 and 2 may be selected so that V gsth is greater than that of V gsch 2 .
- Other die sizes and ratings can be used as desired for a particular application.
- FIGS. 2 and 2A show a first manner in which the die of FIG. 1 can be mounted on a lead frame and interconnected and packaged in an insulation housing.
- the same numerals are used throughout to identify common components.
- the lead frame in FIGS. 2 and 2A a split frame structure, forming an SOIC; or MLP; or TSSOP package. More specifically, the two N channel switches (sometimes called digital switches or FETS or MOSFETs) 1 and 3 are mounted on the spilt pads 25 and 26 respectively of a conventional downset conductive lead frame, using silver loaded epoxy or an equivalent low resistance adhesive (e.g., solder/film/epoxy or the like).
- Conductive adhesive is then dispensed upon the N channel switch 1 prior to mounting the P channel MOSFET 2 on the source of MOSFET 1 , in a die-on-die configuration.
- the top metalization of MOSFET 1 may be passivated with appropriate material to protect the gate bus metal against shorting to the source metal by the conductive adhesive applied to bond MOSFET die 2 . Note that in order to use this package arrangement, the die may be suitably thinned prior to assembly.
- wirebonds are formed between bond pads on die 1 , 2 and 3 and the pins GND/S 1 and IN ( 23 ) in order to form the connections of the circuit of FIG. 1 .
- the bond wires may be gold although, in larger die packages, aluminum could also be used. Copperstrap or ribbon bonding technologies could also be used.
- the gate pads of digital switches 2 and 3 may be enlarged to allow use of two wire bonds.
- the subassembly is encapsulated in an insulating housing (e.g. mold compound).
- an insulating housing e.g. mold compound.
- SOIC packaging the coplanar terminals D 1 , S 1 , V cc and IN extend out of the encapsulant as shown in FIG. 2 .
- FIGS. 3 and 3a show the arrangement for the circuit of FIG. 1 on a single lead frame pad 30 .
- An internal isolating substrate or film 31 electrically isolates the bottom drains D 2 and D 3 of FETS 2 and 3 from the lead frame.
- Conductive traces 32 and 33 are die bond pads for FETs 2 and 3 . Following the die bond process stage pads 32 and 33 are wirebonded to enable the circuit of FIG. 1 .
- the substrate 31 may also carry surface mounted passive components if desired.
- FIG. 4 shows a third arrangement of the parts, using a single downset lead frame 40 , with the N channel switch 3 mounted on the V cc terminal lead.
- the main MOSFET 1 may be a die of dimension 80 ⁇ 157 mils.
- the driver die 2 and 3 may both be 20 ⁇ 20 mils.
- the P channel die or switch 2 is mounted atop the source of the main MOSFET 1 as by a conductive adhesive.
- FETS 2 and 3 in FIG. 4 are conventional vertical conduction FETS, but, if desired, could be bipolar transistors rated at 8 volts or greater with a 1.8 volt drive.
- FIG. 5 is a further package arrangement like that of FIG. 4 , in which FETS 2 and 3 are both on respective terminals GND/S and V cc of the lead frame. Note that the G 1 pad of MOSFET 1 is enlarged in FIG. 5 .
- FIG. 6 is a still further embodiment for the circuit of FIG. 1 in which both FETS 2 and 3 are integrated into a common chip 50 .
- the chip 50 has a common source pad for both S 2 and S 3 of FIG. 1 , and a common gate for both G 2 and G 3 of FIG. 1 . It also has spaced drain pads D 2 and D 3 on the die upper surface.
- the benefit of the use of an IC 50 containing both driver switches 2 and 3 is that the die-on-die bonding of the single IC 50 enables the use of a much larger area main switch 1 . Further, the structure has reduced capacitance and avoids the need for a split lead frame.
- FIGS. 1 to 6 show a circuit and various package layouts for a non-inverting MOSFET plus an integrated driver device.
- a similar device whose circuit topology is shown in FIG. 7 (with a common driver for FETS 2 and 3 ), can be used to provide a solution which reduces the high current gate driver requirements of power MOSFET's in high frequency dc to dc converters.
- the configuration of FIG. 7 inverts the I/P drive signal. Additional invertors may be required on the output of the driver IC prior to the MOSFET 1 with integrated driver stage.
- the circuit of FIG. 7 inverts the topology of the circuit of FIG. 1 , with P channel FET 2 on the high side of the circuit and the N channel FET 3 on the low side.
- the target application for the circuit of FIG. 7 is a 3 MHz converter and eliminates the need for a high current drive from the control IC (which drives terminal 23 ).
- the gate G 1 is connected to D 2 , D 3 and is redistributed from the main pad to the top of die 2 and 3 for bonding.
- N channel FET 1 may have a size of about 102 ⁇ 157 mils and about 3.5 mohm.
- P channel FET 2 may have a size of 31.5 ⁇ 15.75 mils and an on resistance of 250 mohm.
- N channel FET 3 may have a size of 23.6 ⁇ 15.75 mils and an on resistance of 250 mohms.
- FIGS. 8 and 9 Device package designs for the circuit of FIG. 7 are shown in FIGS. 8 and 9 . Note in these cases the configuration of MOSFETs is a common drain, as opposed to the common source in the non-inverting designs of FIGS. 1 to 6 .
- the three devices 1 , 2 and 3 may also be incorporated into MLP, SOIC or TSSOP style plastic encapsulated packages.
- the integrated substrate and die wirebond pad package solutions previously described are also applicable to the inverting topology.
- the single lead frame pad 60 receives the main MOSFET 1 and a passivation layer 61 atop S 1 of MOSFET 1 receives a conductive layer 62 which is an N/P channel bond pad.
- the drains of driver FETS 2 and 3 are conductively connected to layer 62 using a conductive adhesive film or paste.
- the gate of main FET 1 is redistributed atop conductive layer 62 in a suitable manner.
- FIG. 9 shows a modification of FIG. 8 in which both MOSFETs 2 and 3 are integrated, like FIG. 6 , into a common chip 70 .
- This structure has the same benefits as those of FIG. 6 .
- the digital switch IC 70 may be fixed to the surface of source S 1 using an insulation polyimide film. Front side drain connections are required.
Abstract
A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.
Description
This application claims the benefit of U.S. Provisional Application No. 60/288,193, filed May 2, 2001.
This invention relates to semiconductor devices and more specifically relates to a power MOSFET device with driver FETs integrated into or copacked with the same package to provide drive current to the gate circuit of the power MOSFET.
Power MOSFETs frequently require a high gate current pulse for their operation. For example, circuits containing control or synchronous power MOSFETs frequently require a high gate pulse current for their operation. As a specific example, high frequency dc to dc converters such as synchronous buck converters are operated in the region of 3 MHz and above, at breakdown voltages of about 30 volts and below. The gate driver current ig for the control and synchronous MOSFETs of those circuits is determined, approximately by:
ig=Qg/tON
ig=Qg/tON
For a typical SO-8 packaged device such as the IRF7811W made by the International Rectifier Corporation, the gate charge Qg required to turn on the MOSFET is in the region of 14nC. If the MOSFET turn on time tON is limited to 10 ns, the switching current can therefore be of the order 1.4A. This poses a problem for control ICs where capability to deliver this current level is not economically viable, given manufacturing complexity versus chip area required.
Solving this problem has typically been addressed by the addition of separate driver ICs placed in circuit between the control IC and the MOSFETs. As switching frequencies increase, the layout related circuit efficiency of this approach reduces, and the parasitic inductances caused by the distance between the separate components cause higher losses during switching.
A driver stage is placed inside the MOSFET package, and the driver current requirement can therefore be reduced to that of two small driver FETs. The total active area of these devices is approximately ¼ that of the main FET/switch. The input drive current will therefore, be reduced by similar proportions thereby enabling the driver devices to be driven directly by the control IC, removing the need for discrete driver ICs. In one embodiment of the invention, the internal driver stage uses two separate MOSFET chips in a totem pole configuration. This minimizes the wafer level manufacturing complexity for providing the desired function. The small driver chips can also be integrated with one another, or into the main chip.
The three devices, the main MOSFET and the two smaller driver MOSFETs, when discrete chips, may be copacked in standard small footprint plastic encapsulated packages, such as the well known TSSOP, SOIC, or MLP packages.
A single input line 23 from a suitable driver integrated circuit (Driver I/P) is connected to gates G2 and G3 of MOSFETs 2 and 3 respectively. The sources S2 and S3 of FETS 2 and 3 respectively are connected to a common node and to G1 of MOSFET 1. Input power terminal I/P and output power terminal O/P are connected as shown with respect to ground GND. An optional resistor 24 may be connected as shown.
In a typical embodiment, the N channel power switch or MOSFET 1 may be a die having an area of 70×102 mils with an RDSON less than about 14 mohm. The P channel gate driver FET 2 may also have a dimension of about 31×29 mils and an RDSON of less about 140 mohm. The N-channel driver MOSFET may have a dimension of 29×31 mils or less and an RDSON of 140 mohm Resistor 24 may be about 50 ohm and acts to ensure that the gate of MOSFET 1 is pulled down to ground when the driver I/P reaches ground. Without this, an offset voltage equivilent roughly to that of the P-channel driver FET threshold voltage may appear at G1. This could trigger a false switching of MOSFET 1. Alternatively, the threshold voltage of FETs 1 and 2 may be selected so that Vgsth is greater than that of V gsch 2. Other die sizes and ratings can be used as desired for a particular application.
Thereafter, wirebonds are formed between bond pads on die 1, 2 and 3 and the pins GND/S1 and IN (23) in order to form the connections of the circuit of FIG. 1. The bond wires may be gold although, in larger die packages, aluminum could also be used. Copperstrap or ribbon bonding technologies could also be used. The gate pads of digital switches 2 and 3 may be enlarged to allow use of two wire bonds.
Following the wirebond process the subassembly is encapsulated in an insulating housing (e.g. mold compound). Subsequent processes follow the conventional process route for SOIC, TSSOP or MLP packages, depending on which packaging technology is adopted. In the case of SOIC packaging, the coplanar terminals D1, S1, Vcc and IN extend out of the encapsulant as shown in FIG. 2.
The previous FIGS. 1 to 6 show a circuit and various package layouts for a non-inverting MOSFET plus an integrated driver device. A similar device, whose circuit topology is shown in FIG. 7 (with a common driver for FETS 2 and 3), can be used to provide a solution which reduces the high current gate driver requirements of power MOSFET's in high frequency dc to dc converters. The configuration of FIG. 7 , however, inverts the I/P drive signal. Additional invertors may be required on the output of the driver IC prior to the MOSFET 1 with integrated driver stage.
Thus, the circuit of FIG. 7 inverts the topology of the circuit of FIG. 1 , with P channel FET 2 on the high side of the circuit and the N channel FET 3 on the low side. The target application for the circuit of FIG. 7 is a 3 MHz converter and eliminates the need for a high current drive from the control IC (which drives terminal 23). The gate G1 is connected to D2, D3 and is redistributed from the main pad to the top of die 2 and 3 for bonding. In a typical application, N channel FET 1 may have a size of about 102×157 mils and about 3.5 mohm. P channel FET 2 may have a size of 31.5×15.75 mils and an on resistance of 250 mohm. N channel FET 3 may have a size of 23.6×15.75 mils and an on resistance of 250 mohms.
Device package designs for the circuit of FIG. 7 are shown in FIGS. 8 and 9 . Note in these cases the configuration of MOSFETs is a common drain, as opposed to the common source in the non-inverting designs of FIGS. 1 to 6. The three devices 1, 2 and 3 may also be incorporated into MLP, SOIC or TSSOP style plastic encapsulated packages. The integrated substrate and die wirebond pad package solutions previously described are also applicable to the inverting topology.
Referring to FIG. 8 , the single lead frame pad 60 receives the main MOSFET 1 and a passivation layer 61 atop S1 of MOSFET 1 receives a conductive layer 62 which is an N/P channel bond pad. The drains of driver FETS 2 and 3 are conductively connected to layer 62 using a conductive adhesive film or paste. The gate of main FET 1 is redistributed atop conductive layer 62 in a suitable manner.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.
Claims (18)
1. A power MOSFET with an integrated P channel driver FET and an N channel driver FET in a common package; said common package comprising a lead frame that includes a plurality of terminals and a conductive support having extending terminals; said power MOSFET having a drain electrode fixed to said conductive support; said P channel and N channel driver FETs having respective gate, source and drain electrodes, one of said source or drain electrodes of each of said driver FETs connected at a node to define a series totem pole arrangement with the others of said source or drain electrodes of each of said driver FETS at the outer ends of said totem pole; the outer ends of said totem pole circuit connected to a Vcc terminal and a ground terminal respectively; and a driver input control terminal connected to said gate electrodes of said P and N channel driver FETs; said power MOSFET having a source electrode connected to said ground terminal; said node between said N and P channel drivers driver FETs connected to the gate electrode of said power MOSFET; and a single, common insulation housing enclosing said power MOSFET, said conductive support and said N and P channel driver FETs; said extending terminals including a drain terminal which is connected to said power MOSFET drain electrode, and said plurality of terminals including said ground terminal, said Vcc terminal and said driver input control terminal.
2. The device of claim 1 , wherein said conductive support comprises a lead frame.
3. The device of claim 1 , wherein the total area of said N and P channel driver FETs is about ¼ that of said power MOSFET.
4. The device of claim 2 , wherein the total area of said N and P channel driver FETs is about ¼ that of said power MOSFET.
5. The device of claim 1 , wherein one of said P and N channel driver FETs is mounted on the source electrode of said power FET.
6. The device of claim 2 , wherein one of said P and N channel driver FETs is mounted on the source electrode of said power FET.
7. The device of claim 2 1, wherein one of said P and N channel driver FETs is mounted on one of said plurality of terminals.
8. The device of claim 1 , wherein said N and P channel driver FETs are integrated into a common chip.
9. The device of claim 2 , wherein said N and P channel driver FETs are integrated into a common chip.
10. The device of claim 2 1, wherein said lead frame has first and second insulated pads; said power MOSFET supported on said first pad; at least one of said P and N channel driver FETs mounted on said second pad.
11. The device of claim 10 , wherein the total area of said N and P channel driver FETs is about ¼ that of said power MOSFET.
12. The device of claim 1 , wherein said source electrodes of said P and N channel driver FETs are connected at said node.
13. The device of claim 2 , wherein said source of said P and N channel driver FETs are connected at said node.
14. The device of claim 3 , wherein said source terminals of said P and N channel driver FETs are connected at said node.
15. The device of claim 1 , wherein said drain terminals of said P and N channel driver FETs are connected at said node.
16. The device of claim 2 , wherein said drain terminals of said P and N channel driver FETs are connected at said node.
17. The device of claim 3 , wherein said drain terminals of said P and N channel driver FETs are connected at said node.
18. A power MOSFET with an integrated P channel driver FET and an N channel driver FET in a common package; said common package comprising
a lead frame that includes a plurality of terminals and a conductive support having extending terminals; said power MOSFET having a drain electrode fixed to said conductive support; said P channel and N channel driver FETs having respective gate, source and drain electrodes, one of said source or drain electrodes of each of said driver FETs connected at a node to define a series totem pole arrangement with the others of said source or drain electrodes of each of said driver FETS at the outer ends of said totem pole; the outer ends of said totem pole circuit connected to a V cc terminal and a ground terminal respectively; and
a driver input control terminal coupled to said gate electrodes of said P and N channel driver FETs; said power MOSFET having a source electrode connected to said ground terminal; said node between said N and P channel driver FETs connected to the gate electrode of said power MOSFET; and a single, common insulation housing enclosing said power MOSFET, said conductive support and said N and P channel driver FETs; said extending terminals including a drain terminal which is connected to said power MOSFET drain electrode, and said plurality of terminals including said ground terminal and said V cc terminal.
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US11/183,302 USRE41719E1 (en) | 2001-05-02 | 2005-07-15 | Power MOSFET with integrated drivers in a common package |
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US28819301P | 2001-05-02 | 2001-05-02 | |
US10/138,130 US6593622B2 (en) | 2001-05-02 | 2002-05-02 | Power mosfet with integrated drivers in a common package |
US11/183,302 USRE41719E1 (en) | 2001-05-02 | 2005-07-15 | Power MOSFET with integrated drivers in a common package |
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Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7116728B2 (en) * | 2001-05-25 | 2006-10-03 | Matsushita Electric Industrial Co., Ltd. | Quadrature alignment in communications receivers using dual delay lines |
US6992520B1 (en) * | 2002-01-22 | 2006-01-31 | Edward Herbert | Gate drive method and apparatus for reducing losses in the switching of MOSFETs |
US7183616B2 (en) * | 2002-03-31 | 2007-02-27 | Alpha & Omega Semiconductor, Ltd. | High speed switching MOSFETS using multi-parallel die packages with/without special leadframes |
US6841852B2 (en) * | 2002-07-02 | 2005-01-11 | Leeshawn Luo | Integrated circuit package for semiconductor devices with improved electric resistance and inductance |
US7763974B2 (en) * | 2003-02-14 | 2010-07-27 | Hitachi, Ltd. | Integrated circuit for driving semiconductor device and power converter |
US20040217488A1 (en) * | 2003-05-02 | 2004-11-04 | Luechinger Christoph B. | Ribbon bonding |
CN1860669A (en) | 2003-09-30 | 2006-11-08 | 皇家飞利浦电子股份有限公司 | Integrated interface circuitry for integrated VRM power field effect transistors |
WO2005122249A2 (en) * | 2004-06-03 | 2005-12-22 | International Rectifier Corporation | Semiconductor device module with flip chip devices on a common lead frame |
US20050280133A1 (en) * | 2004-06-21 | 2005-12-22 | Alpha & Omega Semiconductor | Multiple device package |
JP4477952B2 (en) * | 2004-07-09 | 2010-06-09 | 株式会社ルネサステクノロジ | Semiconductor device, DC / DC converter and power supply system |
US7759775B2 (en) * | 2004-07-20 | 2010-07-20 | Alpha And Omega Semiconductor Incorporated | High current semiconductor power device SOIC package |
US7898092B2 (en) * | 2007-11-21 | 2011-03-01 | Alpha & Omega Semiconductor, | Stacked-die package for battery power management |
US7884454B2 (en) | 2005-01-05 | 2011-02-08 | Alpha & Omega Semiconductor, Ltd | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
US20060145312A1 (en) * | 2005-01-05 | 2006-07-06 | Kai Liu | Dual flat non-leaded semiconductor package |
US7612439B2 (en) * | 2005-12-22 | 2009-11-03 | Alpha And Omega Semiconductor Limited | Semiconductor package having improved thermal performance |
DE102005027356B4 (en) * | 2005-06-13 | 2007-11-22 | Infineon Technologies Ag | Semiconductor power device stack in flat conductor technology with surface-mountable external contacts and a method for producing the same |
US7504733B2 (en) * | 2005-08-17 | 2009-03-17 | Ciclon Semiconductor Device Corp. | Semiconductor die package |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
US7443018B2 (en) * | 2005-11-09 | 2008-10-28 | Stats Chippac Ltd. | Integrated circuit package system including ribbon bond interconnect |
US7446375B2 (en) * | 2006-03-14 | 2008-11-04 | Ciclon Semiconductor Device Corp. | Quasi-vertical LDMOS device having closed cell layout |
US7618896B2 (en) * | 2006-04-24 | 2009-11-17 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple dies and a common node structure |
US20080036078A1 (en) * | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
JP5390064B2 (en) * | 2006-08-30 | 2014-01-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US20080111219A1 (en) * | 2006-11-14 | 2008-05-15 | Gem Services, Inc. | Package designs for vertical conduction die |
DE102007013186B4 (en) * | 2007-03-15 | 2020-07-02 | Infineon Technologies Ag | Semiconductor module with semiconductor chips and method for producing the same |
US7872356B2 (en) * | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
US7773381B2 (en) * | 2007-09-26 | 2010-08-10 | Rohm Co., Ltd. | Semiconductor device |
EP2212997B1 (en) * | 2007-10-05 | 2013-03-06 | Telefonaktiebolaget LM Ericsson (publ) | Drive circuit for a power switch component |
US8138593B2 (en) * | 2007-10-22 | 2012-03-20 | Analog Devices, Inc. | Packaged microchip with spacer for mitigating electrical leakage between components |
US7952418B2 (en) * | 2008-06-27 | 2011-05-31 | Dell Products L.P. | Enhanced transistor gate drive |
US7847375B2 (en) * | 2008-08-05 | 2010-12-07 | Infineon Technologies Ag | Electronic device and method of manufacturing same |
US8049312B2 (en) * | 2009-01-12 | 2011-11-01 | Texas Instruments Incorporated | Semiconductor device package and method of assembly thereof |
US8164199B2 (en) * | 2009-07-31 | 2012-04-24 | Alpha and Omega Semiconductor Incorporation | Multi-die package |
US9257375B2 (en) | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
US20110049580A1 (en) * | 2009-08-28 | 2011-03-03 | Sik Lui | Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET |
US20110148376A1 (en) * | 2009-12-23 | 2011-06-23 | Texas Instruments Incorporated | Mosfet with gate pull-down |
CN201838586U (en) * | 2010-01-22 | 2011-05-18 | 成都芯源系统有限公司 | Synchronous rectification unit package, synchronous rectification circuit, integrated circuit and power adapter |
JP4985810B2 (en) * | 2010-03-23 | 2012-07-25 | サンケン電気株式会社 | Semiconductor device |
US8896131B2 (en) | 2011-02-03 | 2014-11-25 | Alpha And Omega Semiconductor Incorporated | Cascode scheme for improved device switching behavior |
US8742490B2 (en) * | 2011-05-02 | 2014-06-03 | Monolithic Power Systems, Inc. | Vertical power transistor die packages and associated methods of manufacturing |
US9166487B2 (en) * | 2013-12-06 | 2015-10-20 | Zentel Electronics Corp. | Package structure integrating a start-up component, a controller, and a power switch |
US9536800B2 (en) | 2013-12-07 | 2017-01-03 | Fairchild Semiconductor Corporation | Packaged semiconductor devices and methods of manufacturing |
CN106664085B (en) * | 2014-07-03 | 2019-10-22 | 三菱电机株式会社 | The gate driving circuit of insulated-gate type power semiconductor |
US9571093B2 (en) | 2014-09-16 | 2017-02-14 | Navitas Semiconductor, Inc. | Half bridge driver circuits |
US9537338B2 (en) | 2014-09-16 | 2017-01-03 | Navitas Semiconductor Inc. | Level shift and inverter circuits for GaN devices |
CN107112988B (en) | 2014-11-07 | 2018-05-04 | 贝能思科技有限公司 | Switch driver with prevention cross-conduction circuit |
US9831867B1 (en) | 2016-02-22 | 2017-11-28 | Navitas Semiconductor, Inc. | Half bridge driver circuits |
RU180845U1 (en) * | 2018-02-06 | 2018-06-28 | Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" | OUTPUT FRAME OF PLASTIC CASE OF POWERFUL SEMICONDUCTOR DEVICE |
RU180407U1 (en) * | 2018-02-06 | 2018-06-13 | Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" | OUTPUT FRAME OF THE INTEGRAL IC |
US11289437B1 (en) * | 2020-10-28 | 2022-03-29 | Renesas Electronics Corporation | Semiconductor device |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5084753A (en) * | 1989-01-23 | 1992-01-28 | Analog Devices, Inc. | Packaging for multiple chips on a single leadframe |
US5289061A (en) * | 1991-08-27 | 1994-02-22 | Nec Corporation | Output gate for a semiconductor IC |
US5313095A (en) * | 1992-04-17 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multiple-chip semiconductor device and a method of manufacturing the same |
US5792676A (en) * | 1995-10-03 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating power semiconductor device and lead frame |
US5814884A (en) * | 1996-10-24 | 1998-09-29 | International Rectifier Corporation | Commonly housed diverse semiconductor die |
US6066890A (en) * | 1995-11-13 | 2000-05-23 | Siliconix Incorporated | Separate circuit devices in an intra-package configuration and assembly techniques |
US20010012189A1 (en) * | 1998-03-25 | 2001-08-09 | Tien-Hao Tang | Gate-voltage controlled electrostatic discharge protection circuit |
US6388319B1 (en) * | 1999-05-25 | 2002-05-14 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
US6448643B2 (en) * | 2000-05-24 | 2002-09-10 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
-
2002
- 2002-05-02 US US10/138,130 patent/US6593622B2/en not_active Expired - Lifetime
-
2005
- 2005-07-15 US US11/183,302 patent/USRE41719E1/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5084753A (en) * | 1989-01-23 | 1992-01-28 | Analog Devices, Inc. | Packaging for multiple chips on a single leadframe |
US5289061A (en) * | 1991-08-27 | 1994-02-22 | Nec Corporation | Output gate for a semiconductor IC |
US5313095A (en) * | 1992-04-17 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Multiple-chip semiconductor device and a method of manufacturing the same |
US5792676A (en) * | 1995-10-03 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating power semiconductor device and lead frame |
US6066890A (en) * | 1995-11-13 | 2000-05-23 | Siliconix Incorporated | Separate circuit devices in an intra-package configuration and assembly techniques |
US5814884A (en) * | 1996-10-24 | 1998-09-29 | International Rectifier Corporation | Commonly housed diverse semiconductor die |
US6133632A (en) * | 1996-10-24 | 2000-10-17 | International Rectifier Corp. | Commonly housed diverse semiconductor die |
US5814884C1 (en) * | 1996-10-24 | 2002-01-29 | Int Rectifier Corp | Commonly housed diverse semiconductor die |
US20010012189A1 (en) * | 1998-03-25 | 2001-08-09 | Tien-Hao Tang | Gate-voltage controlled electrostatic discharge protection circuit |
US6388319B1 (en) * | 1999-05-25 | 2002-05-14 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
US6448643B2 (en) * | 2000-05-24 | 2002-09-10 | International Rectifier Corporation | Three commonly housed diverse semiconductor dice |
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US6593622B2 (en) | 2003-07-15 |
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