USRE41494E1 - Extended cardbus/PC card controller with split-bridge technology - Google Patents
Extended cardbus/PC card controller with split-bridge technology Download PDFInfo
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- USRE41494E1 USRE41494E1 US11/183,298 US18329805A USRE41494E US RE41494 E1 USRE41494 E1 US RE41494E1 US 18329805 A US18329805 A US 18329805A US RE41494 E USRE41494 E US RE41494E
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- bus
- interface
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- electronics
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
Definitions
- the present invention is generally related to data processing systems, and more particularly to computer systems having at least one host processor and connectable to a plurality of peripherals devices including notebook computers, storage devices, displays, keyboards, mouse's and so forth.
- PCI bus is pervasive in the industry, but as a parallel data bus is not easily bridged to other PCI based devices.
- Full bridges are known, such as used in traditional laptop computer/docking stations. However, separating the laptop computer from the docking station a significant distance has not been possible.
- processing power of computer systems has been resident within the traditional computer used by the user because the microprocessor had to be directly connected to and resident on the PCI motherboard. Thus, upgrading processing power usually meant significant costs and/or replacing the computer system.
- the PCI bus is primarily a wide multiplexed address and data bus that provides support for everything from a single data word for every address to very long bursts of data words for a single address, with the implication being that burst data is intended for sequential addresses.
- the highest performance of the PCI bus comes from the bursts of data, however most PCI devices require reasonable performance for even the smallest single data word operations.
- Many PCI devices utilize only the single data mode for their transfers.
- there has been at least pseudo isochronous behavior demanded from the bus placing limits on an individual device's utilization of the bus, thus virtually guaranteeing every device gets a dedicated segment of time on a very regular interval and within a relatively short time period.
- PCI bus The fundamental reason behind such operation of the PCI bus is to enable such things as real time audio and video data streams to be mixed with other operations on the bus without introducing major conflicts or interruption of data output.
- spoken words being broken into small unconnected pieces and you get the picture.
- PCI 2.1 these artifacts could and did occur because devices could get on the bus and hold it for indefinite periods of time.
- time slot intervals Before modification of the spec for version 2.1, there really was no way to guarantee performance of devices on the bus, or to guarantee time slot intervals when devices would get on the bus. Purists may argue that PCI is still theoretically not an isochronous bus, but as in most things in PC engineering, it is close enough.
- Typical high speed serial bus operation allows the possibility of all sizes of data transfers across the bus like PCI, but it certainly favors the very long bursts of data unlike PCI.
- the typical operation of a serial bus includes an extensive header of information for every data transaction on the bus much like Ethernet, which requires on the order of 68 bytes of header of information for every data transaction regardless of length. In other words, every data transaction on Ethernet would have to include 68 bytes of data along with the header information just to approach 50% utilization of the bus. As it turns out Ethernet also requires some guaranteed dead time between operations to “mostly” prevent collisions from other Ethernet devices on the widely disperse bus, and that dead time further reduces the average performance.
- FC FiberChannel
- Split-BridgeTM technology fundamentals are a natural for extending anything that exists within a computer. It basically uses a single-byte of overhead for 32 bits of data and address—actually less when you consider that byte enables, which are not really “overhead”, are included as well.
- PCI bridge First of all is the splitting of a PCI bridge into two separate and distinct pieces.
- a PCI bridge was never intended to be resident in two separate modules or chips and no mechanism existed to allow the sharing of setup information across two separate and distinct devices.
- a PCI bridge requires a number of programmable registers that supply information to both ports of a typical device. For the purpose of the following discussion, the two ports are defined into a north and south segment of the complete bridge.
- the north segment is typically the configuration port of choice and the south side merely takes the information from the registers on the north side and operates accordingly.
- the problem exists when the north and south portions are physically and spatially separated and none of the register information is available to the south side because all the registers are in the north chip.
- a typical system solution conceived by the applicant prior to the invention of Split-BridgeTM technology would have been to merely create a separate set of registers in the south chip for configuration of that port. However, merely creating a separate set of registers in the south port would still leave the set up of those registers to the initialization code of the operating system and hence would have required a change to the system software.
- Split-BridgeTM technology chose to make the physical splitting of the bridge into two separate and spaced devices “transparent” to the system software (in other words, no knowledge to the system software that two devices were in fact behaving as one bridge chip).
- all accesses to the configuration space were encoded, serialized, and “echoed” across the serial link to a second set of relevant registers in the south side.
- Such transparent echo between halves of a PCI bridge or any other bus bridge is an innovation that significantly enhances the operation of the technology.
- the 8 bit to 10 bit encoding of the data on the bus is not new, but follows existing published works.
- the direct sending of 32 bits of information along with the 4 bits of control or byte enables, along with an additional 4 bits of extension represents a 40 bit for every 36 bits of existing PCI data, address, and control or a flat 10% overhead regardless of the transfer size or duration, and this approach is new and revolutionary.
- Extending the 4 bit extension to 12 or more bits and include other functionality such as error correction or retransmit functionality is also within the scope of the Split-BridgeTM technology.
- the present invention achieves technical advantages as an improved extended cardbus/PC card controller incorporating the proprietary serial high speed Split-BridgeTM technology providing serial communications between a parallel system bus and a remote peripheral device.
- the improved controller includes the conventional system frontside controls, I/O controls, a cardbus translator having PC card slots adapted to receive a PCMCIA card or cards, and one end of the split bridge serial communication link comprising the proprietary serial Split-BridgeTM technology.
- the controller may further include super I/O circuitry for communicating remote I/O devices with the system bus as the super I/O devices become more readily available in the market.
- FIG. 1 illustrates prior art computer systems depicted as a traditional performance desk top computer shown at 10 , and a portable computing device 12 , such as a notebook or laptop computer, mechanically coupled to mechanical docking station 14 ;
- a portable computing device 12 such as a notebook or laptop computer, mechanically coupled to mechanical docking station 14 ;
- FIG. 2 is a block diagram of a prior art bridge 16 used to couple two system computing buses, such as used between the portable computing device 12 and the mechanical docking station 14 shown in FIG. 1 ;
- FIG. 3 illustrates the proprietary Split-BridgeTM technology serial communication technology of the applicant enabling high speed serial communications within the modular computer system of the present invention
- FIG. 4 is a diagram of a conventional cardbus/PC controller
- FIG. 5 is a block diagram of an improved extended cardbus/PC card controller having an integrated serial Split-BridgeTM interface according to the preferred embodiment of the present invention.
- FIG. 3 there is depicted the proprietary Split-BridgeTM technology serial communications technology of the present applicant, discussed in great detail in commonly assigned U.S. patent applications Ser. No. 09/130,057 filed Jun. 6, 1998, and Ser. No. 09/130,058 also filed Jun. 6, 1998 the teachings of which are incorporated herein by reference.
- the Split-BridgeTM technology revolutionizes the status quo for computer systems.
- the Split-BridgeTM technology does not require the need for custom hardware or custom software to achieve full performance serial communication between devices, including devices having parallel data buses including the PCI bus.
- the Split-BridgeTM technology appears just like a standard PCI bridge, and all software operating systems and device drivers already take such standard devices into consideration.
- OS Operating System
- the modular computing system has simple elegance, allowing the PCI bus which is so pervasive in the computer industry, that possible applications of the initial PCI form of Split-BridgeTM technology are all most limitless.
- Cardbus controller 20 is seen to have conventional system front side control circuitry 22 , input/output (I/O) control circuitry 24 a cardbus translator circuitry 26 adapted to couple to and communicably interface with one or more PC cards inserted into respective slots 28 , and being improved to include a serial Split-BridgeTM interface generally show at 30 .
- the serial Split-BridgeTM interface portion 30 is adapted to serially communicate data and control signals between the parallel system bus 32 via a duplex serial link 34 to a remote peripheral device (not shown) converting the parallel data to outgoing serial data and converting incoming serial data to parallel data.
- the proprietary Split-BridgeTM technology when employed in the extended cardbus/PC card controller 20 , significantly expands the interconnectivity of a standard communications network by allowing devices accessing the parallel systems bus 32 to communicate with a variety of external devices via PC cards, an extended cardbus, or advantageously via a serial link when employing the high speed serial Split-BridgeTM technology according to the present invention.
- All of the electronics comprising the controller 20 can be embodied in discrete circuitry, in an application specific integrated circuit (ASIC), or combination thereof, to provide the multi-function interface capability between the parallel system bus 32 and remote peripheral devices.
- ASIC application specific integrated circuit
- the controller 20 can communicate with either Cardbus or PCMCIA, or via the serial link Split-BridgeTM remote PCI devices. Since much of the PCI interface electronics are commonly used by the respective interfaces, the integrating of the circuitry 30 is very economical.
- the present invention 20 facilitates the evolution of information transfer to offer high speed serial link connectivity exceeding data rates of 1.0 GHZ for use with PCI, Cardbus, integrated, or other parallel I/O bus architectures.
- conventional digital signal processors such as those manufactured by Texas Instruments Incorporated of Dallas, Tex., (DSPs) being employed on extended Cardbus/PC card controllers are well adapted to interface with and incorporate the serial Split-BridgeTM technology interface. Integrating commercially available Cardbus/PC card controller electronics with the proprietary serial Split-BridgeTM technology significantly improves performance and available features of the device 30 with nominal additional cost associated therewith.
- the price versus performance improvement of the present invention shown in FIG. 4 is a quantum leap over existing price-performance points.
- the Split-BridgeTM serial interface electronics 30 can be designed into a custom Application Specific Integrated Circuit (ASIC) along with other electronics, moreover, multiple interfaces 30 can be employed on to a single controller 20 and multiplexed to interface with multiple internal or external devices and users. Accordingly, limitation to integration of a single Split-BridgeTM interface is not to be inferred, but rather parallel buses and possibly future general serial buses, can be interfaced to other devices using the proprietary Split-BridgeTM serial technology.
- ASIC Application Specific Integrated Circuit
- the improved Cardbus/PC card controller 20 facilitates improved connectivity between a system parallel bus and remote peripheral devices, allowing data connectivity via either the proprietary serial Split-BridgeTM technology, or via the standard PC card slots such as those based on the PCMCIA standards.
- Existing electronics, including DSPs, are well adapted to interface with ASICs or other discrete/custom componentry comprising the interface and employing the serials Split-BridgeTM technology.
Abstract
Description
Claims (36)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/183,298 USRE41494E1 (en) | 2000-04-19 | 2005-07-15 | Extended cardbus/PC card controller with split-bridge technology |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US19831700P | 2000-04-19 | 2000-04-19 | |
US09/559,677 US6594719B1 (en) | 2000-04-19 | 2000-04-27 | Extended cardbus/pc card controller with split-bridge ™technology |
US11/183,298 USRE41494E1 (en) | 2000-04-19 | 2005-07-15 | Extended cardbus/PC card controller with split-bridge technology |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/559,677 Reissue US6594719B1 (en) | 2000-04-19 | 2000-04-27 | Extended cardbus/pc card controller with split-bridge ™technology |
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USRE41494E1 true USRE41494E1 (en) | 2010-08-10 |
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Application Number | Title | Priority Date | Filing Date |
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US09/559,677 Ceased US6594719B1 (en) | 2000-04-19 | 2000-04-27 | Extended cardbus/pc card controller with split-bridge ™technology |
US11/183,298 Expired - Lifetime USRE41494E1 (en) | 2000-04-19 | 2005-07-15 | Extended cardbus/PC card controller with split-bridge technology |
Family Applications Before (1)
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US09/559,677 Ceased US6594719B1 (en) | 2000-04-19 | 2000-04-27 | Extended cardbus/pc card controller with split-bridge ™technology |
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US (2) | US6594719B1 (en) |
EP (3) | EP1275048B1 (en) |
AT (1) | ATE352066T1 (en) |
AU (2) | AU2001257103A1 (en) |
CA (2) | CA2445716C (en) |
DE (1) | DE60126074T2 (en) |
WO (2) | WO2001082089A2 (en) |
Cited By (3)
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US20090252054A1 (en) * | 2008-04-02 | 2009-10-08 | Ozdal Barkan | Reduced Power Transmission |
US8060675B2 (en) | 1998-08-06 | 2011-11-15 | Frank Ahern | Computing module with serial data connectivity |
US9712459B1 (en) * | 2010-01-27 | 2017-07-18 | Marvell International Ltd. | Low-to-high speed cut-through communication |
Families Citing this family (10)
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US6594719B1 (en) | 2000-04-19 | 2003-07-15 | Mobility Electronics Inc. | Extended cardbus/pc card controller with split-bridge ™technology |
US6748458B2 (en) * | 2001-08-31 | 2004-06-08 | Hewlett-Packard Development Company, L.P. | Modular input/output expansion system for an external computer |
US6813667B2 (en) | 2001-09-05 | 2004-11-02 | Hewlett-Packard Development Company, L.P. | Bus extender and formatter apparatus and methods |
US6990549B2 (en) * | 2001-11-09 | 2006-01-24 | Texas Instruments Incorporated | Low pin count (LPC) I/O bridge |
TWI226552B (en) * | 2003-11-20 | 2005-01-11 | Rdc Semiconductor Co Ltd | Bus integrating system |
CA2489999A1 (en) * | 2003-12-09 | 2005-06-09 | Lorne M. Trottier | A secure integrated media center |
US7908623B2 (en) * | 2004-05-12 | 2011-03-15 | Matrox Electronic Systems Ltd. | Set top box for PC/HDTV multimedia center |
EP1659499A1 (en) * | 2004-11-16 | 2006-05-24 | RDC Semiconductor Co., Ltd. | Bus integrating system |
US7769939B2 (en) * | 2006-06-26 | 2010-08-03 | Thomson Licensing | Apparatus and method for interfacing electronic devices |
US10225290B2 (en) * | 2016-07-15 | 2019-03-05 | Genband Us Llc | Systems and methods for extending DSP capability of existing computing devices |
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CA2445716A1 (en) | 2001-11-01 |
WO2001082090A3 (en) | 2002-02-21 |
EP1275049B1 (en) | 2016-02-17 |
CA2445711A1 (en) | 2001-11-01 |
CA2445711C (en) | 2010-04-13 |
WO2001082089A2 (en) | 2001-11-01 |
EP1275048A2 (en) | 2003-01-15 |
CA2445716C (en) | 2005-12-20 |
EP1275048B1 (en) | 2007-01-17 |
EP1801704A3 (en) | 2008-10-29 |
DE60126074D1 (en) | 2007-03-08 |
WO2001082090A2 (en) | 2001-11-01 |
ATE352066T1 (en) | 2007-02-15 |
DE60126074T2 (en) | 2007-08-23 |
EP1801704A2 (en) | 2007-06-27 |
AU2001257103A1 (en) | 2001-11-07 |
WO2001082089A3 (en) | 2002-01-10 |
AU2001251674A1 (en) | 2001-11-07 |
EP1275049A2 (en) | 2003-01-15 |
US6594719B1 (en) | 2003-07-15 |
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