USRE41363E1 - Thin film transistor substrate - Google Patents

Thin film transistor substrate Download PDF

Info

Publication number
USRE41363E1
USRE41363E1 US11/296,847 US29684705A USRE41363E US RE41363 E1 USRE41363 E1 US RE41363E1 US 29684705 A US29684705 A US 29684705A US RE41363 E USRE41363 E US RE41363E
Authority
US
United States
Prior art keywords
pattern
film pattern
electrode
insulating layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US11/296,847
Inventor
Jueng-gil Lee
Jung-Ho Lee
Hyo-Rak Nam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=36627376&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=USRE41363(E1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from KR1019950042618A external-priority patent/KR0183757B1/en
Priority claimed from KR1019960013912A external-priority patent/KR100219480B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to US11/296,847 priority Critical patent/USRE41363E1/en
Application granted granted Critical
Publication of USRE41363E1 publication Critical patent/USRE41363E1/en
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG ELECTRONICS CO., LTD.
Anticipated expiration legal-status Critical
Assigned to TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG DISPLAY CO., LTD.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for manufacturing a liquid crystal display. More particularly, present invention relates to an improved method for manufacturing a thin film transistor-liquid crystal display which reduces the number of photolithography processes that must be performed.
  • TFT-LCD thin film transistor LCD
  • advantages include low power consumption, low drive voltage, a thinness, and lightness of weight, among others.
  • the process of manufacturing a TFT is complicated, resulting in low productivity and high manufacturing costs.
  • a mask is used in every step for manufacturing a TFT, at least seven masks are required. Therefore, various methods for increasing productivity of the TFT and lowering the manufacturing costs have been studied. In particular, a method for reducing the number of the masks used during the manufacturing process has been widely researched.
  • FIGS. 1 to 5 are sectional views for explaining a conventional method for manufacturing an LCD, as disclosed in U.S. Pat. No. 5,054,887.
  • reference characters “A” and “B” denote a TFT area and a pad area, respectively.
  • FIG. 1 after forming a first metal film by depositing pure Al on a transparent substrate 2 , gate patterns 4 and 4 a are formed out of the first metal film by performing a first photolithography on the first metal film. The gate patterns are then used as a gate electrode 4 in the TFT area and as a gate pad 4 a in the pad area.
  • an anodized film 6 is formed by oxidizing the first metal film using the photoresist pattern as an anti-oxidation film.
  • the anodized film 6 is then formed on the entire surface of the gate electrode 4 formed in the TFT area, and on a portion of the gate pad 4 a in the pad area.
  • an insulating film 8 is formed by depositing a layer such as a nitride film over the anodized film 6 .
  • a semiconductor film is then formed by subsequently depositing an amorphous silicon film 10 and an amorphous silicon film 12 doped with impurities on the entire surface of the substrate 2 on which the insulating film 8 is formed.
  • a semiconductor film pattern 10 and 12 to be used as an active portion is then formed in the TFT area by performing a third photolithography on the semiconductor film.
  • a fourth photoresist pattern (not shown) is then formed that exposes a portion of the gate pad 4 a formed in the pad area by performing a fourth photolithography on the entire surface of the substrate 2 on which the semiconductor film pattern is formed. Then, a contact hole is then formed in the insulating film 8 , which contact hole exposes a portion of the gate pad 4 a. The contact hole is formed by etching the insulating film 8 using the fourth photoresist pattern as a mask. A source electrode 14 a and a drain electrode 14 b are then formed in the TFT area by depositing a chromium (“Cr”) film on the entire surface of the substrate having the contact hole and performing a fifth photolithography on the Cr film.
  • Cr chromium
  • a pad electrode 14 c connected to the gate pad 4 a through the contact hole is formed.
  • the impurity doped-amorphous silicon film 12 on the upper portion of the gate electrode 4 formed in the TFT area during the photolithography process is partially etched, thus exposing a portion of the amorphous silicon film 10 .
  • a protection film 16 is then formed by depositing an oxide film over the entire surface of the substrate 2 on which the source electrode 14 a, the drain electrode 14 b and the pad electrode 14 c are formed. Then, contact holes are formed that expose a portion of the drain electrode 14 b of the TFT area and a portion of the pad electrode 14 c of the pad area. The contact holes are formed by performing a sixth photolithography on the protection film 16 .
  • pixel electrodes 18 and 18 a are formed by depositing indium tin oxide (“ITO”), a transparent conductive material, over the entire surface of the substrate, including the contact hole, and performing a seventh photolithography process on the resultant ITO film.
  • ITO indium tin oxide
  • the drain electrode 14 b and the pixel electrode 18 are connected in the TFT area
  • the pad electrode 14 c and the pixel electrode 18 a are connected in the pad area.
  • pure aluminum (“Al”) is used as the gate electrode material to lower the resistance of a gate line.
  • An anodizing process is therefore required to prevent a hillock caused by the Al. This additional anodizing step complicates the manufacturing process, reduces productivity, and increases manufacturing costs.
  • an improved method for manufacturing a liquid crystal display comprising the steps of forming a gate electrode and a gate pad by a first photolithography process by sequentially depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively; forming an insulating film over the entire surface of the substrate on which the gate electrode and the gate pad are formed; forming a semiconductor film pattern over the insulating film of the TFT area using a second photolithography process; forming a source electrode and a drain electrode in the TFT area using a third photolithography process, the source electrode and the drain electrode comprising a third metal film; forming a protection film pattern over the substrate on which the source electrode and the drain electrode are formed using a fourth photolithography process, the protection film pattern exposing a portion of the drain electrode and a portion of the gate pad; and forming a pixel electrode over the substrate on which the protection film pattern is formed using a fifth photolithography process
  • the first metal film preferably comprises one of aluminum or an aluminum alloy and the second metal film comprises a refractory metal. More specifically, the second metal film preferably comprises a metal selected from the group consisting of Cr, Ta, Mo, and Ti.
  • the step of forming the gate electrode includes the steps of forming the first metal film and the second metal film over a substrate in the described order; forming a photoresist pattern over a portion of the second metal film; etching the second metal film using the photoresist pattern as a mask; reflowing the photoresist pattern; etching the first metal film using the reflowed photoresist pattern as a mask; and removing the reflowed photoresist pattern.
  • the step of reflowing the photoresist pattern may be performed in multiple steps.
  • the step of forming the gate electrode preferably includes the steps of forming the first metal film and the second metal film on the substrate in the described order; forming a photoresist pattern on a portion of the second metal film; etching the second metal film by etching using the photoresist pattern as a mask; and etching the first metal film.
  • the etching of the second metal film may be either a wet or dry etch and a step of baking the photoresist pattern may be included after the step of etching the second metal film.
  • the step of forming the gate electrode preferably includes the steps of forming the first metal film and the second metal film on a substrate; forming a photoresist pattern on a portion of the second metal film; etching the second metal film using the photoresist pattern as a mask; etching the first metal film using the patterned second metal film; and re-etching the patterned second metal film.
  • a step of baking the photoresist pattern may be included prior to the step of etching the first metal film after the step of etching the second metal film.
  • the present invention it is possible to prevent a battery effect and a hillock caused by directly contact of Al to the ITO by forming the gate electrode in a double structure of Al or an Al alloy and a refractory metal film. Also, it is possible to omit the anodizing process and to simultaneously etch the insulating layer and the protection film due to a capping film, thus reducing the number of the photolithography processes. Also, since it is possible to form the first metal film larger than or identical to the second metal film, an undercut is not generated in the gate electrode. Therefore, it is possible to prevent the deterioration of insulation characteristics due to poor step coverage during deposition of the insulating film after forming the gate electrode.
  • FIGS. 1 through 5 are sectional views illustrating a method for manufacturing liquid crystal display according to a conventional method
  • FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to first through fourth preferred embodiments of the present invention.
  • FIGS. 7 through 11 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention.
  • FIG. 12 is a sectional view showing generation of an undercut in a gate electrode
  • FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention.
  • FIGS. 17 through 19 are sectional views illustrating a method for manufacturing a liquid crystal display according to a third preferred embodiment of the present invention.
  • FIGS. 20 through 23 are sectional views illustrating a method for manufacturing a liquid crystal display according to a fourth preferred embodiment of the present invention.
  • FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to the present invention, in which reference numeral 100 denotes a mask pattern for forming a gateline; reference numeral 105 denotes a mask pattern for forming a gate pad; reference numeral 110 denotes a mask pattern for forming a data line, reference numeral 115 denotes a mask pattern for forming a data pad; reference numeral 120 denotes a mask pattern for forming a semiconductor film; reference numeral 130 denotes a mask pattern for forming a source electrode/drain electrode; reference numeral 140 denotes a mask pattern for forming a contact hole for connecting a pixel electrode to the drain electrode in the TFT area; reference numeral 145 denotes a mask pattern for forming a contact hole for connecting a gate pad in the pad area to the pixel electrode; reference numeral 150 denotes a mask pattern for forming a pixel electrode in the TFT area; and reference numeral 155 denotes
  • the gate line 100 is arranged horizontally, and the data line 110 is arranged perpendicular to the gate line.
  • the plurality of gate lines 100 and data lines 110 in the device are arranged together in a matrix pattern.
  • the gate pad 105 is provided at the end portion of the gate line 100
  • the data pad 115 is provided at the end portion of the data line 110 .
  • Pixel portions are respectively arranged in the matrix pattern in the portion bounded by the two adjacent gate lines and the data line.
  • the gate electrodes of the respective TFTs are formed so as to protrude into the pixel portions from the respective gate lines.
  • the semiconductor film 120 is formed between the drain electrodes and the gate electrodes of the respective TFTs.
  • the source electrodes of the TFTs are formed in protruding portions from the data line 110 .
  • the pixel electrodes 150 comprise transparent ITO and are formed in the respective pixel portions.
  • FIGS. 7 through 11 are sectional views for explaining a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention.
  • Reference character “C” represents the TFT area, which is a sectional view taken along I-I′ of FIG. 6
  • reference character “D” represents the pad area, which is a sectional view taken along II-II′ of FIG. 6 .
  • FIG. 7 shows the steps for forming the gate electrode, in which a first metal film 22 is formed by depositing an Al or an Al-alloy film to a thickness of 2,000 ⁇ 4,000 ⁇ over a transparent substrate 20 .
  • a second metal film 24 is then formed by depositing a refractory metal film to a thickness 500 ⁇ 2,000 ⁇ over the first metal film.
  • Gate patterns are then formed in the TFT area and the pad area by performing a first photolithography on the first and the second metal films 22 and 24 .
  • the gate patterns are used as a gate electrode in the TFT area and as a gate pad in the pad area.
  • the first and the second metal films are then wet or dry etched using a mask.
  • the first metal film 22 is preferably formed of Al or an Al-alloy such as Al—Nd or Al—Ta. It is possible to lower the resistance of the gate line and to prevent generation of a hillock when the gate electrode is formed of the Al alloy.
  • the second metal film 24 is preferably formed of one refractory metal selected from the group consisting of Cr, Ta, Mo, and Ti. The second metal film acts as a capping film to prevent the Al alloy from contacting the ITO film to be formed in a subsequent process. Because a capping film is formed on the Al or Al-alloy, a high temperature oxidation process and a photolithography process for forming an oxidized film are not required. Also, since the second metal film 24 does not include Al, no battery effect is generated, even though the second metal film 24 directly contacts the ITO film formed in a subsequent process.
  • FIG. 8 shows the steps for forming a semiconductor film pattern, in which an insulating film 26 is formed by depositing a nitride film to a thickness of about 4,000 ⁇ over the entire surface of the substrate on which a gate pattern is formed.
  • a semiconductor film preferably comprised of an amorphous silicon film 28 and an impurity doped-amorphous silicon film 30 is formed to a thickness of 1,000 ⁇ 2,000 ⁇ and a thickness of 500 ⁇ , respectively, on the insulating layer 26 .
  • a semiconductor film pattern to be used as an active area is then formed in the TFT area by performing a second photolithography on the semiconductor film.
  • FIG. 9 shows the steps for forming a source electrode and a drain electrode.
  • a third metal film is formed by depositing a Cr film to a thickness of 1,000 ⁇ 2,000 ⁇ over the entire surface of the substrate 20 on which the semiconductor film pattern is formed.
  • the third metal film is preferably deposited using a sputtering method.
  • a source electrode 32 a and a drain electrode 32 b are then formed in the TFT area by performing a third photolithography on the third metal film.
  • FIG. 10 shows the steps for forming a protection film pattern.
  • the protection film 34 is formed by depositing an insulating material ,e.g., an oxide film to a thickness of 1,000 ⁇ 3,000 ⁇ over the entire surface of the substrate on which the source electrode 32 a and the drain electrode 32 b are formed.
  • a protection film pattern 34 is formed by performing a fourth photolithography on the protection film.
  • the protection film pattern 34 exposes a portion of the drain electrode 32 b and a portion of the gate electrode 22 and 24 formed in the pad area, i.e., a gate pad.
  • the protection film 34 and the insulating film 26 in the pad area over the gate pad are simultaneously etched to expose a portion of the capping film 24 .
  • FIG. 11 shows the steps for forming a pixel electrode.
  • a transparent conductive film by a sputtering method over the entire surface of the substrate on which the protection film pattern is formed, pixel electrodes 36 and 36 a are formed in the TFT area and the pad area by performing a fifth photolithography on the ITO film.
  • the pixel electrode 36 and the drain electrode 32 b are connected in the TFT area and the pixel electrode 36 a, and the gate pad 22 and 24 are connected in the pad area.
  • the method for forming a liquid crystal display according to a first embodiment of the present invention prevents the occurrence of a battery effect and prevents the formation of an Al hillock caused by contact of Al to the ITO.
  • This method achieves these goals by forming a gate electrode using Al or an Al-alloy and by forming the capping film on the gate electrode using a refractory metal.
  • the method of the first preferred embodiment also makes it possible to reduce the number of photolithography processes by omitting the anodizing process and simultaneously forming the contact on the insulating film and the protection film.
  • the first metal film 22 and the second metal film 24 which comprise the gate electrode in the first embodiment of the present invention are etched using only one mask. As a result of this use of a single mask, an undercut may be generated in the gate electrode as shown in FIG. 12 . As a result, step coverage becomes poor in a subsequent insulating film depositing process, thus creating a risk of deteriorating insulation characteristics.
  • a method for preventing the generation of the undercut in the gate electrode is provided.
  • FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11 .
  • FIG. 13 shows the step of forming the conductive films for the gate electrode.
  • a first metal film 42 is formed by depositing an Al film or an Al-alloy film on a transparent substrate 40 to a thickness of 2,000 ⁇ 4,000 ⁇ .
  • a second metal film 44 used as a capping film, is then formed by depositing a refractory metal, such as Cr, Ta, Mo, or Ti, preferably Cr, over the first metal film 42 .
  • a refractory metal such as Cr, Ta, Mo, or Ti, preferably Cr
  • Al—Nd or Al—Ta may be used for the Al-alloy film.
  • FIG. 14 shows the step of forming a photoresist pattern 46 .
  • a photoresist pattern 46 is formed by coating photoresist over the second metal film 44 and by exposing and developing the photoresist.
  • the second metal film 44 is then etched using the photoresist pattern 46 as a mask.
  • An undercut is generated in the second metal film 44 during this etching process by sufficiently overetching the second metal film 44 .
  • FIG. 15 shows the step of reflowing the photoresist 46 .
  • the substrate is heated to a temperature above 100° C. to reflow the photoresist 46 .
  • a multiple-step heat treatment may be performed on the substrate to improve the reflow characteristic of the photoresist 46 .
  • the reflowed photoresist 46 a completely covers the patterned second metal film 44 .
  • FIG. 16 shows the steps of forming the gate electrode.
  • the first metal film 42 is etched using the reflowed photoresist pattern 46 a of FIG. 15 as a mask, after which the reflowed photoresist 46 a is removed. Since the etched first metal film 42 is now wider than the second metal film 44 by the thickness of the reflowed photoresist 46 a of FIG. 15 , the step coverage of the insulating film is favorable in a subsequent insulating film depositing step. In order to prevent the first metal film 42 from contacting the ITO formed in a subsequent process, it is preferable to control the thickness and the size of the photoresist pattern to make the patterned second metal film 44 larger than the contact hole for connecting the ITO and the gate pad.
  • FIGS. 17 through 19 are sectional views for explaining a method for manufacturing a liquid crystal display according to a third preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11 .
  • FIG. 17 shows the step of forming conductive films 52 and 54 for the gate electrode and a photoresist pattern 56 . These steps are identical to the steps described with reference to FIG. 13 for the second preferred embodiment of the present invention.
  • FIG. 18 shows the step of patterning the second metal film 54 .
  • the second metal film 54 is wet or dry etched using the photoresist pattern 56 of FIG. 17 as a mask.
  • the photoresist pattern may then be removed, or it may remain until after the first metal film 52 is etched.
  • an undercut may be generated to narrow the width of the first metal film 52 .
  • baking may be performed on the photoresist pattern to prevent lifting of the photoresist pattern.
  • FIG. 19 shows the step of forming the gate electrode by etching the first metal film 52 using the patterned second metal film 54 as a mask. If the photoresist pattern 56 is not removed in the previous step, the photoresist pattern 56 can be used as a mask and it can be removed after etching the first metal film 52 .
  • FIGS. 20 through 23 are sectional views for explaining a method for manufacturing a liquid crystal display according to a fourth preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11 .
  • FIG. 20 shows the steps of forming conductive films 62 and 64 for the gate electrode and a photoresist pattern 66 . These steps are identical to the steps described with reference to FIG. 13 and 17 for the second and third preferred embodiments of the present invention.
  • FIG. 21 shows the step of etching the second metal film, in which the second metal film 64 is wet etched using the photoresist pattern 66 as a mask. At this time, the second metal film 64 is sufficiently etched so as to generate an undercut.
  • FIG. 22 shows the step of etching the first metal film 62 .
  • this step an undercut is formed in the gate electrode as shown in FIG. 12 when the first metal film 62 is wet etched using the patterned second metal film 64 as a mask.
  • FIG. 23 shows the step of re-etching the second metal film, in which the width of the lower portion of the first metal film 62 becomes wider than that of the second metal film 64 after the patterned second metal film 64 is re-etched. As a result of this re-etching, the undercut of the gate electrode is removed. To avoid lifting of the photoresist pattern 66 when etching the first metal film 62 or when re-etching the second metal film 64 , baking may be performed on the second metal film 64 after performing the first etching on the second metal film 64 .
  • the gate electrode is formed in a two-layered-structure of Al or Al-alloy and a refractory metal. Therefore, it is possible to prevent a battery effect caused by directly contacting the Al to the ITO and it is also possible to prevent the generation of a hillock of the Al due to the stress relaxation of the refractory metal. It is also possible to reduce the number of photolithography processes by omitting the anodizing process and simultaneously etching the insulating film and the protection film.

Abstract

A TFT substrate includes a gate electrode and gate pad on a transparent substrate, an insulating layer on the gate electrode and exposing a portion of the gate pad, a semiconductor film on the insulating layer and the gate electrode, an impurity doped semiconductor film on the semiconductor film, the impurity doped semiconductor film contacting a top surface of the semiconductor film over the gate electrode, source and drain electrodes and a data line on a portion of the impurity doped semiconductor film, a protection film on the source and drain electrodes and the insulating layer in a gate pad area, the protection film having a contact hole over the drain electrode exposing a top surface of the gate pad, a first pixel electrode electrically connected to the drain electrode on the protection film, and a second pixel electrode directly connected to the exposed top surface of the gate pad.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This is a divisional application of application Ser. No. 09/391,454, filed Sep. 8, 1999 now U.S. Pat. No. 6,339,230 which is a continuation application of application Ser. No. 08/754,644, filed Nov. 21, 1996 now U.S. Pat. No. 6,008,065, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a liquid crystal display. More particularly, present invention relates to an improved method for manufacturing a thin film transistor-liquid crystal display which reduces the number of photolithography processes that must be performed.
A thin film transistor LCD (“TFT-LCD”), which uses the thin film transistor as the active device, has various advantages over other LCDs. These advantages include low power consumption, low drive voltage, a thinness, and lightness of weight, among others.
Since the thin film transistor (“TFT”) is significantly thinner than a conventional transistor, the process of manufacturing a TFT is complicated, resulting in low productivity and high manufacturing costs. In particular, since a mask is used in every step for manufacturing a TFT, at least seven masks are required. Therefore, various methods for increasing productivity of the TFT and lowering the manufacturing costs have been studied. In particular, a method for reducing the number of the masks used during the manufacturing process has been widely researched.
FIGS. 1 to 5 are sectional views for explaining a conventional method for manufacturing an LCD, as disclosed in U.S. Pat. No. 5,054,887.
In the drawings, reference characters “A” and “B” denote a TFT area and a pad area, respectively. Referring to FIG. 1, after forming a first metal film by depositing pure Al on a transparent substrate 2, gate patterns 4 and 4a are formed out of the first metal film by performing a first photolithography on the first metal film. The gate patterns are then used as a gate electrode 4 in the TFT area and as a gate pad 4a in the pad area.
As shown in FIG. 2, after forming by general photolithography a second photoresist pattern (not shown) that covers a portion of the pad area, an anodized film 6 is formed by oxidizing the first metal film using the photoresist pattern as an anti-oxidation film. The anodized film 6 is then formed on the entire surface of the gate electrode 4 formed in the TFT area, and on a portion of the gate pad 4a in the pad area.
Referring to FIG. 3, an insulating film 8 is formed by depositing a layer such as a nitride film over the anodized film 6. A semiconductor film is then formed by subsequently depositing an amorphous silicon film 10 and an amorphous silicon film 12 doped with impurities on the entire surface of the substrate 2 on which the insulating film 8 is formed. A semiconductor film pattern 10 and 12 to be used as an active portion is then formed in the TFT area by performing a third photolithography on the semiconductor film.
As shown in FIG. 4, a fourth photoresist pattern (not shown) is then formed that exposes a portion of the gate pad 4a formed in the pad area by performing a fourth photolithography on the entire surface of the substrate 2 on which the semiconductor film pattern is formed. Then, a contact hole is then formed in the insulating film 8, which contact hole exposes a portion of the gate pad 4a. The contact hole is formed by etching the insulating film 8 using the fourth photoresist pattern as a mask. A source electrode 14a and a drain electrode 14b are then formed in the TFT area by depositing a chromium (“Cr”) film on the entire surface of the substrate having the contact hole and performing a fifth photolithography on the Cr film. In the pad area, a pad electrode 14c connected to the gate pad 4a through the contact hole is formed. At this time, the impurity doped-amorphous silicon film 12 on the upper portion of the gate electrode 4 formed in the TFT area during the photolithography process is partially etched, thus exposing a portion of the amorphous silicon film 10.
Referring to FIG. 5, a protection film 16 is then formed by depositing an oxide film over the entire surface of the substrate 2 on which the source electrode 14a, the drain electrode 14b and the pad electrode 14c are formed. Then, contact holes are formed that expose a portion of the drain electrode 14b of the TFT area and a portion of the pad electrode 14c of the pad area. The contact holes are formed by performing a sixth photolithography on the protection film 16.
Subsequently, pixel electrodes 18 and 18a are formed by depositing indium tin oxide (“ITO”), a transparent conductive material, over the entire surface of the substrate, including the contact hole, and performing a seventh photolithography process on the resultant ITO film. As a result of this seventh lithography, the drain electrode 14b and the pixel electrode 18 are connected in the TFT area, and the pad electrode 14c and the pixel electrode 18a are connected in the pad area.
According to the conventional method for manufacturing the LCD, pure aluminum (“Al”) is used as the gate electrode material to lower the resistance of a gate line. An anodizing process is therefore required to prevent a hillock caused by the Al. This additional anodizing step complicates the manufacturing process, reduces productivity, and increases manufacturing costs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method for manufacturing a liquid crystal display in which manufacturing costs are reduced and productivity increased by reducing the number of photolithography processes performed.
It is another object of the present invention to provide a method for manufacturing a liquid crystal display by which it is possible to prevent the deterioration of device characteristics by preventing the generation of an undercut in a gate electrode.
To achieve the above objects, there is provided an improved method for manufacturing a liquid crystal display according to the present invention, comprising the steps of forming a gate electrode and a gate pad by a first photolithography process by sequentially depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively; forming an insulating film over the entire surface of the substrate on which the gate electrode and the gate pad are formed; forming a semiconductor film pattern over the insulating film of the TFT area using a second photolithography process; forming a source electrode and a drain electrode in the TFT area using a third photolithography process, the source electrode and the drain electrode comprising a third metal film; forming a protection film pattern over the substrate on which the source electrode and the drain electrode are formed using a fourth photolithography process, the protection film pattern exposing a portion of the drain electrode and a portion of the gate pad; and forming a pixel electrode over the substrate on which the protection film pattern is formed using a fifth photolithography process, the pixel electrode being connected to the drain electrode and the gate pad.
The first metal film preferably comprises one of aluminum or an aluminum alloy and the second metal film comprises a refractory metal. More specifically, the second metal film preferably comprises a metal selected from the group consisting of Cr, Ta, Mo, and Ti.
The step of forming the gate electrode includes the steps of forming the first metal film and the second metal film over a substrate in the described order; forming a photoresist pattern over a portion of the second metal film; etching the second metal film using the photoresist pattern as a mask; reflowing the photoresist pattern; etching the first metal film using the reflowed photoresist pattern as a mask; and removing the reflowed photoresist pattern. The step of reflowing the photoresist pattern may be performed in multiple steps.
The step of forming the gate electrode preferably includes the steps of forming the first metal film and the second metal film on the substrate in the described order; forming a photoresist pattern on a portion of the second metal film; etching the second metal film by etching using the photoresist pattern as a mask; and etching the first metal film. The etching of the second metal film may be either a wet or dry etch and a step of baking the photoresist pattern may be included after the step of etching the second metal film.
The step of forming the gate electrode preferably includes the steps of forming the first metal film and the second metal film on a substrate; forming a photoresist pattern on a portion of the second metal film; etching the second metal film using the photoresist pattern as a mask; etching the first metal film using the patterned second metal film; and re-etching the patterned second metal film. A step of baking the photoresist pattern may be included prior to the step of etching the first metal film after the step of etching the second metal film.
According to the present invention, it is possible to prevent a battery effect and a hillock caused by directly contact of Al to the ITO by forming the gate electrode in a double structure of Al or an Al alloy and a refractory metal film. Also, it is possible to omit the anodizing process and to simultaneously etch the insulating layer and the protection film due to a capping film, thus reducing the number of the photolithography processes. Also, since it is possible to form the first metal film larger than or identical to the second metal film, an undercut is not generated in the gate electrode. Therefore, it is possible to prevent the deterioration of insulation characteristics due to poor step coverage during deposition of the insulating film after forming the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
FIGS. 1 through 5 are sectional views illustrating a method for manufacturing liquid crystal display according to a conventional method;
FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to first through fourth preferred embodiments of the present invention;
FIGS. 7 through 11 are sectional views illustrating a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention;
FIG. 12 is a sectional view showing generation of an undercut in a gate electrode;
FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention;
FIGS. 17 through 19 are sectional views illustrating a method for manufacturing a liquid crystal display according to a third preferred embodiment of the present invention; and
FIGS. 20 through 23 are sectional views illustrating a method for manufacturing a liquid crystal display according to a fourth preferred embodiment of the present invention.
 DETAILED DESCRIPTION OF THE INVENTION
FIG. 6 is a schematic plan view of the mask patterns used for manufacturing a liquid crystal display according to the present invention, in which reference numeral 100 denotes a mask pattern for forming a gateline; reference numeral 105 denotes a mask pattern for forming a gate pad; reference numeral 110 denotes a mask pattern for forming a data line, reference numeral 115 denotes a mask pattern for forming a data pad; reference numeral 120 denotes a mask pattern for forming a semiconductor film; reference numeral 130 denotes a mask pattern for forming a source electrode/drain electrode; reference numeral 140 denotes a mask pattern for forming a contact hole for connecting a pixel electrode to the drain electrode in the TFT area; reference numeral 145 denotes a mask pattern for forming a contact hole for connecting a gate pad in the pad area to the pixel electrode; reference numeral 150 denotes a mask pattern for forming a pixel electrode in the TFT area; and reference numeral 155 denotes a mask pattern for forming a pixel electrode in the pad portion.
Referring to FIG. 6, the gate line 100 is arranged horizontally, and the data line 110 is arranged perpendicular to the gate line. The plurality of gate lines 100 and data lines 110 in the device are arranged together in a matrix pattern. The gate pad 105 is provided at the end portion of the gate line 100, and the data pad 115 is provided at the end portion of the data line 110. Pixel portions are respectively arranged in the matrix pattern in the portion bounded by the two adjacent gate lines and the data line. The gate electrodes of the respective TFTs are formed so as to protrude into the pixel portions from the respective gate lines. The semiconductor film 120 is formed between the drain electrodes and the gate electrodes of the respective TFTs. The source electrodes of the TFTs are formed in protruding portions from the data line 110. The pixel electrodes 150 comprise transparent ITO and are formed in the respective pixel portions.
FIGS. 7 through 11 are sectional views for explaining a method for manufacturing a liquid crystal display according to a first preferred embodiment of the present invention. Reference character “C” represents the TFT area, which is a sectional view taken along I-I′ of FIG. 6, and reference character “D” represents the pad area, which is a sectional view taken along II-II′ of FIG. 6.
FIG. 7 shows the steps for forming the gate electrode, in which a first metal film 22 is formed by depositing an Al or an Al-alloy film to a thickness of 2,000˜4,000 Å over a transparent substrate 20. A second metal film 24 is then formed by depositing a refractory metal film to a thickness 500˜2,000 Å over the first metal film. Gate patterns are then formed in the TFT area and the pad area by performing a first photolithography on the first and the second metal films 22 and 24. The gate patterns are used as a gate electrode in the TFT area and as a gate pad in the pad area. The first and the second metal films are then wet or dry etched using a mask.
The first metal film 22 is preferably formed of Al or an Al-alloy such as Al—Nd or Al—Ta. It is possible to lower the resistance of the gate line and to prevent generation of a hillock when the gate electrode is formed of the Al alloy. The second metal film 24 is preferably formed of one refractory metal selected from the group consisting of Cr, Ta, Mo, and Ti. The second metal film acts as a capping film to prevent the Al alloy from contacting the ITO film to be formed in a subsequent process. Because a capping film is formed on the Al or Al-alloy, a high temperature oxidation process and a photolithography process for forming an oxidized film are not required. Also, since the second metal film 24 does not include Al, no battery effect is generated, even though the second metal film 24 directly contacts the ITO film formed in a subsequent process.
FIG. 8 shows the steps for forming a semiconductor film pattern, in which an insulating film 26 is formed by depositing a nitride film to a thickness of about 4,000 Å over the entire surface of the substrate on which a gate pattern is formed. A semiconductor film preferably comprised of an amorphous silicon film 28 and an impurity doped-amorphous silicon film 30 is formed to a thickness of 1,000˜2,000 Å and a thickness of 500 Å, respectively, on the insulating layer 26. A semiconductor film pattern to be used as an active area is then formed in the TFT area by performing a second photolithography on the semiconductor film.
FIG. 9 shows the steps for forming a source electrode and a drain electrode. A third metal film is formed by depositing a Cr film to a thickness of 1,000˜2,000 Å over the entire surface of the substrate 20 on which the semiconductor film pattern is formed. The third metal film is preferably deposited using a sputtering method. A source electrode 32a and a drain electrode 32b are then formed in the TFT area by performing a third photolithography on the third metal film.
FIG. 10 shows the steps for forming a protection film pattern. The protection film 34 is formed by depositing an insulating material ,e.g., an oxide film to a thickness of 1,000˜3,000 Å over the entire surface of the substrate on which the source electrode 32a and the drain electrode 32b are formed. A protection film pattern 34 is formed by performing a fourth photolithography on the protection film. The protection film pattern 34 exposes a portion of the drain electrode 32b and a portion of the gate electrode 22 and 24 formed in the pad area, i.e., a gate pad. The protection film 34 and the insulating film 26 in the pad area over the gate pad are simultaneously etched to expose a portion of the capping film 24.
FIG. 11 shows the steps for forming a pixel electrode. After forming the ITO film, a transparent conductive film, by a sputtering method over the entire surface of the substrate on which the protection film pattern is formed, pixel electrodes 36 and 36a are formed in the TFT area and the pad area by performing a fifth photolithography on the ITO film. As a result, the pixel electrode 36 and the drain electrode 32b are connected in the TFT area and the pixel electrode 36a, and the gate pad 22 and 24 are connected in the pad area.
The method for forming a liquid crystal display according to a first embodiment of the present invention prevents the occurrence of a battery effect and prevents the formation of an Al hillock caused by contact of Al to the ITO. This method achieves these goals by forming a gate electrode using Al or an Al-alloy and by forming the capping film on the gate electrode using a refractory metal. The method of the first preferred embodiment also makes it possible to reduce the number of photolithography processes by omitting the anodizing process and simultaneously forming the contact on the insulating film and the protection film.
The first metal film 22 and the second metal film 24 which comprise the gate electrode in the first embodiment of the present invention are etched using only one mask. As a result of this use of a single mask, an undercut may be generated in the gate electrode as shown in FIG. 12. As a result, step coverage becomes poor in a subsequent insulating film depositing process, thus creating a risk of deteriorating insulation characteristics. In the second through fourth embodiments of the present invention, a method for preventing the generation of the undercut in the gate electrode is provided.
FIGS. 13 through 16 are sectional views illustrating a method for manufacturing a liquid crystal display according to a second preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11.
FIG. 13 shows the step of forming the conductive films for the gate electrode. Initially, a first metal film 42 is formed by depositing an Al film or an Al-alloy film on a transparent substrate 40 to a thickness of 2,000˜4,000 Å. A second metal film 44, used as a capping film, is then formed by depositing a refractory metal, such as Cr, Ta, Mo, or Ti, preferably Cr, over the first metal film 42. In this process, Al—Nd or Al—Ta may be used for the Al-alloy film.
FIG. 14 shows the step of forming a photoresist pattern 46. A photoresist pattern 46 is formed by coating photoresist over the second metal film 44 and by exposing and developing the photoresist. The second metal film 44 is then etched using the photoresist pattern 46 as a mask. An undercut is generated in the second metal film 44 during this etching process by sufficiently overetching the second metal film 44.
FIG. 15 shows the step of reflowing the photoresist 46. The substrate is heated to a temperature above 100° C. to reflow the photoresist 46. A multiple-step heat treatment may be performed on the substrate to improve the reflow characteristic of the photoresist 46. As a result of the reflowing process, the reflowed photoresist 46a completely covers the patterned second metal film 44.
FIG. 16 shows the steps of forming the gate electrode. First, the first metal film 42 is etched using the reflowed photoresist pattern 46a of FIG. 15 as a mask, after which the reflowed photoresist 46a is removed. Since the etched first metal film 42 is now wider than the second metal film 44 by the thickness of the reflowed photoresist 46a of FIG. 15, the step coverage of the insulating film is favorable in a subsequent insulating film depositing step. In order to prevent the first metal film 42 from contacting the ITO formed in a subsequent process, it is preferable to control the thickness and the size of the photoresist pattern to make the patterned second metal film 44 larger than the contact hole for connecting the ITO and the gate pad.
FIGS. 17 through 19 are sectional views for explaining a method for manufacturing a liquid crystal display according to a third preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11.
FIG. 17 shows the step of forming conductive films 52 and 54 for the gate electrode and a photoresist pattern 56. These steps are identical to the steps described with reference to FIG. 13 for the second preferred embodiment of the present invention.
FIG. 18 shows the step of patterning the second metal film 54. In this step, the second metal film 54 is wet or dry etched using the photoresist pattern 56 of FIG. 17 as a mask. The photoresist pattern may then be removed, or it may remain until after the first metal film 52 is etched.
If the second metal film 54 is wet etched in this step, an undercut may be generated to narrow the width of the first metal film 52. In this case, if the photoresist pattern is not removed, baking may be performed on the photoresist pattern to prevent lifting of the photoresist pattern.
FIG. 19 shows the step of forming the gate electrode by etching the first metal film 52 using the patterned second metal film 54 as a mask. If the photoresist pattern 56 is not removed in the previous step, the photoresist pattern 56 can be used as a mask and it can be removed after etching the first metal film 52.
FIGS. 20 through 23 are sectional views for explaining a method for manufacturing a liquid crystal display according to a fourth preferred embodiment of the present invention. The initial steps of the process, through the step of forming the gate electrode, are shown. All subsequent steps are similar to those shown for the first preferred embodiment in FIGS. 8 to 11.
FIG. 20 shows the steps of forming conductive films 62 and 64 for the gate electrode and a photoresist pattern 66. These steps are identical to the steps described with reference to FIG. 13 and 17 for the second and third preferred embodiments of the present invention.
FIG. 21 shows the step of etching the second metal film, in which the second metal film 64 is wet etched using the photoresist pattern 66 as a mask. At this time, the second metal film 64 is sufficiently etched so as to generate an undercut.
FIG. 22 shows the step of etching the first metal film 62. In this step an undercut is formed in the gate electrode as shown in FIG. 12 when the first metal film 62 is wet etched using the patterned second metal film 64 as a mask.
FIG. 23 shows the step of re-etching the second metal film, in which the width of the lower portion of the first metal film 62 becomes wider than that of the second metal film 64 after the patterned second metal film 64 is re-etched. As a result of this re-etching, the undercut of the gate electrode is removed. To avoid lifting of the photoresist pattern 66 when etching the first metal film 62 or when re-etching the second metal film 64, baking may be performed on the second metal film 64 after performing the first etching on the second metal film 64.
According to the above-mentioned preferred methods for manufacturing the liquid crystal display according to the present invention, the gate electrode is formed in a two-layered-structure of Al or Al-alloy and a refractory metal. Therefore, it is possible to prevent a battery effect caused by directly contacting the Al to the ITO and it is also possible to prevent the generation of a hillock of the Al due to the stress relaxation of the refractory metal. It is also possible to reduce the number of photolithography processes by omitting the anodizing process and simultaneously etching the insulating film and the protection film.
Since it is possible to form the Al film or Al-alloy film formed on the lower area to be identical in size or larger than the refractory metal formed on the upper portion, an undercut is not generated in the gate electrode. Therefore, it is possible to prevent the deterioration of insulation characteristics caused by poor step coverage.
The present invention is not limited to the above-described embodiments. Various changes and modifications may be effected by one having an ordinary skill in the art and remain within the scope of the invention, as defined by the appended claims.

Claims (24)

1. A TFT substrate, comprising:
a gate electrode, a gate pad and a gate line formed on a transparent substrate and comprising a first wire pattern containing Al formed over the transparent substrate, and a second wire pattern containing a refractory metal formed over the first wire pattern;
an insulating layer pattern formed over the gate electrode and exposing a portion of the second wire pattern of the gate pad containing the refractory metal;
a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;
an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contacts contact a top surface of the semiconductor film pattern formed over the gate electrode;
a source electrode, connected to a data line, and a drain electrode, and a data line formed over a portion portions of the impurity doped semiconductor film pattern;
a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;
a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and
a second pixel electrode pattern directly connected to the exposed top surface of the second wire pattern of the gate pad containing the refractory metal,
wherein the semiconductor film pattern includes a portion disposed between the source electrode and the drain electrode, and wherein a portion of the protection film pattern directly contacts a top surface of the portion of the semiconductor film pattern disposed between the source electrode and the drain electrode, and
wherein an interior angle formed between a lateral surface of the first wire pattern containing Al and the transparent substrate is smaller than an interior angle formed between a lateral surface of the second wire pattern containing the refractory metal and the transparent substrate.
2. A TFT substrate as recited in claim 1, wherein the gate electrode, the gate pad and the gate line comprise a metal film pattern and wherein a width of the metal film pattern becomes narrower from the bottom of the metal film pattern.
3. A TFT substrate as recited in claim 1, wherein a portion of the protection film pattern directly contacts the semiconductor film pattern located between the source electrode and the drain electrode.
4. A TFT substrate as recited in claim 1, wherein the insulating layer pattern comprises a nitride film of the formula SiNx.
5. A TFT substrate, comprising:
a gate electrode, a gate pad and a gate line which form a metal film pattern, wherein a width of the metal film pattern becomes narrower from a bottom of the metal film pattern and the metal film pattern comprises a first wire pattern containing Al, and a second wire pattern containing Mo formed over the first wire pattern;
an insulating layer pattern formed over the gate electrode and exposing a portion of the second wire pattern of the gate pad containing Mo;
a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;
an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contacts contact a top surface of the semiconductor film pattern formed over the gate electrode;
a source electrode, connected to a data line, and a drain electrode, and a data line formed over a portion portions of the impurity doped semiconductor film pattern;
a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;
a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and
a second pixel electrode pattern electrically connected to the exposed area top surface of the second wire pattern of the gate pad containing Mo,
wherein the second wire pattern containing Mo has a portion that protrudes beyond and overhangs an edge of an upper surface of the first wire pattern containing Al.
6. A TFT substrate as recited in claim 5, wherein a portion of the protection film pattern directly contacts the semiconductor film pattern located disposed between the source electrode and the drain electrode.
7. A TFT substrate as recited in claim 5, wherein the insulating layer pattern comprises a nitride film of the formula SiNx.
8. A TFT substrate, comprising:
a gate electrode, a gate pad and a gate line formed on a transparent substrate;
an insulating layer pattern formed over the gate electrode and exposing a portion of the gate pad;
a semiconductor film pattern formed over the insulating layer pattern and over the gate electrode;
an impurity doped semiconductor film pattern formed on the semiconductor film pattern, wherein entire bottom surfaces of the impurity doped semiconductor film pattern contact a top surface of the semiconductor film pattern formed over the gate electrode;
a source electrode connected to a data line, and a drain electrode, which are formed over portions of the impurity doped semiconductor film pattern;
a protection film pattern formed over the source electrode and the drain electrode and over the insulating layer pattern in an area of the gate pad, the protection film pattern having a contact hole over the drain electrode and exposing a top surface of the gate pad;
a first pixel electrode pattern electrically connected to the drain electrode on the protection film pattern; and
a second pixel electrode pattern directly connected to the exposed top surface of the gate pad,
wherein the gate electrode, the gate pad and the gate line comprise a first metal film pattern formed over the transparent substrate and a second metal film pattern formed over the first metal film pattern and the second pixel electrode pattern is directly connected to the second metal film pattern, and
wherein an inside angle formed between a lateral surface of the first metal film pattern and the transparent substrate is smaller than an inside angle formed between a lateral surface of the second metal film pattern and the transparent substrate.
9. A TFT substrate as recited in claim 8, wherein the second metal film pattern comprises a metal selected from the group consisting of Cr, Mo, Ta and Ti.
10. A TFT substrate as recited in claim 9, wherein the first metal film pattern comprises Al or an Al-alloy.
11. A TFT substrate as recited in claim 1, wherein the second wire pattern containing the refractory metal has a portion that protrudes beyond and overhangs an edge of an upper surface of the first wire pattern containing Al.
12. A TFT substrate as recited in claim 11, wherein a thickness of the first wire pattern containing Al is 2,000-4000 Å.
13. A TFT substrate as recited in claim 1, wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern.
14. A TFT substrate as recited in claim 1, wherein the insulating layer pattern comprises a nitride film and a thickness of the protection film pattern is less than a thickness of the insulating layer pattern.
15. A TFT substrate as recited in claim 14, wherein the thickness of the protection film pattern is 1,000-3,000 Å and the thickness of the insulating layer pattern is more than 3000 Å.
16. A TFT substrate as recited in claim 10, wherein a thickness of the second metal film pattern is the same or less than that of the first metal film pattern.
17. A TFT substrate as recited in claim 8, wherein a width of the second metal film is the same or less than that of the upper surface of the first metal film pattern.
18. A TFT substrate as recited in claim 8, wherein the second metal film pattern has a portion that protrudes beyond and overhangs an edge of an upper surface of the first metal film pattern.
19. A TFT substrate as recited in claim 8, wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern.
20. A TFT substrate as recited in claim 5, wherein an interior angle formed between a lateral surface of the first wire pattern containing Al and the transparent substrate, is smaller than an interior angle formed between a lateral surface of the second wire pattern containing Mo and the transparent substrate.
21. A TFT substrate as recited in claim 20, wherein a thickness of the first wire pattern containing Al is 2,000-4,000 Å.
22. A TFT substrate as recited in claim 21, wherein the insulating layer pattern comprises a nitride film and the protection film pattern is comprised of an insulating material different from the nitride film of the insulating layer pattern.
23. A TFT substrate as recited in claim 20, wherein the insulating layer pattern comprises a nitride film and a thickness of the protection film pattern is less than a thickness of the insulating layer pattern.
24. A TFT substrate as recited in claim 23, wherein the thickness of the protection film pattern is 1,000-3,000 Å and the thickness of the insulating layer pattern is more than 3000 Å.
US11/296,847 1995-11-21 2005-12-08 Thin film transistor substrate Expired - Lifetime USRE41363E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/296,847 USRE41363E1 (en) 1995-11-21 2005-12-08 Thin film transistor substrate

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
KR1019950042618A KR0183757B1 (en) 1995-11-21 1995-11-21 Method of manufacturing thin-film transistor liquid crystal display device
KR95-42618 1995-11-21
KR1019960013912A KR100219480B1 (en) 1995-11-29 1996-04-30 Thin film transistor liquid crystal display device and its manufacturing method
KR96-13912 1996-04-30
US08/754,644 US6008065A (en) 1995-11-21 1996-11-21 Method for manufacturing a liquid crystal display
US09/391,454 US6339230B1 (en) 1995-11-21 1999-09-08 Method for manufacturing a liquid crystal display
US10/032,443 US6661026B2 (en) 1995-11-21 2002-01-02 Thin film transistor substrate
US11/296,847 USRE41363E1 (en) 1995-11-21 2005-12-08 Thin film transistor substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/032,443 Reissue US6661026B2 (en) 1995-11-21 2002-01-02 Thin film transistor substrate

Publications (1)

Publication Number Publication Date
USRE41363E1 true USRE41363E1 (en) 2010-06-01

Family

ID=36627376

Family Applications (5)

Application Number Title Priority Date Filing Date
US08/754,644 Expired - Lifetime US6008065A (en) 1995-11-21 1996-11-21 Method for manufacturing a liquid crystal display
US09/391,454 Expired - Lifetime US6339230B1 (en) 1995-11-21 1999-09-08 Method for manufacturing a liquid crystal display
US09/443,386 Expired - Lifetime US6331443B1 (en) 1995-11-21 1999-11-19 Method for manufacturing a liquid crystal display
US10/032,443 Ceased US6661026B2 (en) 1995-11-21 2002-01-02 Thin film transistor substrate
US11/296,847 Expired - Lifetime USRE41363E1 (en) 1995-11-21 2005-12-08 Thin film transistor substrate

Family Applications Before (4)

Application Number Title Priority Date Filing Date
US08/754,644 Expired - Lifetime US6008065A (en) 1995-11-21 1996-11-21 Method for manufacturing a liquid crystal display
US09/391,454 Expired - Lifetime US6339230B1 (en) 1995-11-21 1999-09-08 Method for manufacturing a liquid crystal display
US09/443,386 Expired - Lifetime US6331443B1 (en) 1995-11-21 1999-11-19 Method for manufacturing a liquid crystal display
US10/032,443 Ceased US6661026B2 (en) 1995-11-21 2002-01-02 Thin film transistor substrate

Country Status (5)

Country Link
US (5) US6008065A (en)
EP (2) EP1338914A3 (en)
JP (5) JP3891617B2 (en)
DE (1) DE69635239T2 (en)
TW (1) TW426809B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368076B2 (en) 1999-07-22 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US9048220B2 (en) 2010-06-21 2015-06-02 Joled Inc. Method of crystallizing silicon thin film and method of manufacturing silicon thin-film transistor device

Families Citing this family (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3866783B2 (en) * 1995-07-25 2007-01-10 株式会社 日立ディスプレイズ Liquid crystal display
KR100190041B1 (en) * 1995-12-28 1999-06-01 윤종용 Method of fabricating liquid crystal display device
KR100190023B1 (en) * 1996-02-29 1999-06-01 윤종용 Tft-lcd and fabrication method thereof
US6940566B1 (en) * 1996-11-26 2005-09-06 Samsung Electronics Co., Ltd. Liquid crystal displays including organic passivation layer contacting a portion of the semiconductor layer between source and drain regions
CN1148600C (en) * 1996-11-26 2004-05-05 三星电子株式会社 Liquid crystal display using organic insulating material and manufacturing methods thereof
JP3760008B2 (en) * 1996-11-29 2006-03-29 セイコーエプソン株式会社 Liquid crystal panel substrate, liquid crystal panel using the same, and projection display device
JPH10198292A (en) * 1996-12-30 1998-07-31 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
KR100229613B1 (en) * 1996-12-30 1999-11-15 구자홍 Lcd device and its manufacturing method
KR100248123B1 (en) 1997-03-04 2000-03-15 구본준 Thin-film transistor and method for manufacturing thereof
KR100252306B1 (en) * 1997-07-04 2000-04-15 구본준, 론 위라하디락사 Active matrix substrate and manufacturing method of the same
US6333518B1 (en) * 1997-08-26 2001-12-25 Lg Electronics Inc. Thin-film transistor and method of making same
KR100338008B1 (en) * 1997-11-20 2002-10-25 삼성전자 주식회사 Molybdenum nitride-metal alloy film and fabricating method thereof, lcd wires and fabricating method thereof, lcd and fabricating method thereof
KR100276442B1 (en) * 1998-02-20 2000-12-15 구본준 Liquid crystal display device and its fabrication method
JPH11258632A (en) * 1998-03-13 1999-09-24 Toshiba Corp Array substrate for display device
JPH11258633A (en) * 1998-03-13 1999-09-24 Toshiba Corp Production of array substrate for display device
JP4458563B2 (en) * 1998-03-31 2010-04-28 三菱電機株式会社 Thin film transistor manufacturing method and liquid crystal display device manufacturing method using the same
KR100482167B1 (en) * 1998-07-30 2005-07-18 엘지.필립스 엘시디 주식회사 LCD and its manufacturing method
US6297519B1 (en) * 1998-08-28 2001-10-02 Fujitsu Limited TFT substrate with low contact resistance and damage resistant terminals
USRE39452E1 (en) * 1998-08-28 2007-01-02 Fujitsu Limited TFT substrate with low contact resistance and damage resistant terminals
KR100303446B1 (en) * 1998-10-29 2002-10-04 삼성전자 주식회사 Manufacturing method of thin film transistor substrate for liquid crystal display device
US6368978B1 (en) * 1999-03-04 2002-04-09 Applied Materials, Inc. Hydrogen-free method of plasma etching indium tin oxide
KR100333983B1 (en) * 1999-05-13 2002-04-26 윤종용 thin film transistor array panel for liquid crystal display having wide viewing angle and manufacturing method thereof
TW428328B (en) * 1999-07-30 2001-04-01 Hannstar Display Corp Fabricating method of thin film transistor
JP2001053283A (en) * 1999-08-12 2001-02-23 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
GB9919913D0 (en) * 1999-08-24 1999-10-27 Koninkl Philips Electronics Nv Thin-film transistors and method for producing the same
KR100632216B1 (en) * 1999-12-16 2006-10-09 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystal display device and manufacturing method thereof
KR100325079B1 (en) * 1999-12-22 2002-03-02 주식회사 현대 디스플레이 테크놀로지 Method of manufacturing lcd having high aperture ratio and high transmittance
KR100601177B1 (en) * 2000-02-10 2006-07-13 삼성전자주식회사 Thin film transistor panels for liquid crystal display and method manufacturing the same
US7023021B2 (en) 2000-02-22 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4118484B2 (en) 2000-03-06 2008-07-16 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP2001257350A (en) 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd Semiconductor device and its preparation method
JP4700160B2 (en) 2000-03-13 2011-06-15 株式会社半導体エネルギー研究所 Semiconductor device
JP4118485B2 (en) * 2000-03-13 2008-07-16 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4683688B2 (en) 2000-03-16 2011-05-18 株式会社半導体エネルギー研究所 Method for manufacturing liquid crystal display device
JP4393662B2 (en) 2000-03-17 2010-01-06 株式会社半導体エネルギー研究所 Method for manufacturing liquid crystal display device
JP2001281698A (en) * 2000-03-30 2001-10-10 Advanced Display Inc Production method for optoelectronic element
US6789910B2 (en) 2000-04-12 2004-09-14 Semiconductor Energy Laboratory, Co., Ltd. Illumination apparatus
TW447138B (en) * 2000-04-28 2001-07-21 Unipac Optoelectronics Corp Manufacturing method of thin-film transistor
JP2001343659A (en) * 2000-06-02 2001-12-14 Casio Comput Co Ltd Active matrix type liquid crystal display panel and method of manufacture
US6900084B1 (en) 2000-05-09 2005-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a display device
US6798064B1 (en) * 2000-07-12 2004-09-28 Motorola, Inc. Electronic component and method of manufacture
TWI253538B (en) * 2000-09-30 2006-04-21 Au Optronics Corp Thin film transistor flat display and its manufacturing method
KR100400765B1 (en) * 2000-11-13 2003-10-08 엘지.필립스 엘시디 주식회사 Method for forming thin-film and liquid crystal display device fabricated by the same method
TW525216B (en) 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
KR100715943B1 (en) * 2001-01-29 2007-05-08 삼성전자주식회사 Liquid crystal display device and method for manufacturing the same
JP4410951B2 (en) * 2001-02-27 2010-02-10 Ｎｅｃ液晶テクノロジー株式会社 Pattern forming method and manufacturing method of liquid crystal display device
SG179310A1 (en) 2001-02-28 2012-04-27 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US7071037B2 (en) 2001-03-06 2006-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR100796749B1 (en) 2001-05-16 2008-01-22 삼성전자주식회사 A thin film transistor array substrate for a liquid crystal display
JP4920140B2 (en) * 2001-05-18 2012-04-18 ゲットナー・ファンデーション・エルエルシー Liquid crystal display device and manufacturing method thereof
JP2003172946A (en) * 2001-09-28 2003-06-20 Fujitsu Display Technologies Corp Substrate for liquid crystal display device and liquid crystal display device using the substrate
JP4723787B2 (en) * 2002-07-09 2011-07-13 シャープ株式会社 FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE
KR100484092B1 (en) 2002-12-26 2005-04-18 엘지.필립스 엘시디 주식회사 Dual Panel Type Electroluminescent Device and Method for Fabricating the same
KR100497095B1 (en) 2002-12-26 2005-06-28 엘지.필립스 엘시디 주식회사 Array substrate for dual panel type electroluminescent device and method for fabricating the same
KR100503129B1 (en) * 2002-12-28 2005-07-22 엘지.필립스 엘시디 주식회사 Dual Panel Type Electroluminescent Device and Method for Fabricating the same
KR100500147B1 (en) 2002-12-31 2005-07-07 엘지.필립스 엘시디 주식회사 The organic electro-luminescence device and method for fabricating of the same
US7250720B2 (en) 2003-04-25 2007-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device
TW589663B (en) * 2003-05-12 2004-06-01 Au Optronics Corp Flat panel display and manufacturing method thereof
JP4517063B2 (en) * 2003-05-27 2010-08-04 日本電気株式会社 Liquid crystal display
KR100566612B1 (en) * 2003-09-23 2006-03-31 엘지.필립스 엘시디 주식회사 Poly Silicon Thin Film Transistor and the fabrication method thereof
JP3769564B2 (en) * 2003-10-06 2006-04-26 セイコーエプソン株式会社 Liquid crystal panel substrate, liquid crystal panel using the same, and projection display device
KR101023978B1 (en) * 2004-03-18 2011-03-28 삼성전자주식회사 Method of making semi-transmission lcd and semi-transmission lcd thereof
KR101087398B1 (en) 2004-06-30 2011-11-25 엘지디스플레이 주식회사 pad structure of liquid crystal display device and fabrication method thereof
KR101061850B1 (en) * 2004-09-08 2011-09-02 삼성전자주식회사 Thin film transistor array panel and manufacturing method thereof
JP2006178426A (en) * 2004-11-24 2006-07-06 Sanyo Electric Co Ltd Display device and method for manufacturing the same
US7049163B1 (en) * 2005-03-16 2006-05-23 Chunghwa Picture Tubes, Ltd. Manufacture method of pixel structure
KR20060125066A (en) * 2005-06-01 2006-12-06 삼성전자주식회사 Array substrate having enhanced aperture ratio, method of manufacturing the same
KR20070009013A (en) * 2005-07-14 2007-01-18 삼성전자주식회사 Flat panel display and method of making flat panel display
US7601566B2 (en) * 2005-10-18 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2007114360A (en) 2005-10-19 2007-05-10 Nec Lcd Technologies Ltd Liquid crystal display provided with thin film transistor and its manufacturing method
JP4544532B2 (en) * 2006-03-03 2010-09-15 東京エレクトロン株式会社 Substrate processing method
JP4842709B2 (en) * 2006-05-31 2011-12-21 株式会社 日立ディスプレイズ Manufacturing method of display device
US7749907B2 (en) * 2006-08-25 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7932183B2 (en) * 2006-11-14 2011-04-26 Mitsubishi Electric Corporation Method of manufacturing multilayer thin film pattern and display device
KR20080078164A (en) * 2007-02-22 2008-08-27 삼성전자주식회사 Manufacturing method of liquid crystal display
US8110829B2 (en) * 2007-05-31 2012-02-07 Lg Display Co., Ltd. Array substrate of liquid crystal display and method for fabricating the same
US20090001373A1 (en) * 2007-06-26 2009-01-01 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel Ltd.) Electrode of aluminum-alloy film with low contact resistance, method for production thereof, and display unit
JP5250832B2 (en) * 2007-07-09 2013-07-31 ゴールドチャームリミテッド Active matrix drive display device
KR101308534B1 (en) * 2007-07-18 2013-09-23 삼성디스플레이 주식회사 Display substrate and method for manufacturing the same
TWI348765B (en) * 2007-08-29 2011-09-11 Au Optronics Corp Pixel structure and fabricating method for thereof
JP5427390B2 (en) 2007-10-23 2014-02-26 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP5380037B2 (en) 2007-10-23 2014-01-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
KR101448903B1 (en) * 2007-10-23 2014-10-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing semiconductor device
JP5357493B2 (en) * 2007-10-23 2013-12-04 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
KR101446249B1 (en) 2007-12-03 2014-10-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
EP2232561A4 (en) * 2007-12-03 2015-05-06 Semiconductor Energy Lab Manufacturing method of thin film transistor and manufacturing method of display device
CN101217153B (en) * 2008-01-18 2012-02-29 友达光电股份有限公司 An active member array structure and the corresponding manufacturing method
US8035107B2 (en) * 2008-02-26 2011-10-11 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device
CN101939694B (en) 2008-02-27 2014-01-29 株式会社半导体能源研究所 Liquid crystal display device and manufacturing method thereof, and electronic device
US8101442B2 (en) * 2008-03-05 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing EL display device
US7749820B2 (en) * 2008-03-07 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, manufacturing method thereof, display device, and manufacturing method thereof
US7989275B2 (en) * 2008-03-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, manufacturing method thereof, display device, and manufacturing method thereof
US7883943B2 (en) 2008-03-11 2011-02-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor and method for manufacturing display device
US7985605B2 (en) * 2008-04-17 2011-07-26 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and manufacturing method thereof
US9041202B2 (en) 2008-05-16 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US7790483B2 (en) * 2008-06-17 2010-09-07 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and manufacturing method thereof, and display device and manufacturing method thereof
US20100138765A1 (en) * 2008-11-30 2010-06-03 Nokia Corporation Indicator Pop-Up
US8207026B2 (en) * 2009-01-28 2012-06-26 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of thin film transistor and manufacturing method of display device
JP5503995B2 (en) * 2009-02-13 2014-05-28 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7989234B2 (en) 2009-02-16 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor and method for manufacturing display device
US8202769B2 (en) * 2009-03-11 2012-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP5539765B2 (en) * 2009-03-26 2014-07-02 株式会社半導体エネルギー研究所 Method for manufacturing transistor
CN102576739B (en) * 2009-11-27 2014-10-29 夏普株式会社 Thin film transistor and manufacturing method for same, semiconductor device and manufacturing method for same, and display device
TWM423257U (en) * 2011-06-01 2012-02-21 Chunghwa Picture Tubes Ltd Pixel array substrate and display panel
CN102637632B (en) * 2011-06-10 2014-12-10 京东方科技集团股份有限公司 Thin-film transistor array and method for manufacturing same
JP5411236B2 (en) * 2011-11-15 2014-02-12 ゲットナー・ファンデーション・エルエルシー Liquid crystal display device and manufacturing method thereof
KR101932495B1 (en) * 2012-05-11 2018-12-27 삼성전자주식회사 Semiconductor package and method of manufacturing the semiconductor package
CN102956551B (en) * 2012-11-02 2015-01-07 京东方科技集团股份有限公司 Fabrication method of array substrate, array substrate and display device
CN103928453B (en) * 2013-01-11 2016-09-28 北京京东方光电科技有限公司 A kind of array base palte and manufacture method thereof
TWI582967B (en) * 2014-04-01 2017-05-11 鴻海精密工業股份有限公司 Display array substrate and manufacturing method thereof
CN103972243B (en) * 2014-04-24 2017-03-29 京东方科技集团股份有限公司 A kind of array base palte and preparation method thereof, display device
CN104375344B (en) * 2014-11-21 2017-09-15 深圳市华星光电技术有限公司 Liquid crystal display panel and its color membrane array substrate
CN106057667B (en) * 2016-07-06 2019-02-05 京东方科技集团股份有限公司 The production method of film pattern, the production method of substrate and substrate, display device
CN107706196B (en) * 2017-09-28 2021-05-25 京东方科技集团股份有限公司 Array substrate, preparation method thereof and display device
KR20210053373A (en) * 2019-11-01 2021-05-12 삼성디스플레이 주식회사 Method of manufacturing photo sensor
KR20210101353A (en) 2020-02-07 2021-08-19 삼성디스플레이 주식회사 Method for fabricating the conductive pattern and display device and method of fabricating the same
CN111584520B (en) * 2020-05-25 2023-09-12 成都京东方显示科技有限公司 Array substrate, display panel and manufacturing method of array substrate

Citations (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5863150A (en) 1981-10-12 1983-04-14 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPS6144468A (en) 1984-08-09 1986-03-04 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPS61193128A (en) 1985-02-21 1986-08-27 Mitsubishi Electric Corp Matrix type display device
US4778560A (en) * 1986-06-03 1988-10-18 Matsushita Electric Industrial Co., Ltd. Method for production of thin film transistor array substrates
EP0301571A2 (en) * 1987-07-30 1989-02-01 Sharp Kabushiki Kaisha Thin film transistor array
JPS6484668A (en) 1987-09-26 1989-03-29 Casio Computer Co Ltd Thin film transistor
EP0312389A2 (en) * 1987-10-15 1989-04-19 Sharp Kabushiki Kaisha A liquid-crystal panel
JPH01151236A (en) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp Taper-etching of aluminum film
US5032531A (en) * 1988-07-08 1991-07-16 Hitachi, Ltd. Method of manufacturing active matrix panel
US5054887A (en) * 1988-08-10 1991-10-08 Sharp Kabushiki Kaisha Active matrix type liquid crystal display
JPH03274029A (en) 1990-03-23 1991-12-05 Sanyo Electric Co Ltd Thin film transistor array of active matrix type display device and production thereof
US5075244A (en) * 1989-11-16 1991-12-24 Fuji Xerox Co., Ltd. Method of manufacturing image sensors
JPH0420930A (en) 1990-05-16 1992-01-24 Nippon Telegr & Teleph Corp <Ntt> Wiring structure
JPH04155315A (en) 1990-10-19 1992-05-28 Hitachi Ltd Manufacture of multi-layer film wiring body
JPH04213427A (en) 1990-12-11 1992-08-04 Fujitsu Ltd Production of electrode wiring of multiplayered metal film
US5153754A (en) 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
US5156986A (en) * 1990-10-05 1992-10-20 General Electric Company Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
US5162933A (en) * 1990-05-16 1992-11-10 Nippon Telegraph And Telephone Corporation Active matrix structure for liquid crystal display elements wherein each of the gate/data lines includes at least a molybdenum-base alloy layer containing 0.5 to 10 wt. % of chromium
JPH04326330A (en) 1991-04-26 1992-11-16 Sharp Corp Liquid crystal display device and its manufacture
JPH04335617A (en) 1991-05-13 1992-11-24 Sharp Corp Active matrix substrate
JPH05142570A (en) 1991-11-20 1993-06-11 Sharp Corp Active matrix substrate
JPH05165059A (en) 1991-12-13 1993-06-29 Casio Comput Co Ltd Manufacture of thin film transistor
JPH05165056A (en) 1991-12-17 1993-06-29 Oki Electric Ind Co Ltd Manufacture of lower base board for active matrix type liquid crystal display
JPH05218025A (en) * 1992-02-05 1993-08-27 Fujitsu Ltd Method of manufacturing semiconductor device
JPH05299655A (en) * 1992-04-08 1993-11-12 Nec Corp Thin film transistor
JPH05323373A (en) 1992-05-22 1993-12-07 Fujitsu Ltd Production of thin film transistor panel
JPH063698A (en) * 1992-06-19 1994-01-14 Nec Corp Thin film transistor device
JPH06138487A (en) 1992-10-29 1994-05-20 Hitachi Ltd Semiconductor device and liquid crystal display device
JPH06140296A (en) 1992-10-26 1994-05-20 Fujitsu Ltd Pattern forming method
JPH06160906A (en) * 1993-08-12 1994-06-07 Toshiba Corp Active matrix type display device
JPH06188419A (en) * 1992-12-16 1994-07-08 Matsushita Electric Ind Co Ltd Manufacture of thin-film transistor
JPH06202153A (en) 1992-12-28 1994-07-22 Fujitsu Ltd Thin-film transistor matrix device and its production
US5334859A (en) 1991-09-05 1994-08-02 Casio Computer Co., Ltd. Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film
JPH06214255A (en) 1993-01-18 1994-08-05 Hitachi Ltd Wiring material and liquid crystal display device and production of liquid crystal display device
JPH06232398A (en) * 1992-12-15 1994-08-19 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor and manufacture of semiconductor device
JPH06265936A (en) * 1993-03-12 1994-09-22 Rohm Co Ltd Liquid crystal display device
US5374837A (en) * 1991-11-25 1994-12-20 Matsushita Electric Industrial Co., Ltd. Thin film transistor array substrate acting as an active matrix substrate
US5397719A (en) 1992-07-22 1995-03-14 Samsung Electronics Co., Ltd. Method for manufacturing a display panel
JPH07263700A (en) 1994-03-17 1995-10-13 Fujitsu Ltd Manufacture of thin film transistor
US5462886A (en) * 1992-11-27 1995-10-31 Fuji Xerox Co., Ltd. Method of manufacturing a semiconductor element
US5621556A (en) 1994-04-28 1997-04-15 Xerox Corporation Method of manufacturing active matrix LCD using five masks
US5726077A (en) * 1994-06-03 1998-03-10 Frontec Incorporated Method of producing an electro-optical device
US5738948A (en) 1994-09-29 1998-04-14 Kabushiki Kaisha Toshiba Electrode-wiring material and electrode-wiring substrate using the same
US5811318A (en) * 1995-12-28 1998-09-22 Samsung Electronics Co., Ltd. Method for manufacturing a liquid crystal display
US5811835A (en) * 1995-08-23 1998-09-22 Kabushiki Kaisha Toshiba Thin-film transistor with edge inclined gates and liquid crystal display device furnished with the same
US6368227B1 (en) * 2000-11-17 2002-04-09 Steven Olson Method of swinging on a swing

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6149988A (en) * 1986-09-26 2000-11-21 Semiconductor Energy Laboratory Co., Ltd. Method and system of laser processing
GB2211362A (en) * 1987-10-15 1989-06-28 Johnson Electric Ind Mfg Fuel pump motor
JPH04234930A (en) * 1991-01-10 1992-08-24 Shimano Inc Reel for fishing
US5468987A (en) * 1991-03-06 1995-11-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
TW223178B (en) * 1992-03-27 1994-05-01 Semiconductor Energy Res Co Ltd Semiconductor device and its production method
JPH06160905A (en) * 1992-11-26 1994-06-07 Sanyo Electric Co Ltd Liquid crystal display device and its production
JP3573778B2 (en) * 1993-03-12 2004-10-06 株式会社東芝 Liquid crystal display
US5663077A (en) * 1993-07-27 1997-09-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films
JP4366732B2 (en) * 1998-09-30 2009-11-18 ソニー株式会社 Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5863150A (en) 1981-10-12 1983-04-14 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPS6144468A (en) 1984-08-09 1986-03-04 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPS61193128A (en) 1985-02-21 1986-08-27 Mitsubishi Electric Corp Matrix type display device
US4778560A (en) * 1986-06-03 1988-10-18 Matsushita Electric Industrial Co., Ltd. Method for production of thin film transistor array substrates
EP0301571A2 (en) * 1987-07-30 1989-02-01 Sharp Kabushiki Kaisha Thin film transistor array
JPS6484668A (en) 1987-09-26 1989-03-29 Casio Computer Co Ltd Thin film transistor
EP0312389A2 (en) * 1987-10-15 1989-04-19 Sharp Kabushiki Kaisha A liquid-crystal panel
JPH01151236A (en) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp Taper-etching of aluminum film
US5032531A (en) * 1988-07-08 1991-07-16 Hitachi, Ltd. Method of manufacturing active matrix panel
US5054887A (en) * 1988-08-10 1991-10-08 Sharp Kabushiki Kaisha Active matrix type liquid crystal display
US5153754A (en) 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
US5075244A (en) * 1989-11-16 1991-12-24 Fuji Xerox Co., Ltd. Method of manufacturing image sensors
JPH03274029A (en) 1990-03-23 1991-12-05 Sanyo Electric Co Ltd Thin film transistor array of active matrix type display device and production thereof
JPH0420930A (en) 1990-05-16 1992-01-24 Nippon Telegr & Teleph Corp <Ntt> Wiring structure
US5162933A (en) * 1990-05-16 1992-11-10 Nippon Telegraph And Telephone Corporation Active matrix structure for liquid crystal display elements wherein each of the gate/data lines includes at least a molybdenum-base alloy layer containing 0.5 to 10 wt. % of chromium
US5156986A (en) * 1990-10-05 1992-10-20 General Electric Company Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
JPH04155315A (en) 1990-10-19 1992-05-28 Hitachi Ltd Manufacture of multi-layer film wiring body
JPH04213427A (en) 1990-12-11 1992-08-04 Fujitsu Ltd Production of electrode wiring of multiplayered metal film
JPH04326330A (en) 1991-04-26 1992-11-16 Sharp Corp Liquid crystal display device and its manufacture
JPH04335617A (en) 1991-05-13 1992-11-24 Sharp Corp Active matrix substrate
US5334859A (en) 1991-09-05 1994-08-02 Casio Computer Co., Ltd. Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film
JPH05142570A (en) 1991-11-20 1993-06-11 Sharp Corp Active matrix substrate
US5374837A (en) * 1991-11-25 1994-12-20 Matsushita Electric Industrial Co., Ltd. Thin film transistor array substrate acting as an active matrix substrate
JPH05165059A (en) 1991-12-13 1993-06-29 Casio Comput Co Ltd Manufacture of thin film transistor
JPH05165056A (en) 1991-12-17 1993-06-29 Oki Electric Ind Co Ltd Manufacture of lower base board for active matrix type liquid crystal display
JPH05218025A (en) * 1992-02-05 1993-08-27 Fujitsu Ltd Method of manufacturing semiconductor device
JPH05299655A (en) * 1992-04-08 1993-11-12 Nec Corp Thin film transistor
JPH05323373A (en) 1992-05-22 1993-12-07 Fujitsu Ltd Production of thin film transistor panel
JPH063698A (en) * 1992-06-19 1994-01-14 Nec Corp Thin film transistor device
US5397719A (en) 1992-07-22 1995-03-14 Samsung Electronics Co., Ltd. Method for manufacturing a display panel
JPH06140296A (en) 1992-10-26 1994-05-20 Fujitsu Ltd Pattern forming method
JPH06138487A (en) 1992-10-29 1994-05-20 Hitachi Ltd Semiconductor device and liquid crystal display device
US5462886A (en) * 1992-11-27 1995-10-31 Fuji Xerox Co., Ltd. Method of manufacturing a semiconductor element
JPH06232398A (en) * 1992-12-15 1994-08-19 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor and manufacture of semiconductor device
JPH06188419A (en) * 1992-12-16 1994-07-08 Matsushita Electric Ind Co Ltd Manufacture of thin-film transistor
US5483082A (en) * 1992-12-28 1996-01-09 Fujitsu Limited Thin film transistor matrix device
JPH06202153A (en) 1992-12-28 1994-07-22 Fujitsu Ltd Thin-film transistor matrix device and its production
JPH06214255A (en) 1993-01-18 1994-08-05 Hitachi Ltd Wiring material and liquid crystal display device and production of liquid crystal display device
JPH06265936A (en) * 1993-03-12 1994-09-22 Rohm Co Ltd Liquid crystal display device
JPH06160906A (en) * 1993-08-12 1994-06-07 Toshiba Corp Active matrix type display device
JPH07263700A (en) 1994-03-17 1995-10-13 Fujitsu Ltd Manufacture of thin film transistor
US5621556A (en) 1994-04-28 1997-04-15 Xerox Corporation Method of manufacturing active matrix LCD using five masks
US5726077A (en) * 1994-06-03 1998-03-10 Frontec Incorporated Method of producing an electro-optical device
US5738948A (en) 1994-09-29 1998-04-14 Kabushiki Kaisha Toshiba Electrode-wiring material and electrode-wiring substrate using the same
US5811835A (en) * 1995-08-23 1998-09-22 Kabushiki Kaisha Toshiba Thin-film transistor with edge inclined gates and liquid crystal display device furnished with the same
US5811318A (en) * 1995-12-28 1998-09-22 Samsung Electronics Co., Ltd. Method for manufacturing a liquid crystal display
US6368227B1 (en) * 2000-11-17 2002-04-09 Steven Olson Method of swinging on a swing

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
K. Fuji "Japanese Hournal of Applied Physics" vol. 31 1992 Pt. 1, No. 12B pp. 4574-4578. *
Patent Abstracts of Japan, vol. 11, No. 19 (P-537) & JP 61 193128 A (Mitsubishi) abstract. *
Patent Abstracts of Japan, vol. 18, No. 194 (P-1722) & JP 06 003698 A (NEC) abstract. *
Patent Abstracts of Japan, vol. 18, No. 381 (P-1797) & JP 06 160906 A (Sanyo) abstract. *
S. Wolf & R. Tauber, "Silicon Processing for the VLSI Era" vol. 1, pp. 534-535: 559-565: 452-453. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368076B2 (en) 1999-07-22 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US8624253B2 (en) 1999-07-22 2014-01-07 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US9048220B2 (en) 2010-06-21 2015-06-02 Joled Inc. Method of crystallizing silicon thin film and method of manufacturing silicon thin-film transistor device

Also Published As

Publication number Publication date
JP2004157554A (en) 2004-06-03
DE69635239T2 (en) 2006-07-06
US6661026B2 (en) 2003-12-09
JP2006106788A (en) 2006-04-20
EP0775931A3 (en) 1998-03-25
US6008065A (en) 1999-12-28
DE69635239D1 (en) 2005-11-10
TW426809B (en) 2001-03-21
JP2006148150A (en) 2006-06-08
EP0775931A2 (en) 1997-05-28
JP2004006936A (en) 2004-01-08
US6331443B1 (en) 2001-12-18
JP3891617B2 (en) 2007-03-14
JPH09171197A (en) 1997-06-30
US6339230B1 (en) 2002-01-15
EP0775931B1 (en) 2005-10-05
EP1338914A3 (en) 2003-11-19
US20020106825A1 (en) 2002-08-08
EP1338914A2 (en) 2003-08-27

Similar Documents

Publication Publication Date Title
USRE41363E1 (en) Thin film transistor substrate
USRE39211E1 (en) Method for manufacturing a liquid crystal display
US6081308A (en) Method for manufacturing liquid crystal display
JP4169896B2 (en) Thin film transistor and manufacturing method thereof
US6927105B2 (en) Thin film transistor array substrate and manufacturing method thereof
US7095459B2 (en) Array substrate for liquid crystal display and method for fabricating the same
JP4272272B2 (en) Wiring composition, metal wiring using the composition and manufacturing method thereof, display device using the wiring and manufacturing method thereof
US6859252B2 (en) Active matrix substrate and manufacturing method thereof
US20050024549A1 (en) Method for manufacturing thin film transistor array
JP2004163969A (en) Method for manufacturing liquid crystal display device
US6872603B2 (en) Method for forming interconnections including multi-layer metal film stack for improving corrosion and heat resistances
US8093595B2 (en) Thin film array panel and manufacturing method thereof
US6376288B1 (en) Method of forming thin film transistors for use in a liquid crystal display
US5999235A (en) Liquid crystal displaying apparatus and method of manufacturing TFT array
JPH0964364A (en) Manufacture of semiconductor device
KR100238206B1 (en) Thin-film transistor liquid crystal display device and its manufacturing method
KR100219480B1 (en) Thin film transistor liquid crystal display device and its manufacturing method
KR100451849B1 (en) manufacturing method of an array panel of liquid crystal display
KR0183757B1 (en) Method of manufacturing thin-film transistor liquid crystal display device
JPH0766422A (en) Array substrate for liquid crystal display device
JPH09232585A (en) Electronic device with anodic oxide film, and etching of anodic oxide film
KR100265053B1 (en) Display panel and manufacturing method thereof
KR19990009763A (en) Thin film transistor substrate having a single film gate line and manufacturing method thereof
JPH06265933A (en) Liquid crystal display device and its production
JPH06110085A (en) Active matrix panel and its manufacture

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRONICS CO., LTD.;REEL/FRAME:029019/0139

Effective date: 20120904

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., CHINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG DISPLAY CO., LTD.;REEL/FRAME:060778/0432

Effective date: 20220602