USRE41205E1 - Method of fabricating a semiconductor device - Google Patents

Method of fabricating a semiconductor device Download PDF

Info

Publication number
USRE41205E1
USRE41205E1 US10/952,576 US95257604A USRE41205E US RE41205 E1 USRE41205 E1 US RE41205E1 US 95257604 A US95257604 A US 95257604A US RE41205 E USRE41205 E US RE41205E
Authority
US
United States
Prior art keywords
insulating
layer
forming
gate
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/952,576
Inventor
Jae-Yeong Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to US10/952,576 priority Critical patent/USRE41205E1/en
Application granted granted Critical
Publication of USRE41205E1 publication Critical patent/USRE41205E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present invention relates to a method of fabricating a semiconductor device which reduces leakage current by controlling an etch of a field oxide layer when a contact hole is formed.
  • a technique of forming a borderless contact has been developed to reduce leakage current by forming the contact hole to be overlapped with a field oxide layer, which provides an easy process and prevents the etch of the field oxide layer.
  • FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art.
  • a field oxide layer 13 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 11 by shallow trench isolation (hereinafter abbreviated STI).
  • the field oxide layer 13 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 11 , by forming trenches 12 which are slant to a predetermined degree by carrying out an anisotropic etch such as reaction ion etching(hereinafter abbreviated RIE) and the like on the exposed parts of the semiconductor substrate 11 , by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.
  • RIE reaction ion etching
  • a gate oxide layer 15 has been formed on the active area of the semiconductor substrate 11 .
  • polysilicon doped with impurities is deposited on the gate insulating layer 15 by chemical vapor deposition(hereinafter abbreviated CVD).
  • CVD chemical vapor deposition
  • a gate 17 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 11 by photolithography including anisotropic etches such as RME and the like.
  • Lightly doped regions 19 for LDD(lightly doped drain) regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 11 with n typed impurities in use of the gate 17 as a mask.
  • a sidewall spacer 21 is formed at the sides of the gate 17 .
  • the sidewall spacer 21 is formed by deposing silicon oxide on the semiconductor substrate 11 to cover the field oxide layer 13 and gate 17 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 11 exposed by RIE.
  • Heavily doped regions 23 for a source and a drain region are formed by implanting with n typed impurity ions heavily into the exposed portions of the semiconductor substrate 11 in use of the gate 17 and sidewall spacer 21 as a mask.
  • a first insulating interlayer layer 25 is formed by depositing silicon nitride on the semiconductor substrate 11 by CVD to cover the field oxide layer 13 , gate 17 , and sidewall spacer spacers 21 by CVD.
  • a A second insulating interlayer layer 27 is formed by depositing silicon oxide or BPSG (boro phospho silicate glass) on the first insulating interlayer layer 25 to a substantial thickness by CVD or by coating SOG ( spin on glass ) the first insulating interlayer layer 25 with SOG(spin on glass) .
  • a first and aFirst and second contact holeholes 29 and 31 respectively exposing the gate 17 and heavily doped regions 23 respectively are formed by patterning the second and first insulating interlayerslayers 27 and 25 by photolithography including anisotropic etchetching such as RIE and the like.
  • the first and second contact holes 29 and 31 are formed by sufficiently etching, that is overetching the second insulating interlayerlayer 27 sufficiently, which means that the second insulating interlayerlayer 27 is overetched to expose portions of the first insulating interlayerlayer 25 correspondingwhich correspond to the heavily doped regions 23 , and then by etching the first insulating interlayerlayer 25 .
  • the first insulating interlayerlayer 25 serves as an etch stop layer and prevents the field oxide layer 13 from being etched in spite ofeven when sufficiently etching the second insulating interlayerlayer 27 sufficiently .
  • an electrically-conductive substance such as polysilicon, Al aluminum, and the like is deposited on the second insulating interlayer layer 27 and through the first and second contact holes 29 to 31 to be contacted brought into contact with the gate 17 and heavily of doped regions 23 through the first and second contact holes 29 and 31 .
  • a first and a first and second plug plugs 33 and 35 are formed in the first and second contact holes 29 and 31 , respectively, by removing the electrically-conductive substance through chemical mechanical polishing ( CMP ) to expose the surface of the second insulating interlayer layer 27 by chemical-mechanical polishing(hereinafter abbreviated CMP) .
  • CMP chemical mechanical polishing
  • TheIn the above-mentioned method offor fabricating a semiconductor device preventsaccording to the conventional art, in order to define the first and second contact holes which expose the gate and heavily doped regions, the second layer is over- etched to expose portions of the first insulating layer which correspond to the heavily doped regions, and then the first insulation layer dielectric is etched, whereby the field oxide layer is prevented from being etchedby overetching the second insulating interlayer to expose portions of the first insulating interlayer corresponding to the heavily doped regions for forming the first and second contact holes exposing the gate and heavily doped regions and by etching the first insulating interlayer successively .
  • the method offor fabricating a semiconductor device of the related art causessuffers from defects in that a leakage current is likely to be generated due to thea difference in heat expansion coefficient between the semiconductor substrate and the first insulating interlayerlayer made of silicon nitride as well as due to stress caused by lattice mismatch.
  • the present invention is directed to a method of fabricating a semiconductor device that substantially obviates one or more of the proulenis due to limitations and disadvantages of the related art.
  • TheAn object of the present invention is to provide a method offor fabricating a semiconductor device which prevents the leakage current occurrence by avoiding the stress generation due to the contact between thea semiconductor substrate and insulating interlayeran insulation layer, so that a leakage current is not generated.
  • the present invention includesthe above object, according to one aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a field oxide layer definingwhich defines an active area and a field area, on a semiconductor substrate of a first conductive type, forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor substrate in use ofusing the gate as a mask, forming a first insulating interlayerlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate, to cover the field oxide layer and the gate, forming a second insulating interlayerlayer on the first insulating interlayerlayer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer
  • the present invention includesaccording to another aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a field oxide layer definingwhich defines an active area and a field area, on a semiconductor substrate of a first conductive type, forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate, forming a sidewall spacer at a side of the gate, forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate, forming a sidewall spacer at a side of the gate, forming heavily doped regions of the second conductive type in the semiconductor substrate in use ofusing the gate as a mask whereinso that the heavily doped regions are substantially overlapped with the lightly doped regions, forming a first insulating interlayerlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate, to cover the field oxide layer and the gate,
  • FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art
  • FIG. 2A to FIG. 2D show cross-sectional views of fabricating a semiconductor device according to the present invention.
  • FIG. 2A to FIG. 2D show cross-sectional views of fabricating a semiconductor device according to the present invention.
  • a field oxide layer 43 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 41 by shallow trench isolation (hereinafter abbreviated STI).
  • the field oxide layer 43 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 41 , by forming trenches 42 which are slant to a predetermined degree by carrying out an anisotropic etch such as RIE and the like on the exposed parts of the semiconductor substrate 41 , by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.
  • the field oxide layer 41 may be formed by local oxidation of silicon(LOCOS).
  • a gate oxide layer 45 has been formed on the active area of the semiconductor substrate 41 .
  • polysilicon doped with impurities is deposited on the gate insulating layer 45 by CVD.
  • a gate 47 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 41 by photolithography including anisotropic etches such as RIE and the like.
  • Lightly doped regions 49 for LDD regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 41 with n typed impurities such as P, As, etc, in use of the gate 17 as a mask.
  • a sidewall spacer 51 is formed at the sides of the gate 47 .
  • the sidewall spacer 51 is formed by deposing silicon oxide on the semiconductor substrate 41 to cover the field oxide layer 43 and gate 47 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 41 exposed by RIE.
  • Heavily doped regions 53 for a source and a drain region are formed by implanting with n typed impurity ions such as P, As, etc, heavily into the exposed portions of the semiconductor substrate 41 in use of the gate 47 and sidewall spacer 51 as a mask.
  • a first insulating interlayer layer 55 which has a thickness of 100 to 300 ⁇ thick is formed by depositing silicon oxide on the semiconductor substrate 41 by CVD to cover the field oxide layer 43 , gate 47 , and sidewall spacer 51 by CVD spacers 51 .
  • a heat expansion coefficient and lattice mismatch of silicon oxide for the first insulating layer 55 against the semiconductor substrate 41 are less than those of silicon nitride, thereby reducing a leakage current due to stress.
  • a second insulating interlayer layer 57 which has a thickness of 100 to 300 ⁇ thick is formed by depositing silicon nitride of which an etch rate is different from that of silicon oxide on the first insulating layer 55 by through CVD.
  • a third insulating interlayer layer 59 which has a thickness of 500 to 10000 ⁇ thick is formed by depositing silicon oxide or BPSG (boro phospho silicate glass) on the second insulating interlayer layer 57 by CVD or by coating SOG ( spin on glass ) on the second insulating layer 57 with SOG(spin on glass) .
  • silicon oxide or BPSG boro phospho silicate glass
  • SOG spin on glass
  • the surface of the third insulating interlayerlayer 59 becomes even, therespective portions of the third insulating interlayerlayer 59 corresponding to the gate 47 and the heavily doped regions 53 differ in thickness. Namely, the portion of the third insulating interlayerlayer 59 corresponding to the heavily doped regions 59 is thicker than the other portion of the third insulating layer 59 corresponding to the gate 47 . In this case,It is to be readily understood that the third insulating interlayerlayer 59 may be formed with at least doubleby one or more layers of the above-mentioned substances.
  • a first and a second contact holeFirst and second contact holes 61 and 63 respectively exposing the gate 47 and heavily doped regions 53 respectively are formed by successively patterning the third, second, and first insulating interlayerslayers 59 , 57 , and 55 successively bythrough photolithography including an anisotropic etchetching such as RIE and the like.
  • portions of the second insulating interlayer layer 57 corresponding to the heavily doped regions 53 are exposed by overetching over- etching the third insulating interlayer layer 59 with a gas of C2F6 or C4F 8 C 2 F 6 or C 4 F 8 which is mixed with O 2 O 2 .
  • the second insulating layer 57 of which an etch rate is different from that of the third insulating layer 59 is used as an etch-stop layer.
  • the first and second contact holes 61 and 63 are formed by etching the first insulating layer 55 to expose the semiconductor substrate 41 in use of using the gas of C2F6 or C4F 8 C 2 F 6 or C 4 F 8 which is mixed with O2. which has been used for O 2 as in the case of etching the third insulating interlayer layer 59 .
  • the field oxide layer 43 is prevented from being damagedbecause it is easy to control the etch-end point owing to the thin first insulating interlayer 55 .
  • an electrically-conductive substance such as polysilicon, Al aluminum, and the like is deposited on the third insulating interlayer layer 59 and through the first and second contact holes 61 and 63 by CVD to be contacted brought into contact with the gate 47 and heavily doped regions 53 through the first and second contact holes 61 and 63 .
  • a first and a second plug first and second plugs 65 and 67 are formed in the first and second contact holes 61 and 63 , respectively, by removing the electrically-conductive substance through CMP to expose the surface of the third insulating interlayer layer 59 by CMP .
  • a first insulating layer made of silicon oxide of which heat expansion coefficient and lattice mismatch are less than those of silicon nitride is formed on a semiconductor substrate, and a second insulating interlayerlayer made of silicon nitride used as an etch-stop layer and a third insulating interlayerlayer made of silicon oxide are formed on the first insulating interlayerlayer successively.
  • a first and a second contact hole a first and second holes exposing a gate and heavily doped regions are formed by patterning the third to first insulating interlayers layers by photolithography in order, wherein the third insulating interlayer are overetched layer is over- etched to expose a portion of the second insulating interlayer layer corresponding to the heavily doped regions.
  • the second insulating interlayer layer used as an etch-stop layer prevents the first insulating interlayer layer and field oxide layer from being etched.
  • the present invention prevents the a leakage current occurrence from being generated by avoiding the stress generation due to the contact between the semiconductor substrate and insulating interlayer layer.

Abstract

The present invention relates to a method of fabricating a semiconductor device which reducesThe leakage current by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming ain a semiconductor device is reduced. A field oxide layer defining an active area and a field areais formed on a semiconductor substrateof a first conductive type, forming a. A gate is formed on thean active area of the semiconductor substrate. by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductorare formed on the substrate in use ofusing the gate as a mask, forming a. A first insulating interlayerlayer is formed on the semiconductor substrate by depositing an insulator of whichhaving the heat expansion coefficient and lattice mismatch that are less than those of the semiconductor substrateto cover the field oxide layer and the gate, forming a. A second insulating interlayerlayer is formed on the first insulating interlayerlayer by depositing another insulator of whichhaving an etch rate that is different from that of the first insulating interlayer, forming alayer. A third insulating interlayerlayer is formed on the second insulating interlayerlayer by depositing yet another insulator of whichhaving an etch rate that is different from that of the second insulating interlayer, and forming a first contact holelayer. First and second contact holes exposing the gate and heavily doped regions respectivelyare formed by patterning the third to first insulating interlayer successively by photolithographylayers.

Description

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device which reduces leakage current by controlling an etch of a field oxide layer when a contact hole is formed.
2. Discussion of Related Art
As the integration of a semiconductor device increases, so the size of an unit transistor decreases. Thus, sizes of contact holes exposing impurity regions are reduced as well as the impurity regions for source and drain regions are decreased in size, causing difficulty in process. Besides, leakage current on the operation of the device is brought about by the etch of a field oxide layer due to misalignment in forming the contact holes.
Therefore, a technique of forming a borderless contact has been developed to reduce leakage current by forming the contact hole to be overlapped with a field oxide layer, which provides an easy process and prevents the etch of the field oxide layer.
FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art.
Referring to FIG. 1A, a field oxide layer 13 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 11 by shallow trench isolation (hereinafter abbreviated STI). In this case, the field oxide layer 13 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 11, by forming trenches 12 which are slant to a predetermined degree by carrying out an anisotropic etch such as reaction ion etching(hereinafter abbreviated RIE) and the like on the exposed parts of the semiconductor substrate 11, by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.
After a gate oxide layer 15 has been formed on the active area of the semiconductor substrate 11, polysilicon doped with impurities is deposited on the gate insulating layer 15 by chemical vapor deposition(hereinafter abbreviated CVD). Then, a gate 17 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 11 by photolithography including anisotropic etches such as RME and the like.
Lightly doped regions 19 for LDD(lightly doped drain) regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 11 with n typed impurities in use of the gate 17 as a mask.
Referring to FIG. 1B, a sidewall spacer 21 is formed at the sides of the gate 17. In this case, the sidewall spacer 21 is formed by deposing silicon oxide on the semiconductor substrate 11 to cover the field oxide layer 13 and gate 17 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 11 exposed by RIE.
Heavily doped regions 23 for a source and a drain region are formed by implanting with n typed impurity ions heavily into the exposed portions of the semiconductor substrate 11 in use of the gate 17 and sidewall spacer 21 as a mask.
Referring to FIG. 1C, a first insulating interlayer layer 25 is formed by depositing silicon nitride on the semiconductor substrate 11 by CVD to cover the field oxide layer 13, gate 17, and sidewall spacer spacers 21 by CVD. And, a A second insulating interlayer layer 27 is formed by depositing silicon oxide or BPSG (boro phospho silicate glass) on the first insulating interlayer layer 25 to a substantial thickness by CVD or by coating SOG (spin on glass) the first insulating interlayer layer 25 with SOG(spin on glass) .
A first and aFirst and second contact holeholes 29 and 31respectively exposing the gate 17and heavily doped regions 23respectively are formed by patterning the second and first insulating interlayerslayers 27 and 25 by photolithography including anisotropic etchetching such as RIE and the like. As the thickness of the second insulating interlayerlayer 27 is irregular due to thea height difference between the gate 17 and heavily doped regions 23, the first and second contact holes 29 and 31 are formed by sufficiently etching, that is overetching the second insulating interlayerlayer 27 sufficiently, which means that the second insulating interlayerlayer 27 is overetched to expose portions of the first insulating interlayerlayer 25correspondingwhich correspond to the heavily doped regions 23, and then by etching the first insulating interlayerlayer 25.
In this case, as theAt this time, since an etch rate of the first insulating interlayerlayer 25 is different from that of the second insulating interlayerlayer 27, the first insulating interlayerlayer 25serves as an etch stop layer and prevents the field oxide layer 13 from being etched in spite ofeven when sufficiently etching the second insulating interlayerlayer 27sufficiently .
Referring to FIG. 1D, an electrically-conductive substance such as polysilicon, Al aluminum, and the like is deposited on the second insulating interlayer layer 27 and through the first and second contact holes 29 to 31 to be contacted brought into contact with the gate 17 and heavily of doped regions 23 through the first and second contact holes 29 and 31 . Then, a first and a first and second plug plugs 33 and 35 are formed in the first and second contact holes 29 and 31, respectively, by removing the electrically-conductive substance through chemical mechanical polishing (CMP) to expose the surface of the second insulating interlayer layer 27by chemical-mechanical polishing(hereinafter abbreviated CMP) .
TheIn the above-mentioned method offor fabricating a semiconductor device preventsaccording to the conventional art, in order to define the first and second contact holes which expose the gate and heavily doped regions, the second layer is over-etched to expose portions of the first insulating layer which correspond to the heavily doped regions, and then the first insulation layer dielectric is etched, whereby the field oxide layer is prevented from being etchedby overetching the second insulating interlayer to expose portions of the first insulating interlayer corresponding to the heavily doped regions for forming the first and second contact holes exposing the gate and heavily doped regions and by etching the first insulating interlayer successively .
UnfortunatelyHowever, the method offor fabricating a semiconductor device of the related art causessuffers from defects in that a leakage current is likely to be generated due to thea difference in heat expansion coefficient between the semiconductor substrate and the first insulating interlayerlayer made of silicon nitride as well as due to stress caused by lattice mismatch.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a semiconductor device that substantially obviates one or more of the proulenis due to limitations and disadvantages of the related art.
TheAn object of the present invention is to provide a method offor fabricating a semiconductor device which prevents the leakage current occurrence by avoiding the stress generation due to the contact between thea semiconductor substrate and insulating interlayeran insulation layer, so that a leakage current is not generated.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
ToIn order to achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includesthe above object, according to one aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a field oxide layer definingwhich defines an active area and a field area, on a semiconductor substrate of a first conductive type, forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor substrate in use ofusing the gate as a mask, forming a first insulating interlayerlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate, to cover the field oxide layer and the gate, forming a second insulating interlayerlayer on the first insulating interlayerlayer by depositing another insulator of which an etch rate is different from that of the first insulating interlayerlayer, forming a third insulating interlayerlayer on the second insulating interlayerlayer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayerlayer, and forming a first contact holefirst and second contact holes respectively exposing the gate and heavily dopedimpurity regions respectively by successively patterning the third to first insulating interlayer successively bylayers through photolithography.
In another aspect, the present invention includesAccording to another aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a field oxide layer definingwhich defines an active area and a field area, on a semiconductor substrate of a first conductive type, forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate, forming a sidewall spacer at a side of the gate, forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate, forming a sidewall spacer at a side of the gate, forming heavily doped regions of the second conductive type in the semiconductor substrate in use ofusing the gate as a mask whereinso that the heavily doped regions are substantially overlapped with the lightly doped regions, forming a first insulating interlayerlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate, to cover the field oxide layer and the gate, forming a second insulating interlayerlayer on the first insulating interlayerlayer by depositing another insulator of which an etch rate is different from that of the first insulating interlayerlayer, forming a third insulating interlayerlayer on the second insulating interlayerlayer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayerlayer, forming a first contact holefirst and second contact holes respectively exposing the gate and heavily doped regions respectively by successively patterning the third to first insulating interlayer successively bylayer through photolithography, and forming first and second plugs in the first and second contact holes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the inventing and together with the description serve to explain the principle of the invention. In the drawings:
FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art; and
FIG. 2A to FIG. 2D show cross-sectional views of fabricating a semiconductor device according to the present invention.
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIG. 2A to FIG. 2D show cross-sectional views of fabricating a semiconductor device according to the present invention.
Referring to FIG. 2A, a field oxide layer 43 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 41 by shallow trench isolation (hereinafter abbreviated STI). In this case, the field oxide layer 43 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 41, by forming trenches 42 which are slant to a predetermined degree by carrying out an anisotropic etch such as RIE and the like on the exposed parts of the semiconductor substrate 41, by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers. Besides, the field oxide layer 41 may be formed by local oxidation of silicon(LOCOS).
After a gate oxide layer 45 has been formed on the active area of the semiconductor substrate 41, polysilicon doped with impurities is deposited on the gate insulating layer 45 by CVD. Then, a gate 47 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 41 by photolithography including anisotropic etches such as RIE and the like.
Lightly doped regions 49 for LDD regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 41 with n typed impurities such as P, As, etc, in use of the gate 17 as a mask.
Referring to FIG. 2B, a sidewall spacer 51 is formed at the sides of the gate 47. In this case, the sidewall spacer 51 is formed by deposing silicon oxide on the semiconductor substrate 41 to cover the field oxide layer 43 and gate 47 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 41 exposed by RIE.
Heavily doped regions 53 for a source and a drain region are formed by implanting with n typed impurity ions such as P, As, etc, heavily into the exposed portions of the semiconductor substrate 41 in use of the gate 47 and sidewall spacer 51 as a mask.
Referring to FIG. 2C, a first insulating interlayer layer 55 which has a thickness of 100 to 300 Å thick is formed by depositing silicon oxide on the semiconductor substrate 41 by CVD to cover the field oxide layer 43, gate 47, and sidewall spacer 51 by CVD spacers 51. In this case, a heat expansion coefficient and lattice mismatch of silicon oxide for the first insulating layer 55 against the semiconductor substrate 41 are less than those of silicon nitride, thereby reducing a leakage current due to stress.
And, a second insulating interlayer layer 57 which has a thickness of 100 to 300 Å thick is formed by depositing silicon nitride of which an etch rate is different from that of silicon oxide on the first insulating layer 55 by through CVD.
Then, a third insulating interlayer layer 59 which has a thickness of 500 to 10000 Å thick is formed by depositing silicon oxide or BPSG (boro phospho silicate glass) on the second insulating interlayer layer 57 by CVD or by coating SOG (spin on glass) on the second insulating layer57 with SOG(spin on glass) .
AsSince the surface of the third insulating interlayerlayer 59 becomes even, therespective portions of the third insulating interlayerlayer 59 corresponding to the gate 47 and the heavily doped regions 53 differ in thickness. Namely, the portion of the third insulating interlayerlayer 59 corresponding to the heavily doped regions 59 is thicker than the other portion of the third insulating layer 59corresponding to the gate 47. In this case,It is to be readily understood that the third insulating interlayerlayer 59 may be formed with at least doubleby one or more layers of the above-mentioned substances.
A first and a second contact holeFirst and second contact holes 61 and 63respectively exposing the gate 47 and heavily doped regions 53respectively are formed by successively patterning the third, second, and first insulating interlayerslayers 59, 57, and 55successively bythrough photolithography including an anisotropic etchetching such as RIE and the like.
When the first and second contact holes 61 and 63 are formed, portions of the second insulating interlayer layer 57 corresponding to the heavily doped regions 53 are exposed by overetching over-etching the third insulating interlayer layer 59 with a gas of C2F6 or C4F8 C 2 F 6 or C 4 F 8 which is mixed with O2 O 2. In this case, the second insulating layer 57 of which an etch rate is different from that of the third insulating layer 59 is used as an etch-stop layer.
After the exposed portions of the second insulating interlayer layer 57 has been etched by C2HF6O2 C 2 HF 6 O 2, the first and second contact holes 61 and 63 are formed by etching the first insulating layer 55 to expose the semiconductor substrate 41 in use of using the gas of C2F6 or C4F8 C 2 F 6 or C 4 F 8 which is mixed with O2. which has been used for O2 as in the case of etching the third insulating interlayer layer 59. In this case, due to the fact that it is easy to control an etching end point owing to thinness of the first insulation layer 55, the field oxide layer 43 is prevented from being damagedbecause it is easy to control the etch-end point owing to the thin first insulating interlayer 55 .
Referring to FIG. 2D, an electrically-conductive substance such as polysilicon, Al aluminum, and the like is deposited on the third insulating interlayer layer 59 and through the first and second contact holes 61 and 63 by CVD to be contacted brought into contact with the gate 47 and heavily doped regions 53through the first and second contact holes 61 and 63 . Then, a first and a second plug first and second plugs 65 and 67 are formed in the first and second contact holes 61 and 63, respectively, by removing the electrically-conductive substance through CMP to expose the surface of the third insulating interlayer layer 59by CMP .
As mentioned inAs apparent from the above description ofin the method of fabricating a semiconductor device ofaccording to the present invention, a first insulating layer made of silicon oxide of which heat expansion coefficient and lattice mismatch are less than those of silicon nitride is formed on a semiconductor substrate, and a second insulating interlayerlayer made of silicon nitride used as an etch-stop layer and a third insulating interlayerlayer made of silicon oxide are formed on the first insulating interlayerlayer successively.
And, a first and a second contact hole a first and second holes exposing a gate and heavily doped regions are formed by patterning the third to first insulating interlayers layers by photolithography in order, wherein the third insulating interlayer are overetched layer is over-etched to expose a portion of the second insulating interlayer layer corresponding to the heavily doped regions. In this case, the second insulating interlayer layer used as an etch-stop layer prevents the first insulating interlayer layer and field oxide layer from being etched.
Accordingly, the present invention prevents the a leakage current occurrence from being generated by avoiding the stress generation due to the contact between the semiconductor substrate and insulating interlayer layer.
It will be apparent to those skilled in the art that various modifications and variations can be made in a method of fabricating a semiconductor device of the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and equivalents.

Claims (25)

1. A method of fabricating a semiconductor device comprising the steps of:
forming a field oxide layerdefining , which defines an active area and a field area on a semiconductor substrate of a first conductive type;
forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;
forming impurity regions of a second conductive type in the semiconductor substrate in use of using the gate as a mask;
forming a first insulating interlayer layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;
forming a second insulating interlayer layer on the first insulating interlayer layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer layer;
forming a third insulating interlayer layer on the second insulating interlayer layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer layer; and
forming a first contact hole and second contact holes respectively exposing the gate and heavily doped impurity regions respectively by successively patterning the third to first insulating interlayer successively by layers through photolithography,
wherein the second insulating layer is etched by C 2 HF 6 O 2 , and
wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.
2. The method of fabricating a semiconductor device according to claim 1, wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon.
3. The method of fabricating a semiconductor device according to claim 1, wherein the first insulating interlayer layer is formed by depositing silicon oxide to a thickness of 100 to 300 Åthick .
4. The method of fabricating a semiconductor device according to claim 3, wherein the first insulating interlayer layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2) (C 2 F 6 +O 2) or (C 4 F 8 +O 2).
5. The method of fabricating a semiconductor device according to claim 1, wherein the second insulating interlayer layer is formed by depositing silicon nitride to a thickness of 100 to 300 Åthick .
6. The method of fabricating a semiconductor device according to claim 5, wherein the second insulating interlayer is etched by C2HF6O2.
7. The method of fabricating a semiconductor device according to claim 1, wherein the third insulating interlayer layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating with spin on glass.
8. The method of fabricating a semiconductor device according to claim 7, wherein the third insulating interlayer of a single layer is formed with one or more layers made of silicon oxide, boro phospho silicate glass, or spin on glassor wherein the third insulating interlayer of at least double layers is formed with silicon oxide, boro phospho silicate glass and spin on glass .
9. The method of fabricating a semiconductor device according to claim 7, wherein a surface of the third insulating interlayer layer is formed to be even.
10. The method of fabricating a semiconductor device according to claim 7, wherein the third insulating interlayer layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2) (C 2 F 6 +O 2) or (C 4 F 8 +O 2).
11. The method of fabricating a semiconductor device according to claim 10, wherein the third insulating interlayer layer is overetched over-etched to expose the second insulating interlayer layer corresponding to the heavily doped impurity regions.
12. The method of fabricating a semiconductor device according to claim 1, the method further comprising the step of forming first and second plugs in the first and second contact holes.
13. A method of fabricating a semiconductor device comprising the steps of
forming a field oxide layer defining which defines an active area and a field area on a semiconductor substrate of a first conductive type;
forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;
forming a sidewall spacer at a side of the gate;
forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;
forming a sidewall spacer at a side of the gate;
forming heavily doped regions of the second conductive type in the semiconductor substrate in use of using the gate and sidewall spacer as a mask wherein so that the heavily doped regions are overlapped with the lightly doped regions;
forming a first insulating interlayer layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;
forming a second insulating interlayer layer on the first insulating interlayer layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer layer;
forming a third insulating interlayer layer on the second insulating interlayer layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer layer;
forming a first contact hole first and second contact holes respectively exposing the gate and heavily doped regions respectively by successively patterning the third to first insulating interlayer successively by layers through photolithography; and
forming first and second plugs in the first and second contact holes,
wherein the second insulating layer is etched by C 2 HF 6 O 2 , and
wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.
14. A method of fabricating a semiconductor device comprising the steps of:
forming a field oxide layer, which defines an active area and a field area on a semiconductor substrate of a first conductive type;
forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;
forming impurity regions of a second conductive type in the semiconductor substrate using the gate as a mask;
forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;
forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;
forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass; and
forming a first contact hole and second contact holes respectively exposing the gate and impurity regions by successively patterning the third to first insulating layers through photolithography,
wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.
15. The method of fabricating a semiconductor device according to claim 14, wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon.
16. The method of fabricating a semiconductor device according to claim 14, wherein the first insulating layer is formed by depositing silicon oxide to a thickness of 100 to 300 Å.
17. The method of fabricating a semiconductor device according to claim 16, wherein the first insulating layer is etched by a mixed gas of (C 2 F 6 +O 2) or (C 4 F 8 +O 2).
18. The method of fabricating a semiconductor device according to claim 14, wherein the second insulating layer is formed by depositing silicon nitride to a thickness of 100 to 300 Å.
19. The method of fabricating a semiconductor device according to claim 18, wherein the second insulating layer is etched by C2 HF 6 O 2.
20. The method of fabricating a semiconductor device according to claim 14, wherein the third insulating layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating spin on glass.
21. The method of fabricating a semiconductor device according to claim 20, wherein a surface of the third insulating layer is formed to be even.
22. The method of fabricating a semiconductor device according to claim 20, wherein the third insulating layer is etched by a mixed gas of (C 2 F 6 +O 2) or (C 4 F 8 +O 2).
23. The method of fabricating a semiconductor device according to claim 22, wherein the third insulating layer is over-etched to expose the second insulating layer corresponding to the impurity regions.
24. The method of fabricating a semiconductor device according to claim 14, further comprising the step of forming first and second plugs in the first and second contact holes.
25. A method of fabricating a semiconductor device comprising the steps of
forming a field oxide layer which defines an active area and a field area on a semiconductor substrate of a first conductive type;
forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;
forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;
forming a sidewall spacer at a side of the gate;
forming heavily doped regions of the second conductive type in the semiconductor substrate using the gate and sidewall spacer as a mask so that the heavily doped regions are overlapped with the lightly doped regions;
forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;
forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;
forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass;
forming first and second contact holes respectively exposing the gate and heavily doped regions by successively patterning the third to first insulating layers through photolithography; and
forming first and second plugs in the first and second contact holes,
wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.
US10/952,576 1999-08-21 2004-09-28 Method of fabricating a semiconductor device Expired - Lifetime USRE41205E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/952,576 USRE41205E1 (en) 1999-08-21 2004-09-28 Method of fabricating a semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR99-34743 1999-08-21
KR1019990034743A KR100333361B1 (en) 1999-08-21 1999-08-21 a method for fabricating a semiconductor device
US09/609,390 US6339003B1 (en) 1999-08-21 2000-07-03 Method of fabricating a semiconductor device
US10/952,576 USRE41205E1 (en) 1999-08-21 2004-09-28 Method of fabricating a semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/609,390 Reissue US6339003B1 (en) 1999-08-21 2000-07-03 Method of fabricating a semiconductor device

Publications (1)

Publication Number Publication Date
USRE41205E1 true USRE41205E1 (en) 2010-04-06

Family

ID=19608138

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/609,390 Ceased US6339003B1 (en) 1999-08-21 2000-07-03 Method of fabricating a semiconductor device
US10/952,576 Expired - Lifetime USRE41205E1 (en) 1999-08-21 2004-09-28 Method of fabricating a semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/609,390 Ceased US6339003B1 (en) 1999-08-21 2000-07-03 Method of fabricating a semiconductor device

Country Status (2)

Country Link
US (2) US6339003B1 (en)
KR (1) KR100333361B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551901B1 (en) 2001-08-21 2003-04-22 Lsi Logic Corporation Method for preventing borderless contact to well leakage
US7098515B1 (en) 2001-08-21 2006-08-29 Lsi Logic Corporation Semiconductor chip with borderless contact that avoids well leakage
US8159038B2 (en) * 2008-02-29 2012-04-17 Infineon Technologies Ag Self aligned silicided contacts
CN115295615A (en) * 2022-10-08 2022-11-04 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
US5811343A (en) * 1996-07-15 1998-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectric
US5912188A (en) * 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
US6077731A (en) * 1996-01-19 2000-06-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US6159844A (en) * 1998-05-29 2000-12-12 Philips Electronics North America Corp. Fabrication of gate and diffusion contacts in self-aligned contact process
US6159839A (en) * 1999-02-11 2000-12-12 Vanguard International Semiconductor Corporation Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6326270B1 (en) * 1998-10-16 2001-12-04 Samsung Electronics Co., Ltd. Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines
US6333558B1 (en) * 1998-05-27 2001-12-25 Sony Corporation Semiconductor device and method for fabricating the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
US6077731A (en) * 1996-01-19 2000-06-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US5811343A (en) * 1996-07-15 1998-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectric
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
US5912188A (en) * 1997-08-04 1999-06-15 Advanced Micro Devices, Inc. Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
US6333558B1 (en) * 1998-05-27 2001-12-25 Sony Corporation Semiconductor device and method for fabricating the same
US6159844A (en) * 1998-05-29 2000-12-12 Philips Electronics North America Corp. Fabrication of gate and diffusion contacts in self-aligned contact process
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6326270B1 (en) * 1998-10-16 2001-12-04 Samsung Electronics Co., Ltd. Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines
US6159839A (en) * 1999-02-11 2000-12-12 Vanguard International Semiconductor Corporation Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Also Published As

Publication number Publication date
KR20010018687A (en) 2001-03-15
US6339003B1 (en) 2002-01-15
KR100333361B1 (en) 2002-04-18

Similar Documents

Publication Publication Date Title
KR100431656B1 (en) Method of manufacturing semiconductor device
US6297126B1 (en) Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
US6323104B1 (en) Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry
KR101815527B1 (en) Semiconductor device and method for manufacturing the same
KR100846099B1 (en) Method of manufacturing semiconductor device including recessed channel transistor
KR100338778B1 (en) Method for fabricating MOS transistor using selective silicide process
US6528368B1 (en) Method for fabricating semiconductor device, and semiconductor device, having storage node contact flugs
US6265302B1 (en) Partially recessed shallow trench isolation method for fabricating borderless contacts
US5885895A (en) Method of forming a self-aligned contact of a DRAM cell
US6051479A (en) Method of fabricating shallow trench isolation
US20030124776A1 (en) Method for manufacturing semiconductor device
USRE41205E1 (en) Method of fabricating a semiconductor device
KR100281124B1 (en) Semicon ductor and method for fabricating the same
US20040198038A1 (en) Method of forming shallow trench isolation with chamfered corners
US6211021B1 (en) Method for forming a borderless contact
US6383921B1 (en) Self aligned silicide contact method of fabrication
KR100377833B1 (en) Semiconductor device with borderless contact structure and method of manufacturing the same
US8222715B2 (en) Semiconductor device capable of reducing a contact resistance of a lower electrode and a contact pad and providing an align margin between the lower electrode and the contact pad
KR20060042460A (en) Method for manufacturing a transistor having a recess channel
KR100244426B1 (en) Method of forming contact hole in semiconductor device
US20060258115A1 (en) Semiconductor device and method of manufacturing the same
KR100589498B1 (en) Method of manufacturing semiconductor device
KR20000039307A (en) Method for forming contact of semiconductor device
KR100571414B1 (en) Contact formation method of semiconductor device
KR100262012B1 (en) A method of fabricating semiconductor device

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12