USRE40859E1 - Method and system for displaying an analog image by a digital display device - Google Patents
Method and system for displaying an analog image by a digital display device Download PDFInfo
- Publication number
- USRE40859E1 USRE40859E1 US10/720,001 US72000103A USRE40859E US RE40859 E1 USRE40859 E1 US RE40859E1 US 72000103 A US72000103 A US 72000103A US RE40859 E USRE40859 E US RE40859E
- Authority
- US
- United States
- Prior art keywords
- phase
- signal
- circuit
- frequency
- time reference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
Description
Hor_Rcount−Th/Trclk (1)
where Trclk represents the clock period of reference clock and Th represents the horizontal period (time between two successive Hsync pulses).
Pnom=srs_htotal*Qdto/Hor_Rcount (2)
Here, Qdto is DTO module, (i.e., 2**n, where n is the number of bits in DTO). It should be noted that Pnom isn't dependent on locking scheme. That is, the clock signal can be locked on HSYNC, VSYNC, or the like.
Ppdp=Pnom/Kpdp (3)
Npdp=Ppdp/Knpdp (4)
Knpdp=2 . . . 16
Fdp=Pnom/(Kfdp*Vdiv*Hor_Rcount) (5a)
Fdp=Pnom/(Kfdp*Vtotal*Hor_Rcount) (5b)
Claims (18)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/720,001 USRE40859E1 (en) | 1997-02-24 | 2003-11-20 | Method and system for displaying an analog image by a digital display device |
US11/408,669 USRE41192E1 (en) | 1997-02-24 | 2006-04-21 | Method and system for displaying an analog image by a digital display device |
US12/624,053 USRE42615E1 (en) | 1997-02-24 | 2009-11-23 | Method and system for displaying an analog image by a digital display device |
US13/168,832 USRE43573E1 (en) | 1997-02-24 | 2011-06-24 | Method and system for displaying an analog image by a digital display device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/803,824 US5796392A (en) | 1997-02-24 | 1997-02-24 | Method and apparatus for clock recovery in a digital display unit |
US09/082,070 US6320574B1 (en) | 1997-02-24 | 1998-05-20 | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
US10/720,001 USRE40859E1 (en) | 1997-02-24 | 2003-11-20 | Method and system for displaying an analog image by a digital display device |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/803,824 Continuation US5796392A (en) | 1997-02-24 | 1997-02-24 | Method and apparatus for clock recovery in a digital display unit |
US09/082,070 Reissue US6320574B1 (en) | 1997-02-24 | 1998-05-20 | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/082,070 Division US6320574B1 (en) | 1997-02-24 | 1998-05-20 | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
US11/408,669 Division USRE41192E1 (en) | 1997-02-24 | 2006-04-21 | Method and system for displaying an analog image by a digital display device |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE40859E1 true USRE40859E1 (en) | 2009-07-21 |
Family
ID=25187534
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/803,824 Expired - Lifetime US5796392A (en) | 1997-02-24 | 1997-02-24 | Method and apparatus for clock recovery in a digital display unit |
US09/082,070 Ceased US6320574B1 (en) | 1997-02-24 | 1998-05-20 | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
US10/720,001 Expired - Lifetime USRE40859E1 (en) | 1997-02-24 | 2003-11-20 | Method and system for displaying an analog image by a digital display device |
US11/408,669 Expired - Lifetime USRE41192E1 (en) | 1997-02-24 | 2006-04-21 | Method and system for displaying an analog image by a digital display device |
US12/624,053 Ceased USRE42615E1 (en) | 1997-02-24 | 2009-11-23 | Method and system for displaying an analog image by a digital display device |
US13/168,832 Expired - Lifetime USRE43573E1 (en) | 1997-02-24 | 2011-06-24 | Method and system for displaying an analog image by a digital display device |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/803,824 Expired - Lifetime US5796392A (en) | 1997-02-24 | 1997-02-24 | Method and apparatus for clock recovery in a digital display unit |
US09/082,070 Ceased US6320574B1 (en) | 1997-02-24 | 1998-05-20 | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/408,669 Expired - Lifetime USRE41192E1 (en) | 1997-02-24 | 2006-04-21 | Method and system for displaying an analog image by a digital display device |
US12/624,053 Ceased USRE42615E1 (en) | 1997-02-24 | 2009-11-23 | Method and system for displaying an analog image by a digital display device |
US13/168,832 Expired - Lifetime USRE43573E1 (en) | 1997-02-24 | 2011-06-24 | Method and system for displaying an analog image by a digital display device |
Country Status (5)
Country | Link |
---|---|
US (6) | US5796392A (en) |
EP (1) | EP0865019A3 (en) |
JP (1) | JP2942750B2 (en) |
KR (1) | KR100280041B1 (en) |
TW (1) | TW424218B (en) |
Cited By (1)
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---|---|---|---|---|
USRE42615E1 (en) * | 1997-02-24 | 2011-08-16 | Genesis Microchip (Delaware) Inc. | Method and system for displaying an analog image by a digital display device |
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Also Published As
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KR19980071593A (en) | 1998-10-26 |
JP2942750B2 (en) | 1999-08-30 |
JPH10285022A (en) | 1998-10-23 |
EP0865019A2 (en) | 1998-09-16 |
USRE43573E1 (en) | 2012-08-14 |
US5796392A (en) | 1998-08-18 |
USRE41192E1 (en) | 2010-04-06 |
KR100280041B1 (en) | 2001-02-01 |
EP0865019A3 (en) | 1999-06-09 |
US6320574B1 (en) | 2001-11-20 |
TW424218B (en) | 2001-03-01 |
USRE42615E1 (en) | 2011-08-16 |
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