|Publication number||USRE39413 E1|
|Application number||US 10/139,132|
|Publication date||28 Nov 2006|
|Filing date||2 May 2002|
|Priority date||28 Feb 1996|
|Also published as||US5798302, US6057602|
|Publication number||10139132, 139132, US RE39413 E1, US RE39413E1, US-E1-RE39413, USRE39413 E1, USRE39413E1|
|Inventors||Guy F. Hudson, Russell C. Zahorik|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (2), Classifications (17), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a reissue of U.S. patent application Ser. No. 09/134,279, filed Aug. 14, 1998, issued as U.S. Pat. No. 6,057,602; which is a divisional of U.S. patent application Ser. No. 08/608,186, filed Feb. 28, 1996, issued as U.S. Pat. No. 5,798,302.
The present invention relates to chemical-mechanical planarization of semiconductor wafers; more specifically, the present invention relates to a polish-stop layer for effectively endpointing chemical-mechanical planarization processes that use either hard or soft polishing pads.
Chemical-mechanical planarization (“CMP”) processes remove material from the surface of a wafer in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry solution generally contains small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. The polishing pad is generally a planar pad made from a relatively porous material such as blown polyurethane. Thus, when the pad and/or the wafer moves with respect to the other material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and by the chemicals in the slurry (chemical removal).
In the operation of the conventional planarizer 10, the wafer 50 is positioned face-downward against the polishing pad 40, and then the platen 20 and the wafer carrier 30 move relative to one another. As the face of the wafer 50 moves across the planarizing surface 42 of the polishing pad 40, the polishing pad 40 and the slurry 44 remove material from the wafer 50.
CMP processes must consistently and accurately produce a uniform, planar surface on the wafer because it is important to accurately focus circuit patterns on the wafer. As the density of integrated circuits increases, currently lithographic techniques must accurately focus the critical dimensions of photo-patterns to within a tolerance of approximately 0.35-0.5 μm. Focusing the photo-patterns to such small tolerances, however, is very difficult when the distance between the emission source and the surface of the wafer varies because the surface of the wafer is not uniformly planar. In fact, when the surface of the wafer is not uniformly planar, several devices on the wafer may be defective. Thus, CMP processes must create a highly uniform, planar surface.
In the competitive semiconductor industry, it is also highly desirable to maximize the throughput of CMP processes to produce accurate, planar surfaces as quickly as possible. The throughput of CMP processes is a function of several factors, two of which are the ability to accurately stop the CMP process at a desired endpoint and the rate at which material is removed from the wafer (the “polishing rate”). Accurately stopping the CMP process at a desired endpoint is important to maintaining a high throughput because the thickness of the dielectric layer must be within and acceptable range; if the thickness of the dielectric layer is not within an acceptable range, the wafer must be re-planarized until it reaches the desired endpoint. Maintaining a high, consistent polishing rate is also important to sustaining a high throughput because the polishing rate determines the length of the planarization process. Thus, it is desirable to stop the CMP process at the desired endpoint and to maintain a high polishing rate.
In operation, the insulative layer 70 of the stop-on-feature wafer 50(a) or the conductive layer 90 of the interconnect wafer 50(b) is planarized until the polishing pad (shown in
U.S. Pat. No. 5,246,884 to Jaso et al. discloses using diamond or diamond-like carbon (“DLC”) as a chemical-mechanical polish stop. In particular, a metallized semiconductor chip is coated with a first layer of silicon dioxide followed by a second layer of diamond or DLC as an etch stop. The DLC is deposited at about 75° C. to about 350° C. to form a layer of DLC with a thickness of 750 Å to 1000 Å. U.S. Pat. No. 5,246,884 discloses that DLC effectively stops planarization with softer polishing pads, such as an IC-40 or an IC-60 polishing pad, but that no difference in the thickness uniformly or planarity was observed when harder polishing pads were used to planarize wafers. U.S. Pat. No. 5,246,884 discloses that diamond or DLC works well as an etch stop with soft polishing pads because these substances are exceptionally hard.
One problem with DLC polish-stop layers is that they do not effectively endpoint CMP processing with hard polishing pads. Hard polishing pads are often the pad of choice for many CMP applications; compared to softer polishing pads, hard polishing pads reduce dishing over large features, withstand higher down forces, and resist wear better. Hard polishing pads, however, effectively planarize DLC because the carbon atoms are bonded to each other and to adjacent hydrogen atoms in a manner that prevents the carbon atoms from moving with respect to each other and along substantially parallel, horizontal planes. Thus, because hard pads effectively planarize DLC, it would be desirable to make polish-stop layer from a material that effectively endpoints CMP processing with hard polishing pads.
Another problem with DLC polish-stop layers is that they are relatively time consuming to deposit on and remove from the wafers. Polish-stop layers made from DLC are deposited to a thickness of approximately 750 Å to approximately 1000 Å. As with any material; the process time to deposit a layer of DLC increases with increasing layer thickness. Moreover, in the case of interconnect wafers, the DLC layers is also cleaned from the surface of the wafer after the CMP process is finished to accommodate subsequent processing of the wafer. Thus, since the time to deposit and clean material increases with increasing layer thickness, it is desirable to reduce the thickness of the polish-stop layer without significantly impairing its effectiveness.
The inventive semiconductor wafer enhances polish-stop endpointing in chemical-mechanical planarized processes with both hard and soft polishing pads. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low fiction materials positioned over the substrate, and an upper layer deposited on the low friction stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists planarization because it induces the polishing pad to slide over the wafer without removing material. Thus, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.
In an inventive method for chemical-mechanical planarization, a stratum of low friction material is deposited over a semiconductor substrate form a polish-stop surface of low friction material at a level substantially proximate to a desired endpoint of the planarization process. The low friction stratum is covered with an upper layer of material having a polishing rate higher than that of the low friction stratum. After the upper layer of material is deposited, the substrate is mounted to a wafer carrier of a chemical-mechanical planarization machine, and the upper layer is pressed against a polishing pad in the presence of a slurry. The polishing pad may be either a hard or a soft polishing pad. At least one of the wafer carrier or the polishing pad is moved with respect to the other to impart relative motion between the wafer and the polishing pad. In operation, the low friction stratum resists chemical-mechanical planarization with the polishing pad and the slurry to substantially stop the planarization process at the desired endpoint.
The present invention is a semiconductor wafer, and a method for making the semiconductor wafer, that effectively resists planarization using hard polishing pads, high down forces, and aggressive slurries. An important aspect of the invention is the discovery that a thin stratum of a low friction material substantially resists planarization by both hard and soft polishing pads. One suitable low friction material is graphitic carbon, which acts as a bearing between the polishing pad and the wafer because the carbon atoms bond to only a portion of the adjacent carbon atoms in a manner that allows adjacent, parallel layers of carbon atoms to slide over one another. Therefore, a graphitic carbon stratum with a polish-stop surface positioned proximate to a desired planarization endpoint effectively stops the planarization process at the desired endpoint with both hard and soft polishing pads.
In operation, the upper layer 190 of either the stop-on-feature wafer 150(a) or the interconnect wafer 150(b) is planarized in a CMP machine 10, as described above with respect to
One advantage of the present invention is that a low friction stratum 180 made from graphitic carbon has a very low polishing rate even when hard polishing pads, aggressive slurries, and high down forces are used in the CMP process. For example, after being planarized for approximately 60 second with a Rodel IC-1000 polishing pad and a Rodel ILD 1300 slurry (manufactured by Rodel Corporation of Newark, Delaware), graphitic carbon stratums with a thickness of approximately 300 Å to 500 Å experienced a film loss of only approximately 0.99% to 2.17%. Similarly, after being planarized for 60 seconds with a Rodel Politex polishing pad and a Rodel MSW 2000 slurry, graphitic carbon stratums with thicknesses of approximately 300 Å to 500 Å experienced a film loss of approximately 1% to 8.4%. The Rodel IC-1000 polishing pad is a hard polishing pad and the Rodel MSW 2000 slurry is an aggressive slurry with aluminum dioxide particles. Conversely, the Rodel Politex polishing pad is a soft pad and the Rodel ILD 1300 slurry is a non-aggressive slurry. As shown by the results of the tests, graphitic carbon effectively stops planarization with hard polishing pads, soft polishing pads, aggressive slurries, and non-aggressive slurries. Methods in accordance with the invention are accordingly useful for planarizing a wafer using polishing pads having a Rockwell hardness between approximately 75 and 90. Therefore, even when hard polishing pads are used, a low friction stratum 180 made from graphitic carbon stops the CMP process at a desired endpoint.
Compared to typical DLC polish-stop layers, the graphitic carbon stratum of the present invention has a much lower polishing rate with hard polishing pads. The graphitic carbon stratum of the invention is essentially free of carbon-hydrogen bonds and has an SP-3 lattice structure to allow the layers of carbon atoms in the stratum to slide with respect to each other. Conversely, DLC has an SP-4 lattice structure and an important aspect of most DLC polish-stop layers is the incorporation of hydrogen into the DLC material, both of which act to restrict the layers of carbon atoms in the polish-stop layer from moving with respect to each other. DLC, in fact, is usually deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition processes that use a carrier gas containing hydrogen that enhances the incorporation of hydrogen into the DLC material. As stated above, however, the present invention preferably deposits the graphitic carbon stratum by plasma vapor deposition from a carbon target. Thus, by providing a graphitic carbon stratum that is essentially free of carbon-hydrogen bons and has an SP-3 lattice structure, the present invention uses a low friction layer instead of a hard layer to reduce the polishing rate with hard pads.
Another advantage of the present invention is that a low friction stratum made from graphitic carbon enhances the throughput of the CMP process because only a thin layer of graphitic carbon is required to provide an effective polish-stop layer. Unlike the DLC, a graphite carbon stratum with a thickness of only 100 Å provides an effective polish-stop layer for both hard and soft polishing pads. The throughput of the CMP process is accordingly enhanced because it takes less time to deposit and clean a thin stratum of graphitic carbon than a thicker layer of DLC.
Still another advantage of the present invention is that the graphitic carbon stratum may be deposited on the wafer at a low temperature that does not damage or alter other electrical components. Many electrical components of integrated circuits are formed in silicon, which anneals at approximately 450° C. A low friction stratum 180 made from graphitic carbon is preferably deposited at a temperature of between approximately 50° C. and 150° C. Therefore, the deposition temperature of a low friction stratum 180 made from graphitic carbon does not damage or alter the other electrical components on the wafer.
An additional advantage of the present invention is that it enhances the throughput of the CMP process because a low friction stratum 180 made from graphitic carbon effectively stops further planarization even when higher down forces are used to increase the polishing rate. Higher down forces on the order of 7-9 psi generally reduce the effectiveness of polish-stop layers. In the case of a low friction stratum 180 made from graphitic carbon, however, the above-listed tests were performed with a down force of approximately 7.0-7.5 psi. Therefore, CMP processes that use higher down forces to achieve higher polishing rates may be effectively end-pointed with a low friction stratum 180 made from graphitic carbon.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
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|U.S. Classification||438/689, 216/89, 438/690, 216/95, 216/88, 216/38, 216/81, 438/691, 257/752, 438/693, 216/52, 438/692, 216/53|
|International Classification||H01L21/3105, H01L23/48|
|20 Sep 2007||FPAY||Fee payment|
Year of fee payment: 8
|12 Dec 2011||REMI||Maintenance fee reminder mailed|
|27 Apr 2012||LAPS||Lapse for failure to pay maintenance fees|