USRE39126E1 - Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs - Google Patents

Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs Download PDF

Info

Publication number
USRE39126E1
USRE39126E1 US08/527,954 US52795495A USRE39126E US RE39126 E1 USRE39126 E1 US RE39126E1 US 52795495 A US52795495 A US 52795495A US RE39126 E USRE39126 E US RE39126E
Authority
US
United States
Prior art keywords
insulation layer
tungsten
conductive material
contact hole
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/527,954
Inventor
Chris C. Yu
Trung T. Doan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US08/527,954 priority Critical patent/USRE39126E1/en
Application granted granted Critical
Publication of USRE39126E1 publication Critical patent/USRE39126E1/en
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F3/00Brightening metals by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation

Definitions

  • the disclosed invention relates to the field of semiconductor manufacture. More specifically, a chemical mechanical wafer polishing process is described which produces improved flush and protruding tungsten plugs rather than the recessed plugs produced by conventional tungsten plug etchback techniques. Coupling with subsequent layers of conductive material such as sputtered aluminum is therefore more easily accomplished.
  • Integrated circuits are chemically and physically integrated into a substrate, such as a silicon or gallium arsenide wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication. Up to a thousand or more devices are formed simultaneously on the surface of a single wafer of semiconductor material.
  • Another method which has been used to produce a planar wafer surface is to use the oxide reflow method described above, then spin coat the wafer with photoresist.
  • the spin coating of the material on the wafer surface fills the low points and produces a planar surface from which to start.
  • a dry etch which removes photoresist and oxide at a rate sufficiently close to 1:1, removes the photoresist and the high points of the wafer, thereby producing a planar oxide layer on the wafer surface.
  • CMP chemical mechanical planarization
  • Deposited conductors are an integral part of every integrated circuit, and provide the role of surface wiring for conducting current. Specifically, the deposited conductors are used to wire together the various components that are formed in the surface of the wafer. Electronic devices formed within the wafer have active areas which must be contacted with conductive runners, such as metal. Typically, a layer of insulating material is applied stop the wafer and selectively masked to provide contact opening patterns. The layer is subsequently etched, for instance with a reactive ion etch (RIE), to provide contact openings from the upper surface of the insulating layer down into the wafer to provide electrical contact with selected active areas.
  • RIE reactive ion etch
  • Certain metals and allows deposited by vacuum evaporation and sputtering techniques do not provide the most desired coverage within the contact openings when applied to the surface of a wafer.
  • An example of a metal which typically provides such poor coverage is sputtered aluminum, or alloys of aluminum with silicon and/or copper.
  • One metallization scheme which does provide good coverage within contact vias is tungsten deposited by the chemical vapor deposition (CVD) technique. Tungsten is not, however, as conductive as aluminum. Accordingly, a tungsten layer is typically etched or polished back to provide a plug within the insulation layer, the plug having a flat upper surface which is flush with the surface of the insulator. A layer of aluminum would subsequently be applied atop the wafer surface to contact the plug. The aluminum layer is then selectively etched to provide the desired interconnecting runners coupling the tungsten with other circuitry.
  • FIG. 1 shows a desirable outcome of a process to produce a tungsten plug.
  • a material such as an oxide layer 10 covers the material of the wafer surface 12 .
  • the tungsten 14 which fills the contact hole 16 in the oxide material 10 is level with the surface of the oxide layer.
  • FIG. 2 illustrates one problem with present methods of tungsten etch backs, an over etching within the contacts which recesses the tungsten 14 within the contact hole 16 in the wafer surface 10 . This can provide for poor contact between the tungsten plug 14 with the aluminum or aluminum alloy layer (not shown) which would be subsequently deposited by sputtering. It is difficult to provide reliable contacts between the aluminum and the recessed tungsten plugs which result from conventional tungsten etchback techniques such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • another conventional tungsten etch back means includes a single-step CMP etchback using a polishing slurry and polishing pad.
  • a layer of tungsten is formed by CVD or other means onto the wafer surface, thereby filling the contact holes in the insulation layer with tungsten.
  • the surface of the wafer is polished to remove the tungsten overlying the surface of the wafer, which leaves the contact holes filled with tungsten. Due to the chemical nature of the slurry and compressible nature of the polishing pad, a certain amount of the tungsten material is removed from the contact holes, leaving the recessed tungsten structure 14 of FIG. 2 .
  • An object of the invention is to provide a process for forming contacts (plugs) of tungsten or other conductive materials that results in a more uniform, nonrecessed plug.
  • Another object of the invention is to provide a process for forming a plug of tungsten or other conductive material which results in a better surface to connect with another material such as a layer of aluminum by virtue of the more uniform, nonrecessed characteristics of the plug.
  • Yet another object of the invention is to provide a process for forming a plug of tungsten of other conductive material which can produce uniform, protruding plugs which allow for easier coupling with subsequent layers of conductive material than recessed plugs produced by conventional methods.
  • a substrate of a material such as silicon having a layer of oxide (BPSG) is manufactured with contact holes therein, and a layer of metal such as tungsten is formed upon the substrate to fill the contact holes.
  • a first CMP step which is selective to the plug material, removes the upper layer of tungsten from the oxide surface while removing very little or no oxide from the wafer surface.
  • a portion of the tungsten below the level of the oxide surface is also removed, thereby recessing the tungsten plugs.
  • This recessed plug which is typical of conventional plug formation, is difficult to couple with a subsequent layer of metal or other material.
  • a second CMP step which is selective to oxide material of the wafer surface, removes a portion of the insulation material to a level even with, or slightly below, the level of the tungsten plugs.
  • the slurry of the oxide CMP can be formulated so as to remove a desired amount of tungsten. This can be accomplished by increasing the amount of etchant that is selective to the material of the plug.
  • FIG. 1 is a cross-section of a desirable plug
  • FIG. 2 is a cross-section of a recessed plug typically produced by a conventional CMP process
  • FIG. 3 is a cross-section of a first step in the inventive process showing a layer of conductive material (such as tungsten) formed over the substrate; and
  • FIG. 4 is a cross-section of a protruding plug embodiment which can be produced by the inventive two-step process.
  • the inventive process formed plugs from a conductive material (in the instant case tungsten) which were even with, and in a second embodiment slightly protruding from, a an insulation layer comprising an insulating material or a dielectric material, such as an oxide material (BPSG in the instant case, or other materials such as SiO 2 ) or a nonoxide material (such as polyimide ).
  • a conductive material in the instant case tungsten
  • a conductive material in the instant case tungsten
  • a dielectric material such as an oxide material (BPSG in the instant case, or other materials such as SiO 2 ) or a nonoxide material (such as polyimide ).
  • the inventive process began with a wafer as shown in FIG. 3 fabricated by means known in the art having a layer of insulation material 10 such as an oxide (BPSG) which is approximately 2-3 ⁇ m thick.
  • BPSG oxide
  • Contact holes 16 were formed into material 10 by any conventional process.
  • a layer of metal 30 tungsten in the instant case, filled the contact holes 16 and extended over the insulation 10 surface.
  • the tungsten layer 30 was formed by chemical vapor deposition (CVD) to most efficiently fill the contact holes 16 , but workable methods known in the art are also possible.
  • the layer of tungsten 30 over the oxide surface 10 in the instant case was approximately 10K ⁇ thick, but other thicknesses are possible as the layer is removed in subsequent wafer processing steps.
  • CMP chemical mechanical polishing
  • the tungsten 14 was slightly recessed at this stage in the process as shown resulting from the mechanical erosion of the tungsten from the fibers of the polishing pad.
  • the magnitude of the recess typically varied from approximately 0.5K ⁇ to 3K ⁇ below the surface of the oxide 10 .
  • the chemical component of the slurry oxidized the tungsten, and the tungsten oxide was removed mechanically with the abrasive material in the slurry. Additionally, a small portion of the tungsten was removed by the abrasive. In any case, the CMP process used is selective to tungsten and leaves the insulation layer relatively unaffected.
  • the second step involved a CMP process which was selective to the material of the insulation layer, although it may be desirable to remove a small amount of the tungsten as well to either to polish the tungsten or to provide a convex protruding plug. If tungsten is removed at this step, it is done at a much slower rate than the removal of the insulation material.
  • a slurry containing etchants selective to the oxide was added between a rotating polish pad and the wafer surface.
  • the colloidal silica slurry used in the instant case contained abrasives as described above, and also etchants selective to the oxide, such as a basic mixture of H 2 O and KOH. In most cases, if other nonoxide insulators are used other chemical etchants would be required. As shown in FIG.
  • the insulation material 10 was removed from around the tungsten plugs 14 , resulting in a plug 14 which was even with the surface of the insulation material 10 .
  • the action of the pad abraded the surface of the tungsten and the oxide material sufficient to polish out surface irregularities.
  • the tungsten was polished at a slow rate, less than 50 ⁇ /minute, but the oxide underlayer was polished at a high rate, greater than 2500 ⁇ /minute.
  • a layer of 0.5K ⁇ -3K ⁇ of the insulation material is removed at the second CMP step, as this is the usual extent to which the tungsten is recessed within the contact hole.
  • a second embodiment of the first step was also used to successfully form the tungsten plugs.
  • This process used a novel polishing slurry comprising aluminum oxide (Al 2 O 3 ) abrasive particles and a basic mixture of H 2 O and H 2 O 2 . It was found that the second base of the mixture as described above, KOH or NH 4 OH, had little effect on the speed or quality of the etch.
  • H 2 O 2 is used to oxidize the tungsten surface, forming tungsten oxide. The formed tungsten oxide is subsequently removed by the polishing process, creating a fresh tungsten surface for continued surface reaction between H 2 O 2 and the tungsten surface.
  • the first embodiment of the first step describes the use of H 2 O 2 and a second chemical component such as KOH or NH 4 OH which served to remove tungsten oxide chemically. It has been found that the tungsten oxide is sufficiently removed by the mechanical polishing effect of the abrasive within the slurry. With this new slurry, a polishing rate of 1K ⁇ /minute to 3K ⁇ /minute was found, depending on the H 2 O 2 to H 2 O ratio. A 100% solution of H 2 O 2 removed the tungsten oxide at about 3K ⁇ /minute while a 1:1 ratio by volume of H 2 O 2 to H 2 O removed the tungsten oxide at around 0.5K ⁇ /minute. Using the inventive slurry, a good tungsten to insulation (i.e. BPSG) polishing selectivity was obtained, and was determined to be approximately 20:1.
  • a good tungsten to insulation i.e. BPSG
  • the second wafer polishing step which removed the oxide 10 was continued to remove additional insulation material 10 and to produce a convexly rounded protruding tungsten plug 40 as shown in FIG. 4 , although this is not a requirement of the inventive process.
  • the rounded surfaces of the tungsten plugs 40 provided surfaces which were easily coupled to layers of aluminum (not shown) formed by sputtering or other means during subsequent wafer processing steps. Tungsten plugs with a diameter of less than 1 micron were produced
  • the inventive two-step process resulted in more planarized wafer surface due to the oxide polishing in the second step.

Abstract

A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in recessed plugs which are not easily or reliably coupled with subsequent layers of sputtered aluminum or other conductors. The inventive process uses a two-step chemical mechanical planarization technique. An insulation layer with contact holes is formed, and a metal layer is formed thereover. A polishing pad rotates against the wafer surface while a slurry selective to the metal removes the metal overlying the wafer surface, and also recesses the metal within the contact holes due to the chemical nature and fibrous element of the polishing pad. A second CMP step uses a slurry having an acid or base selective to the insulation material to remove the insulator from around the metal. The slurry also contains abrasive materials which polish the metal surface so as to make the metal level with the insulation layer surface. Removal of the insulation material can continue, thereby producing a slightly protruding plug which results in a more reliable contact from the substrate to subsequent conductive layers.

Description

FIELD OF THE INVENTION
The disclosed invention relates to the field of semiconductor manufacture. More specifically, a chemical mechanical wafer polishing process is described which produces improved flush and protruding tungsten plugs rather than the recessed plugs produced by conventional tungsten plug etchback techniques. Coupling with subsequent layers of conductive material such as sputtered aluminum is therefore more easily accomplished.
BACKGROUND OF THE INVENTION
Integrated circuits are chemically and physically integrated into a substrate, such as a silicon or gallium arsenide wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication. Up to a thousand or more devices are formed simultaneously on the surface of a single wafer of semiconductor material.
It is essential for high device yields to start with a flat semiconductor wafer. If the process steps of device fabrication are performed on a wafer surface that is not uniform, various problems can occur which may result in a large number of inoperable devices.
Previous methods used to ensure the wafer surface planarity included forming an oxide such as borophosphosilicate glass (BPSG) layer on the wafer surface, then heating the wafer to reflow and planarize the oxide layer. This “reflow” method of planarizing the wafer surface was sufficient with fairly large device geometries, but as the technology allowed for smaller device feature sizes, this method produced unsatisfactory results.
Another method which has been used to produce a planar wafer surface is to use the oxide reflow method described above, then spin coat the wafer with photoresist. The spin coating of the material on the wafer surface fills the low points and produces a planar surface from which to start. Next, a dry etch, which removes photoresist and oxide at a rate sufficiently close to 1:1, removes the photoresist and the high points of the wafer, thereby producing a planar oxide layer on the wafer surface.
Most recently, chemical mechanical planarization (CMP) processes have been used to planarize the surface of wafers in preparation for device fabrication. The CMP process involves holding a thin flat wafer of semiconductor material against a rotating wetted polishing pad surface under a controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution used as a chemical etch component in combination with alumina or silica particles used as an abrasive etch component may be used. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft wetted pad material such as blown polyurethane.
Such apparatus for polishing thin flat semiconductor wafers are well known in the art. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh, for instance, disclose such apparatus.
Deposited conductors are an integral part of every integrated circuit, and provide the role of surface wiring for conducting current. Specifically, the deposited conductors are used to wire together the various components that are formed in the surface of the wafer. Electronic devices formed within the wafer have active areas which must be contacted with conductive runners, such as metal. Typically, a layer of insulating material is applied stop the wafer and selectively masked to provide contact opening patterns. The layer is subsequently etched, for instance with a reactive ion etch (RIE), to provide contact openings from the upper surface of the insulating layer down into the wafer to provide electrical contact with selected active areas.
Certain metals and allows deposited by vacuum evaporation and sputtering techniques do not provide the most desired coverage within the contact openings when applied to the surface of a wafer. An example of a metal which typically provides such poor coverage is sputtered aluminum, or alloys of aluminum with silicon and/or copper. One metallization scheme which does provide good coverage within contact vias is tungsten deposited by the chemical vapor deposition (CVD) technique. Tungsten is not, however, as conductive as aluminum. Accordingly, a tungsten layer is typically etched or polished back to provide a plug within the insulation layer, the plug having a flat upper surface which is flush with the surface of the insulator. A layer of aluminum would subsequently be applied atop the wafer surface to contact the plug. The aluminum layer is then selectively etched to provide the desired interconnecting runners coupling the tungsten with other circuitry.
FIG. 1 shows a desirable outcome of a process to produce a tungsten plug. In accordance with wafer fabrication techniques, a material such as an oxide layer 10 covers the material of the wafer surface 12. The tungsten 14 which fills the contact hole 16 in the oxide material 10 is level with the surface of the oxide layer. FIG. 2 illustrates one problem with present methods of tungsten etch backs, an over etching within the contacts which recesses the tungsten 14 within the contact hole 16 in the wafer surface 10. This can provide for poor contact between the tungsten plug 14 with the aluminum or aluminum alloy layer (not shown) which would be subsequently deposited by sputtering. It is difficult to provide reliable contacts between the aluminum and the recessed tungsten plugs which result from conventional tungsten etchback techniques such as reactive ion etching (RIE).
In addition to RIE, another conventional tungsten etch back means includes a single-step CMP etchback using a polishing slurry and polishing pad. A layer of tungsten is formed by CVD or other means onto the wafer surface, thereby filling the contact holes in the insulation layer with tungsten. The surface of the wafer is polished to remove the tungsten overlying the surface of the wafer, which leaves the contact holes filled with tungsten. Due to the chemical nature of the slurry and compressible nature of the polishing pad, a certain amount of the tungsten material is removed from the contact holes, leaving the recessed tungsten structure 14 of FIG. 2.
U.S. Pat. No. 4,992,135 describes a method of etching back tungsten layers, which is incorporated herein by reference.
A need remains for improved methods of etching back tungsten layers on semiconductor wafers to allow for good contact with layers of metal or other conductive material which are subsequently deposited.
SUMMARY OF THE INVENTION
An object of the invention is to provide a process for forming contacts (plugs) of tungsten or other conductive materials that results in a more uniform, nonrecessed plug.
Another object of the invention is to provide a process for forming a plug of tungsten or other conductive material which results in a better surface to connect with another material such as a layer of aluminum by virtue of the more uniform, nonrecessed characteristics of the plug.
Yet another object of the invention is to provide a process for forming a plug of tungsten of other conductive material which can produce uniform, protruding plugs which allow for easier coupling with subsequent layers of conductive material than recessed plugs produced by conventional methods.
These objects of the invention are realized with an inventive two-step process of plug formation which uses chemical mechanical planarization (CMP) technology. A substrate of a material such as silicon having a layer of oxide (BPSG) is manufactured with contact holes therein, and a layer of metal such as tungsten is formed upon the substrate to fill the contact holes. A first CMP step, which is selective to the plug material, removes the upper layer of tungsten from the oxide surface while removing very little or no oxide from the wafer surface. During the last phase of the step which completely removes metal residue including barriers such as titanium nitride and titanium layers over the surface of the wafer, a portion of the tungsten below the level of the oxide surface is also removed, thereby recessing the tungsten plugs. This recessed plug, which is typical of conventional plug formation, is difficult to couple with a subsequent layer of metal or other material.
Therefore, a second CMP step which is selective to oxide material of the wafer surface, removes a portion of the insulation material to a level even with, or slightly below, the level of the tungsten plugs. To shape the tungsten extending above the surface so as to remove the concave shape resulting from the plug recess, the slurry of the oxide CMP can be formulated so as to remove a desired amount of tungsten. This can be accomplished by increasing the amount of etchant that is selective to the material of the plug.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-section of a desirable plug;
FIG. 2 is a cross-section of a recessed plug typically produced by a conventional CMP process;
FIG. 3 is a cross-section of a first step in the inventive process showing a layer of conductive material (such as tungsten) formed over the substrate; and
FIG. 4 is a cross-section of a protruding plug embodiment which can be produced by the inventive two-step process.
DETAILED DESCRIPTION OF THE INVENTION
The inventive process formed plugs from a conductive material (in the instant case tungsten) which were even with, and in a second embodiment slightly protruding from, a an insulation layer comprising an insulating material or a dielectric material, such as an oxide material (BPSG in the instant case, or other materials such as SiO2) or a nonoxide material (such as polyimide). The shape of the protruding plugs was controllably convex and allowed for an improved surface with which to couple a subsequent layer of conductive material such as aluminum.
The inventive process began with a wafer as shown in FIG. 3 fabricated by means known in the art having a layer of insulation material 10 such as an oxide (BPSG) which is approximately 2-3 μm thick. Contact holes 16 were formed into material 10 by any conventional process. A layer of metal 30, tungsten in the instant case, filled the contact holes 16 and extended over the insulation 10 surface. The tungsten layer 30 was formed by chemical vapor deposition (CVD) to most efficiently fill the contact holes 16, but workable methods known in the art are also possible. The layer of tungsten 30 over the oxide surface 10 in the instant case was approximately 10KÅ thick, but other thicknesses are possible as the layer is removed in subsequent wafer processing steps.
Next, the wafer was subjected to a chemical mechanical polishing (CMP) process which was selective to tungsten. The process employed a polishing pad mounted on a rotating platen. A slurry, containing abrasive particles such as Al2O3 and etchants such as H2O2 and either KOH or NH4OH, or other acids or bases, removed the tungsten at a predictable rate, while removing very little of the insulation. This process is described in U.S. Pat. No. 4,992,135. The polishing pad was held in contact with the wafer surface at a pressure of 7-9 psi for approximately 5-10 minutes. This process resulted in the structure of FIG. 2, a tungsten plug 14 within the contact holes 16 in the oxide 10. The tungsten 14 was slightly recessed at this stage in the process as shown resulting from the mechanical erosion of the tungsten from the fibers of the polishing pad. The magnitude of the recess typically varied from approximately 0.5KÅ to 3KÅ below the surface of the oxide 10. To selectively remove the tungsten, the chemical component of the slurry oxidized the tungsten, and the tungsten oxide was removed mechanically with the abrasive material in the slurry. Additionally, a small portion of the tungsten was removed by the abrasive. In any case, the CMP process used is selective to tungsten and leaves the insulation layer relatively unaffected.
The second step involved a CMP process which was selective to the material of the insulation layer, although it may be desirable to remove a small amount of the tungsten as well to either to polish the tungsten or to provide a convex protruding plug. If tungsten is removed at this step, it is done at a much slower rate than the removal of the insulation material. A slurry containing etchants selective to the oxide was added between a rotating polish pad and the wafer surface. The colloidal silica slurry used in the instant case contained abrasives as described above, and also etchants selective to the oxide, such as a basic mixture of H2O and KOH. In most cases, if other nonoxide insulators are used other chemical etchants would be required. As shown in FIG. 1, the insulation material 10 was removed from around the tungsten plugs 14, resulting in a plug 14 which was even with the surface of the insulation material 10. The action of the pad abraded the surface of the tungsten and the oxide material sufficient to polish out surface irregularities. The tungsten was polished at a slow rate, less than 50Å/minute, but the oxide underlayer was polished at a high rate, greater than 2500Å/minute. Typically, a layer of 0.5KÅ-3KÅ of the insulation material is removed at the second CMP step, as this is the usual extent to which the tungsten is recessed within the contact hole.
A second embodiment of the first step was also used to successfully form the tungsten plugs. This process used a novel polishing slurry comprising aluminum oxide (Al2O3) abrasive particles and a basic mixture of H2O and H2O2. It was found that the second base of the mixture as described above, KOH or NH4OH, had little effect on the speed or quality of the etch. In this novel slurry, H2O2 is used to oxidize the tungsten surface, forming tungsten oxide. The formed tungsten oxide is subsequently removed by the polishing process, creating a fresh tungsten surface for continued surface reaction between H2O2 and the tungsten surface. In contrast, the first embodiment of the first step describes the use of H2O2 and a second chemical component such as KOH or NH4OH which served to remove tungsten oxide chemically. It has been found that the tungsten oxide is sufficiently removed by the mechanical polishing effect of the abrasive within the slurry. With this new slurry, a polishing rate of 1KÅ/minute to 3KÅ/minute was found, depending on the H2O2 to H2O ratio. A 100% solution of H2O2 removed the tungsten oxide at about 3KÅ/minute while a 1:1 ratio by volume of H2O2 to H2O removed the tungsten oxide at around 0.5KÅ/minute. Using the inventive slurry, a good tungsten to insulation (i.e. BPSG) polishing selectivity was obtained, and was determined to be approximately 20:1.
In other embodiment of the invention, the second wafer polishing step which removed the oxide 10 was continued to remove additional insulation material 10 and to produce a convexly rounded protruding tungsten plug 40 as shown in FIG. 4, although this is not a requirement of the inventive process. The rounded surfaces of the tungsten plugs 40 provided surfaces which were easily coupled to layers of aluminum (not shown) formed by sputtering or other means during subsequent wafer processing steps. Tungsten plugs with a diameter of less than 1 micron were produced
In addition to producing uniform plugs which were not recessed within the insulation layer, the inventive two-step process resulted in more planarized wafer surface due to the oxide polishing in the second step.
What have been described are specific configurations of the invention, as applied to particular embodiments. Clearly, variations can be made to the original methods and materials described in this document for adapting the invention to other embodiments. For example, insulators other than those comprising oxide could be used, for example Si3N4. For these nonoxide insulators, however, a chemical etchant other than the KOH and water solution would most likely be required. Also, various acids, bases, and abrasive materials can be used in the CMP slurry to maintain the scope and spirit of the invention. Therefore, the invention should be read as limited only by the appended claims.

Claims (46)

1. A method of producing a conductive plug in an insulation layer, comprising the steps of:
a) removing a portion of the insulation layer to form a contact hole within the insulation layer;
b) applying a layer of conductive material to a surface of the insulation layer, thereby filling said contact hole with said conductive material and resulting in a layer of said conductive material over said insulation layer surface;
c) removing at least a portion of said conductive material from said surface of the insulation layer and leaving said contact hole substantially filled with said conductive material, said removing being performed by chemical mechanical planarization with a slurry comprising an abrasive material and an oxidizing component, said oxidizing component comprising hydrogen peroxide and water wherein a ratio by volume of hydrogen peroxide to water is in the range of 1:0 to 1:1;
d) removing some of the insulation layer to lower said insulation layer surface with respect to an upper surface of said conductive material.
2. The method of claim 1, wherein said contact hole is formed by etching.
3. The method of claim 1, wherein said layer of conductive layer material is formed by chemical vapor deposition.
4. The method of claim 1, wherein said abrasive material comprises aluminum oxide.
5. The method of claim 1, wherein step d) is done by chemical mechanical planarization.
6. The method of claim 5, wherein step d) comprises the use of a slurry having an a second abrasive material and a compound which selectively removes a portion of the insulation layer.
7. The method of claim 6, wherein said second abrasive material comprises silica.
8. The method of claim 6, wherein said compound comprises potassium hydroxide.
9. The method of claim 1, wherein between 0.5KÅ and 3KÅ of the substrate material insulation layer is removed during step d).
10. The method of claim 1, wherein step d) continues until said insulation layer surface is substantially even with said upper surface of said conductive material.
11. The method of claim 1, wherein step d) continues until said insulation layer surface is lower than said upper surface of said conductive material, thereby resulting in said conductive material protruding from said insulation layer surface.
12. The method of claim 1, wherein the plug formed comprises tungsten.
13. The method of claim 12, wherein during step c) a portion of said tungsten reacts with said hydrogen peroxide to form tungsten oxide.
14. The method of claim 1, wherein the insulation layer comprises an insulating a dielectric layer material.
15. The method of claim 14, wherein between 0.5 KÅ and 3KÅ of the substrate material insulation layer is removed in step d).
16. The method of claim 1, wherein the substrate material insulation layer comprises polyimide.
17. A method of chemical mechanical planarization of an oxide material, comprising the steps of:
a) etching a portion of the oxide material to form a contact hole within said oxide material;
b) applying a layer of tungsten to a surface of the oxide material, thereby filling said contact hole with said tungsten and resulting in a layer of said tungsten material over said oxide material;
c) chemically and mechanically removing at least a portion of said tungsten from said surface of said oxide material with a first solution comprising H2O2 water, and an abrasive material, and leaving said contact hole substantially filed with said tungsten, wherein a ratio by a volume of said H2O2 to said water is in the range of 1:0 to 1:1;
d) chemically and mechanically removing a portion of the oxide material with a second solution comprising KOH and an abrasive material to lower said surface of said oxide material with respect to an upper surface of said tungsten;
whereby a plug of tungsten is formed in said contact hole.
18. The method of claim 17, wherein between 0.5KÅ and 3KÅ of said oxide material is removed during step d).
19. The method of claim 17, wherein step d) continues until said surface of said oxide material is substantially even with said upper surface of said tungsten.
20. The method of claim 17, wherein step d) continues until said surface of said oxide material is lower than said upper surface of said conductive material, thereby resulting in said tungsten protruding from the oxide material.
21. A method of producing a conductive plug in an insulation layer, comprising the steps of:
a) removing a portion of the insulation layer to form a contact hole within the insulation layer;
b) applying a layer of conductive material to a surface of the insulation layer, thereby filling said contact hole with said conductive material and resulting in a layer of said conductive material over said insulation layer surface;
c) removing at least a portion of said conductive material from said surface of the insulation layer and leaving said contact hole substantially filled with said conductive material;
d) removing some of the insulation layer by chemical mechanical planarization using a slurry, said slurry having an abrasive material and a compound which selectively removes a portion of said insulation layer to lower said insulation layer surface with respect to an upper surface of said conductive material;
e) removing at least a portion of said conductive material from said surface of the insulation layer and leaving said contact hole substantially filled with said conductive material, said removing being performed by chemical mechanical planarization with a slurry comprising an abrasive material and an oxidizing component and a carrier, wherein a ratio by volume of the oxidizing component to the carrier is in the range of 1:0 to 1:1;
f) removing some of the insulation layer to lower said insulation layer surface with respect to an upper surface of said conductive material.
22. The method of claim 21, wherein said abrasive material comprises silica.
23. The method of claim 21, wherein said compound comprises potassium hydroxide.
24. A method of producing a conductive plug in an insulation layer, comprising the steps of:
a) removing a portion of the insulation layer to form a contact hole within the insulation layer;
b) applying a layer of conductive material to a surface of the insulation layer, thereby filling said contact hole with said conductive material and resulting in a layer of said conductive material over said insulation layer surface;
c) removing at least a portion of said conductive material from said surface of the insulation layer and leaving said contact hole substantially filled with said conductive material, said removing being performed by chemical mechanical planarization with a slurry comprising an abrasive material and an oxidizing component, said oxidizing component consisting essentially of hydrogen peroxide and, optionally, water in a ratio by volume of water to hydrogen peroxide of up to 1:1; and
d) removing some of the insulation layer to lower said insulation layer surface with respect to an upper surface of said conductive material.
25. The method of claim 24, wherein said contact hole is formed by etching.
26. The method of claim 24, wherein said conductive layer is formed by chemical vapor deposition.
27. The method of claim 24, wherein said abrasive material comprises aluminum oxide.
28. The method of claim 24, wherein step d) is done by chemical mechanical planarization.
29. The method of claim 28, wherein step d) comprises the use of a slurry having a second abrasive material and a compound which selectively removes a portion of the insulation layer.
30. The method of claim 29, wherein said second abrasive material comprises silica.
31. The method of claim 29, wherein said compound comprises potassium hydroxide.
32. The method of claim 24, wherein between 0.5KÅ AND 3KÅ of the insulation layer is removed during step d).
33. The method of claim 24, wherein step d) continued until said insulation layer surface is substantially even with said upper surface of said conductive material.
34. The method of claim 24, wherein step d) continues until said insulation layer surface is lower than said upper surface of said conductive material, thereby resulting in said conductive material protruding from said insulation layer surface.
35. The method of claim 24, wherein the plug formed comprises tungsten.
36. The method of claim 35, wherein during step c) a portion of said tungsten reacts with said hydrogen peroxide to form tungsten oxide.
37. The method of claim 24, wherein the insulation layer comprises a dielectric material.
38. The method of claim 37, wherein between 0.5KÅ and 3KÅ of the insulation layer is removed in step d).
39. The method of claim 24, wherein the insulation layer comprises polyimide.
40. A method of chemical mechanical planarization of an oxide material, comprising the steps of:
a) etching a portion of the oxide material to form a contact hole within said oxide material;
b) applying a layer of tungsten to a surface of the oxide material, thereby filling said contact hole with said tungsten and resulting in a layer of said tungsten material over said oxide material;
c) chemically and mechanically removing at least a portion of said tungsten from said surface of said oxide material with a first solution and an abrasive material, and leaving said contact hole substantially filled with said tungsten, said first solution consisting essentially of hydrogen peroxide and, optionally, water in a ratio by volume of water to hydrogen peroxide of up to 1:1;
d) chemically and mechanically removing a portion of the oxide material with a second solution comprising KOH and an abrasive material to lower said surface of said oxide material with respect to an upper surface of said tungsten; and
whereby a plug of tungsten is formed in said contact hole.
41. The method of claim 40, wherein between 0.5KÅ and 3KÅ and said oxide material is removing during step d).
42. The method of claim 40, wherein step d) continues until said surface of said oxide material is substantially even with said upper surface of said tungsten.
43. The method of claim 40, wherein step d) continues until said surface of said oxide material is lower than said upper surface of said conductive material, thereby resulting in said tungsten protruding from the oxide material.
44. A method of producing a conductive plug in an insulation layer, comprising the steps of:
a) removing a portion of the insulation layer to form a contact hole within the insulation layer;
b) applying a layer of conductive material to a surface of the insulation layer, thereby filling said contact hole with said conductive material and resulting in a layer of said conductive material over said insulation layer surface;
c) removing at least a portion of said conductive material from said surface of the insulation layer and leaving said contact hole substantially filled with said conductive material, said removing being performed by chemical mechanical planarization with a slurry comprising an abrasive material and a solution, said solution consisting essentially of an oxidizing component and, optionally, a carrier in a ratio by volume of carrier to oxidizing component of up to 1:1; and
d) removing some of the insulation layer to lower said insulation layer by chemical mechanical planarization using a slurry, said slurry having an abrasive material and a compound which selectively removes a portion of said insulation layer surface with respect to an upper surface of said conductive material.
45. The method of claim 44, wherein said abrasive material comprises silica.
46. The method of claim 44, wherein said compound comprises potassium hydroxide.
US08/527,954 1992-01-24 1995-09-14 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs Expired - Lifetime USRE39126E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/527,954 USRE39126E1 (en) 1992-01-24 1995-09-14 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/824,980 US5244534A (en) 1992-01-24 1992-01-24 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US08/527,954 USRE39126E1 (en) 1992-01-24 1995-09-14 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/824,980 Reissue US5244534A (en) 1992-01-24 1992-01-24 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

Publications (1)

Publication Number Publication Date
USRE39126E1 true USRE39126E1 (en) 2006-06-13

Family

ID=25242798

Family Applications (2)

Application Number Title Priority Date Filing Date
US07/824,980 Ceased US5244534A (en) 1992-01-24 1992-01-24 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US08/527,954 Expired - Lifetime USRE39126E1 (en) 1992-01-24 1995-09-14 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US07/824,980 Ceased US5244534A (en) 1992-01-24 1992-01-24 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

Country Status (3)

Country Link
US (2) US5244534A (en)
JP (2) JPH0821557B2 (en)
DE (1) DE4301451C2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090186995A1 (en) * 2008-01-18 2009-07-23 Jo Ann Canich Production of Propylene-Based Polymers
US20090239379A1 (en) * 2008-03-24 2009-09-24 Wayne Huang Methods of Planarization and Electro-Chemical Mechanical Polishing Processes

Families Citing this family (199)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604158A (en) * 1993-03-31 1997-02-18 Intel Corporation Integrated tungsten/tungsten silicide plug process
US5937327A (en) * 1993-04-23 1999-08-10 Ricoh Company, Ltd. Method for improving wiring contact in semiconductor devices
US5391258A (en) * 1993-05-26 1995-02-21 Rodel, Inc. Compositions and methods for polishing
US5938504A (en) 1993-11-16 1999-08-17 Applied Materials, Inc. Substrate polishing apparatus
US5643053A (en) * 1993-12-27 1997-07-01 Applied Materials, Inc. Chemical mechanical polishing apparatus with improved polishing control
US5582534A (en) * 1993-12-27 1996-12-10 Applied Materials, Inc. Orbital chemical mechanical polishing apparatus and method
US5501755A (en) * 1994-02-18 1996-03-26 Minnesota Mining And Manufacturing Company Large area multi-electrode radiation detector substrate
US5650039A (en) * 1994-03-02 1997-07-22 Applied Materials, Inc. Chemical mechanical polishing apparatus with improved slurry distribution
US6027997A (en) * 1994-03-04 2000-02-22 Motorola, Inc. Method for chemical mechanical polishing a semiconductor device using slurry
US5527423A (en) * 1994-10-06 1996-06-18 Cabot Corporation Chemical mechanical polishing slurry for metal layers
US5599739A (en) * 1994-12-30 1997-02-04 Lucent Technologies Inc. Barrier layer treatments for tungsten plug
US5489552A (en) * 1994-12-30 1996-02-06 At&T Corp. Multiple layer tungsten deposition process
JP3318813B2 (en) * 1995-02-13 2002-08-26 ソニー株式会社 Multi-layer wiring formation method
US5658829A (en) 1995-02-21 1997-08-19 Micron Technology, Inc. Semiconductor processing method of forming an electrically conductive contact plug
US5580821A (en) * 1995-02-21 1996-12-03 Micron Technology, Inc. Semiconductor processing method of forming an electrically conductive contact plug
WO1996027206A2 (en) * 1995-02-24 1996-09-06 Intel Corporation Polysilicon polish for patterning improvement
US5527736A (en) * 1995-04-03 1996-06-18 Taiwan Semiconductor Manufacturing Co. Dimple-free tungsten etching back process
US6069081A (en) * 1995-04-28 2000-05-30 International Buiness Machines Corporation Two-step chemical mechanical polish surface planarization technique
US5668063A (en) * 1995-05-23 1997-09-16 Watkins Johnson Company Method of planarizing a layer of material
US5578529A (en) * 1995-06-02 1996-11-26 Motorola Inc. Method for using rinse spray bar in chemical mechanical polishing
US5614444A (en) * 1995-06-06 1997-03-25 Sematech, Inc. Method of using additives with silica-based slurries to enhance selectivity in metal CMP
US6110820A (en) * 1995-06-07 2000-08-29 Micron Technology, Inc. Low scratch density chemical mechanical planarization process
US6046110A (en) * 1995-06-08 2000-04-04 Kabushiki Kaisha Toshiba Copper-based metal polishing solution and method for manufacturing a semiconductor device
JP3108861B2 (en) * 1995-06-30 2000-11-13 キヤノン株式会社 Active matrix substrate, display device using the substrate, and manufacturing method thereof
US5763325A (en) * 1995-07-04 1998-06-09 Fujitsu Limited Fabrication process of a semiconductor device using a slurry containing manganese oxide
US5976971A (en) * 1995-07-19 1999-11-02 Ricoh Company, Ltd. Fabrication process of a semiconductor device having an interconnection structure
US5693239A (en) * 1995-10-10 1997-12-02 Rodel, Inc. Polishing slurries comprising two abrasive components and methods for their use
US5726099A (en) * 1995-11-07 1998-03-10 International Business Machines Corporation Method of chemically mechanically polishing an electronic component using a non-selective ammonium persulfate slurry
US5885899A (en) * 1995-11-14 1999-03-23 International Business Machines Corporation Method of chemically mechanically polishing an electronic component using a non-selective ammonium hydroxide slurry
US5573633A (en) * 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
JPH09139368A (en) * 1995-11-14 1997-05-27 Sony Corp Chemically and mechanically polishing method
JPH09148431A (en) * 1995-11-21 1997-06-06 Nec Corp Manufacture of semiconductor device
US5994220A (en) 1996-02-02 1999-11-30 Micron Technology, Inc. Method for forming a semiconductor connection with a top surface having an enlarged recess
US6420786B1 (en) 1996-02-02 2002-07-16 Micron Technology, Inc. Conductive spacer in a via
US6406998B1 (en) * 1996-02-05 2002-06-18 Micron Technology, Inc. Formation of silicided contact by ion implantation
US6075606A (en) 1996-02-16 2000-06-13 Doan; Trung T. Endpoint detector and method for measuring a change in wafer thickness in chemical-mechanical polishing of semiconductor wafers and other microelectronic substrates
US5769689A (en) * 1996-02-28 1998-06-23 Rodel, Inc. Compositions and methods for polishing silica, silicates, and silicon nitride
US5827780A (en) * 1996-04-01 1998-10-27 Hsia; Liang Choo Additive metalization using photosensitive polymer as RIE mask and part of composite insulator
US5940729A (en) * 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
US5693561A (en) * 1996-05-14 1997-12-02 Lucent Technologies Inc. Method of integrated circuit fabrication including a step of depositing tungsten
US5948700A (en) * 1996-05-20 1999-09-07 Chartered Semiconductor Manufacturing Ltd. Method of planarization of an intermetal dielectric layer using chemical mechanical polishing
US5904563A (en) * 1996-05-20 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal alignment mark generation
JP3076244B2 (en) * 1996-06-04 2000-08-14 日本電気株式会社 Polishing method of multilayer wiring
US5993686A (en) * 1996-06-06 1999-11-30 Cabot Corporation Fluoride additive containing chemical mechanical polishing slurry and method for use of same
WO1997048132A1 (en) * 1996-06-11 1997-12-18 Advanced Micro Devices, Inc. Method for forming co-planar conductor and insulator features using chemical mechanical planarization
DE69709870T2 (en) * 1996-07-18 2002-08-22 Advanced Micro Devices Inc USE OF AN ETCHING LAYER IN AN INTEGRATED CIRCUIT FOR THE PRODUCTION OF STACKED ARRANGEMENTS
US5942449A (en) * 1996-08-28 1999-08-24 Micron Technology, Inc. Method for removing an upper layer of material from a semiconductor wafer
KR19980019046A (en) * 1996-08-29 1998-06-05 고사이 아키오 Abrasive composition and use of the same
US5916453A (en) * 1996-09-20 1999-06-29 Fujitsu Limited Methods of planarizing structures on wafers and substrates by polishing
US6033596A (en) * 1996-09-24 2000-03-07 Cabot Corporation Multi-oxidizer slurry for chemical mechanical polishing
US6039891A (en) * 1996-09-24 2000-03-21 Cabot Corporation Multi-oxidizer precursor for chemical mechanical polishing
US5783489A (en) * 1996-09-24 1998-07-21 Cabot Corporation Multi-oxidizer slurry for chemical mechanical polishing
US6413870B1 (en) * 1996-09-30 2002-07-02 International Business Machines Corporation Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby
US6020263A (en) * 1996-10-31 2000-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of recovering alignment marks after chemical mechanical polishing of tungsten
US5985746A (en) * 1996-11-21 1999-11-16 Lsi Logic Corporation Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
US6068787A (en) * 1996-11-26 2000-05-30 Cabot Corporation Composition and slurry useful for metal CMP
US5958288A (en) * 1996-11-26 1999-09-28 Cabot Corporation Composition and slurry useful for metal CMP
SG54606A1 (en) * 1996-12-05 1998-11-16 Fujimi Inc Polishing composition
JPH10172969A (en) 1996-12-06 1998-06-26 Nec Corp Manufacture of semiconductor device
US5759917A (en) 1996-12-30 1998-06-02 Cabot Corporation Composition for oxide CMP
US5981385A (en) * 1997-01-27 1999-11-09 Taiwan Semiconductor Manufacturing Company Ltd. Dimple elimination in a tungsten etch back process by reverse image patterning
US6048789A (en) * 1997-02-27 2000-04-11 Vlsi Technology, Inc. IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids
US6593657B1 (en) 1997-03-03 2003-07-15 Micron Technology, Inc. Contact integration article
US5756398A (en) * 1997-03-17 1998-05-26 Rodel, Inc. Composition and method for polishing a composite comprising titanium
JP3111928B2 (en) 1997-05-14 2000-11-27 日本電気株式会社 Polishing method of metal film
US5899738A (en) * 1997-05-23 1999-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the alignment marks without requiring extra masking steps
AU2792797A (en) * 1997-05-26 1998-12-30 Hitachi Limited Polishing method and semiconductor device manufacturing method using the same
KR100266749B1 (en) * 1997-06-11 2000-09-15 윤종용 A method of forming contact plug of semiconductor device
US5770103A (en) * 1997-07-08 1998-06-23 Rodel, Inc. Composition and method for polishing a composite comprising titanium
US6051495A (en) * 1997-10-31 2000-04-18 Advanced Micro Devices, Inc. Seasoning of a semiconductor wafer polishing pad to polish tungsten
US6008123A (en) * 1997-11-04 1999-12-28 Lucent Technologies Inc. Method for using a hardmask to form an opening in a semiconductor substrate
US6190237B1 (en) * 1997-11-06 2001-02-20 International Business Machines Corporation pH-buffered slurry and use thereof for polishing
US6362101B2 (en) * 1997-11-24 2002-03-26 United Microelectronics Corp. Chemical mechanical polishing methods using low pH slurry mixtures
US6093658A (en) * 1997-12-22 2000-07-25 Philips Electronics North America Corporation Method for making reliable interconnect structures
US6143642A (en) * 1997-12-22 2000-11-07 Vlsi Technology, Inc. Programmable semiconductor structures and methods for making the same
US6077762A (en) * 1997-12-22 2000-06-20 Vlsi Technology, Inc. Method and apparatus for rapidly discharging plasma etched interconnect structures
US5928968A (en) * 1997-12-22 1999-07-27 Vlsi Technology, Inc. Semiconductor pressure transducer structures and methods for making the same
US6153531A (en) * 1997-12-22 2000-11-28 Philips Electronics North America Corporation Method for preventing electrochemical erosion of interconnect structures
US6028004A (en) * 1998-01-06 2000-02-22 International Business Machines Corporation Process for controlling the height of a stud intersecting an interconnect
US5897426A (en) 1998-04-24 1999-04-27 Applied Materials, Inc. Chemical mechanical polishing with multiple polishing pads
US6051500A (en) * 1998-05-19 2000-04-18 Lucent Technologies Inc. Device and method for polishing a semiconductor substrate
US6300241B1 (en) 1998-08-19 2001-10-09 National Semiconductor Corporation Silicon interconnect passivation and metallization process optimized to maximize reflectance
US6066552A (en) * 1998-08-25 2000-05-23 Micron Technology, Inc. Method and structure for improved alignment tolerance in multiple, singularized plugs
US6203407B1 (en) 1998-09-03 2001-03-20 Micron Technology, Inc. Method and apparatus for increasing-chemical-polishing selectivity
US6093652A (en) * 1998-09-03 2000-07-25 Micron Technology, Inc. Methods of forming insulative plugs, and oxide plug forming methods
KR100292154B1 (en) * 1998-09-09 2001-06-01 황인길 Metal plug formation method of semiconductor device
JP2000091278A (en) 1998-09-10 2000-03-31 Nec Corp Manufacture of semiconductor device
US6221775B1 (en) 1998-09-24 2001-04-24 International Business Machines Corp. Combined chemical mechanical polishing and reactive ion etching process
US6008876A (en) * 1998-12-03 1999-12-28 National Semiconductor Corporation Polished self-aligned pixel for a liquid crystal silicon light valve
US5982472A (en) * 1998-12-14 1999-11-09 National Semiconductor Corporation Self-aligned pixel with support pillars for a liquid crystal light valve
US6261158B1 (en) 1998-12-16 2001-07-17 Speedfam-Ipec Multi-step chemical mechanical polishing
KR20000041399A (en) * 1998-12-22 2000-07-15 김영환 Chemical mechanical polishing method for planarization of semiconductor device
US6740590B1 (en) 1999-03-18 2004-05-25 Kabushiki Kaisha Toshiba Aqueous dispersion, aqueous dispersion for chemical mechanical polishing used for manufacture of semiconductor devices, method for manufacture of semiconductor devices, and method for formation of embedded writing
US6555466B1 (en) * 1999-03-29 2003-04-29 Speedfam Corporation Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers
US6235633B1 (en) 1999-04-12 2001-05-22 Taiwan Semiconductor Manufacturing Company Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process
US6589872B1 (en) 1999-05-03 2003-07-08 Taiwan Semiconductor Manufacturing Company Use of low-high slurry flow to eliminate copper line damages
US6375693B1 (en) 1999-05-07 2002-04-23 International Business Machines Corporation Chemical-mechanical planarization of barriers or liners for copper metallurgy
US6153526A (en) * 1999-05-27 2000-11-28 Taiwan Semiconductor Manufacturing Company Method to remove residue in wolfram CMP
US6488730B2 (en) 1999-07-01 2002-12-03 Cheil Industries, Inc. Polishing composition
JP4554011B2 (en) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
US6383934B1 (en) 1999-09-02 2002-05-07 Micron Technology, Inc. Method and apparatus for chemical-mechanical planarization of microelectronic substrates with selected planarizing liquids
US6306768B1 (en) 1999-11-17 2001-10-23 Micron Technology, Inc. Method for planarizing microelectronic substrates having apertures
US6372632B1 (en) 2000-01-24 2002-04-16 Taiwan Semiconductor Manufacturing Company Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer
TWI296006B (en) 2000-02-09 2008-04-21 Jsr Corp
US6498101B1 (en) 2000-02-28 2002-12-24 Micron Technology, Inc. Planarizing pads, planarizing machines and methods for making and using planarizing pads in mechanical and chemical-mechanical planarization of microelectronic device substrate assemblies
US6313038B1 (en) 2000-04-26 2001-11-06 Micron Technology, Inc. Method and apparatus for controlling chemical interactions during planarization of microelectronic substrates
US6387289B1 (en) 2000-05-04 2002-05-14 Micron Technology, Inc. Planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies
KR100517911B1 (en) * 2000-05-19 2005-10-04 주식회사 하이닉스반도체 Semiconductor fabrication method capable of preventing misalign between bottom electrode and storage node contact and oxidation of diffusion barrier layer
US6612901B1 (en) 2000-06-07 2003-09-02 Micron Technology, Inc. Apparatus for in-situ optical endpointing of web-format planarizing machines in mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies
US6520834B1 (en) * 2000-08-09 2003-02-18 Micron Technology, Inc. Methods and apparatuses for analyzing and controlling performance parameters in mechanical and chemical-mechanical planarization of microelectronic substrates
US6838382B1 (en) 2000-08-28 2005-01-04 Micron Technology, Inc. Method and apparatus for forming a planarizing pad having a film and texture elements for planarization of microelectronic substrates
US6736869B1 (en) 2000-08-28 2004-05-18 Micron Technology, Inc. Method for forming a planarizing pad for planarization of microelectronic substrates
US7074113B1 (en) * 2000-08-30 2006-07-11 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
US7129160B2 (en) * 2002-08-29 2006-10-31 Micron Technology, Inc. Method for simultaneously removing multiple conductive materials from microelectronic substrates
US7192335B2 (en) 2002-08-29 2007-03-20 Micron Technology, Inc. Method and apparatus for chemically, mechanically, and/or electrolytically removing material from microelectronic substrates
US6551935B1 (en) * 2000-08-31 2003-04-22 Micron Technology, Inc. Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods
US7094131B2 (en) 2000-08-30 2006-08-22 Micron Technology, Inc. Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material
US6592443B1 (en) * 2000-08-30 2003-07-15 Micron Technology, Inc. Method and apparatus for forming and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates
US7078308B2 (en) * 2002-08-29 2006-07-18 Micron Technology, Inc. Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate
US7153195B2 (en) 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for selectively removing conductive material from a microelectronic substrate
US7112121B2 (en) 2000-08-30 2006-09-26 Micron Technology, Inc. Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate
US7220166B2 (en) 2000-08-30 2007-05-22 Micron Technology, Inc. Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US7160176B2 (en) 2000-08-30 2007-01-09 Micron Technology, Inc. Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate
US7134934B2 (en) 2000-08-30 2006-11-14 Micron Technology, Inc. Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium
US6609947B1 (en) 2000-08-30 2003-08-26 Micron Technology, Inc. Planarizing machines and control systems for mechanical and/or chemical-mechanical planarization of micro electronic substrates
US7153410B2 (en) 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
US6623329B1 (en) 2000-08-31 2003-09-23 Micron Technology, Inc. Method and apparatus for supporting a microelectronic substrate relative to a planarization pad
US6652764B1 (en) 2000-08-31 2003-11-25 Micron Technology, Inc. Methods and apparatuses for making and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates
US6867448B1 (en) 2000-08-31 2005-03-15 Micron Technology, Inc. Electro-mechanically polished structure
US6383065B1 (en) 2001-01-22 2002-05-07 Cabot Microelectronics Corporation Catalytic reactive pad for metal CMP
JP3639223B2 (en) 2001-05-14 2005-04-20 松下電器産業株式会社 Method for forming buried wiring
KR100389927B1 (en) * 2001-06-07 2003-07-04 삼성전자주식회사 Semiconductor device having multilevel interconnections and method for manufacturing the same
US6589099B2 (en) 2001-07-09 2003-07-08 Motorola, Inc. Method for chemical mechanical polishing (CMP) with altering the concentration of oxidizing agent in slurry
US6811470B2 (en) 2001-07-16 2004-11-02 Applied Materials Inc. Methods and compositions for chemical mechanical polishing shallow trench isolation substrates
TW591089B (en) * 2001-08-09 2004-06-11 Cheil Ind Inc Slurry composition for use in chemical mechanical polishing of metal wiring
US6953389B2 (en) * 2001-08-09 2005-10-11 Cheil Industries, Inc. Metal CMP slurry compositions that favor mechanical removal of oxides with reduced susceptibility to micro-scratching
US6866566B2 (en) * 2001-08-24 2005-03-15 Micron Technology, Inc. Apparatus and method for conditioning a contact surface of a processing pad used in processing microelectronic workpieces
US6677239B2 (en) 2001-08-24 2004-01-13 Applied Materials Inc. Methods and compositions for chemical mechanical polishing
US6722943B2 (en) 2001-08-24 2004-04-20 Micron Technology, Inc. Planarizing machines and methods for dispensing planarizing solutions in the processing of microelectronic workpieces
US6666749B2 (en) 2001-08-30 2003-12-23 Micron Technology, Inc. Apparatus and method for enhanced processing of microelectronic workpieces
US6531384B1 (en) * 2001-09-14 2003-03-11 Motorola, Inc. Method of forming a bond pad and structure thereof
JP2003100869A (en) * 2001-09-27 2003-04-04 Toshiba Corp Semiconductor device and its manufacturing method
JP2003188254A (en) 2001-12-18 2003-07-04 Hitachi Ltd Semiconductor device and manufacturing method therefor
KR100442962B1 (en) * 2001-12-26 2004-08-04 주식회사 하이닉스반도체 Method for manufacturing of metal line contact plug of semiconductor device
US7004819B2 (en) 2002-01-18 2006-02-28 Cabot Microelectronics Corporation CMP systems and methods utilizing amine-containing polymers
US7199056B2 (en) * 2002-02-08 2007-04-03 Applied Materials, Inc. Low cost and low dishing slurry for polysilicon CMP
US7131889B1 (en) 2002-03-04 2006-11-07 Micron Technology, Inc. Method for planarizing microelectronic workpieces
KR100487917B1 (en) * 2002-05-20 2005-05-06 주식회사 하이닉스반도체 Chemical mechanical polishing method of semiconductor device
US6596640B1 (en) * 2002-06-21 2003-07-22 Intel Corporation Method of forming a raised contact for a substrate
US6869335B2 (en) * 2002-07-08 2005-03-22 Micron Technology, Inc. Retaining rings, planarizing apparatuses including retaining rings, and methods for planarizing micro-device workpieces
US7341502B2 (en) 2002-07-18 2008-03-11 Micron Technology, Inc. Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
US6860798B2 (en) 2002-08-08 2005-03-01 Micron Technology, Inc. Carrier assemblies, planarizing apparatuses including carrier assemblies, and methods for planarizing micro-device workpieces
US7094695B2 (en) 2002-08-21 2006-08-22 Micron Technology, Inc. Apparatus and method for conditioning a polishing pad used for mechanical and/or chemical-mechanical planarization
US7004817B2 (en) 2002-08-23 2006-02-28 Micron Technology, Inc. Carrier assemblies, planarizing apparatuses including carrier assemblies, and methods for planarizing micro-device workpieces
US7011566B2 (en) 2002-08-26 2006-03-14 Micron Technology, Inc. Methods and systems for conditioning planarizing pads used in planarizing substrates
US6924653B2 (en) * 2002-08-26 2005-08-02 Micron Technology, Inc. Selectively configurable microelectronic probes
US7008299B2 (en) 2002-08-29 2006-03-07 Micron Technology, Inc. Apparatus and method for mechanical and/or chemical-mechanical planarization of micro-device workpieces
US6841991B2 (en) * 2002-08-29 2005-01-11 Micron Technology, Inc. Planarity diagnostic system, E.G., for microelectronic component test systems
US7063597B2 (en) 2002-10-25 2006-06-20 Applied Materials Polishing processes for shallow trench isolation substrates
US7074114B2 (en) 2003-01-16 2006-07-11 Micron Technology, Inc. Carrier assemblies, polishing machines including carrier assemblies, and methods for polishing micro-device workpieces
US6884152B2 (en) * 2003-02-11 2005-04-26 Micron Technology, Inc. Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces
US6872132B2 (en) 2003-03-03 2005-03-29 Micron Technology, Inc. Systems and methods for monitoring characteristics of a polishing pad used in polishing micro-device workpieces
US7131891B2 (en) 2003-04-28 2006-11-07 Micron Technology, Inc. Systems and methods for mechanical and/or chemical-mechanical polishing of microfeature workpieces
US6935929B2 (en) 2003-04-28 2005-08-30 Micron Technology, Inc. Polishing machines including under-pads and methods for mechanical and/or chemical-mechanical polishing of microfeature workpieces
US20050022456A1 (en) * 2003-07-30 2005-02-03 Babu S. V. Polishing slurry and method for chemical-mechanical polishing of copper
US7186653B2 (en) * 2003-07-30 2007-03-06 Climax Engineered Materials, Llc Polishing slurries and methods for chemical mechanical polishing
US7030603B2 (en) 2003-08-21 2006-04-18 Micron Technology, Inc. Apparatuses and methods for monitoring rotation of a conductive microfeature workpiece
US7112122B2 (en) * 2003-09-17 2006-09-26 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
US20070284743A1 (en) * 2003-12-12 2007-12-13 Samsung Electronics Co., Ltd. Fabricating Memory Devices Using Sacrificial Layers and Memory Devices Fabricated by Same
US7265050B2 (en) * 2003-12-12 2007-09-04 Samsung Electronics Co., Ltd. Methods for fabricating memory devices using sacrificial layers
US7223693B2 (en) * 2003-12-12 2007-05-29 Samsung Electronics Co., Ltd. Methods for fabricating memory devices using sacrificial layers and memory devices fabricated by same
US7291556B2 (en) 2003-12-12 2007-11-06 Samsung Electronics Co., Ltd. Method for forming small features in microelectronic devices using sacrificial layers
US7255810B2 (en) * 2004-01-09 2007-08-14 Cabot Microelectronics Corporation Polishing system comprising a highly branched polymer
US7153777B2 (en) * 2004-02-20 2006-12-26 Micron Technology, Inc. Methods and apparatuses for electrochemical-mechanical polishing
US6971945B2 (en) * 2004-02-23 2005-12-06 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Multi-step polishing solution for chemical mechanical planarization
US7086927B2 (en) 2004-03-09 2006-08-08 Micron Technology, Inc. Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
US20050233563A1 (en) * 2004-04-15 2005-10-20 Texas Instruments Incorporated Recess reduction for leakage improvement in high density capacitors
US7066792B2 (en) 2004-08-06 2006-06-27 Micron Technology, Inc. Shaped polishing pads for beveling microfeature workpiece edges, and associate system and methods
US7033253B2 (en) 2004-08-12 2006-04-25 Micron Technology, Inc. Polishing pad conditioners having abrasives and brush elements, and associated systems and methods
US7566391B2 (en) 2004-09-01 2009-07-28 Micron Technology, Inc. Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media
CN100442108C (en) * 2004-09-15 2008-12-10 中芯国际集成电路制造(上海)有限公司 Aluminum cemical mechanical polishing eat-back for liquid crystal device on silicon
US20060088976A1 (en) * 2004-10-22 2006-04-27 Applied Materials, Inc. Methods and compositions for chemical mechanical polishing substrates
US8038752B2 (en) 2004-10-27 2011-10-18 Cabot Microelectronics Corporation Metal ion-containing CMP composition and method for using the same
US7778812B2 (en) * 2005-01-07 2010-08-17 Micron Technology, Inc. Selecting data to verify in hardware device model simulation test generation
US7264539B2 (en) 2005-07-13 2007-09-04 Micron Technology, Inc. Systems and methods for removing microfeature workpiece surface defects
US7323410B2 (en) * 2005-08-08 2008-01-29 International Business Machines Corporation Dry etchback of interconnect contacts
US7438626B2 (en) * 2005-08-31 2008-10-21 Micron Technology, Inc. Apparatus and method for removing material from microfeature workpieces
US7326105B2 (en) * 2005-08-31 2008-02-05 Micron Technology, Inc. Retaining rings, and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces
US7294049B2 (en) 2005-09-01 2007-11-13 Micron Technology, Inc. Method and apparatus for removing material from microfeature workpieces
US7799689B2 (en) * 2006-11-17 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd Method and apparatus for chemical mechanical polishing including first and second polishing
JP2008135452A (en) * 2006-11-27 2008-06-12 Fujimi Inc Polishing composition and polishing method
US7754612B2 (en) 2007-03-14 2010-07-13 Micron Technology, Inc. Methods and apparatuses for removing polysilicon from semiconductor workpieces
KR101477661B1 (en) * 2008-07-17 2014-12-31 삼성전자주식회사 Seam-free tungsten pattern using a tungsten regrowing and method for manufacturing the same
US8211325B2 (en) * 2009-05-07 2012-07-03 Applied Materials, Inc. Process sequence to achieve global planarity using a combination of fixed abrasive and high selectivity slurry for pre-metal dielectric CMP applications
JP2011029552A (en) * 2009-07-29 2011-02-10 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
US8575022B2 (en) * 2011-11-28 2013-11-05 International Business Machines Corporation Top corner rounding of damascene wire for insulator crack suppression
US9048410B2 (en) * 2013-05-31 2015-06-02 Micron Technology, Inc. Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls
US10163700B2 (en) * 2016-01-06 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming conductive structure using polishing process
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3841031A (en) * 1970-10-21 1974-10-15 Monsanto Co Process for polishing thin elements
US4193226A (en) * 1977-09-21 1980-03-18 Kayex Corporation Polishing apparatus
DD239927A3 (en) * 1981-08-12 1986-10-15 Werk Fernsehelektronik Veb TWO-STEP APPLICATION METHOD FOR TREATING A DEEP III-B DEEP V-SEMICONDUCTOR COMPONENTS
US4714686A (en) * 1985-07-31 1987-12-22 Advanced Micro Devices, Inc. Method of forming contact plugs for planarized integrated circuits
JPS6390838A (en) 1986-09-30 1988-04-21 ナームローゼ フェンノートチャップ フィリップス グロエイラムペンファブリーケン Manufacture of electrical mutual connection
JPS6417879A (en) * 1987-07-14 1989-01-20 Sumitomo Metal Mining Co Method for etching gallium phosphide crystal and liquid etchant used therefor
US4811522A (en) * 1987-03-23 1989-03-14 Gill Jr Gerald L Counterbalanced polishing apparatus
EP0343698A1 (en) 1988-04-22 1989-11-29 Koninklijke Philips Electronics N.V. Process for producing interconnect structures on a semiconductor device, especially on an LSI circuit
JPH0242728A (en) 1988-08-02 1990-02-13 Sony Corp Manufacture of semiconductor device
US4992135A (en) * 1990-07-24 1991-02-12 Micron Technology, Inc. Method of etching back of tungsten layers on semiconductor wafers, and solution therefore
US5055426A (en) * 1990-09-10 1991-10-08 Micron Technology, Inc. Method for forming a multilevel interconnect structure on a semiconductor wafer
JPH03244130A (en) 1990-02-22 1991-10-30 Sony Corp Manufacture of semiconductor device
US5063175A (en) 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US5137597A (en) * 1991-04-11 1992-08-11 Microelectronics And Computer Technology Corporation Fabrication of metal pillars in an electronic component using polishing
US5152868A (en) * 1990-03-06 1992-10-06 France Telecom Elastomer connector for integrated circuits or similar, and method of manufacturing same
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3841031A (en) * 1970-10-21 1974-10-15 Monsanto Co Process for polishing thin elements
US4193226A (en) * 1977-09-21 1980-03-18 Kayex Corporation Polishing apparatus
DD239927A3 (en) * 1981-08-12 1986-10-15 Werk Fernsehelektronik Veb TWO-STEP APPLICATION METHOD FOR TREATING A DEEP III-B DEEP V-SEMICONDUCTOR COMPONENTS
US4714686A (en) * 1985-07-31 1987-12-22 Advanced Micro Devices, Inc. Method of forming contact plugs for planarized integrated circuits
US5063175A (en) 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
JPS6390838A (en) 1986-09-30 1988-04-21 ナームローゼ フェンノートチャップ フィリップス グロエイラムペンファブリーケン Manufacture of electrical mutual connection
US4811522A (en) * 1987-03-23 1989-03-14 Gill Jr Gerald L Counterbalanced polishing apparatus
JPS6417879A (en) * 1987-07-14 1989-01-20 Sumitomo Metal Mining Co Method for etching gallium phosphide crystal and liquid etchant used therefor
EP0343698A1 (en) 1988-04-22 1989-11-29 Koninklijke Philips Electronics N.V. Process for producing interconnect structures on a semiconductor device, especially on an LSI circuit
US4936950A (en) * 1988-04-22 1990-06-26 U.S. Philips Corporation Method of forming a configuration of interconnections on a semiconductor device having a high integration density
USRE34583E (en) 1988-04-22 1994-04-12 U.S. Philips Corporation Method of forming a configuration of interconnections on a semiconductor device having a high integration density
JPH0242728A (en) 1988-08-02 1990-02-13 Sony Corp Manufacture of semiconductor device
JPH03244130A (en) 1990-02-22 1991-10-30 Sony Corp Manufacture of semiconductor device
US5152868A (en) * 1990-03-06 1992-10-06 France Telecom Elastomer connector for integrated circuits or similar, and method of manufacturing same
US4992135A (en) * 1990-07-24 1991-02-12 Micron Technology, Inc. Method of etching back of tungsten layers on semiconductor wafers, and solution therefore
US5055426A (en) * 1990-09-10 1991-10-08 Micron Technology, Inc. Method for forming a multilevel interconnect structure on a semiconductor wafer
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
US5137597A (en) * 1991-04-11 1992-08-11 Microelectronics And Computer Technology Corporation Fabrication of metal pillars in an electronic component using polishing

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Advanced Metallization for ULSI Applications", Proceedings of the Conference held Oct. 8-10, 1991.
J. J. Estabil et al., "Electromigration Improvements with Titanium Underlay and Overlay in Al(Cu) Metallurgy", VMIC Conference, pp. 242-248, Jun. 11-12, 1991.
Ronald R. Uttecht et al., "A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications", VMIC Conference, pp. 20-26, Jun. 11-12, 1991.
S. Wolf, "4.4.11 Chemical-Mechanical Polishing," Silicon Processing for the VLSI Era, vol. 2-Process Integration, pp. 238-239, 1990.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090186995A1 (en) * 2008-01-18 2009-07-23 Jo Ann Canich Production of Propylene-Based Polymers
US20090239379A1 (en) * 2008-03-24 2009-09-24 Wayne Huang Methods of Planarization and Electro-Chemical Mechanical Polishing Processes
US8974655B2 (en) 2008-03-24 2015-03-10 Micron Technology, Inc. Methods of planarization and electro-chemical mechanical polishing processes

Also Published As

Publication number Publication date
US5244534A (en) 1993-09-14
JPH0821557B2 (en) 1996-03-04
DE4301451C2 (en) 1999-12-02
JPH05275366A (en) 1993-10-22
JP3494275B2 (en) 2004-02-09
JPH10189602A (en) 1998-07-21
DE4301451A1 (en) 1993-08-05

Similar Documents

Publication Publication Date Title
USRE39126E1 (en) Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US5618381A (en) Multiple step method of chemical-mechanical polishing which minimizes dishing
US5173439A (en) Forming wide dielectric-filled isolation trenches in semi-conductors
KR100359552B1 (en) Combined chemical mechanical polishing and reactive ion etching process
US5913712A (en) Scratch reduction in semiconductor circuit fabrication using chemical-mechanical polishing
EP1011131B1 (en) Methods for enhancing the metal removal rate during the chemical-mechanical polishing process of a semiconductor
US6426288B1 (en) Method for removing an upper layer of material from a semiconductor wafer
US6103625A (en) Use of a polish stop layer in the formation of metal structures
US20010014525A1 (en) Process for forming trenches and contacts during the formation of a semiconductor memory device
JP3297359B2 (en) Method for planarizing semiconductor wafer
EP0696819A1 (en) Diamond-like carbon for use in VLSI and ULSI interconnect systems
KR100271769B1 (en) Method for manufacturing semiconductor device, etchant composition and semiconductor device for manufacturing semiconductor device therefor
JP2004534377A (en) A viscous protective overlay layer for planarizing integrated circuits
US6017803A (en) Method to prevent dishing in chemical mechanical polishing
KR100282240B1 (en) Method for polishing a semiconductor material using cmp(chemical mechanical polishing), slurry used for cmp, and method for manufacturing a semiconductor device
EP0424608B1 (en) Forming wide dielectric filled isolation trenches in semiconductors
US20060261041A1 (en) Method for manufacturing metal line contact plug of semiconductor device
US6251789B1 (en) Selective slurries for the formation of conductive structures
US20020182853A1 (en) Method for removing hard-mask layer after metal-CMP in dual-damascene interconnect structure
US6841470B2 (en) Removal of residue from a substrate
US5633207A (en) Method of forming a wiring layer for a semiconductor device
US6274480B1 (en) Method of Fabricating semiconductor device
US6609954B1 (en) Method of planarization
KR100440082B1 (en) A method for forming a conductive line of a semiconductor device
KR19980048378A (en) Planarization method of semiconductor device

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223