USRE38049E1 - Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing - Google Patents

Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing Download PDF

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USRE38049E1
USRE38049E1 US08/759,058 US75905896A USRE38049E US RE38049 E1 USRE38049 E1 US RE38049E1 US 75905896 A US75905896 A US 75905896A US RE38049 E USRE38049 E US RE38049E
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insulating layer
etch rate
recited
container
forming
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Charles H. Dennison
Michael A. Walker
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Round Rock Research LLC
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Micron Technology Inc
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Priority claimed from US07/973,092 external-priority patent/US5270241A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • This invention relates to semiconductor circuit memory storage devices and more particularly to a process for fabricating three-dimensional stacked capacitor structures that may be used in such storage devices as high-density dynamic random access memories (DRAMs).
  • DRAMs high-density dynamic random access memories
  • stacked storage cell design
  • a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer.
  • a cell constructed in this manner is known as a stacked capacitor cell (STC).
  • STC stacked capacitor cell
  • Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
  • SER soft error rate
  • FIG. 1 (a) on the same page shows a bird's eye-view of storage electrodes.
  • the storage node is formed by two polysilicon layers that form a core electrode encircled by a ring structure.
  • Capacitor dielectric film surrounds the whole surface of the storage node electrode and then is covered with a third polysilicon layer to form the top capacitor electrode and completes the storage cell.
  • This design can be fabricated using current methods and increases storage capacitance by as much as 200%.
  • the present invention develops an existing stacked capacitor fabrication process to construct and optimize a three-dimensional container stacked capacitor cell.
  • the capacitor's bottom plate (or storage node plate) is centered over a buried contact (or node contact) connected to an access transistor's diffusion area.
  • the method presented herein provides fabrication uniformity and repeatability of the three-dimensional container cell.
  • the invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process.
  • An existing capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor.
  • the capacitor design of the present invention defines a stacked capacitor storage cell that is used in a DRAM process, however it will be evident to one skilled in the art to incorporate these steps into other processes requiring volatile memory cells, such as VRAMs or the like.
  • the present invention develops the container capacitor by etching a contact opening into a low etch rate oxide.
  • the contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls.
  • a high etch-rate oxide such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container.
  • the high etch-rate oxide is planarized back to the thin poly by using Chemical Mechanical Polishing (CMP). This CMP step is selective such that oxide is removed with sufficient overetch and stops on the thin poly.
  • CMP Chemical Mechanical Polishing
  • the resuIting exposed poly is then removed to separate neighboring containers either through an isotropic wet poly etch or an additional CMP with the chemical aspect modified to now etch and selectively remove the poly and not the oxide.
  • the two oxides, having different etch rates, are then etched by a single wet dilute BOE etch step, thereby leaving a free-standing poly container cell, with all the inside (high etch rate) oxide removed, that is equal in height to the depth of the original contact opening.
  • a pre-determined amount of low etch rate oxide is removed, thereby leaving oxide surrounding the , container, poly for both structural support and process integration for further processing which requires oxide to be left above the word lines.
  • the present invention uses a higher etch-rate oxide inside the container to block the container poly etch.
  • This high etch rate oxide is completely removed during oxide etch back. This protects the container during processing without adding photoresist and introducing extra processing steps or unwarranted contaminants.
  • a standard CMP oxide etch is utilized that allows fabrication uniformity and repeatability across the wafer which cannot be achieved by resist filled container processes.
  • Another advantage of filling the container with high etch rate oxide is that the poly can be etched with a low cost, timed wet poly etch, while partially filled containers (as seen in FIG. 9 ), due to inherent recession of resist 92 height (to allow for sufficient process margin), will not allow a wet poly etch without loss in cell height 93 , loss in uniformity and repeatability across the wafer's surface. Because this invention can be etched isotropically at poly etch, it avoids the recessing (overetch of the storage poly container 93 in FIG. 9) and splintering effects caused by a dry etch poly process.
  • splintering effects 101 of storage node poly 93 result from a dry anisotropic etch (due to non-uniform etching of polycrystalline silicon 93 ) because the plasma etch reacts faster along heavily doped grain boundaries. Splinters 101 later tend to ‘break off’ in subsequent processing leading to contamination particulates.
  • the trenching of the poly leads to the side-walls of the poly container to be exposed, thus making it impossible to wet etch the oxide around the cell without translating the trenched poly horizontal portion of the etch into surrounding oxide 91 thereby leaving a ring of thin oxide around he the container cell.
  • the present invention also protects the vertical sidewall of the oxide form by covering it with poly, thereby making a horizontal wet oxide etch back possible.
  • all films which see etch processing, CMP or otherwise, are subsequently removed thereby acting as sacrificial films such that particles created during the CMP etch do not contaminate the inside of the poly containers.
  • FIG. 1 shows a gray scale reproduction of a SEM photograph of an array of poly containers 12 which demonstrates the uniformity and repeatability of poly containers 12 across substrate 11 that results from utilizing the process steps of the present invention discussed hereinafter.
  • FIG. 1 is a gray-scale reproduction of a SEM (Scanning Electronic Microscope) photograph of a cross-sectional view of an array of container poly rings;
  • FIG. 2 is a composite cross-sectional view of an in-process wafer portion depicting the beginning steps of the present invention, said steps comprising forming a planarized layer of low etch rate oxide, etching a buried contact and placing a thin layer of conformal poly;
  • FIG. 3 is a cross-sectional view of the in-process wafer portion of FIG. 2 after formation of a layer of high etch rate oxide;
  • FIG. 4 is a cross-sectional view of the in-process wafer portion of FIG. 3 after planarization of the high etch rate oxide;
  • FIG. 5 is a cross-sectional view of the in-process wafer portion of FIG. 4 following a wet etch back of the exposed thin poly layer;
  • FIG. 6 is a cross-sectional view of the in-process wafer portion of FIG. 5 following an etch of both low etch rate and high etch rate oxides;
  • FIG. 7 is a cross-sectional view of the in-process wafer portion of FIG. 6 following blanket formations of conformal cell dielectric and polysilicon, respectively;
  • FIG. 8 is a cross-sectional view of a storage cell created by the present invention when integrated into a stacked capacitor fabrication process.
  • FIG. 9 is a composite cross-sectional view of an in-process wafer portion depicting a container cell filled with photoresist prior to patterning.
  • FIG. 10 is a composite cross-sectional view of the in-process wafer portion of FIG. 9 depicting splintering of storage node poly and formation of a thin ring of oxide surrounding the storage node poly following an anisotropic etching to pattern a container cell.
  • the invention is directed to maximizing storage cell surface area, as well as providing uniform and repeatable, defect free, storage cell structures across a given substrate, in a high density/high volume DRAM fabrication process, in a sequence shown in FIGS. 2-7.
  • a silicon wafer is prepared using conventional process steps up to the point of processing an array of storage cell capacitors. Capacitor cell fabrication will now follow.
  • each memory cell will make contact directly to an underlying diffusion area.
  • Each underlying diffusion area will have two storage node connections isolated from a single digit line contact by access transistors formed by poly word lines crossing the active area.
  • each diffusion area within the array is isolated from one another by a thick field oxide.
  • the diffusion areas can be arranged in interdigitated columns and non-interdigitated rows or simply parallel and in line to one another in both the vertical and horizontal directions.
  • the diffusion areas are used to form active MOS transistors (serving as access transistors to each individual capacitor) that can be doped as NMOS or PMOS type FETs depending on the desired use.
  • a thick layer of low etch rate oxide 21 is formed over an existing topography of a given substrate.
  • Oxide 21 is then planarized, preferably by chemical-mechanical planarization (CMP) techniques down to a predetermined thickness.
  • CMP chemical-mechanical planarization
  • the thickness of planarized oxide 21 depends on the height that is desired for the poly container structure yet to be formed.
  • the height of the resulting poly structure will determine the capacitor plate surface area that will be required to sufficiently hold a charge. It has been shown that a structure of approximately 1.0-1.5 ⁇ is sufficient to construct a reliable 64M DRAM cell using optimized cell dielectric (Container height depends on such factors as container diameter, dielectric constant and thickness of oxides used which are brought to light in the continuing discussion.).
  • a contact opening 22 is then etched into oxide 21 thereby allowing access to the underlying topography (for DRAM-capacitor purposes this opening would normally expose a diffusion region conductively doped into a starting substrate).
  • Contact opening 22 not only allows access to the underlying topography but also provides a form for a subsequent placed layer of thin poly.
  • This thin poly is now formed, preferably by CVD, as a layer of conformal polysilicon 23 and is placed overlying planarized oxide 21 , the patterned edges of oxide 21 and the exposed underlying topography.
  • Poly 23 may either have been deposited insitu doped or deposited insitu doped and rugged HSG poly for added cell capacitance or it may be subsequently doped.
  • Oxide 31 is thick enough to completely fill the poly lined contact opening 22 .
  • oxide layer 31 is removed down to poly 23 , preferably by CMP which will selectively stop on the first exposed upper regions of poly 23 .
  • the exposed upper portions of poly 23 are removed to separate neighboring poly structures, thereby forming individual containers 51 residing in contact openings 22 and exposing underlying oxide 21 .
  • the areas of poly 23 that are removed may be accomplished by performing a poly etch selective to oxide, which could be a timed wet etch or an optimized CMP poly etch.
  • a very significant advantage of this process flow when a CMP etch step is utilized is that the inside of the future container 51 is protected from ‘slurry’ contamination that is inherent in the CMP step which proves difficult to remove in high aspect ratio storage containers (0.5 ⁇ inside diameter by 1.5 ⁇ high).
  • both oxides 21 and 31 which have different etch rates, are now exposed.
  • an oxide etch is performed such that oxide 31 is completely removed from inside container 51 while a portion of oxide 21 remains at the base of container 51 and thereby providing an insulating layer between the underlying topography and subsequent layers.
  • a An etch rate ratio of 2:1 or greater between (a ratio of 4:1 is preferred) oxide 31 and oxide 22 21 provides sufficient process margin to ensure all of high etch rate oxide 31 inside container 51 is removed during the single etch step, while a portion of oxide 22 21 remains to provide adequate insulation from subsequently formed layers.
  • FIG. 8 depicts a cross-section of the present invention integrated into a stacked capacitor process on starting substrate 81 .
  • Container 51 connects to diffusion area 82 and thereby serves as a storage node container plate.
  • Diffusion area 82 is accessed by word line 85 (separated by gate insulator 83 ) which in turn spans the channel's active area between diffusion areas 82 .
  • the poly of container 51 is doped to the same conductivity type as underlying diffusion region 82 to insure a good ohmic contact.

Abstract

An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation to U.S. patent application Ser. No. 07/850,746, filed Mar. 13, 1992, now U.S. Pat. No. 5,162,248.
FIELD OF THE INVENTION
This invention relates to semiconductor circuit memory storage devices and more particularly to a process for fabricating three-dimensional stacked capacitor structures that may be used in such storage devices as high-density dynamic random access memories (DRAMs).
BACKGROUND OF THE INVENTION
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of “stacked storage cell” design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by N. Shinmura, et al., entitled “A Stacked Capacitor Cell with Ring Structure,” Extended Abstracts of the 22nd International Conference on Solid State Devices and Materials, 1990, pp. 833-836, discusses a 3-dimensional stacked capacitor incorporating a ring structure around the main electrode to effectively double the capacitance of a conventional stacked capacitor.
The ring structure and its development is shown in FIGS. 1(c) through 1(g), pp. 834 of the article mentioned above. FIG. 1(a), on the same page shows a bird's eye-view of storage electrodes. The storage node is formed by two polysilicon layers that form a core electrode encircled by a ring structure. Capacitor dielectric film surrounds the whole surface of the storage node electrode and then is covered with a third polysilicon layer to form the top capacitor electrode and completes the storage cell. This design can be fabricated using current methods and increases storage capacitance by as much as 200%.
Also, in a paper submitted by T. Kaga, et al., entitled “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's,” IEEE Transactions on Electron Devices. VOL. 38, NO. 2, February 1991, pp. 255-261, discusses a self-aligned stacked-capacitor cell for 64-Mb DRAM's, called a CROWN cell. The CROWN cell and its development are shown in FIGS. 7(d) through 7(f), pp. 258 of this article. The crown shaped storage electrode is formed over word and bit lines and separated by a an oxide/nitride insulating layer with the top insulating layer being removed to form the crown shape. Capacitor dielectric film surrounds the whole surface of the storage node electrode and the top capacitor electrode is formed to complete the storage cell.
The present invention develops an existing stacked capacitor fabrication process to construct and optimize a three-dimensional container stacked capacitor cell. The capacitor's bottom plate (or storage node plate) is centered over a buried contact (or node contact) connected to an access transistor's diffusion area. The method presented herein provides fabrication uniformity and repeatability of the three-dimensional container cell.
SUMMARY OF THE INVENTION
The invention is directed to maximizing storage cell surface area in a high density/high volume DRAM (dynamic random access memory) fabrication process. An existing capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The capacitor design of the present invention defines a stacked capacitor storage cell that is used in a DRAM process, however it will be evident to one skilled in the art to incorporate these steps into other processes requiring volatile memory cells, such as VRAMs or the like.
After a silicon wafer is prepared using conventional process steps, the present invention develops the container capacitor by etching a contact opening into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly by using Chemical Mechanical Polishing (CMP). This CMP step is selective such that oxide is removed with sufficient overetch and stops on the thin poly. The resuIting exposed poly is then removed to separate neighboring containers either through an isotropic wet poly etch or an additional CMP with the chemical aspect modified to now etch and selectively remove the poly and not the oxide. The two oxides, having different etch rates, are then etched by a single wet dilute BOE etch step, thereby leaving a free-standing poly container cell, with all the inside (high etch rate) oxide removed, that is equal in height to the depth of the original contact opening. In addition, a pre-determined amount of low etch rate oxide is removed, thereby leaving oxide surrounding the , container, poly for both structural support and process integration for further processing which requires oxide to be left above the word lines.
The present invention uses a higher etch-rate oxide inside the container to block the container poly etch. This high etch rate oxide is completely removed during oxide etch back. This protects the container during processing without adding photoresist and introducing extra processing steps or unwarranted contaminants. A standard CMP oxide etch is utilized that allows fabrication uniformity and repeatability across the wafer which cannot be achieved by resist filled container processes.
Another advantage of filling the container with high etch rate oxide is that the poly can be etched with a low cost, timed wet poly etch, while partially filled containers (as seen in FIG. 9), due to inherent recession of resist 92 height (to allow for sufficient process margin), will not allow a wet poly etch without loss in cell height 93, loss in uniformity and repeatability across the wafer's surface. Because this invention can be etched isotropically at poly etch, it avoids the recessing (overetch of the storage poly container 93 in FIG. 9) and splintering effects caused by a dry etch poly process.
As seen in FIG. 10, splintering effects 101 of storage node poly 93 result from a dry anisotropic etch (due to non-uniform etching of polycrystalline silicon 93) because the plasma etch reacts faster along heavily doped grain boundaries. Splinters 101 later tend to ‘break off’ in subsequent processing leading to contamination particulates. The trenching of the poly leads to the side-walls of the poly container to be exposed, thus making it impossible to wet etch the oxide around the cell without translating the trenched poly horizontal portion of the etch into surrounding oxide 91 thereby leaving a ring of thin oxide around he the container cell.
The present invention also protects the vertical sidewall of the oxide form by covering it with poly, thereby making a horizontal wet oxide etch back possible. In addition, all films which see etch processing, CMP or otherwise, are subsequently removed thereby acting as sacrificial films such that particles created during the CMP etch do not contaminate the inside of the poly containers.
FIG. 1 shows a gray scale reproduction of a SEM photograph of an array of poly containers 12 which demonstrates the uniformity and repeatability of poly containers 12 across substrate 11that results from utilizing the process steps of the present invention discussed hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a gray-scale reproduction of a SEM (Scanning Electronic Microscope) photograph of a cross-sectional view of an array of container poly rings;
FIG. 2 is a composite cross-sectional view of an in-process wafer portion depicting the beginning steps of the present invention, said steps comprising forming a planarized layer of low etch rate oxide, etching a buried contact and placing a thin layer of conformal poly;
FIG. 3 is a cross-sectional view of the in-process wafer portion of FIG. 2 after formation of a layer of high etch rate oxide;
FIG. 4 is a cross-sectional view of the in-process wafer portion of FIG. 3 after planarization of the high etch rate oxide;
FIG. 5 is a cross-sectional view of the in-process wafer portion of FIG. 4 following a wet etch back of the exposed thin poly layer;
FIG. 6 is a cross-sectional view of the in-process wafer portion of FIG. 5 following an etch of both low etch rate and high etch rate oxides;
FIG. 7 is a cross-sectional view of the in-process wafer portion of FIG. 6 following blanket formations of conformal cell dielectric and polysilicon, respectively;
FIG. 8 is a cross-sectional view of a storage cell created by the present invention when integrated into a stacked capacitor fabrication process; and
FIG. 9 is a composite cross-sectional view of an in-process wafer portion depicting a container cell filled with photoresist prior to patterning; and
FIG. 10 is a composite cross-sectional view of the in-process wafer portion of FIG. 9 depicting splintering of storage node poly and formation of a thin ring of oxide surrounding the storage node poly following an anisotropic etching to pattern a container cell.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The invention is directed to maximizing storage cell surface area, as well as providing uniform and repeatable, defect free, storage cell structures across a given substrate, in a high density/high volume DRAM fabrication process, in a sequence shown in FIGS. 2-7.
A silicon wafer is prepared using conventional process steps up to the point of processing an array of storage cell capacitors. Capacitor cell fabrication will now follow.
The storage capacitor of each memory cell will make contact directly to an underlying diffusion area. Each underlying diffusion area will have two storage node connections isolated from a single digit line contact by access transistors formed by poly word lines crossing the active area. Normally each diffusion area within the array is isolated from one another by a thick field oxide. The diffusion areas can be arranged in interdigitated columns and non-interdigitated rows or simply parallel and in line to one another in both the vertical and horizontal directions. As previously mentioned, the diffusion areas are used to form active MOS transistors (serving as access transistors to each individual capacitor) that can be doped as NMOS or PMOS type FETs depending on the desired use.
Referring now to FIG. 2, a thick layer of low etch rate oxide 21 is formed over an existing topography of a given substrate. Oxide 21 is then planarized, preferably by chemical-mechanical planarization (CMP) techniques down to a predetermined thickness. The thickness of planarized oxide 21 depends on the height that is desired for the poly container structure yet to be formed. The height of the resulting poly structure will determine the capacitor plate surface area that will be required to sufficiently hold a charge. It has been shown that a structure of approximately 1.0-1.5μ is sufficient to construct a reliable 64M DRAM cell using optimized cell dielectric (Container height depends on such factors as container diameter, dielectric constant and thickness of oxides used which are brought to light in the continuing discussion.). A contact opening 22 is then etched into oxide 21 thereby allowing access to the underlying topography (for DRAM-capacitor purposes this opening would normally expose a diffusion region conductively doped into a starting substrate). Contact opening 22 not only allows access to the underlying topography but also provides a form for a subsequent placed layer of thin poly. This thin poly is now formed, preferably by CVD, as a layer of conformal polysilicon 23 and is placed overlying planarized oxide 21, the patterned edges of oxide 21 and the exposed underlying topography. Poly 23 may either have been deposited insitu doped or deposited insitu doped and rugged HSG poly for added cell capacitance or it may be subsequently doped.
Referring now to FIG. 3, a thick layer of oxide 31 having a high etch rate is formed over poly 23. Oxide 31 is thick enough to completely fill the poly lined contact opening 22.
Referring now to FIG. 4, oxide layer 31 is removed down to poly 23, preferably by CMP which will selectively stop on the first exposed upper regions of poly 23.
Referring now to FIG. 5, the exposed upper portions of poly 23 are removed to separate neighboring poly structures, thereby forming individual containers 51 residing in contact openings 22 and exposing underlying oxide 21. The areas of poly 23 that are removed may be accomplished by performing a poly etch selective to oxide, which could be a timed wet etch or an optimized CMP poly etch. A very significant advantage of this process flow when a CMP etch step is utilized is that the inside of the future container 51 is protected from ‘slurry’ contamination that is inherent in the CMP step which proves difficult to remove in high aspect ratio storage containers (0.5μ inside diameter by 1.5μ high).
Referring now to FIG. 6, both oxides 21 and 31, which have different etch rates, are now exposed. At this point, an oxide etch is performed such that oxide 31 is completely removed from inside container 51 while a portion of oxide 21 remains at the base of container 51 and thereby providing an insulating layer between the underlying topography and subsequent layers. A An etch rate ratio of 2:1 or greater between (a ratio of 4:1 is preferred) oxide 31 and oxide 22 21provides sufficient process margin to ensure all of high etch rate oxide 31 inside container 51 is removed during the single etch step, while a portion of oxide 22 21remains to provide adequate insulation from subsequently formed layers.
Referring now to FIG. 7, when using this structure to form a capacitor storage node plate container 51and, the remaining portion of oxide 21 is coated with a capacitor cell dielectric 71. And, finally Finally a second conformal poly layer 72 is placed to onto blanket cell dielectric 71 and serves as a common capacitor cell plate to the entire array of containers 51. From this point on the wafer is completed using conventional fabrication process steps.
FIG. 8 depicts a cross-section of the present invention integrated into a stacked capacitor process on starting substrate 81. Container 51 connects to diffusion area 82 and thereby serves as a storage node container plate. Diffusion area 82 is accessed by word line 85 (separated by gate insulator 83) which in turn spans the channel's active area between diffusion areas 82. The poly of container 51 is doped to the same conductivity type as underlying diffusion region 82 to insure a good ohmic contact.
It is to be understood that although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the structures and process steps presented herein without departing from the invention as recited in the several claims appended hereto.

Claims (66)

We claim:
1. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a conductive containers container having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said conductive container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
2. A process as recited in claim 1, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
3. A process as recited in claim 1, wherein said second insulating layer is a sacrificial layer conducive to said chemical mechanical planarization.
4. A process as recited in claim 1, wherein said first and said second insulating layers are oxides.
5. A process as recited in claim 1, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
6. A process as recited in claim 5, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
7. A process as recited in claim 5, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 4:1.
8. A process as recited in claim 1, wherein said first and said second conductive layers are doped polysilicon.
9. A process as recited in claim 8, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
10. A process as recited in claim 1, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
11. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container forms thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion via chemical mechanical planarization until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a conductive containers container having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said conductive container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
12. A process as recited in claim 1 11, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
13. A process as recited in claim 1 11, wherein said second insulating layer is a sacrificial layer that is planarized by chemical mechanical planarization.
14. A process as recited in claim 1 11, wherein said first and said second insulating layers are oxides.
15. A process as recited in claim 1 11, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
16. A process as recited in claim 15, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
17. A process as recited in claim 15, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 4:1.
18. A process as recited in claim 1, wherein said first and said second conductive layers are doped polysilicon.
19. A process as recited in claim 18, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
20. A process as recited in claim 1 11, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
21. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form, thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion via chemical mechanical planarization until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a conductive containers container having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said conductive container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
22. A process as recited in claim 21, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
23. A process as recited in claim 21, wherein said second insulating layer is a sacrificial layer conducive to said chemical mechanical planarization.
24. A process as recited in claim 21, wherein said first and said second insulating layers are oxides.
25. A process as recited in claim 21, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
26. A process as recited in claim 25, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
27. A process as recited in claim 25, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio ob of 4:1.
28. A process as recited in claim 21, wherein said first and said second conductive layers are doped polysilicon.
29. A process as recited in claim 28, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
30. A process as recited in claim 21, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
31. A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form, thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a container storage capacitors capacitor having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said an underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said storage capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
32. A process as recited in claim 31, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
33. A process as recited in claim 31, wherein said second insulating layer is a sacrificial layer conductive conducive to said chemical mechanical planarization.
34. A process as recited in claim 31, wherein said first and said second insulating layers are oxides.
35. A process as recited in claim 31, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
36. A process as recited in claim 35, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
37. A process as recited in claim 35, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 4:1.
38. A process as recited in claim 31, wherein said first and said second conductive layers are doped polysilicon.
39. A process as recited in claim 38, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
40. A process as recited in claim 31, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
41. A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form, thereby lining said container form.
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion via chemical mechanical planarization until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a container storage capacitors capacitor having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said an underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said storage capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
42. A process as recited in claim 41, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
43. A process as recited in claim 41, wherein said second insulating layer is a sacrificial layer that is planarized by chemical mechanical planarization.
44. A process as recited in claim 41, wherein said first and said second insulating layers are oxides.
45. A process as recited in claim 41, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
46. A process as recited in claim 45, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
47. A process as recited in claim 45, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 4:1.
48. A process as recited in claim 41, wherein said first and said second conductive layers are doped polysilicon.
49. A process as recited in claim 48, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
50. A process as recited in claim 41, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
51. A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form, thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive layer upper layer portion via chemical mechanical planarization until underlying said first insulating layer is exposed, thereby separating said first conductive layer into individual said forming a container storage capacitors capacitor having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed, thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive with said exposed inner walls and an inner bottom portion of said storage capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive with said third insulating layer.
52. A process as recited in claim 51, wherein said first insulating layer is planarized prior to said step of patterning and etching an opening into said first insulating layer.
53. A process as recited in claim 51, wherein said second insulating layer is a sacrificial layer conducive to said chemical mechanical planarization.
54. A process as recited in claim 51, wherein said first and said second insulating layers are oxides.
55. A process as recited in claim 51, wherein said first insulating layer etch rate is a lower etch rate than said second insulating layer etch rate.
56. A process as recited in claim 55, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 2:1 or greater.
57. A process as recited in claim 55, wherein the etch rate ratio between said second insulating layer etch rate and said first insulating layer etch rate is a ratio of 4:1.
58. A process as recited in claim 51, wherein said first and said second conductive layers are doped polysilicon.
59. A process as recited in claim 58, wherein said doped polysilicon is formed by insitu in situ doped chemical vapor deposition.
60. A process as recited in claim 51, wherein said first, said second and said third insulating layers are formed by chemical vapor deposition.
61. A process for fabricating a capacitor on a substrate, said process comprising the steps of:
providing a first insulating layer on said substrate, said insulating layer having an opening therein forming a container and being subject to a first etch rate;
forming a generally conformal first conductive layer over said first insulating layer and in said container;
forming a second insulating layer above said first conductive layer, wherein said second insulating layer is subject to a second etch rate;
removing at least a portion of said second insulating layer through use of chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
removing at least a portion of an upper portion of said first conductive layer until said first insulating layer is exposed; and
etching said first and second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said first conductive layer within said container, and such that said first insulating layer is partially removed.
62. The process of claim 61, further comprising the step of forming a third insulating layer over said inner walls of said first conductive layer within said container.
63. The process of claim 62, further comprising the step of forming a second conductive layer over at least a portion of said third insulating layer.
64. A process for fabricating a DRAM containing storage capacitor on a silicon substrate having an existing topography including active areas, word lines and digit lines, said process comprising the steps of:
providing a first insulating layer having a first etch rate, over said existing topography;
forming an opening into said first insulating layer, said opening thereby forming a container;
forming a conformal first conductive layer over said first insulating layer and said container, thereby lining said container;
forming a second insulating layer having a second etch rate, over said first conductive layer;
removing said second insulating layer through use of chemical mechanical planarization until an upper portion of said first conductive layer is exposed;
removing at least a portion of an upper portion of said first conductive layer until said first insulating layer is exposed, thereby forming a conductive container having inner and outer walls; and
etching said first and second insulating layers such that said second insulating layer is completely removed, thereby exposing the entire inner walls of said first conductive layer within said container, and such that said first insulating layer is partially removed.
65. The process of claim 64, further comprising the step of forming a third insulating layer over said inner walls and an inner bottom portion of said conductive container.
66. The process of claim 65, further comprising the step of forming a second conductive layer over at least a portion of said third insulating layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39665E1 (en) * 1992-03-13 2007-05-29 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297960A (en) * 1998-04-16 1999-10-29 Mitsubishi Electric Corp Semiconductor device and manufacture therefor
US5162248A (en) * 1992-03-13 1992-11-10 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
DE4221431A1 (en) * 1992-06-30 1994-01-05 Siemens Ag Manufacturing process for a key capacitor
JP2865155B2 (en) * 1992-07-23 1999-03-08 日本電気株式会社 Semiconductor device and manufacturing method thereof
DE4447804C2 (en) * 1993-02-12 2002-01-24 Micron Technology Inc Conducting structure prodn. on topography of substrate
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
DE4404129C2 (en) * 1993-02-12 2000-04-20 Micron Technology Inc Method of manufacturing a multi-pin conductive structure
US5340763A (en) * 1993-02-12 1994-08-23 Micron Semiconductor, Inc. Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same
US6030847A (en) * 1993-04-02 2000-02-29 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5392189A (en) 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US6791131B1 (en) 1993-04-02 2004-09-14 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US6531730B2 (en) * 1993-08-10 2003-03-11 Micron Technology, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5318927A (en) * 1993-04-29 1994-06-07 Micron Semiconductor, Inc. Methods of chemical-mechanical polishing insulating inorganic metal oxide materials
US5278091A (en) * 1993-05-04 1994-01-11 Micron Semiconductor, Inc. Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node
US5340765A (en) * 1993-08-13 1994-08-23 Micron Semiconductor, Inc. Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon
US5354705A (en) * 1993-09-15 1994-10-11 Micron Semiconductor, Inc. Technique to fabricate a container structure with rough inner and outer surfaces
US5407534A (en) * 1993-12-10 1995-04-18 Micron Semiconductor, Inc. Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal
US5656531A (en) * 1993-12-10 1997-08-12 Micron Technology, Inc. Method to form hemi-spherical grain (HSG) silicon from amorphous silicon
US5972771A (en) * 1994-03-11 1999-10-26 Micron Technology, Inc. Enhancing semiconductor structure surface area using HSG and etching
US5418180A (en) * 1994-06-14 1995-05-23 Micron Semiconductor, Inc. Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon
US5538592A (en) * 1994-07-22 1996-07-23 International Business Machines Corporation Non-random sub-lithography vertical stack capacitor
JP2956482B2 (en) * 1994-07-29 1999-10-04 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
US5527423A (en) * 1994-10-06 1996-06-18 Cabot Corporation Chemical mechanical polishing slurry for metal layers
US6121081A (en) * 1994-11-15 2000-09-19 Micron Technology, Inc. Method to form hemi-spherical grain (HSG) silicon
JPH08153858A (en) * 1994-11-29 1996-06-11 Nec Corp Manufacture of semiconductor device
US5663107A (en) * 1994-12-22 1997-09-02 Siemens Aktiengesellschaft Global planarization using self aligned polishing or spacer technique and isotropic etch process
US5658381A (en) * 1995-05-11 1997-08-19 Micron Technology, Inc. Method to form hemispherical grain (HSG) silicon by implant seeding followed by vacuum anneal
US5665625A (en) * 1995-05-19 1997-09-09 Micron Technology, Inc. Method of forming capacitors having an amorphous electrically conductive layer
US5663088A (en) * 1995-05-19 1997-09-02 Micron Technology, Inc. Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer
US5668063A (en) * 1995-05-23 1997-09-16 Watkins Johnson Company Method of planarizing a layer of material
US7294578B1 (en) 1995-06-02 2007-11-13 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US5950092A (en) * 1995-06-02 1999-09-07 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US6716769B1 (en) 1995-06-02 2004-04-06 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US5597756A (en) * 1995-06-21 1997-01-28 Micron Technology, Inc. Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack
US6388314B1 (en) 1995-08-17 2002-05-14 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US5627094A (en) * 1995-12-04 1997-05-06 Chartered Semiconductor Manufacturing Pte, Ltd. Stacked container capacitor using chemical mechanical polishing
US5946566A (en) * 1996-03-01 1999-08-31 Ace Memory, Inc. Method of making a smaller geometry high capacity stacked DRAM device
US5885864A (en) * 1996-10-24 1999-03-23 Micron Technology, Inc. Method for forming compact memory cell using vertical devices
US6534409B1 (en) * 1996-12-04 2003-03-18 Micron Technology, Inc. Silicon oxide co-deposition/etching process
US5937314A (en) 1997-02-28 1999-08-10 Micron Technology, Inc. Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
US6063656A (en) * 1997-04-18 2000-05-16 Micron Technology, Inc. Cell capacitors, memory cells, memory arrays, and method of fabrication
US6258662B1 (en) * 1997-05-06 2001-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming cylindrical DRAM capacitors
US5903491A (en) * 1997-06-09 1999-05-11 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US5936874A (en) * 1997-06-19 1999-08-10 Micron Technology, Inc. High density semiconductor memory and method of making
US6027860A (en) * 1997-08-13 2000-02-22 Micron Technology, Inc. Method for forming a structure using redeposition of etchable layer
US6100139A (en) * 1997-12-02 2000-08-08 Oki Electric Industry Co., Ltd. Method for producing semiconductor device
JPH11186524A (en) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp Semiconductor device and its manufacture
US6369432B1 (en) 1998-02-23 2002-04-09 Micron Technology, Inc. Enhanced capacitor shape
US6673671B1 (en) 1998-04-16 2004-01-06 Renesas Technology Corp. Semiconductor device, and method of manufacturing the same
WO1999062116A1 (en) * 1998-05-25 1999-12-02 Hitachi, Ltd. Semiconductor device and process for manufacturing the same
US6200901B1 (en) 1998-06-10 2001-03-13 Micron Technology, Inc. Polishing polymer surfaces on non-porous CMP pads
US6174817B1 (en) 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
US6383886B1 (en) 1998-09-03 2002-05-07 Micron Technology, Inc. Method to reduce floating grain defects in dual-sided container capacitor fabrication
US6235639B1 (en) * 1998-11-25 2001-05-22 Micron Technology, Inc. Method of making straight wall containers and the resultant containers
US6358793B1 (en) * 1999-02-26 2002-03-19 Micron Technology, Inc. Method for localized masking for semiconductor structure development
US6364749B1 (en) 1999-09-02 2002-04-02 Micron Technology, Inc. CMP polishing pad with hydrophilic surfaces for enhanced wetting
KR100311050B1 (en) 1999-12-14 2001-11-05 윤종용 Method for manufacturing electrode of capacitor
FR2813142B1 (en) * 2000-08-17 2002-11-29 St Microelectronics Sa MANUFACTURE OF METAL FRAME CAPACITORS
US7153410B2 (en) * 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
US6639266B1 (en) 2000-08-30 2003-10-28 Micron Technology, Inc. Modifying material removal selectivity in semiconductor structure development
US7160176B2 (en) * 2000-08-30 2007-01-09 Micron Technology, Inc. Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate
US7112121B2 (en) * 2000-08-30 2006-09-26 Micron Technology, Inc. Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate
US7192335B2 (en) * 2002-08-29 2007-03-20 Micron Technology, Inc. Method and apparatus for chemically, mechanically, and/or electrolytically removing material from microelectronic substrates
US7094131B2 (en) * 2000-08-30 2006-08-22 Micron Technology, Inc. Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material
US7134934B2 (en) * 2000-08-30 2006-11-14 Micron Technology, Inc. Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium
US7078308B2 (en) * 2002-08-29 2006-07-18 Micron Technology, Inc. Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate
US7153195B2 (en) * 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for selectively removing conductive material from a microelectronic substrate
US7220166B2 (en) 2000-08-30 2007-05-22 Micron Technology, Inc. Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US7129160B2 (en) 2002-08-29 2006-10-31 Micron Technology, Inc. Method for simultaneously removing multiple conductive materials from microelectronic substrates
US7074113B1 (en) 2000-08-30 2006-07-11 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
US6495406B1 (en) * 2000-08-31 2002-12-17 Micron Technology, Inc. Method of forming lightly doped drain MOS transistor including forming spacers on gate electrode pattern before exposing gate insulator
US6403455B1 (en) 2000-08-31 2002-06-11 Samsung Austin Semiconductor, L.P. Methods of fabricating a memory device
US6689668B1 (en) 2000-08-31 2004-02-10 Samsung Austin Semiconductor, L.P. Methods to improve density and uniformity of hemispherical grain silicon layers
JP2002076293A (en) * 2000-09-01 2002-03-15 Matsushita Electric Ind Co Ltd Method for manufacturing capacitor and semiconductor device
KR100338780B1 (en) 2000-09-15 2002-06-01 윤종용 Semiconductor memory device for reducing the damage of interlevel dielectric layer, and fabrication method thereof
US6498088B1 (en) * 2000-11-09 2002-12-24 Micron Technology, Inc. Stacked local interconnect structure and method of fabricating same
KR100355239B1 (en) 2000-12-26 2002-10-11 삼성전자 주식회사 Semiconductor memory device having cylinder type capacitor and fabrication method thereof
US6756308B2 (en) * 2001-02-13 2004-06-29 Ekc Technology, Inc. Chemical-mechanical planarization using ozone
US6410955B1 (en) * 2001-04-19 2002-06-25 Micron Technology, Inc. Comb-shaped capacitor for use in integrated circuits
KR100535074B1 (en) * 2001-06-26 2005-12-07 주식회사 하이닉스반도체 Slurry for Chemical Mechanical Polishing of Ruthenium and the Process for Polishing Using It
US6888217B2 (en) * 2001-08-30 2005-05-03 Micron Technology, Inc. Capacitor for use in an integrated circuit
KR100450679B1 (en) * 2002-07-25 2004-10-01 삼성전자주식회사 Manufacturing method for storage node of semiconductor memory device using two step etching process
US6884692B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Method for forming conductive material in opening and structures regarding same
JP2005057263A (en) * 2003-07-31 2005-03-03 Samsung Electronics Co Ltd Etching method for manufacturing semiconductor device
KR100546381B1 (en) 2003-09-22 2006-01-26 삼성전자주식회사 Method for manufacturing semiconductor device including wet etching process
US7112122B2 (en) 2003-09-17 2006-09-26 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
JP4908748B2 (en) * 2003-09-22 2012-04-04 三星電子株式会社 Etching method for manufacturing semiconductor device
US7153777B2 (en) 2004-02-20 2006-12-26 Micron Technology, Inc. Methods and apparatuses for electrochemical-mechanical polishing
US7241655B2 (en) * 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
US7566391B2 (en) 2004-09-01 2009-07-28 Micron Technology, Inc. Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media
US7619298B1 (en) * 2005-03-31 2009-11-17 Xilinx, Inc. Method and apparatus for reducing parasitic capacitance
US7256131B2 (en) * 2005-07-19 2007-08-14 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432799A (en) 1982-03-08 1984-02-21 Salazar Paul V Refractory compositions and method
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
JPS62286270A (en) * 1986-06-05 1987-12-12 Sony Corp Semiconductor memory
US4785337A (en) * 1986-10-17 1988-11-15 International Business Machines Corporation Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
US4877750A (en) * 1987-11-17 1989-10-31 Mitsubishi Denki Kabushiki Kaisha Method of fabricating a trench capacitor cell for a semiconductor memory device
JPH0274752A (en) * 1988-09-08 1990-03-14 Ig Tech Res Inc Siding board
JPH0294554A (en) * 1988-09-30 1990-04-05 Toshiba Corp Semiconductor storage device and manufacture thereof
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US5045899A (en) * 1989-12-01 1991-09-03 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory having stacked capacitor structure
US5150276A (en) * 1992-01-24 1992-09-22 Micron Technology, Inc. Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings
US5162248A (en) * 1992-03-13 1992-11-10 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5185282A (en) * 1989-11-23 1993-02-09 Electronics And Telecommunications Research Institute Method of manufacturing DRAM cell having a cup shaped polysilicon storage electrode
US5313089A (en) * 1992-05-26 1994-05-17 Motorola, Inc. Capacitor and a memory cell formed therefrom
US5364809A (en) * 1991-05-23 1994-11-15 Samsung Electronics Co., Ltd. Method of fabricating a capacitor for a dynamic random access memory cell

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474752A (en) * 1987-09-17 1989-03-20 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP2528731B2 (en) * 1990-01-26 1996-08-28 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432799A (en) 1982-03-08 1984-02-21 Salazar Paul V Refractory compositions and method
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
JPS62286270A (en) * 1986-06-05 1987-12-12 Sony Corp Semiconductor memory
US4785337A (en) * 1986-10-17 1988-11-15 International Business Machines Corporation Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
US4877750A (en) * 1987-11-17 1989-10-31 Mitsubishi Denki Kabushiki Kaisha Method of fabricating a trench capacitor cell for a semiconductor memory device
JPH0274752A (en) * 1988-09-08 1990-03-14 Ig Tech Res Inc Siding board
JPH0294554A (en) * 1988-09-30 1990-04-05 Toshiba Corp Semiconductor storage device and manufacture thereof
US5185282A (en) * 1989-11-23 1993-02-09 Electronics And Telecommunications Research Institute Method of manufacturing DRAM cell having a cup shaped polysilicon storage electrode
US5045899A (en) * 1989-12-01 1991-09-03 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory having stacked capacitor structure
US5364809A (en) * 1991-05-23 1994-11-15 Samsung Electronics Co., Ltd. Method of fabricating a capacitor for a dynamic random access memory cell
US5150276A (en) * 1992-01-24 1992-09-22 Micron Technology, Inc. Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings
US5162248A (en) * 1992-03-13 1992-11-10 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5313089A (en) * 1992-05-26 1994-05-17 Motorola, Inc. Capacitor and a memory cell formed therefrom

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"A Stacked Capacitor Cell with Ring Structure" by N. Shinmura et al., pp. 833-836. (Extended abstacts of the 22nd International Conference on Solid State Devices 1990). *
"Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb Dram's" by T. Kaga et al., IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 255-261.* *
"Stacked Capacitor DRAM Cell with Vertical Fins", IBM TDB, Jul. 1990, pp. 245-247.* *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39665E1 (en) * 1992-03-13 2007-05-29 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

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