USRE36839E - Method and apparatus for reducing power consumption in digital electronic circuits - Google Patents
Method and apparatus for reducing power consumption in digital electronic circuits Download PDFInfo
- Publication number
- USRE36839E USRE36839E US09/212,854 US21285498A USRE36839E US RE36839 E USRE36839 E US RE36839E US 21285498 A US21285498 A US 21285498A US RE36839 E USRE36839 E US RE36839E
- Authority
- US
- United States
- Prior art keywords
- clock
- functional blocks
- power
- functional block
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Definitions
- This invention relates generally to digital electronic equipment, and more particularly to methods and apparatus for reducing power consumption for personal computer systems.
- Portable computers typically depend on batteries for power. Obviously, the less power consumed by the portable computer circuitry and peripherals, the longer the batteries will last.
- desktop computers that consume less power. This is because reduced power consumption reduces energy costs and, in a cumulative sense, reduces the negative environmental impacts of excessive energy consumption.
- desktop computers designed to consume less power also generate less heat, which means that they can be made smaller and with reduced cooling requirements.
- the methods for reducing power consumption were often implemented in software on the computer. By implementing the method in software, valuable computational time is lost to the power consumption reduction function.
- Other methods employed in the prior art reduce power consumption through hardware devices which monitor energy usage or which use timers to shut off peripherals or FSBs.
- the hardware functionality which reduces power consumption can be provided as a stand-alone integrated circuit, or it can be formed as part of a "chip set" used by the computer system. In either case, expensive, additional circuitry separate from the computer logic is required.
- the present invention provides a method and apparatus for reducing power consumption in digital electronic circuits and, more particularly, in personal computer systems.
- the operation of the present invention is transparent to the computer system and to software running on the computer system.
- An integrated circuit with power conservation in accordance with the present invention includes a number of functional blocks, each of which has digital circuitry and at least one output control line.
- the integrated circuit also includes a power controller coupled to the output control line of each of the functional blocks.
- the power controller reduces power consumed by selected functional blocks in response to control signals on the control lines.
- each functional block within the integrated circuit generates a signal indicating whether that functional block is busy and/or if a "neighboring" functional block will be required.
- These functional blocks can be arbitrarily small and are not limited to the fairly large functional system block (FSBTM) circuitry of some previous power management techniques.
- FSBTM is a trademark of VLSI Technology, Inc. of San Jose, Calif.
- a given functional block If a given functional block is not busy, it can be deactivated (by stopping its clock, disabling its power rails, etc.).
- the activation or deactivation of the functional blocks is controlled by the flow of data within the integrated circuit, allowing the integrated circuit to minimize power without any explicit intervention from software or hardware timers. Because the data flow controls the clocking, the present invention is particularly effective with such devices as PCI bus devices, or ISA/EISA bus slave devices.
- a system with power conservation includes a number of functional blocks capable of processing data, where each of the functional blocks include a modulated clock input and up to N+1 clock control lines, where N is the number of neighbors of a particular functional block that are connected to the particular functional block by a data path.
- the system with power conservation also includes a clock controller having an input clock, and is coupled to the modulated clock inputs and the clock control lines of the functional blocks.
- each of the functional blocks can provide a signal to the clock controller requesting that it and/or its neighbors be activated or deactivated.
- a method for reducing power consumption in a digital electronic circuit includes the steps of: a) receiving a control signal from a number of functional blocks; b) deactivating a particular functional block upon a request from that particular functional block or from another functional block, and in the absence of a request from another functional block requesting the activation of that particular functional block; and c) activating a functional block upon a request of another functional block.
- Each functional block consumes less power when deactivated than when activated.
- the functional blocks are activated by providing a full-speed clock to the functional block, and are deactivated by not applying the clock to the block. This can be accomplished with a "modulated clock" which is derived from a regular output clock as modulated by signals provided by the clock control lines.
- the present invention therefore has several advantages over the prior art.
- the operation of the present invention is transparent to the computer system and to software running in the computer system in that the power reduction method operates automatically based upon the flow of data within the digital circuit.
- the present invention by breaking the chip into number of clock regions or functional blocks, minimizes the problem of skew. This allows each functional block to be individually shut-down based upon usage and yet maintains a minimal clock skew within the clock regions. This allows critical data paths and state machines to run in full speed without skew problems. Since the number of functional regions are under the control of the chip designer, the clock driver and distribution for each functional block can be designed to minimize skew between the various blocks.
- the present invention preferably activates and deactivates a functional block by controlling its clock.
- another aspect of the present invention is to control the power applied to the functional block. For example, part or all of the power rail to a particular functional block can be disabled to provide substantial power savings since the pad drivers of those functional blocks would no longer consume any power.
- FIG. 1 is an example of a digital electronic circuit with reduced power consumption in accordance with the present invention
- FIG. 2 is a clock control timing diagram of the circuit of FIG. 1;
- FIG. 3 is an example of a data flow for external interface 0 of FIG. 1;
- FIG. 4 is an example of a clock control decision flow for the external interface 0 of FIG. 1;
- FIG. 5 is a flow diagram of an exemplary sub-function of FIG. 1;
- FIG. 6 is a block diagram of an exemplary clock control of FIG. 1;
- FIG. 7 is an example of data flow from an external interface 0 to external interface 1 of FIG. 1.
- a system 10 with power conservation includes a number of functional blocks 12 including blocks 12a, 12b, 12c, 12d, and 12e.
- the system 10 with power conservation also includes a special block 14 and a clock control 16.
- the system 10 with power conservation is implemented as part of an integrated circuit.
- the system 10 can be implemented as a number of integrated circuits, or with discrete electronic devices.
- the functional blocks 12 all include digital circuitry that are capable of processing data.
- Each of the functional blocks 12 include a modulated clock input line 18a, 18b, 18c, 18d, and 18e, respectively, for the functional blocks 12a-12e.
- the signal carried by the modulated clock inputs 18a14 18e are designated as "mc.”
- Each of the functional blocks 12 also include clock control buses 20a, 20b, 20c, 20d, and 20e, respectively, for each of the functional blocks 12a-12e.
- the clock control buses 20a-20e are buses in that they typically include a number of control lines. Alternatively, any one or more of the clock control buses 20 could include only a single control line, in which case the clock control bus 20 reduces to a clock control line 20.
- the functional blocks 12 are coupled to each other by data paths 22. More particularly, the exemplary system with power conservation of FIG. 1 includes data paths 22a, 22b, 22c, 22d, 22e, 22f, 22g, and 22h. These data paths 22a-2h are shown by way of example and will, of course, vary depending on the implementation of the system 10.
- functional block 12a is designated as "external interface 0."
- Data path 22a allows communication between the system 10 and an external system.
- Data path 22b connects external interface 0 to functional block 12b which, in this case, is designated as "sub-function 1.”
- Data path 22h connects external interface 0 to functional block 12e which, in this example, is labeled "sub-function 2.”
- Sub-function 1 and sub-function 2 are functional blocks of digital circuitry which perform data manipulation, but which do not communicate outside of the system 10.
- External interface 1 communicates with sub-function 1 by data path 22c
- external interface communicates with sub-function 2 by data path 22g.
- External interface 1 and external interface 2 communicate with each other by data path 22e
- external interface 1 communicates with systems outside of system 10 by data path 22d
- external interface 2 communicates with systems outside of system 10 by data path 22f.
- Special block 14 is a block of digital circuitry which is intended to be never shut off during the operation of the system 10.
- An example of a special block 14 is DRAM refresh timer circuitry which must be operating all of the time. Therefore, the special block 14 is coupled to clock control 16 by a clock line 24 which carries the signal output clock regular (OCR).
- the special block 14 may or may not have a special clock control bus 26.
- the various functional blocks 12 have relationships depending upon their inter-connection by data paths ("dp").
- external interface 0 functional block 12a
- functional block 12a has data paths connecting it directly to sub-function 1 (functional block 12b) and sub-function 2 (functional block 12e).
- Functional block 12 is considered to be a "neighbor" of another functional block 12 if the two functional blocks are connected by a data path. Therefore, functional block 12a has two neighbors, namely neighbor 12b coupled by data path 22b and neighbor 12e coupled by data path 22h.
- the concept of neighbors is important because in one aspect of the present invention, a functional block can determine whether a neighbor block is to be activated ("turned-on") or deactivated (“turned-off").
- a functional block If a functional block has N neighbors, it can be provided with N+1 output lines to individually control the activation or deactivation of each of its neighbors and itself. However, a functional block can also be provided with less than N+1 outputs if, for example, it does not need to control certain ones of its neighbors.
- a functional block 12 is activated or deactivated is, in the present embodiment, determined by a signal on modulated clock line 18. If a functional block 12 is active, the mc signal on modulated clock line 18 to that particular functional block will oscillate at about the full clock rate. If a functional block is to be deactivated, the mc signal is essentially turned off.
- the clock control buses 20a are input to clock control 16 to provide a plurality of clock control inputs. As will be discussed in greater detail subsequently, the clock control 16 uses the signals cc on clock control buses 20 to control the modulation of the mc signals on lines 18.
- Clock control 16 has, as an input, an input clock on a line 28. As will be discussed in greater detail subsequently, this input clock is conditioned to provide the output clock regular (OCR) on line 24 and the modulated clocks (mc) on lines 18a-18e. It is considered advantageous in the present invention to have a centralized clock control 16 rather than having each of the functional blocks 12 having the circuitry shut off its own clock base on data flow. This is because the system 10, by having a centralized clock control 16, more accurately allows the control of skew across the circuit. As it is well known to those skilled in the art, skew becomes a substantial problem in high speed digital circuitry in that phase shifts between the clocks can accumulate to cause data errors. By dividing the system 10 into a number of functional blocks 12 and by providing a centralized clock controller, each of the modulated clocks 18 are substantially in phase, thereby minimizing skew problems.
- a "cascading" or “pipeline” effect can be achieved.
- a particular functional block can cause a neighbor functional block to turn on, and that neighbor functional block can turn on the next functional block, etc. in the direction of data flow.
- Functional blocks that are no longer needed can be turned off behind the flow of data. Therefore, it is considered an important aspect of the present invention that a separate, centralized clock control 16 communicates with and controls the various functional blocks 12.
- FIG. 2 a clock control timing diagram is illustrated.
- the input clock on line 28 is shown in the top row.
- the output clock regular (OCR) on line 24 is illustrated.
- a clock control signal (cc) from a bus 20 is shown below the output clock regular, and a modulated clock signal (me) on a line 18 is shown below the control clock signal.
- any digital circuitry in the system 10 be operated from either the output clock regular (OCR) or from one of the modulated clock (mc) to minimize skew along the integrated circuit.
- OCR output clock regular
- mc modulated clock
- the modulated clock (mc) on lines 18 therefore operates at two fundamental frequencies: full on and off.
- a first frequency F 1 the modulated clock signal mc on line 18 has about the same frequency as the output clock regular or, for that matter, the input clock on line 28 (except that it is relatively skewed with respect to the input clock).
- a typical frequency F 1 is about 40-80 megahertz.
- the second frequency F 2 is, in the present embodiment, 0 hertz. Therefore, a functional block 12 is either operating at full speed, or not at all. While it is also possible to have a frequency F 2 that is greater than 0 but less than frequency F 1 this will not be a desired mode of operation since there will some activity of the functional block 12 when it is not required by the system. Therefore, the modulated clock of the present invention preferably modulates between a full clock on and a clock off speed.
- FIG. 3 a sample interface data flow is shown for functional block 12a (external interface 0).
- the data paths 22a, 22b, and 22h have each been split into two data paths, i.e. unidirectional data paths that either lead from or lead to the external interface 0.
- the functional block 12a includes latches 30 and 32, logic 34 and 36, internal registers 38, and a multiplexer (MUX) 40.
- MUX multiplexer
- the functional block 12a will be used to illustrate the concept of data flow. For example, data may flow in the direction indicated by arrow 42 from the data path external 22a to either the data path 22b or 22h. Data may also flow in the direction of arrow 44 from the data path 22b or the data path 22h. It is also possible for data to flow in a somewhat circular fashion as indicated by arrow 46 by flowing from the data path external 22a into the latch 30 and then into the internal register 38 and from there into MUX 40 and latch 32 and then out of the data path external 22a. In any event, the functional block 12a (which is typically implemented as a state machine) will know the direction of the data flow.
- This information can then be used to create the control signal (cc) on the clock control buses 20 to control which functional blocks will be activated and which functional blocks 12 will be deactivated.
- the design and operation of functional blocks 12, such as the functional block 12a of FIG. 3, are well known to those skilled in the art.
- the data path external on line 22a is split into two branches depending upon the direction of data flow.
- data flows into latch 30 which is then latched by a clock.
- the data can then flow into logic blocks 34 or 36 (depending upon the direction of data flow), and from there by placed onto data paths 22b or 22h, respectively.
- the data in latch 30 can be stored in internal register 38.
- the output of internal register 38 form inputs to MUX 40 along with data from data paths 22b and 22h.
- An output from MUX 40 is selected by control circuitry (not shown) to be stored in latch 32 and to be placed back on the data path external 22a.
- FIG. 4 a state machine process 46 implemented by the functional block 12a of FIG. 3 is illustrated.
- the design and operation of state machines are, of course, well known to those skilled in the art.
- the state machine process 46 has a base or "idle" state 48 and a number of transient states 50, 52, 54, 56, 58, and 60. Again, this state machine process 46 is offered by way of example and not by way of limitation.
- cc (ei0 -- to -- sf1) enables the clock for sub-function 1 when it is about to receive data from external interface 0
- cc (ei0 -- to -- sf2) enables the clock for sub-function 2 when it is about to receive data from external interface 0
- the state machine process 46 idles in a base state 48. It should be noted that in this state, the clock control values for the external interface 0, the sub-function 1, and the sub-function 2 are all equal to 0, i.e., is indicated that all of these functional blocks should be deactivated. However, it should be noted that other control signals also go into the clock controller which may be activating one of these functional blocks independently of the idle state 48 of external interface 0.
- the state machine process 46 will remain in this idle state 48 until a command is received so that it can enter one of the transient states 50-60. For example, if a "write to sub-function 2" command is received, the state machine process 46 enters the transient state 50. In this state, the external interface 0 is activated (i.e.
- cc(ext -- int0) is set to 1), as is the sub-function 2.
- Data is then processed for sub-function 2 and process control is returned to the idle state 48, where the functional block and its neighbors is deactivated.
- the transient state 52 is entered where the external interface 0 is activated and data is latched from subfunction2. Again, process control then returns to the idle state 48 where the functional blocks 12a, 12b, and 12e are all deactivated. If a "read register" command is received, the external interface 0 is activated and a read from the internal register is performed before returning to the idle state 48.
- transient state 56 activates the clock for external interface 0 and latches data from subfunction 1 before returning to the idle state 48. If a "write to sub-function 1" is received, the external interface 0 is activated, as is sub-function 1 (functional block 12b). Data is then processed for sub-function 1 and the process re-enters the idle state 48. Finally, if a "write register" command is received, state 60 is entered wherein the external interface 0 is enabled and data is written to the internal register. Process control then returns to the idle state 48.
- the various functional blocks 12 are activated, as needed, and are deactivated after they have accomplished their task.
- the clocks to the functional blocks are turned off. As noted previously, this greatly reduces the power consumption of the system.
- FIG. 5 illustrates the operation of a sub-function block, such as subfunction block 1 (functional block 12b).
- subfunction block 1 functional block 12b
- the next functional block also impacts the clock control (cc) signals received by the clock control 16.
- cc clock control
- cc (ei0 -- to -- sf1) enables the clock for sub-function 1 when it is about to receive data from external interface 0
- cc (sf1 -- to -- ei1) enables the clock for external interface 1 when it is about to receive data from sub-function 1
- the clock for sub-function 1 is started in a step 64 when it is recognized that there is data in this path.
- Step 64 then activates both subfunction 1 and external interface 1 (functional block 12c).
- the data is then received and processed by sub-function 1 and, in a step 66, data is passed to external interface 1.
- sub-function 1 is deactivated, as in external interface 1, since they are no longer required, and both of their clocks are stopped to reduce power consumption.
- FIG. 6 a block diagram of clock control 16 of FIG. 1 is illustrated in greater detail.
- the clock control 16 includes a main clock skew correction and buffering logic 68, combinational logic 70, combinational logic 72, clock gating logic 74, clock gating logic 76, and a buffering block 77. It should be noted that this is only a subset of the entire functionality of clock control 16 and it only deals with the modulated clock signal mc for external interface 0 and the modulated clock signal mc for sub-function 1. However, it will be apparent to those skilled in the art how this can be extended to make and use the system 10 of FIG. 1.
- the clock on line 28 is input to the main clock skew correction and buffering logic 68.
- the output of logic circuit 68 is applied to buffering block 77 to produce the output clock regular (OCR) on line 24.
- the output of the buffering logic 68 is also provided to the clock gating logic 74 and 76.
- the purpose of the buffering block 77 is to minimize skew between the output clock regular on line 24 and the modulated clocks on lines 18a and 18b by emulating (with buffers) the delays caused by logic 74 and 76.
- the combinational logic for clock control 70 and 72 have, as inputs, various clock control lines from clock control buses 20.
- Logic 70 and 72 also includes an "ACS enable" line 78 which turns on or off the power reduction system of the present invention.
- ACS line 78 when the ACS line 78 is enabled, functional blocks 12 will be turned on and off as required, but when ACS is not enabled, all of the functional blocks 12 will be on all of the time, providing no power consumption reduction.
- the combinational logic 70 receives various cc signals derived from clock control buses 20a, 20b, and 20e.
- the combinational logic for external interface 0 receives information from external interface 0 and its two neighbors, sub-function 1 and sub-function 2.
- the output from combinational logic 70 on a line 80 is input to the clock gating logic 74 where it "modulates" the output clock regular.
- modulation it is meant that the signal on line 80 will allow the output clock regular to be passed through to line 18a when external interface 0 is to be activated, and the output clock regular is blocked from being placed on line 18a when the external interface is to be deactivated.
- the signal on line 80 "modulates” the output clock regular signal in a fashion very analogous to the way a modulation signal modulates a higher-frequency carrier signal in amplitude-modulated radio signals.
- combinational logic 72 has, as inputs, lines from buses 20a, 20b, and 20c. In other words, combinational logic 72 receives clock control inputs from sub-function 1 and to its immediate neighbors, external interface 0 and external interface 1. The combinational logic 72 then provides a signal on a line 82 which modulates the output clock regular signal on line 24 within the clock gating logic 76. Similarly, as discussed above, the "modulation" performed by the signal on line 82, permits the output clock regular to be coupled to sub-function 1 when sub-function 1 is to be activated, and prevents the clock from being applied to sub-function 1 when sub-function 1 is to be deactivated.
- FIG. 7 illustrates an example of data flow from external interface 0 to external interface 1.
- the external interface 0 data is idled as is the sub-function 1 data and the external interface 1 data.
- the data 1 is passed to sub-function 1 which, after a time delay, causes the external interface 1 clock to become active.
- the data 1 is passed to external interface 1.
- data2 and data3 are serially present at external interface 0 and are subsequently passed onto sub-function 1 and external interface 1 in a pipeline fashion.
- the external interface 0 clock is deactivated.
- the sub-function 1 clock is deactivated.
- the external interface 1 clock is deactivated.
- the activation and deactivation of the various functional blocks 12 is dependent upon the flow of data within system 10. If data is flowing in the direction of a particular functional block, that functional block is activated to receive the data in a cascading or pipelining fashion. As a particular functional block has completed its task and has returned to an idle state, it is deactivated to conserve power.
Abstract
Description
Claims (28)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/212,854 USRE36839E (en) | 1995-02-14 | 1998-12-16 | Method and apparatus for reducing power consumption in digital electronic circuits |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US38831295A | 1995-02-14 | 1995-02-14 | |
US08/686,272 US5585745A (en) | 1995-02-14 | 1996-07-25 | Method and apparatus for reducing power consumption in digital electronic circuits |
US09/212,854 USRE36839E (en) | 1995-02-14 | 1998-12-16 | Method and apparatus for reducing power consumption in digital electronic circuits |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US38831295A Continuation | 1995-02-14 | 1995-02-14 | |
US08/686,272 Reissue US5585745A (en) | 1995-02-14 | 1996-07-25 | Method and apparatus for reducing power consumption in digital electronic circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE36839E true USRE36839E (en) | 2000-08-29 |
Family
ID=23533597
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/686,272 Ceased US5585745A (en) | 1995-02-14 | 1996-07-25 | Method and apparatus for reducing power consumption in digital electronic circuits |
US09/212,854 Expired - Lifetime USRE36839E (en) | 1995-02-14 | 1998-12-16 | Method and apparatus for reducing power consumption in digital electronic circuits |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/686,272 Ceased US5585745A (en) | 1995-02-14 | 1996-07-25 | Method and apparatus for reducing power consumption in digital electronic circuits |
Country Status (3)
Country | Link |
---|---|
US (2) | US5585745A (en) |
EP (1) | EP0809825A1 (en) |
WO (1) | WO1996025701A1 (en) |
Cited By (72)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6501300B2 (en) * | 2000-11-21 | 2002-12-31 | Hitachi, Ltd. | Semiconductor integrated circuit |
US6611920B1 (en) * | 2000-01-21 | 2003-08-26 | Intel Corporation | Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit |
US6636074B2 (en) | 2002-01-22 | 2003-10-21 | Sun Microsystems, Inc. | Clock gating to reduce power consumption of control and status registers |
US6640322B1 (en) | 2000-03-22 | 2003-10-28 | Sun Microsystems, Inc. | Integrated circuit having distributed control and status registers and associated signal routing means |
US20030235103A1 (en) * | 2002-06-25 | 2003-12-25 | Raad George B. | Circuit, system and method for selectively turning off internal clock drivers |
US6694441B1 (en) | 2000-11-15 | 2004-02-17 | Koninklijke Philips Electronics N.V. | Power management method and arrangement for bus-coupled circuit blocks |
US6822481B1 (en) | 2003-06-12 | 2004-11-23 | Agilent Technologies, Inc. | Method and apparatus for clock gating clock trees to reduce power dissipation |
US6845456B1 (en) | 2001-05-01 | 2005-01-18 | Advanced Micro Devices, Inc. | CPU utilization measurement techniques for use in power management |
EP1503271A2 (en) * | 2003-07-30 | 2005-02-02 | Sony Computer Entertainment Inc. | Power-saving device for controlling circuit operation, and information processing apparatus |
US6889332B2 (en) | 2001-12-11 | 2005-05-03 | Advanced Micro Devices, Inc. | Variable maximum die temperature based on performance state |
US6895520B1 (en) | 2001-03-02 | 2005-05-17 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
US20050188236A1 (en) * | 2004-02-23 | 2005-08-25 | Griffin Daniel J. | System and method for providing clock signals |
US20060156062A1 (en) * | 2002-05-14 | 2006-07-13 | Wolfram Drescher | Method for effecting the controlled shutdown of data processing units |
US7218152B2 (en) | 2005-01-12 | 2007-05-15 | Kabushiki Kaisha Toshiba | System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer |
US7228447B1 (en) * | 2002-09-19 | 2007-06-05 | Cisco Technology, Inc. | Methods and apparatus for monitoring a power source |
US7254721B1 (en) | 2001-05-01 | 2007-08-07 | Advanced Micro Devices, Inc. | System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit |
US7379316B2 (en) | 2005-09-02 | 2008-05-27 | Metaram, Inc. | Methods and apparatus of stacking DRAMs |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US7472220B2 (en) | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US20090152948A1 (en) * | 2003-05-07 | 2009-06-18 | Mosaid Technologies Corporation | Power managers for an integrated circuit |
US20100095094A1 (en) * | 2001-06-20 | 2010-04-15 | Martin Vorbach | Method for processing data |
US20100095088A1 (en) * | 2001-09-03 | 2010-04-15 | Martin Vorbach | Reconfigurable elements |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US7797561B1 (en) | 2006-12-21 | 2010-09-14 | Nvidia Corporation | Automatic functional block level clock-gating |
US7802118B1 (en) * | 2006-12-21 | 2010-09-21 | Nvidia Corporation | Functional block level clock-gating within a graphics processor |
US20100287324A1 (en) * | 1999-06-10 | 2010-11-11 | Martin Vorbach | Configurable logic integrated circuit having a multidimensional structure of configurable elements |
US20110010523A1 (en) * | 1996-12-09 | 2011-01-13 | Martin Vorbach | Runtime configurable arithmetic and logic cell |
US20110119657A1 (en) * | 2007-12-07 | 2011-05-19 | Martin Vorbach | Using function calls as compiler directives |
US7958483B1 (en) * | 2006-12-21 | 2011-06-07 | Nvidia Corporation | Clock throttling based on activity-level signals |
US20110145547A1 (en) * | 2001-08-10 | 2011-06-16 | Martin Vorbach | Reconfigurable elements |
US20110161977A1 (en) * | 2002-03-21 | 2011-06-30 | Martin Vorbach | Method and device for data processing |
US20110173596A1 (en) * | 2007-11-28 | 2011-07-14 | Martin Vorbach | Method for facilitating compilation of high-level code for varying architectures |
US8019589B2 (en) | 2006-07-31 | 2011-09-13 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8281265B2 (en) | 2002-08-07 | 2012-10-02 | Martin Vorbach | Method and device for processing data |
US8280714B2 (en) | 2006-07-31 | 2012-10-02 | Google Inc. | Memory circuit simulation system and method with refresh capabilities |
US8281108B2 (en) | 2002-01-19 | 2012-10-02 | Martin Vorbach | Reconfigurable general purpose processor having time restricted configurations |
US8301872B2 (en) | 2000-06-13 | 2012-10-30 | Martin Vorbach | Pipeline configuration protocol and configuration unit communication |
US8312301B2 (en) | 2001-03-05 | 2012-11-13 | Martin Vorbach | Methods and devices for treating and processing data |
US8310274B2 (en) | 2002-09-06 | 2012-11-13 | Martin Vorbach | Reconfigurable sequencer structure |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8407525B2 (en) | 2001-09-03 | 2013-03-26 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8471593B2 (en) | 2000-10-06 | 2013-06-25 | Martin Vorbach | Logic cell array and bus system |
USRE44365E1 (en) | 1997-02-08 | 2013-07-09 | Martin Vorbach | Method of self-synchronization of configurable elements of a programmable module |
US8566516B2 (en) | 2006-07-31 | 2013-10-22 | Google Inc. | Refresh management of memory modules |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8819505B2 (en) | 1997-12-22 | 2014-08-26 | Pact Xpp Technologies Ag | Data processor having disabled cores |
US8869121B2 (en) | 2001-08-16 | 2014-10-21 | Pact Xpp Technologies Ag | Method for the translation of programs for reconfigurable architectures |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US8972673B2 (en) | 2006-07-31 | 2015-03-03 | Google Inc. | Power management of memory circuits by virtual memory simulation |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US9329666B2 (en) | 2012-12-21 | 2016-05-03 | Advanced Micro Devices, Inc. | Power throttling queue |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US9542353B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5799178A (en) * | 1996-04-19 | 1998-08-25 | Vlsi Technology, Inc. | System and method for starting and maintaining a central processing unit (CPU) clock using clock division emulation (CDE) during break events |
US5983356A (en) * | 1996-06-18 | 1999-11-09 | National Semiconductor Corporation | Power conservation method and apparatus activated by detecting shadowed interrupt signals indicative of system inactivity and excluding prefetched signals |
US5751164A (en) * | 1996-06-24 | 1998-05-12 | Advanced Micro Devices, Inc. | Programmable logic device with multi-level power control |
US5915103A (en) * | 1996-12-05 | 1999-06-22 | Vlsi Technology, Inc. | Method and system for an extensible on silicon bus supporting multiple functional blocks |
GB2323188B (en) * | 1997-03-14 | 2002-02-06 | Nokia Mobile Phones Ltd | Enabling and disabling clocking signals to elements |
US6314523B1 (en) * | 1997-04-09 | 2001-11-06 | Compaq Computer Corporation | Apparatus for distributing power to a system of independently powered devices |
AU9798798A (en) * | 1997-10-10 | 1999-05-03 | Rambus Incorporated | Power control system for synchronous memory device |
US6049882A (en) * | 1997-12-23 | 2000-04-11 | Lg Semicon Co., Ltd. | Apparatus and method for reducing power consumption in a self-timed system |
US6154821A (en) * | 1998-03-10 | 2000-11-28 | Rambus Inc. | Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain |
US6049883A (en) * | 1998-04-01 | 2000-04-11 | Tjandrasuwita; Ignatius B. | Data path clock skew management in a dynamic power management environment |
SE519823C2 (en) | 1998-05-18 | 2003-04-15 | Ericsson Telefon Ab L M | Low power calculator with counter blocks using binary code or Gray code |
JP2000347761A (en) * | 1999-06-02 | 2000-12-15 | Alps Electric Co Ltd | Control circuit |
US6323679B1 (en) * | 1999-11-12 | 2001-11-27 | Sandia Corporation | Flexible programmable logic module |
US6588006B1 (en) * | 1999-12-16 | 2003-07-01 | Lsi Logic Corporation | Programmable ASIC |
GB2360670B (en) * | 2000-03-22 | 2004-02-04 | At & T Lab Cambridge Ltd | Power management system |
EP1204016B1 (en) * | 2000-11-03 | 2007-04-11 | STMicroelectronics S.r.l. | Power down protocol for integrated circuits |
TW482954B (en) * | 2000-11-10 | 2002-04-11 | Via Tech Inc | Internal operation method of chip set to reduce the power consumption |
EP1227385A3 (en) * | 2001-01-24 | 2005-11-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
US6938176B1 (en) * | 2001-10-05 | 2005-08-30 | Nvidia Corporation | Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle |
US7111179B1 (en) | 2001-10-11 | 2006-09-19 | In-Hand Electronics, Inc. | Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters |
EP1363179A1 (en) * | 2002-05-17 | 2003-11-19 | STMicroelectronics S.A. | Architecture for controlling dissipated power in a system on a chip and related system |
WO2004051450A2 (en) * | 2002-12-04 | 2004-06-17 | Koninklijke Philips Electronics N.V. | Software-based control of microprocessor power dissipation |
US6757352B1 (en) * | 2002-12-25 | 2004-06-29 | Faraday Technology Corp. | Real time clock with a power saving counter for embedded systems |
US6915438B2 (en) * | 2003-04-04 | 2005-07-05 | Arraycomm, Inc | Distributed power management method for monitoring control/status signal of sub-modules to manage power of sub-modules by activating clock signal during operation of sub-modules |
US7546559B2 (en) * | 2003-08-01 | 2009-06-09 | Atrenta, Inc. | Method of optimization of clock gating in integrated circuit designs |
US7076748B2 (en) * | 2003-08-01 | 2006-07-11 | Atrenta Inc. | Identification and implementation of clock gating in the design of integrated circuits |
US7251805B2 (en) | 2004-10-12 | 2007-07-31 | Nanotech Corporation | ASICs having more features than generally usable at one time and methods of use |
KR100594943B1 (en) * | 2004-11-30 | 2006-06-30 | 리전츠 오브 더 유니버스티 오브 미네소타 | Metheod for data modulation and demodulation in SoC |
WO2006088167A2 (en) * | 2005-02-16 | 2006-08-24 | Matsushita Electric Industrial Co., Ltd. | Power supply control circuit and electronic circuit |
US8448003B1 (en) | 2007-05-03 | 2013-05-21 | Marvell Israel (M.I.S.L) Ltd. | Method and apparatus for activating sleep mode |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5140184A (en) * | 1989-12-07 | 1992-08-18 | Hitachi, Ltd. | Clock feeding circuit and clock wiring system |
US5239215A (en) * | 1988-05-16 | 1993-08-24 | Matsushita Electric Industrial Co., Ltd. | Large scale integrated circuit configured to eliminate clock signal skew effects |
EP0613074A1 (en) * | 1992-12-28 | 1994-08-31 | Advanced Micro Devices, Inc. | Microprocessor circuit having two timing signals |
EP0624837A1 (en) * | 1993-05-13 | 1994-11-17 | International Business Machines Corporation | Electronic apparatus with reduced power consumption |
GB2279473A (en) * | 1993-06-30 | 1995-01-04 | Intel Corp | Distributed clock signal and clock signal interrupt |
US5430397A (en) * | 1993-01-27 | 1995-07-04 | Hitachi, Ltd. | Intra-LSI clock distribution circuit |
US5638009A (en) * | 1993-10-21 | 1997-06-10 | Sun Microsystems, Inc. | Three conductor asynchronous signaling |
-
1996
- 1996-02-12 EP EP96904627A patent/EP0809825A1/en not_active Withdrawn
- 1996-02-12 WO PCT/US1996/001991 patent/WO1996025701A1/en not_active Application Discontinuation
- 1996-07-25 US US08/686,272 patent/US5585745A/en not_active Ceased
-
1998
- 1998-12-16 US US09/212,854 patent/USRE36839E/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5239215A (en) * | 1988-05-16 | 1993-08-24 | Matsushita Electric Industrial Co., Ltd. | Large scale integrated circuit configured to eliminate clock signal skew effects |
US5140184A (en) * | 1989-12-07 | 1992-08-18 | Hitachi, Ltd. | Clock feeding circuit and clock wiring system |
EP0613074A1 (en) * | 1992-12-28 | 1994-08-31 | Advanced Micro Devices, Inc. | Microprocessor circuit having two timing signals |
US5430397A (en) * | 1993-01-27 | 1995-07-04 | Hitachi, Ltd. | Intra-LSI clock distribution circuit |
EP0624837A1 (en) * | 1993-05-13 | 1994-11-17 | International Business Machines Corporation | Electronic apparatus with reduced power consumption |
GB2279473A (en) * | 1993-06-30 | 1995-01-04 | Intel Corp | Distributed clock signal and clock signal interrupt |
US5638009A (en) * | 1993-10-21 | 1997-06-10 | Sun Microsystems, Inc. | Three conductor asynchronous signaling |
Cited By (132)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110010523A1 (en) * | 1996-12-09 | 2011-01-13 | Martin Vorbach | Runtime configurable arithmetic and logic cell |
USRE45109E1 (en) | 1997-02-08 | 2014-09-02 | Pact Xpp Technologies Ag | Method of self-synchronization of configurable elements of a programmable module |
USRE45223E1 (en) | 1997-02-08 | 2014-10-28 | Pact Xpp Technologies Ag | Method of self-synchronization of configurable elements of a programmable module |
USRE44365E1 (en) | 1997-02-08 | 2013-07-09 | Martin Vorbach | Method of self-synchronization of configurable elements of a programmable module |
US8819505B2 (en) | 1997-12-22 | 2014-08-26 | Pact Xpp Technologies Ag | Data processor having disabled cores |
US8468329B2 (en) | 1999-02-25 | 2013-06-18 | Martin Vorbach | Pipeline configuration protocol and configuration unit communication |
US20100287324A1 (en) * | 1999-06-10 | 2010-11-11 | Martin Vorbach | Configurable logic integrated circuit having a multidimensional structure of configurable elements |
US8312200B2 (en) | 1999-06-10 | 2012-11-13 | Martin Vorbach | Processor chip including a plurality of cache elements connected to a plurality of processor cores |
US8726250B2 (en) | 1999-06-10 | 2014-05-13 | Pact Xpp Technologies Ag | Configurable logic integrated circuit having a multidimensional structure of configurable elements |
US6611920B1 (en) * | 2000-01-21 | 2003-08-26 | Intel Corporation | Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit |
US6640322B1 (en) | 2000-03-22 | 2003-10-28 | Sun Microsystems, Inc. | Integrated circuit having distributed control and status registers and associated signal routing means |
US8301872B2 (en) | 2000-06-13 | 2012-10-30 | Martin Vorbach | Pipeline configuration protocol and configuration unit communication |
US9047440B2 (en) | 2000-10-06 | 2015-06-02 | Pact Xpp Technologies Ag | Logical cell array and bus system |
US8471593B2 (en) | 2000-10-06 | 2013-06-25 | Martin Vorbach | Logic cell array and bus system |
US6694441B1 (en) | 2000-11-15 | 2004-02-17 | Koninklijke Philips Electronics N.V. | Power management method and arrangement for bus-coupled circuit blocks |
US6501300B2 (en) * | 2000-11-21 | 2002-12-31 | Hitachi, Ltd. | Semiconductor integrated circuit |
US6895520B1 (en) | 2001-03-02 | 2005-05-17 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
USRE47420E1 (en) | 2001-03-02 | 2019-06-04 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
USRE48819E1 (en) | 2001-03-02 | 2021-11-16 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
US8312301B2 (en) | 2001-03-05 | 2012-11-13 | Martin Vorbach | Methods and devices for treating and processing data |
US9075605B2 (en) | 2001-03-05 | 2015-07-07 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7647513B2 (en) | 2001-05-01 | 2010-01-12 | Advanced Micro Devices, Inc. | Method and apparatus for improving responsiveness of a power management system in a computing device |
US7254721B1 (en) | 2001-05-01 | 2007-08-07 | Advanced Micro Devices, Inc. | System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit |
US6845456B1 (en) | 2001-05-01 | 2005-01-18 | Advanced Micro Devices, Inc. | CPU utilization measurement techniques for use in power management |
US20100095094A1 (en) * | 2001-06-20 | 2010-04-15 | Martin Vorbach | Method for processing data |
US20110145547A1 (en) * | 2001-08-10 | 2011-06-16 | Martin Vorbach | Reconfigurable elements |
US8869121B2 (en) | 2001-08-16 | 2014-10-21 | Pact Xpp Technologies Ag | Method for the translation of programs for reconfigurable architectures |
US8407525B2 (en) | 2001-09-03 | 2013-03-26 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US20100095088A1 (en) * | 2001-09-03 | 2010-04-15 | Martin Vorbach | Reconfigurable elements |
US8429385B2 (en) | 2001-09-03 | 2013-04-23 | Martin Vorbach | Device including a field having function cells and information providing cells controlled by the function cells |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US6889332B2 (en) | 2001-12-11 | 2005-05-03 | Advanced Micro Devices, Inc. | Variable maximum die temperature based on performance state |
US8281108B2 (en) | 2002-01-19 | 2012-10-02 | Martin Vorbach | Reconfigurable general purpose processor having time restricted configurations |
US6636074B2 (en) | 2002-01-22 | 2003-10-21 | Sun Microsystems, Inc. | Clock gating to reduce power consumption of control and status registers |
US20110161977A1 (en) * | 2002-03-21 | 2011-06-30 | Martin Vorbach | Method and device for data processing |
US7685439B2 (en) * | 2002-05-14 | 2010-03-23 | Nxp B.V. | Method for effecting the controlled shutdown of data processing units |
US20060156062A1 (en) * | 2002-05-14 | 2006-07-13 | Wolfram Drescher | Method for effecting the controlled shutdown of data processing units |
US7089438B2 (en) | 2002-06-25 | 2006-08-08 | Micron Technology, Inc. | Circuit, system and method for selectively turning off internal clock drivers |
US9201489B2 (en) * | 2002-06-25 | 2015-12-01 | Conversant Intellectual Property Management Inc. | Circuit, system and method for selectively turning off internal clock drivers |
US8412968B2 (en) | 2002-06-25 | 2013-04-02 | Mosaid Technologies Incorporated | Circuit, system and method for selectively turning off internal clock drivers |
US20060230303A1 (en) * | 2002-06-25 | 2006-10-12 | Raad George B | Circuit, system and method for selectively turning off internal clock drivers |
US20100174932A1 (en) * | 2002-06-25 | 2010-07-08 | Mosaid Technologies Incorporated | Circuit, system and method for selectively turning off internal clock drivers |
US7669068B2 (en) | 2002-06-25 | 2010-02-23 | Mosaid Technologies Incorporated | Circuit, system and method for selectively turning off internal clock drivers |
US9003214B2 (en) | 2002-06-25 | 2015-04-07 | Conversant Intellectual Property Management Inc. | Circuit, system and method for selectively turning off internal clock drivers |
US20030235103A1 (en) * | 2002-06-25 | 2003-12-25 | Raad George B. | Circuit, system and method for selectively turning off internal clock drivers |
US8281265B2 (en) | 2002-08-07 | 2012-10-02 | Martin Vorbach | Method and device for processing data |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US8803552B2 (en) | 2002-09-06 | 2014-08-12 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
US8310274B2 (en) | 2002-09-06 | 2012-11-13 | Martin Vorbach | Reconfigurable sequencer structure |
US7228447B1 (en) * | 2002-09-19 | 2007-06-05 | Cisco Technology, Inc. | Methods and apparatus for monitoring a power source |
US8762923B2 (en) | 2003-05-07 | 2014-06-24 | Conversant Intellectual Property Management Inc. | Power managers for an integrated circuit |
US20090152948A1 (en) * | 2003-05-07 | 2009-06-18 | Mosaid Technologies Corporation | Power managers for an integrated circuit |
US7996811B2 (en) | 2003-05-07 | 2011-08-09 | Mosaid Technologies Incorporated | Power managers for an integrated circuit |
US8782590B2 (en) | 2003-05-07 | 2014-07-15 | Conversant Intellectual Property Management Inc. | Power managers for an integrated circuit |
US6822481B1 (en) | 2003-06-12 | 2004-11-23 | Agilent Technologies, Inc. | Method and apparatus for clock gating clock trees to reduce power dissipation |
EP1503271A2 (en) * | 2003-07-30 | 2005-02-02 | Sony Computer Entertainment Inc. | Power-saving device for controlling circuit operation, and information processing apparatus |
EP1503271A3 (en) * | 2003-07-30 | 2008-01-02 | Sony Computer Entertainment Inc. | Power-saving device for controlling circuit operation, and information processing apparatus |
US20050188236A1 (en) * | 2004-02-23 | 2005-08-25 | Griffin Daniel J. | System and method for providing clock signals |
US7275168B2 (en) * | 2004-02-23 | 2007-09-25 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | System and method for providing clock signals based on control signals from functional units and on a hibernate signal |
US7218152B2 (en) | 2005-01-12 | 2007-05-15 | Kabushiki Kaisha Toshiba | System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8615679B2 (en) | 2005-06-24 | 2013-12-24 | Google Inc. | Memory modules with reliability and serviceability functions |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US7379316B2 (en) | 2005-09-02 | 2008-05-27 | Metaram, Inc. | Methods and apparatus of stacking DRAMs |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US8582339B2 (en) | 2005-09-02 | 2013-11-12 | Google Inc. | System including memory stacks |
US8811065B2 (en) | 2005-09-02 | 2014-08-19 | Google Inc. | Performing error detection on DRAMs |
US9542353B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US8566556B2 (en) | 2006-02-09 | 2013-10-22 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8797779B2 (en) | 2006-02-09 | 2014-08-05 | Google Inc. | Memory module with memory stack and interface with enhanced capabilites |
US9727458B2 (en) | 2006-02-09 | 2017-08-08 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7761724B2 (en) | 2006-07-31 | 2010-07-20 | Google Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US9047976B2 (en) | 2006-07-31 | 2015-06-02 | Google Inc. | Combined signal delay and power saving for use with a plurality of memory circuits |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US7472220B2 (en) | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US8566516B2 (en) | 2006-07-31 | 2013-10-22 | Google Inc. | Refresh management of memory modules |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8595419B2 (en) | 2006-07-31 | 2013-11-26 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8601204B2 (en) | 2006-07-31 | 2013-12-03 | Google Inc. | Simulating a refresh operation latency |
US8340953B2 (en) | 2006-07-31 | 2012-12-25 | Google, Inc. | Memory circuit simulation with power saving capabilities |
US7730338B2 (en) | 2006-07-31 | 2010-06-01 | Google Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8019589B2 (en) | 2006-07-31 | 2011-09-13 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8631220B2 (en) | 2006-07-31 | 2014-01-14 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8671244B2 (en) | 2006-07-31 | 2014-03-11 | Google Inc. | Simulating a memory standard |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8280714B2 (en) | 2006-07-31 | 2012-10-02 | Google Inc. | Memory circuit simulation system and method with refresh capabilities |
US8972673B2 (en) | 2006-07-31 | 2015-03-03 | Google Inc. | Power management of memory circuits by virtual memory simulation |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8745321B2 (en) | 2006-07-31 | 2014-06-03 | Google Inc. | Simulating a memory standard |
US8868829B2 (en) | 2006-07-31 | 2014-10-21 | Google Inc. | Memory circuit system and method |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8112266B2 (en) | 2006-07-31 | 2012-02-07 | Google Inc. | Apparatus for simulating an aspect of a memory circuit |
US8154935B2 (en) | 2006-07-31 | 2012-04-10 | Google Inc. | Delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8751732B2 (en) | 2006-10-05 | 2014-06-10 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8370566B2 (en) | 2006-10-05 | 2013-02-05 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8977806B1 (en) | 2006-10-05 | 2015-03-10 | Google Inc. | Hybrid memory module |
US8760936B1 (en) | 2006-11-13 | 2014-06-24 | Google Inc. | Multi-rank partial width memory modules |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8446781B1 (en) | 2006-11-13 | 2013-05-21 | Google Inc. | Multi-rank partial width memory modules |
US7797561B1 (en) | 2006-12-21 | 2010-09-14 | Nvidia Corporation | Automatic functional block level clock-gating |
US7802118B1 (en) * | 2006-12-21 | 2010-09-21 | Nvidia Corporation | Functional block level clock-gating within a graphics processor |
US7958483B1 (en) * | 2006-12-21 | 2011-06-07 | Nvidia Corporation | Clock throttling based on activity-level signals |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8675429B1 (en) | 2007-11-16 | 2014-03-18 | Google Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US20110173596A1 (en) * | 2007-11-28 | 2011-07-14 | Martin Vorbach | Method for facilitating compilation of high-level code for varying architectures |
US20110119657A1 (en) * | 2007-12-07 | 2011-05-19 | Martin Vorbach | Using function calls as compiler directives |
US8705240B1 (en) | 2007-12-18 | 2014-04-22 | Google Inc. | Embossed heat spreader |
US8730670B1 (en) | 2007-12-18 | 2014-05-20 | Google Inc. | Embossed heat spreader |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8631193B2 (en) | 2008-02-21 | 2014-01-14 | Google Inc. | Emulation of abstracted DIMMS using abstracted DRAMS |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8762675B2 (en) | 2008-06-23 | 2014-06-24 | Google Inc. | Memory system for synchronous data transmission |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8819356B2 (en) | 2008-07-25 | 2014-08-26 | Google Inc. | Configurable multirank memory system with interface circuit |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US9329666B2 (en) | 2012-12-21 | 2016-05-03 | Advanced Micro Devices, Inc. | Power throttling queue |
Also Published As
Publication number | Publication date |
---|---|
WO1996025701A1 (en) | 1996-08-22 |
EP0809825A1 (en) | 1997-12-03 |
US5585745A (en) | 1996-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE36839E (en) | Method and apparatus for reducing power consumption in digital electronic circuits | |
US5630143A (en) | Microprocessor with externally controllable power management | |
US6694443B1 (en) | System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectively | |
US5910930A (en) | Dynamic control of power management circuitry | |
EP0242010B1 (en) | Clock circuit for a data processor | |
US5452434A (en) | Clock control for power savings in high performance central processing units | |
US5926641A (en) | Clock frequency change circuit | |
JP3734888B2 (en) | Microprocessor with power management function | |
US5632037A (en) | Microprocessor having power management circuitry with coprocessor support | |
KR100881774B1 (en) | Method and apparatus to provide deterministic power-on voltage in a system having processor-controlled voltage level | |
US6988214B1 (en) | Processor power state transistions using separate logic control | |
US20130173951A1 (en) | Controlling communication of a clock signal to a peripheral | |
KR19990076908A (en) | Power Management Device and Method | |
US20080155280A1 (en) | Reducing idle leakage power in an ic | |
US20030159080A1 (en) | Information processing unit | |
US5789952A (en) | Anti-lock CPU clock control method, circuit and apparatus | |
EP1237066B1 (en) | Microprocessor with hardware controlled power management and selectable input/output control pins and method therfor | |
US5375209A (en) | Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin | |
EP1570335B1 (en) | An apparatus and method for address bus power control | |
US6853929B2 (en) | Pipeline control for power management | |
CN114077570A (en) | Semiconductor device with a plurality of transistors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PHILIPS SEMICONDUCTORS INC.;REEL/FRAME:018645/0779 Effective date: 20061130 Owner name: PHILIPS SEMICONDUCTORS VLSI INC., NEW YORK Free format text: CHANGE OF NAME;ASSIGNOR:VLSI TECHNOLOGY, INC.;REEL/FRAME:018635/0570 Effective date: 19990702 |
|
AS | Assignment |
Owner name: PHILIPS SEMICONDUCTORS INC., NEW YORK Free format text: CHANGE OF NAME;ASSIGNOR:PHILIPS SEMICONDUCTORS VLSI INC.;REEL/FRAME:018668/0255 Effective date: 19991220 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: VLSI TECHNOLOGY, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SIMMONS, LAURA E;JAYAVANT, RAJEEV;REEL/FRAME:022562/0724 Effective date: 19950207 |
|
AS | Assignment |
Owner name: HAYSTACK ALLEY, LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B.V.;REEL/FRAME:022575/0968 Effective date: 20090302 |
|
AS | Assignment |
Owner name: MOSAID TECHNOLOGIES INCORPORATED,CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HAYSTACK ALLEY, LLC;REEL/FRAME:024244/0822 Effective date: 20100327 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, CANADA Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196 Effective date: 20111223 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638 Effective date: 20140101 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 276 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |