USRE36773E - Method for plating using nested plating buses and semiconductor device having the same - Google Patents

Method for plating using nested plating buses and semiconductor device having the same Download PDF

Info

Publication number
USRE36773E
USRE36773E US08/970,272 US97027297A USRE36773E US RE36773 E USRE36773 E US RE36773E US 97027297 A US97027297 A US 97027297A US RE36773 E USRE36773 E US RE36773E
Authority
US
United States
Prior art keywords
substrate
plating
receiving area
die
nested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/970,272
Inventor
Victor K. Nomi
John R. Pastore
Twila J. Reeves
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/970,272 priority Critical patent/USRE36773E/en
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of USRE36773E publication Critical patent/USRE36773E/en
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MOTOROLA, INC.
Assigned to CITIBANK, N.A. AS COLLATERAL AGENT reassignment CITIBANK, N.A. AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE ACQUISITION CORPORATION, FREESCALE ACQUISITION HOLDINGS CORP., FREESCALE HOLDINGS (BERMUDA) III, LTD., FREESCALE SEMICONDUCTOR, INC.
Assigned to CITIBANK, N.A., AS COLLATERAL AGENT reassignment CITIBANK, N.A., AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE SEMICONDUCTOR, INC.
Assigned to CITIBANK, N.A., AS NOTES COLLATERAL AGENT reassignment CITIBANK, N.A., AS NOTES COLLATERAL AGENT SECURITY AGREEMENT Assignors: FREESCALE SEMICONDUCTOR, INC.
Anticipated expiration legal-status Critical
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to FREESCALE SEMICONDUCTOR, INC. reassignment FREESCALE SEMICONDUCTOR, INC. PATENT RELEASE Assignors: CITIBANK, N.A., AS COLLATERAL AGENT
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Assignors: CITIBANK, N.A.
Assigned to NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC. reassignment NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Assignors: CITIBANK, N.A.
Assigned to NXP B.V. reassignment NXP B.V. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Assigned to NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC. reassignment NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Definitions

  • the present invention relates to plating and plated devices in general, and more specifically to plating using nested plating buses and semiconductor devices having such nested plating buses.
  • ICs integrated circuits
  • traditional microprocessor circuits are being combined on a single chip with digital signal process circuits.
  • These combined ICs have the advantage of better reliability due to fewer total external connections, but have higher input/output (I/O) counts than many of the individual ICs.
  • I/O input/output
  • these combined devices have I/Os in the 200+ range.
  • new ICs are being designed "from the ground up" with many advanced features which also result in 200+ I/Os. Thus, high I/O counts are becoming more and more commonplace.
  • the OMPAC package (a type of ball grid array or BGA package) consists of a printed circuit board (PCB) or other insulating material substrate having a plurality of conductive traces on both the top and bottom surfaces, vias connecting the top traces to the bottom traces, and solder pads at ends of the bottom traces.
  • the traces, vias, and pads are typically formed of copper and are subsequently plated with nickel and gold.
  • a semiconductor die is attached to the top of the substrate, and wires are used to electrically couple the die to the top set of traces.
  • An organic encapsulation is applied over the die, wires and portions of the top of the substrate.
  • a mass of solder in the form of spheres, paste, or plating is then applied to the solder pads on the bottom of the package. Since OMPAC packages have an array of solder pads covering most of the package bottom, the package is typically much smaller than corresponding peripherally leaded packages. An array takes advantage of the entire area of the package, whereas peripherally leaded packages can only take advantage of the outer perimeter of the package.
  • OMPAC is considered a low cost package.
  • the most expensive individual cost component is the substrate.
  • the cost of a single layer, double sided substrate is significantly lower than that of a multilayer substrate and is therefore preferred for OMPAC applications.
  • One of the limitations of single layer substrates is the restriction in routing electrical connections from the vias to an external plating bus formed at the periphery of the package. Electrical connections to the plating bus are required for electrolytic plating of nickel and gold onto those portions of the copper laminate which will be used for subsequent electrical bonding (i.e. die bonding, wire bonding, and solder ball reflow) or for electrical probing and testing.
  • the nickel and gold plating layers protect the copper from oxidation, resulting in a surface which is easier to bond and probe.
  • all conductive parts which are to be plated are electrically short-circuited so that necessary current applied during the electrolytic process easily passes through all members to be plated. This is typically accomplished by routing all members to an external plating bus. The bus must eventually be removed to create electrical isolation between the various conductive features.
  • the routing density i.e. number of traces per unit area
  • the routing density of a substrate used in OMPAC packages is dictated by the size of the via holes, the size of the annular rings surrounding each via hole, the solder pad diameter, the minimum copper trace width and the minimum gap between copper traces.
  • the external plating connections also often directly limit the number of discrete I/O connections possible for single layer substrate packages. In other words, the need to connect all traces to an external, peripheral plating bus often restricts the routing density for a given size substrate.
  • OMPAC substrate In the case of a typical OMPAC substrate, (assuming 1.5 mm solder pad pitch, 0.25 mm via diameter, 0.50 mm annular via ring diameter, 0.89 mm solder pad diameter, 0.1 mm copper trace width and 0.1 mm gap between copper traces), it is possible to have up to 3 traces between vias on the top surface of the package, and to have up to 2 traces between solder pads on the bottom surface. These traces can be used to either route from wire bond fingers to vias (where wire bond fingers are pads at the ends of top surface traces which surround the die and which receive the bonding wires), or from vias to the external plating bus. These figures put a lower limit on the size of a particular substrate for a given number of I/Os.
  • the via and solder pad pitches would have to be increased to allow more traces to fit between pads and vias, or the via and solder pad diameters would have to be decreased.
  • Increasing the solder pad and via pitches undesirably increases the size of the substrate and size of the final package, whereas decreasing solder pad and via diameters would undesirably increase the cost to manufacture the substrate and reduce the solder joint strength due to the smaller solder pads. Accordingly, it would be desirable to eliminate the need to route traces to external plating buses. This would reduce the number of traces that need to be routed between vias and between solder pads, thereby keeping substrate size to a minimum while increasing routing density.
  • electroless plating is inherently thinner and more porous than electrolytic plating which makes it marginal at preventing oxidation of the underlying copper. This in turn makes it more difficult to achieve good, reliable bonding onto the plated surfaces. Consequently, the use of electroless gold plating is limited to special cases where the time and temperature exposures are short and low enough that the resulting oxidation does not impede the creation of reliable bonds.
  • a plating method is used to plate a plurality of radially arranged conductive members.
  • Each conductive member has an inner end and an outer end.
  • the plurality of conductive members is divided into a first group of conductive members and a second group of conductive members.
  • Each outer end of conductive members in the first group is connected to an outer plating bus.
  • Each inner end of the conductive members of the second group is connected to a nested plating bus inside the outer plating bus, while each outer end of the conductive members of the second group is unconnected to the outer plating bus.
  • the conductive members of both the first and second group are then plated.
  • a semiconductor device includes features of a substrate plated by such a method.
  • FIG. 1 is a top view of a portion of a substrate used for plating, and for making a semiconductor device, in accordance with the present invention.
  • FIG. 2 is an exploded view of a portion of the substrate illustrated in FIG. 1.
  • FIG. 3 is a cross-sectional view of a semiconductor device utilizing a substrate such as that illustrated in FIG. 1, also in accordance with the present invention.
  • the present invention increases the maximum possible I/O count for a given substrate size by allowing a nested plating bus to complement the existing external plating bus.
  • the use of the nested plating bus reduces or eliminates the need for bottom side electrical routing which should improve package reliability and electrical performance by increasing the distance between discrete conductive traces, vias and solder pads on the bottom side of the substrate.
  • FIG. 1 is a top view of a portion of a PCB or other insulating material substrate 10 which is plated by a method in accordance with the present invention.
  • the electrical usefulness of the substrate for an electronic application is created by various conductive elements. These include a plurality of plated through holes or vias 12, a plurality of conductive traces 14, an external plating bus 16, a nested plating bus 18, and a plurality of bonding fingers 20.
  • each of these conductive members is formed of laminated or deposited copper.
  • Conductive traces 14 can be located on any signal routing layer (top or bottom surfaces of single layer double sided substrates, or internal layers of multilayer substrates).
  • Conductive traces 14 are used to route from bonding fingers 20 to vias 12 which are in turn connected to solder pads (not shown) on the bottom of substrate 10.
  • the portions of the traces connecting bonding fingers 20 to vias 12 are electrically functional in a finished semiconductor device in that these portions are used to transmit signals during device operation.
  • the conductive traces 14 are routed to either the nested plating bus 18 which lies within the finished package outline 24, or to the external plating bus 16 which lies outside the finished package outline 24.
  • Finished package outline 24 represents where substrate 10 will be excised to form a completed semiconductor device.
  • the portions of the traces used to route from vias to a plating bus are necessary only for plating purposes, not for functional purposes during semiconductor device operation.
  • nested plating bus 18 also lies within a die receiving area 22, which represents the area of substrate 10 onto which a semiconductor die (not shown in FIG. 1) will eventually be mounted.
  • a die receiving area 22 represents the area of substrate 10 onto which a semiconductor die (not shown in FIG. 1) will eventually be mounted.
  • the present invention does not require that the nested plating bus be within the die receiving area. Benefits of the present invention are reaped as long as the nested plating bus lies within the external finished package outline.
  • FIG. 2 is an exploded view of highlighted region 28 of FIG. 1.
  • conductive traces 14 are connected to vias 12 both above and below the row of bonding fingers 20, and are then routed to either the nested plating bus 18 or to the external plating 16.
  • Traces connected to vias below the row of bonding fingers are a first group of traces, and are also connected to external plating bus 16.
  • Traces connected to vias above the row of bonding fingers are a second group of traces, and are also connected to nested plating bus 18.
  • OMPAC substrates only utilize an external plating bus, such as external plating bus 16.
  • an external plating bus such as external plating bus 16.
  • conductive traces can be routed to only a maximum of six rows of vias.
  • substrate designs require two conductive traces between vias on the bottom side of the substrate, in addition to three conductive traces between vias on the top side of the substrate.
  • the use of both top and bottom side traces in current substrates is undesirable both from a manufacturing/reliability point of view, and from a device operational performance point of view, as discussed above.
  • the present invention permits eight rows of vias without any bottom side traces.
  • FIG. 3 is a cross-sectional view of an OMPAC semiconductor device 30 in accordance with the present invention.
  • Device 30 includes a portion of substrate 10, namely that portion denoted by finished package outline 24 of FIG. 1.
  • a semiconductor die 34 attached to the substrate 10 by means of an adhesive die attach 36.
  • Bonding wires 38 are used to connect the semiconductor die 34 to plated conductive traces 14, or more specifically to bonding fingers 20 at the ends of the conductive traces (although in FIG. 3, the bonding fingers and traces are indistinguishable).
  • a resin package body 40 is then molded or dispensed over the semiconductor die 34, the bonding wires 38, and over most portions of the top side of substrate 10 to provide environmental protection.
  • a mass of solder in the form of spheres, paste or plating 44 is then applied to a plurality of solder pads 42 formed on the bottom side of substrate 10.
  • the pads are electrically coupled to the semiconductor die through vias 12, bonding wires 38 and conductive traces 14.
  • Many of the manufacturing operations thus far described can be performed while substrate 10 is in a strip or sheet form having many die or device sites.
  • device 30 is removed from the surrounding substrate material and forms the outside dimension (the finished package outline) 24 of the individual semiconductor device 30.
  • device 30 is excised after molding package body 40 and after the application of solder 44 to solder pads 42, being practically the last value-added manufacturing step. In another embodiment, excision occurs after molding but before solder 44 is applied.
  • substrate 10 has an etched/milled area 32 which is where a nested plating bus, and perhaps inner portions of conductive traces 14, have been removed from substrate 10 so that the conductive traces are no longer electrically short-circuited together.
  • Area 32 in preferred embodiments, is formed using known etching or milling techniques. Instead, the nested plating bus may be severed by means of punching or other material removal processes. Although a solid area has been removed from substrate 10 as illustrated in FIG. 3, it is also possible to sever the nested plating bus by removing a smaller portion of the substrate, for instance by milling a shape or outline which conforms to the shape of the bus (e.g. a rectangular groove). It is also appropriate to note that the shape of a nested plating bus is not important to practicing the invention.
  • trace 14 in the left half of device 30 begins at bonding finger 20 and terminates at the edge of removed area 32.
  • the trace 14 in the right half of device 30 likewise begins at bonding finger 20, but extends away from area 32 to the finished package outline 24 of substrate 10.
  • the right end of this trace was previously connected to an external plating bus.
  • each trace 14 is divided into two portions, a functional portion 46 and a plating portion 48.
  • the functional portion 46 of each trace is that portion of the trace which electrically couples die 34 to an external I/O connection, such as solder ball 44.
  • the plating portion 48 of each trace is that portion of the trace which routes the trace to a plating bus, either external or nested, but is otherwise not necessary for device operation.
  • Another term for plating portions 48 known in the art in devices having only external plating buses is a plating stub.
  • the benefits of the present invention can likewise be achieved in substrates which have both top and bottom side routing, either top or bottom side routing alone, or external surface routing in conjunction with internal surface routing.
  • the present invention may be practiced wherein a nested plating bus is on one surface of a substrate while the external plating bus is on the opposing surface.
  • the present invention is not limited to applications of OMPAC semiconductor devices or ball grid arrays, but instead can be used in any device or process which is to be plated. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.

Abstract

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

Description

FIELD OF THE INVENTION
The present invention relates to plating and plated devices in general, and more specifically to plating using nested plating buses and semiconductor devices having such nested plating buses.
BACKGROUND OF THE INVENTION
Due to the constant push for smaller and smaller products, it has become common for integrated circuits (ICs) once contained on two or more individual semiconductor die or chips to be combined into a single, larger IC device. For example, traditional microprocessor circuits are being combined on a single chip with digital signal process circuits. These combined ICs have the advantage of better reliability due to fewer total external connections, but have higher input/output (I/O) counts than many of the individual ICs. Often, these combined devices have I/Os in the 200+ range. Additionally, new ICs are being designed "from the ground up" with many advanced features which also result in 200+ I/Os. Thus, high I/O counts are becoming more and more commonplace.
Over Molded Pad Array Carrier or OMPAC is one successful method for containing relatively large I/O count into a small footprint at low cost. The OMPAC package (a type of ball grid array or BGA package) consists of a printed circuit board (PCB) or other insulating material substrate having a plurality of conductive traces on both the top and bottom surfaces, vias connecting the top traces to the bottom traces, and solder pads at ends of the bottom traces. The traces, vias, and pads, are typically formed of copper and are subsequently plated with nickel and gold. A semiconductor die is attached to the top of the substrate, and wires are used to electrically couple the die to the top set of traces. An organic encapsulation is applied over the die, wires and portions of the top of the substrate. A mass of solder in the form of spheres, paste, or plating is then applied to the solder pads on the bottom of the package. Since OMPAC packages have an array of solder pads covering most of the package bottom, the package is typically much smaller than corresponding peripherally leaded packages. An array takes advantage of the entire area of the package, whereas peripherally leaded packages can only take advantage of the outer perimeter of the package.
Due to the basic nature of the package components, OMPAC is considered a low cost package. The most expensive individual cost component is the substrate. The cost of a single layer, double sided substrate is significantly lower than that of a multilayer substrate and is therefore preferred for OMPAC applications. One of the limitations of single layer substrates is the restriction in routing electrical connections from the vias to an external plating bus formed at the periphery of the package. Electrical connections to the plating bus are required for electrolytic plating of nickel and gold onto those portions of the copper laminate which will be used for subsequent electrical bonding (i.e. die bonding, wire bonding, and solder ball reflow) or for electrical probing and testing. The nickel and gold plating layers protect the copper from oxidation, resulting in a surface which is easier to bond and probe. In order to accomplish electrolytic plating, all conductive parts which are to be plated are electrically short-circuited so that necessary current applied during the electrolytic process easily passes through all members to be plated. This is typically accomplished by routing all members to an external plating bus. The bus must eventually be removed to create electrical isolation between the various conductive features.
To achieve a higher I/O count without increasing package size and without moving to a multiple layer substrate, the routing density (i.e. number of traces per unit area) on the outer surfaces must be increased. The routing density of a substrate used in OMPAC packages is dictated by the size of the via holes, the size of the annular rings surrounding each via hole, the solder pad diameter, the minimum copper trace width and the minimum gap between copper traces. Depending on the capabilities of the substrate manufacturer and on the I/O count of the package, the external plating connections also often directly limit the number of discrete I/O connections possible for single layer substrate packages. In other words, the need to connect all traces to an external, peripheral plating bus often restricts the routing density for a given size substrate.
In the case of a typical OMPAC substrate, (assuming 1.5 mm solder pad pitch, 0.25 mm via diameter, 0.50 mm annular via ring diameter, 0.89 mm solder pad diameter, 0.1 mm copper trace width and 0.1 mm gap between copper traces), it is possible to have up to 3 traces between vias on the top surface of the package, and to have up to 2 traces between solder pads on the bottom surface. These traces can be used to either route from wire bond fingers to vias (where wire bond fingers are pads at the ends of top surface traces which surround the die and which receive the bonding wires), or from vias to the external plating bus. These figures put a lower limit on the size of a particular substrate for a given number of I/Os. In order to achieve additional routing, and thus a higher I/O count, with the current single layer OMPAC substrates, the via and solder pad pitches would have to be increased to allow more traces to fit between pads and vias, or the via and solder pad diameters would have to be decreased. Increasing the solder pad and via pitches undesirably increases the size of the substrate and size of the final package, whereas decreasing solder pad and via diameters would undesirably increase the cost to manufacture the substrate and reduce the solder joint strength due to the smaller solder pads. Accordingly, it would be desirable to eliminate the need to route traces to external plating buses. This would reduce the number of traces that need to be routed between vias and between solder pads, thereby keeping substrate size to a minimum while increasing routing density.
One known solution to the routing problem imposed by the need to route traces to an external plating bus is the use of so-called "electroless" plating processes. External plating connections would not be required if the substrates were nickel and gold plated using electroless plating techniques since electroless plating does not require all conductive elements to be short-circuited together. However, electroless plating is inherently thinner and more porous than electrolytic plating which makes it marginal at preventing oxidation of the underlying copper. This in turn makes it more difficult to achieve good, reliable bonding onto the plated surfaces. Consequently, the use of electroless gold plating is limited to special cases where the time and temperature exposures are short and low enough that the resulting oxidation does not impede the creation of reliable bonds.
Therefore, an alternative to the existing external peripheral plating bus used in OMPAC semiconductor devices, and similar devices having wired substrates, would be desirable. Moreover, such an alternative should improve the existing plating process by allowing more traces and vias to be formed in a given area of the substrate than presently possible.
SUMMARY OF THE INVENTION
In accordance with one form of the invention, a plating method is used to plate a plurality of radially arranged conductive members. Each conductive member has an inner end and an outer end. The plurality of conductive members is divided into a first group of conductive members and a second group of conductive members. Each outer end of conductive members in the first group is connected to an outer plating bus. Each inner end of the conductive members of the second group is connected to a nested plating bus inside the outer plating bus, while each outer end of the conductive members of the second group is unconnected to the outer plating bus. The conductive members of both the first and second group are then plated. In another form of the present invention, a semiconductor device includes features of a substrate plated by such a method.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a portion of a substrate used for plating, and for making a semiconductor device, in accordance with the present invention.
FIG. 2 is an exploded view of a portion of the substrate illustrated in FIG. 1.
FIG. 3 is a cross-sectional view of a semiconductor device utilizing a substrate such as that illustrated in FIG. 1, also in accordance with the present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
The present invention increases the maximum possible I/O count for a given substrate size by allowing a nested plating bus to complement the existing external plating bus. In addition, the use of the nested plating bus reduces or eliminates the need for bottom side electrical routing which should improve package reliability and electrical performance by increasing the distance between discrete conductive traces, vias and solder pads on the bottom side of the substrate.
These and other features, and advantages, of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of the present invention which are not specifically illustrated. Also, like reference numerals may be used throughout the various views, indicating identical, corresponding, or similar elements.
FIG. 1 is a top view of a portion of a PCB or other insulating material substrate 10 which is plated by a method in accordance with the present invention. The electrical usefulness of the substrate for an electronic application is created by various conductive elements. These include a plurality of plated through holes or vias 12, a plurality of conductive traces 14, an external plating bus 16, a nested plating bus 18, and a plurality of bonding fingers 20. In a preferred embodiment of the present invention, each of these conductive members is formed of laminated or deposited copper. Conductive traces 14 can be located on any signal routing layer (top or bottom surfaces of single layer double sided substrates, or internal layers of multilayer substrates). Conductive traces 14 are used to route from bonding fingers 20 to vias 12 which are in turn connected to solder pads (not shown) on the bottom of substrate 10. The portions of the traces connecting bonding fingers 20 to vias 12 are electrically functional in a finished semiconductor device in that these portions are used to transmit signals during device operation. For electrolytic plating purposes, the conductive traces 14 are routed to either the nested plating bus 18 which lies within the finished package outline 24, or to the external plating bus 16 which lies outside the finished package outline 24. Finished package outline 24 represents where substrate 10 will be excised to form a completed semiconductor device. The portions of the traces used to route from vias to a plating bus are necessary only for plating purposes, not for functional purposes during semiconductor device operation. As illustrated, nested plating bus 18 also lies within a die receiving area 22, which represents the area of substrate 10 onto which a semiconductor die (not shown in FIG. 1) will eventually be mounted. However, it is important to note that the present invention does not require that the nested plating bus be within the die receiving area. Benefits of the present invention are reaped as long as the nested plating bus lies within the external finished package outline.
FIG. 2 is an exploded view of highlighted region 28 of FIG. 1. As shown, conductive traces 14 are connected to vias 12 both above and below the row of bonding fingers 20, and are then routed to either the nested plating bus 18 or to the external plating 16. Traces connected to vias below the row of bonding fingers are a first group of traces, and are also connected to external plating bus 16. Traces connected to vias above the row of bonding fingers are a second group of traces, and are also connected to nested plating bus 18. In the example shown, it is possible to route conductive traces 14 to eight rows of vias 12, four rows on either side of the row of bonding fingers 20. As illustrated in FIG. 2, all of the routing is on the top side of the substrate which maximizes the electrical isolation on the bottom side of the substrate. In prior art substrates, routing is often needed on both the top and bottom sides of the substrate. However, manufacturers would like to eliminate any unnecessary surface routing for several reasons. One reason is that extraneous routing may create noise during device operation. Another reason is that the more routing there is on the surface, the more likely unwanted short-circuiting will occur between adjacent conductive members.
Current single layer OMPAC substrates only utilize an external plating bus, such as external plating bus 16. With use of only an external plating bus, and assuming the feature dimensions listed in the background, conductive traces can be routed to only a maximum of six rows of vias. Moreover, to achieve this maximum 6 rows of vias, substrate designs require two conductive traces between vias on the bottom side of the substrate, in addition to three conductive traces between vias on the top side of the substrate. The use of both top and bottom side traces in current substrates is undesirable both from a manufacturing/reliability point of view, and from a device operational performance point of view, as discussed above. The present invention permits eight rows of vias without any bottom side traces. Thus, more I/Os can be achieved in a single layer substrate using a plating method in accordance with the present invention, then if using a traditional plating method for a single layer substrate. Moreover, the higher I/O count possible with the present invention can be achieved by routing on only one surface of the substrate, whereas multilayer routing would be necessary to achieve comparable I/O counts on existing substrates and with existing plating techniques. It is important to note, however, that the present invention is not limited to plating substrates having only one-sided routing. Benefits of the present invention can also be obtained in substrates having multiple layers of routing, both external and internal.
FIG. 3 is a cross-sectional view of an OMPAC semiconductor device 30 in accordance with the present invention. Device 30 includes a portion of substrate 10, namely that portion denoted by finished package outline 24 of FIG. 1. Also in device 30 is a semiconductor die 34 attached to the substrate 10 by means of an adhesive die attach 36. Bonding wires 38 are used to connect the semiconductor die 34 to plated conductive traces 14, or more specifically to bonding fingers 20 at the ends of the conductive traces (although in FIG. 3, the bonding fingers and traces are indistinguishable). A resin package body 40 is then molded or dispensed over the semiconductor die 34, the bonding wires 38, and over most portions of the top side of substrate 10 to provide environmental protection. A mass of solder in the form of spheres, paste or plating 44 is then applied to a plurality of solder pads 42 formed on the bottom side of substrate 10. The pads are electrically coupled to the semiconductor die through vias 12, bonding wires 38 and conductive traces 14. Many of the manufacturing operations thus far described can be performed while substrate 10 is in a strip or sheet form having many die or device sites. At some stage in manufacturing, device 30 is removed from the surrounding substrate material and forms the outside dimension (the finished package outline) 24 of the individual semiconductor device 30. In one embodiment of the present invention, device 30 is excised after molding package body 40 and after the application of solder 44 to solder pads 42, being practically the last value-added manufacturing step. In another embodiment, excision occurs after molding but before solder 44 is applied.
As illustrated in FIG. 3, substrate 10 has an etched/milled area 32 which is where a nested plating bus, and perhaps inner portions of conductive traces 14, have been removed from substrate 10 so that the conductive traces are no longer electrically short-circuited together. Area 32, in preferred embodiments, is formed using known etching or milling techniques. Instead, the nested plating bus may be severed by means of punching or other material removal processes. Although a solid area has been removed from substrate 10 as illustrated in FIG. 3, it is also possible to sever the nested plating bus by removing a smaller portion of the substrate, for instance by milling a shape or outline which conforms to the shape of the bus (e.g. a rectangular groove). It is also appropriate to note that the shape of a nested plating bus is not important to practicing the invention.
As illustrated in FIG. 3, trace 14 in the left half of device 30 begins at bonding finger 20 and terminates at the edge of removed area 32. Thus, the right end of this trace was previously connected to a nested plating bus in accordance with the present invention. The trace 14 in the right half of device 30 likewise begins at bonding finger 20, but extends away from area 32 to the finished package outline 24 of substrate 10. Thus, the right end of this trace was previously connected to an external plating bus. As also illustrated in FIG. 3, each trace 14 is divided into two portions, a functional portion 46 and a plating portion 48. The functional portion 46 of each trace is that portion of the trace which electrically couples die 34 to an external I/O connection, such as solder ball 44. The plating portion 48 of each trace is that portion of the trace which routes the trace to a plating bus, either external or nested, but is otherwise not necessary for device operation. Another term for plating portions 48 known in the art in devices having only external plating buses (e.g. like in the right hand portion of device 30) is a plating stub.
The foregoing description and illustrations contained herein demonstrate many of the advantages associated with the present invention. In particular, it has been revealed that use of a nested plating bus increases the maximum possible I/O count for a given substrate. Moreover, the use of a nested plating bus reduces the requirement for bottom side electrical routing which should improve package reliability and electrical performance by increasing the distance between conductive traces and metal features. Another advantage is that depending on the specific substrate configuration, use of a nested plating bus can reduce the length of the plating connections which will reduce electrical parasitics and thus enhance the performance of the semiconductor device.
Thus it is apparent that there has been provided, in accordance with the invention, a method for plating using nested plating buses and a semiconductor device having the same, that fully meets the need and advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, multilayer substrate designs are not shown but will be subject to the limitations and advantages discussed for single layer substrates. In addition, the invention is not limited to any particular shape for a nested plating bus. Furthermore, a substrate used in accordance with the present invention may utilize filled vias as opposed to plated through holes. Furthermore, while a description of the present invention included the elimination of bottom side routing in accordance with one embodiment, the benefits of the present invention can likewise be achieved in substrates which have both top and bottom side routing, either top or bottom side routing alone, or external surface routing in conjunction with internal surface routing. Moreover, the present invention may be practiced wherein a nested plating bus is on one surface of a substrate while the external plating bus is on the opposing surface. In addition, the present invention is not limited to applications of OMPAC semiconductor devices or ball grid arrays, but instead can be used in any device or process which is to be plated. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.

Claims (21)

What is claimed is:
1. A method for plating a plurality of radially arranged conductive members, wherein each conductive member has an inner end and an outer end and wherein the plurality of conductive members is divided into a first group of conductive members and a second group of conductive members, comprising the steps of:
connecting the outer end of each member of the first group to an outer plating bus;
connecting the inner end of each member of the second group to a nested plating bus that is inside the outer plating bus, without connecting the outer end of each member of the second group to the outer plating bus; and
plating the plurality of conductive members.
2. The method of claim 1 wherein the plurality of conductive members comprise a plurality of conductive traces on a surface of a printed wiring substrate.
3. The method of claim 2 wherein the printed wiring substrate has a plurality of bonding fingers for wire bonding to a semiconductor die, and wherein the inner end of each member of the first group is connected to a corresponding bonding finger, and the outer end of each member of the second group is connected to a different corresponding bonding finger than the corresponding bonding finger of each member of the first group.
4. The method of claim 3 wherein the plurality of bonding fingers divides the plurality of conductive members into the first and the second groups of conductive members.
5. A method for plating a wiring substrate comprising the steps of:
providing an insulating substrate material having .[.a surface,.]. a package receiving area, and a die receiving area within the package receiving area;
forming an outer plating bus on .[.the surface of.]. the substrate .[.which.]., .Iadd.wherein the outer plating bus .Iaddend.substantially surrounds the package receiving area;
forming a nested plating bus on .[.the surface of.]. the substrate and within the outer plating bus;
forming a first plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the first plurality of traces being connected to the outer plating bus;
forming a second plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the second plurality of traces being connected to the outer plating bus; and
plating the first and the second pluralities of conductive traces.
6. The method of claim 5 wherein the first and second pluralities of conductive traces are physically separated from one another by a plurality of conductive bonding fingers formed on the .[.the surface of.]. the substrate and substantially surrounding the die receiving area.
7. The method of claim 5 wherein the steps of forming the outer plating bus, the nested plating bus, the first plurality of conductive traces, and the second plurality of conductive traces are accomplished simultaneously.
8. The method of claim 5 wherein the outer plating bus and the nested plating bus are both substantially rectangular rings.
9. The method of claim 5 further comprising the step of removing the nested plating bus from within the package receiving area to form a plurality of plating stubs.
10. The method of claim 9 wherein the step of removing the nested plating bus comprises chemically etching the nested plating bus.
11. The method of claim 9 wherein the step of removing the nested plating bus comprises mechanically removing the nested plating bus.
12. The method of claim 5 wherein the nested plating bus is formed within the die receiving area of the substrate.
13. A method for making a semiconductor device comprising the steps of:
providing a wiring substrate made in accordance with a method comprising the steps of:
providing an insulating substrate material having .[.a surface,.]. a package receiving area, and a die receiving area within the package receiving area;
forming an outer plating bus on .[.the surface of.]. the substrate which substantially surrounds the package receiving area;
forming a nested plating bus on .[.the surface of.]. the substrate and within the outer plating bus;
forming a first plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the first plurality of traces being connected to the outer plating bus;
forming a second plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the second plurality of traces being connected to the nested plating bus without being connected to the outer plating bus;
plating the first and the second pluralities of conductive traces; and
removing the nested plating bus from the .[.surface of the.]. substrate, leaving a plurality of plating stubs on the .[.surface.]. .Iadd.substrate;.Iaddend.
providing a semiconductor die;
positioning the die within the die receiving area;
electrically coupling the die to the first and the second pluralities of conductive traces; and
encapsulating the die in a protective body.
14. The method of claim 13 wherein the step of positioning the die comprises positioning the die over the plurality of plating stubs.
15. The method of claim 13 further comprising the step of excising the package receiving area of the substrate from remaining portions of the substrate.
16. A semiconductor device comprising:
a printed wiring substrate having a periphery, a surface, a die receiving area on the surface, a plurality of conductive bonding fingers formed on the surface and surrounding the die receiving area, a first plurality of conductive vias extending through the substrate and positioned within the plurality of conductive bonding fingers, a second plurality of conductive vias extending through the substrate and positioned without the plurality of conductive bonding fingers, wherein each via of the first and the second pluralities of vias has two associated trace portions on the .[.surface.]. .Iadd.substrate, .Iaddend.a bonding trace portion and a plating trace portion, wherein the bonding trace portion of each via of the first and the second pluralities of vias is routed to a corresponding bonding finger, and wherein the plating trace portion of each via in the second plurality of vias is routed outward to the periphery of the substrate while the plating trace portion of each via in the first plurality of vias is routed inward toward a center of the substrate;
a semiconductor die positioned within the die receiving area;
means for electrically coupling the die to the plurality of bonding fingers on the substrate; and
a protective body encapsulating the semiconductor.
17. The semiconductor device of claim 16 further comprising a recessed portion in .[.the surface of.]. the substrate within the plurality of bonding fingers, and wherein the plating trace portion of each via in the second plurality of vias terminates at the recessed portion.
18. The semiconductor device of claim 16 wherein the printed wiring substrate is selected from a group consisting of: a printed circuit board and a ceramic substrate.
19. A semiconductor device comprising:
a printed wiring substrate having a periphery, .[.a surface,.]. a die receiving area on the .[.surface.]. .Iadd.substrate, .Iaddend.a first and a second plurality of conductive vias extending through the substrate, and a plating trace connected to each via of the first and the second pluralities of vias, wherein the plating traces associated with the first plurality of vias exist on the .[.surface.]. .Iadd.substrate .Iaddend.and terminate at the periphery of the substrate and the plating traces associated with the second plurality of vias exist on the .[.surface.]. .Iadd.substrate .Iaddend.and terminate near the die receiving area;
a semiconductor die positioned within the die receiving area;
means for electrically coupling the semiconductor die to the first and the second pluralities of vias; and
means for providing environmental protection to the semiconductor die.
20. The semiconductor device of claim 19 wherein the printed wiring substrate is selected from a group consisting of: a printed circuit board and a ceramic substrate.
21. The semiconductor device of claim 19 further comprising a functional trace associated with each via of the first and the second pluralities of vias for carrying signals to the semiconductor die.
US08/970,272 1993-10-18 1997-11-14 Method for plating using nested plating buses and semiconductor device having the same Expired - Lifetime USRE36773E (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/970,272 USRE36773E (en) 1993-10-18 1997-11-14 Method for plating using nested plating buses and semiconductor device having the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/136,845 US5467252A (en) 1993-10-18 1993-10-18 Method for plating using nested plating buses and semiconductor device having the same
US08/970,272 USRE36773E (en) 1993-10-18 1997-11-14 Method for plating using nested plating buses and semiconductor device having the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/136,845 Reissue US5467252A (en) 1993-10-18 1993-10-18 Method for plating using nested plating buses and semiconductor device having the same

Publications (1)

Publication Number Publication Date
USRE36773E true USRE36773E (en) 2000-07-11

Family

ID=22474631

Family Applications (2)

Application Number Title Priority Date Filing Date
US08/136,845 Ceased US5467252A (en) 1993-10-18 1993-10-18 Method for plating using nested plating buses and semiconductor device having the same
US08/970,272 Expired - Lifetime USRE36773E (en) 1993-10-18 1997-11-14 Method for plating using nested plating buses and semiconductor device having the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/136,845 Ceased US5467252A (en) 1993-10-18 1993-10-18 Method for plating using nested plating buses and semiconductor device having the same

Country Status (3)

Country Link
US (2) US5467252A (en)
KR (1) KR100232939B1 (en)
MY (1) MY111907A (en)

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278618B1 (en) * 1999-07-23 2001-08-21 National Semiconductor Corporation Substrate strips for use in integrated circuit packaging
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
US6479759B2 (en) * 2000-07-19 2002-11-12 Alcatel Submount, electronic assembly and process for producing the same
US6653214B1 (en) 2002-01-03 2003-11-25 The United States Of America As Represented By The Secretary Of The Air Force Measured via-hole etching
US6686667B2 (en) * 2002-04-22 2004-02-03 Scientek Corp. Image sensor semiconductor package with castellation
US20040026767A1 (en) * 2001-06-27 2004-02-12 Shinko Electric Industries Co., Ltd. Wiring substrate having position information
US20040036068A1 (en) * 2002-08-20 2004-02-26 St Assembly Test Services Pte Ltd Test coupon pattern design to control multilayer saw singulated plastic ball grid array substrate mis-registration
US6731013B2 (en) * 2000-06-28 2004-05-04 Sharp Kabushiki Kaisha Wiring substrate, semiconductor device and package stack semiconductor device
US6790710B2 (en) 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US20040253825A1 (en) * 2003-06-11 2004-12-16 Matsushita Elec. Ind. Co. Ltd. Semiconductor device
US20060055023A1 (en) * 2004-09-10 2006-03-16 Kwun-Yao Ho Chip carrier and chip package structure thereof
US20070132066A1 (en) * 2005-12-13 2007-06-14 Hem Takiar Substrate having minimum kerf width
US20070201247A1 (en) * 2006-02-28 2007-08-30 Minebea Co., Ltd. Spread illuminating apparatus
US20080303166A1 (en) * 2007-06-08 2008-12-11 Chih-Chin Liao Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel
US7611981B1 (en) * 1997-05-09 2009-11-03 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8299602B1 (en) 2008-09-30 2012-10-30 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1516251A (en) * 1994-03-18 2004-07-28 �������ɹ�ҵ��ʽ���� Method for mfg. semiconductor assembly and semiconductor assembly
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
WO1997022993A1 (en) * 1995-12-15 1997-06-26 International Business Machines Corporation Electronic package with spacer means
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
JP3386977B2 (en) 1997-06-05 2003-03-17 新光電気工業株式会社 Multilayer circuit board
JP3669463B2 (en) * 1997-08-05 2005-07-06 Ｔｄｋ株式会社 Resin-encapsulated surface-mount electronic components
JP3466443B2 (en) 1997-11-19 2003-11-10 新光電気工業株式会社 Multilayer circuit board
JP3380151B2 (en) * 1997-12-22 2003-02-24 新光電気工業株式会社 Multilayer circuit board
US6372553B1 (en) * 1998-05-18 2002-04-16 St Assembly Test Services, Pte Ltd Disposable mold runner gate for substrate based electronic packages
JP3526788B2 (en) * 1999-07-01 2004-05-17 沖電気工業株式会社 Method for manufacturing semiconductor device
US6246312B1 (en) 2000-07-20 2001-06-12 Cts Corporation Ball grid array resistor terminator network
US6632343B1 (en) 2000-08-30 2003-10-14 Micron Technology, Inc. Method and apparatus for electrolytic plating of surface metals
TW575949B (en) * 2001-02-06 2004-02-11 Hitachi Ltd Mixed integrated circuit device, its manufacturing method and electronic apparatus
US7180186B2 (en) * 2003-07-31 2007-02-20 Cts Corporation Ball grid array package
US6946733B2 (en) * 2003-08-13 2005-09-20 Cts Corporation Ball grid array package having testing capability after mounting
FR2886477B1 (en) * 2005-05-31 2007-07-06 Valeo Equip Electr Moteur SIGNAL INTERCONNECTION PIECE FOR ROTATING ELECTRICAL MACHINE
JP5174673B2 (en) * 2005-10-14 2013-04-03 エスティーマイクロエレクトロニクス エス．アール．エル． Electronic device with substrate level assembly and method of manufacturing the same
US7736020B2 (en) * 2006-06-16 2010-06-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Illumination device and method of making the device
US7708427B2 (en) * 2006-06-16 2010-05-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Light source device and method of making the device
GB0721927D0 (en) * 2007-11-08 2007-12-19 Cambridge Silicon Radio Ltd Chip packaging
KR101438826B1 (en) * 2008-06-23 2014-09-05 엘지이노텍 주식회사 Light emitting device
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
US8110500B2 (en) * 2008-10-21 2012-02-07 International Business Machines Corporation Mitigation of plating stub resonance by controlling surface roughness
DE102009042479A1 (en) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Method for producing an arrangement having a component on a carrier substrate and arrangement, and method for producing a semifinished product and semifinished product
IT201700103489A1 (en) 2017-09-15 2019-03-15 St Microelectronics Srl METHOD OF MANUFACTURE OF A THIN FILTERING MEMBRANE, ACOUSTIC TRANSDUCER INCLUDING THE FILTERING MEMBRANE, ASSEMBLY METHOD OF THE ACOUSTIC TRANSDUCER AND ELECTRONIC SYSTEM

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829741A (en) * 1973-01-15 1974-08-13 Hobart Mfg Co Mounting for printed circuit boards
US3932016A (en) * 1973-04-02 1976-01-13 Stromberg-Carlson Corporation Printed circuit card receptacle
JPH0222166A (en) * 1988-04-26 1990-01-25 Toto Ltd Dielectric ceramics for electrostatic chuck and production thereof
US4989317A (en) * 1988-11-21 1991-02-05 Hewlett-Packard Company Method for making tab circuit electrical connector supporting multiple components thereon
US5052936A (en) * 1990-10-26 1991-10-01 Amp Incroporated High density electrical connector
JPH04109642A (en) * 1990-08-30 1992-04-10 Sumitomo Metal Mining Co Ltd Film carrier
US5126813A (en) * 1990-03-07 1992-06-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor pressure sensor device with two semiconductor pressure sensor chips and a method of manufacturing thereof
US5189598A (en) * 1990-08-14 1993-02-23 Dallas Semiconductor Corporation Dual function microboard with a row of connectors on two edges
US5218172A (en) * 1990-07-23 1993-06-08 Siemens Nixdorf Informationssysteme Ag Metallized frame which interconnects etched wirings for integrated circuits
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5468995A (en) * 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5583377A (en) * 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5710693A (en) * 1992-11-13 1998-01-20 Seiko Epson Corporation Electronic device having a flat, card-like casing enclosing components for a complete computer system including a sub-printed wiring board attached to an inner surface of the casing and electrically connected to a printed wiring board by a flexible member
US5756380A (en) * 1995-11-02 1998-05-26 Motorola, Inc. Method for making a moisture resistant semiconductor device having an organic substrate

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829741A (en) * 1973-01-15 1974-08-13 Hobart Mfg Co Mounting for printed circuit boards
US3932016A (en) * 1973-04-02 1976-01-13 Stromberg-Carlson Corporation Printed circuit card receptacle
JPH0222166A (en) * 1988-04-26 1990-01-25 Toto Ltd Dielectric ceramics for electrostatic chuck and production thereof
US4989317A (en) * 1988-11-21 1991-02-05 Hewlett-Packard Company Method for making tab circuit electrical connector supporting multiple components thereon
US5126813A (en) * 1990-03-07 1992-06-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor pressure sensor device with two semiconductor pressure sensor chips and a method of manufacturing thereof
US5218172A (en) * 1990-07-23 1993-06-08 Siemens Nixdorf Informationssysteme Ag Metallized frame which interconnects etched wirings for integrated circuits
US5189598A (en) * 1990-08-14 1993-02-23 Dallas Semiconductor Corporation Dual function microboard with a row of connectors on two edges
JPH04109642A (en) * 1990-08-30 1992-04-10 Sumitomo Metal Mining Co Ltd Film carrier
US5052936A (en) * 1990-10-26 1991-10-01 Amp Incroporated High density electrical connector
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5583377A (en) * 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5710693A (en) * 1992-11-13 1998-01-20 Seiko Epson Corporation Electronic device having a flat, card-like casing enclosing components for a complete computer system including a sub-printed wiring board attached to an inner surface of the casing and electrically connected to a printed wiring board by a flexible member
US5468995A (en) * 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5756380A (en) * 1995-11-02 1998-05-26 Motorola, Inc. Method for making a moisture resistant semiconductor device having an organic substrate

Cited By (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7611981B1 (en) * 1997-05-09 2009-11-03 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
US9224676B1 (en) 1998-06-24 2015-12-29 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8963301B1 (en) 1998-06-24 2015-02-24 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
US6278618B1 (en) * 1999-07-23 2001-08-21 National Semiconductor Corporation Substrate strips for use in integrated circuit packaging
US6731013B2 (en) * 2000-06-28 2004-05-04 Sharp Kabushiki Kaisha Wiring substrate, semiconductor device and package stack semiconductor device
US6479759B2 (en) * 2000-07-19 2002-11-12 Alcatel Submount, electronic assembly and process for producing the same
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US8102037B2 (en) 2001-03-27 2012-01-24 Amkor Technology, Inc. Leadframe for semiconductor package
US6861764B2 (en) * 2001-06-27 2005-03-01 Shinko Electric Industries Co., Ltd. Wiring substrate having position information
US6855626B2 (en) 2001-06-27 2005-02-15 Shinko Electric Industries Co., Ltd. Wiring substrate having position information
US20040026767A1 (en) * 2001-06-27 2004-02-12 Shinko Electric Industries Co., Ltd. Wiring substrate having position information
US6653214B1 (en) 2002-01-03 2003-11-25 The United States Of America As Represented By The Secretary Of The Air Force Measured via-hole etching
US6790710B2 (en) 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US20050077613A1 (en) * 2002-01-31 2005-04-14 Mclellan Neil Robert Integrated circuit package
US6686667B2 (en) * 2002-04-22 2004-02-03 Scientek Corp. Image sensor semiconductor package with castellation
US20040036068A1 (en) * 2002-08-20 2004-02-26 St Assembly Test Services Pte Ltd Test coupon pattern design to control multilayer saw singulated plastic ball grid array substrate mis-registration
US6774640B2 (en) 2002-08-20 2004-08-10 St Assembly Test Services Pte Ltd. Test coupon pattern design to control multilayer saw singulated plastic ball grid array substrate mis-registration
US7164196B2 (en) * 2003-06-11 2007-01-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20040253825A1 (en) * 2003-06-11 2004-12-16 Matsushita Elec. Ind. Co. Ltd. Semiconductor device
US7247951B2 (en) * 2004-09-10 2007-07-24 Via Technologies, Inc. Chip carrier with oxidation protection layer
US20060055023A1 (en) * 2004-09-10 2006-03-16 Kwun-Yao Ho Chip carrier and chip package structure thereof
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US8461675B2 (en) * 2005-12-13 2013-06-11 Sandisk Technologies Inc. Substrate panel with plating bar structured to allow minimum kerf width
US20070132066A1 (en) * 2005-12-13 2007-06-14 Hem Takiar Substrate having minimum kerf width
US20070201247A1 (en) * 2006-02-28 2007-08-30 Minebea Co., Ltd. Spread illuminating apparatus
US7532479B2 (en) * 2006-02-28 2009-05-12 Minebea Co., Ltd. Spread illuminating apparatus
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US8637972B2 (en) * 2007-06-08 2014-01-28 Sandisk Technologies Inc. Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel
US20080303166A1 (en) * 2007-06-08 2008-12-11 Chih-Chin Liao Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8729710B1 (en) 2008-01-16 2014-05-20 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8084868B1 (en) 2008-04-17 2011-12-27 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8299602B1 (en) 2008-09-30 2012-10-30 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8432023B1 (en) 2008-10-06 2013-04-30 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8823152B1 (en) 2008-10-27 2014-09-02 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8188579B1 (en) 2008-11-21 2012-05-29 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
US11869829B2 (en) 2009-01-05 2024-01-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8558365B1 (en) 2009-01-09 2013-10-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8729682B1 (en) 2009-03-04 2014-05-20 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US9275939B1 (en) 2011-01-27 2016-03-01 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9508631B1 (en) 2011-01-27 2016-11-29 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9543235B2 (en) 2013-10-24 2017-01-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

Also Published As

Publication number Publication date
MY111907A (en) 2001-02-28
US5467252A (en) 1995-11-14
KR100232939B1 (en) 1999-12-01
KR950012640A (en) 1995-05-16

Similar Documents

Publication Publication Date Title
USRE36773E (en) Method for plating using nested plating buses and semiconductor device having the same
US5864470A (en) Flexible circuit board for ball grid array semiconductor package
KR100319609B1 (en) A wire arrayed chip size package and the fabrication method thereof
US6462274B1 (en) Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages
US5563446A (en) Surface mount peripheral leaded and ball grid array package
JP2944449B2 (en) Semiconductor package and manufacturing method thereof
US6057601A (en) Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
US7405145B2 (en) Ball grid array package substrates with a modified central opening and method for making the same
US6828665B2 (en) Module device of stacked semiconductor packages and method for fabricating the same
US5889325A (en) Semiconductor device and method of manufacturing the same
US5663593A (en) Ball grid array package with lead frame
US5841191A (en) Ball grid array package employing raised metal contact rings
US6300685B1 (en) Semiconductor package
US6882035B2 (en) Die package
US6465882B1 (en) Integrated circuit package having partially exposed conductive layer
US6790760B1 (en) Method of manufacturing an integrated circuit package
US5726860A (en) Method and apparatus to reduce cavity size and the bondwire length in three tier PGA packages by interdigitating the VCC/VSS
JP2003273280A (en) Chip package and its manufacturing method
JP2003273281A (en) Chip package and its manufacturing method
KR20080000879A (en) Ball grid array semiconductor chip package and testing method of the same
US20140284217A1 (en) Minimizing plating stub reflections in a chip package using capacitance
US6882037B2 (en) Die paddle for receiving an integrated circuit die in a plastic substrate
US20030080418A1 (en) Semiconductor device having power supply pads arranged between signal pads and substrate edge
US20230063343A1 (en) Multilevel package substrate device with bga pin out and coaxial signal connections
JPH0517709B2 (en)

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657

Effective date: 20040404

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657

Effective date: 20040404

AS Assignment

Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129

Effective date: 20061201

Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129D

Effective date: 20061201

Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129

Effective date: 20061201

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001

Effective date: 20100413

Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001

Effective date: 20100413

AS Assignment

Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR

Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424

Effective date: 20130521

AS Assignment

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553

Effective date: 20151207

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143

Effective date: 20151207

Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS

Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225

Effective date: 20151207

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517

Effective date: 20151207

AS Assignment

Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001

Effective date: 20160912

Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001

Effective date: 20160912

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001

Effective date: 20160622

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421

Effective date: 20151207

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001

Effective date: 20160622

AS Assignment

Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001

Effective date: 20160912