USRE31734E - Moderate field hole and electron injection from one interface of MIM or MIS structures - Google Patents

Moderate field hole and electron injection from one interface of MIM or MIS structures Download PDF

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USRE31734E
USRE31734E US06/172,058 US17205880A USRE31734E US RE31734 E USRE31734 E US RE31734E US 17205880 A US17205880 A US 17205880A US RE31734 E USRE31734 E US RE31734E
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insulator
silicon
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oxide
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Donnelli J. DiMaria
Donald R. Young
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International Business Machines Corp
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

Definitions

  • the present invention generally relates to semiconductor devices which use a graded band gap structure to promote the injection of holes or electrons at one interface of an insulator under moderate electric field conditions while, simultaneously, electron or hole injection from the opposite interface is blocked. More particularly, the present invention, in a preferred embodiment, relates to a graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure which is useful in performing a memory function.
  • MGOS graded oxide metal-silicon dioxide-silicon
  • One such device known as a beam addressable MOS, employs a metal-oxide-semiconductor structure, including a PN junction, wherein charges are stored in the structure by writing with an electron beam. Readout is also performed with an electron beam, but at a lower current level. The readout is not totally destructive in that upwards of 10 readouts can be performed before the charge in a memory cell must be renewed.
  • the advantage of this device is that very high memory densities can be achieved.
  • the disadvantages are the requirement for an electron beam with a high vacuum, precision electron optics and deflection circuitry which result in a high cost.
  • FET memory devices are also known in the art.
  • One such device employs a MI 1 I 2 S structure wherein I 1 and I 2 denote first and second insulator layers.
  • the I 1 I 2 interface may include a metallic impurity which provides a well-defined electron trapping region. The presence or absence of trapped electrons in this region is used to define a memory function either by different values of capacitance of the structure or by monitoring the value of source-drain current as affected by the trapped electron charges in the presence of suitable-applied gate voltages.
  • Metallic impurities are not always required at the I 1 I 2 interface as the same effect can be realized by using two different kinds of insulators.
  • one such known device employs a MNOS structure where a thin oxide film is first formed on a silicon substrate, and over this thin oxide film is laid a much thicker silicon nitride film.
  • This particular structure has the advantage, when compared with the beam addressable MOS structure, of requiring much simpler equipment for performing the reading and writing operations in the memory device.
  • This particular structure has the advantage, when compared with the beam addressable MOS structure, of requiring much simpler equipment for performing the reading and writing operations in the memory device.
  • This particular structure has the advantage, when compared with the beam addressable MOS structure, of requiring much simpler equipment for performing the reading and writing operations in the memory device.
  • This oxide layer must be quite thin, on the order of about 20 ⁇ thick, in order to allow tunneling of the electrons or holes from the Si substrate. Reliability problems have been encountered with memory devices with this thin tunnel oxide layer because of the high fields across it during operation.
  • the present invention uses a graded band gap structure to make a charge storage device wherein injection of holes or electrons from one contact is possible without compensating injection of electrons or holes from the other contact.
  • An example of a structure employing this band gap reduction is an MGOS FET to perform a memory function. More specifically, the MGOS structure employs hole trapping near the Si--SiO 2 interface of the gate structure in a FET configuration.
  • the "write" step involves hole injection from the gate electrode under moderate voltage bias and transport to the Si--SiO 2 interface where some of the positively-charged holes are trapped in a very stable manner.
  • the “erase” step involves electron injection from the gate electrode under moderate negative voltage bias and transport to the Si--SiO 2 interface where the electrons would annihilate trapped holes very readily.
  • the "read” operations uses the transconductance of the silicon surface to sense the charged state of the oxide region near the Si--SiO 2 interface and uses low grade voltages to prevent further charging of this region.
  • the band gap graded structure may be fabricated by forming several pyrolytic or CVD SiO 2 layers over a relatively thick thermal SiO 2 layer with the pyrolytic SiO 2 layers having sequentially increasing excess Si content.
  • the structure may also be fabricated by controlled Si ion implantation in the thermal SiO 2 layer.
  • FIG. 1 is an energy band diagram of a conventional MOS structure
  • FIG. 2 is an energy band diagram similar to that of FIG. 1, except that the band gap of the oxide continuously decreases toward the metal electrode interface;
  • FIG. 3 is an energy band diagram which is a stepped approximation the continuously graded energy band gap represented by FIG. 2;
  • FIG. 4 is a cross-sectional view of an MGOS structure which exhibits the characteristics of the energy band diagram shown in FIG. 3;
  • FIG. 5 is the energy band diagram of the MGOS structure of FIG. 4 for positive gate bias indicating hole injection and capture;
  • FIG. 6 is an energy band diagram of the MGOS structure of FIG. 4 for negative gate bias indicating electron injection and annihilation of a trapped hole
  • the ⁇ v level is the valence level and the ⁇ c level is the conduction level in the silicon substrate.
  • the conduction level ⁇ c is typically one electron volt higher than the valence level ⁇ v .
  • the ⁇ f level is the fermi level of the metal electrode, in this case, aluminum.
  • the fermi level ⁇ f in the energy diagram lies somewhere between the valence level ⁇ v and the conduction level ⁇ c of the silicon substrate.
  • Between the silicon substrate and the aluminum contact is an insulator of thermal SiO 2 . In this insulator, the energy level difference between the valence level and the conduction level is on the order of nine electron volts.
  • the continuous grading of the band gap of the insulator is a stepped approximation, as illustrated in FIG. 3.
  • the specific structure which produces the energy band gap diagram, shown in FIG. 3, is shown in a generalized cross-sectional view in FIG. 4.
  • a relatively thick thermal SiO 2 insulator layer is grown.
  • successive pyrolytic or chemical vapor deposition (CVD) SiO 2 layers are deposited.
  • CVD chemical vapor deposition
  • pyrolytic oxide layers can be formed with excess silicon as described, for example, in U.S. Pat. No. 3,649,884.
  • the number of pyrolytic layers, the thickness of each layer, and the amount of excess silicon in each successive layer is a matter of design choice. It will be understood by those skilled in the art, however, that a closer approximation to the continuously graded band gap, as represented by FIG. 2, may be achieved by many small steps.
  • the thermal oxide layer on the other hand, must be sufficiently thick when compared with the graded oxide layers to prevent any charge trapping or detrapping in the graded oxide layers from being sensed by the silicon substrate. This thick thermal oxide layer avoids the reliability problems encountered with memory devices with thin tunnel oxide layers like the MNOS structure.
  • FIG. 5 is an energy band diagram for a positive gate bias applied to the metal contact in the structure shown in FIG. 4.
  • the fermi level ⁇ f of the aluminum contact is substantially lowered with respect to the valence level ⁇ v of the silicon substrate.
  • holes represented by open circles tunnel from the gate electrode into the first pyrolytic oxide layer valence band, and then tunnel sequentially from one oxide layer to the next, as represented by the solid arrows.
  • the hole is captured with about 50 ⁇ of the Si--SiO 2 interface, as represented by the dashed arrows.
  • An accumulation of holes at this interface provides a charge storage which can be used to perform a memory function. That is, the "write” step involves hole injection from the gate under moderate positive voltage bias and tunneling to the Si--SiO 2 interface where some of the positively-charged holes are trapped in a very stable manner.
  • the fermi level ⁇ f of the aluminum contact is raised substantially above the conduction level ⁇ c of the silicon substrate, as shown in FIG. 6.
  • electrons are injected at the aluminum contact into the first pyrolytic oxide layer conduction band, and then tunnel sequentially from one oxide layer to the next. Once in the conduction band of the thermal oxide layer, the electrons may recombine with previously-trapped holes.
  • this mechanism provides an "erase” step which involves electron injection from the gate under moderate negative voltage bias and tunneling to the Si--SiO 2 interface where the electrons annihilate trapped holes very readily.
  • the "read” operation uses the transconductance of the silicon surface to sense the charge state of the oxide region near the Si--SiO 2 interface at low gate voltages to prevent further charging of this region. Because of the thickness of the thermal oxide layer, charge trapping or detrapping in the graded pyrolytic oxide layers is not sensed by the silicon during the "read” operations. Also the magnitude of the applied field during the "read” operation is substantially smaller than the field applied for injection.
  • FIG. 7 A MGOS FET device is shown in FIG. 7.
  • the device employs a gate structure like that shown in FIG. 4 but is otherwise conventional.
  • An array of these FET devices would provide for long-term storage, non-destructive readout and low voltage drive requirements.

Abstract

A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection from the opposite interface is blocked due to the larger insulator band gap near this interface. A graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure may be fabricated by forming several pyrolytic or CVD SiO2 layers over a relatively thick thermal SiO2 layer, with the pyrolytic SiO2 layers having sequentially increasing excess Si content. This structure may also be fabricated by controlled Si ion implantation in the thermal SiO2 layer.

Description

BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices which use a graded band gap structure to promote the injection of holes or electrons at one interface of an insulator under moderate electric field conditions while, simultaneously, electron or hole injection from the opposite interface is blocked. More particularly, the present invention, in a preferred embodiment, relates to a graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure which is useful in performing a memory function.
Semiconductor memory devices in various configurations are known in the art. One such device, known as a beam addressable MOS, employs a metal-oxide-semiconductor structure, including a PN junction, wherein charges are stored in the structure by writing with an electron beam. Readout is also performed with an electron beam, but at a lower current level. The readout is not totally destructive in that upwards of 10 readouts can be performed before the charge in a memory cell must be renewed. The advantage of this device is that very high memory densities can be achieved. Among the disadvantages, however, are the requirement for an electron beam with a high vacuum, precision electron optics and deflection circuitry which result in a high cost.
FET memory devices are also known in the art. One such device employs a MI1 I2 S structure wherein I1 and I2 denote first and second insulator layers. The I1 I2 interface may include a metallic impurity which provides a well-defined electron trapping region. The presence or absence of trapped electrons in this region is used to define a memory function either by different values of capacitance of the structure or by monitoring the value of source-drain current as affected by the trapped electron charges in the presence of suitable-applied gate voltages. Metallic impurities are not always required at the I1 I2 interface as the same effect can be realized by using two different kinds of insulators. For example, one such known device employs a MNOS structure where a thin oxide film is first formed on a silicon substrate, and over this thin oxide film is laid a much thicker silicon nitride film. In this structure, electrons or holes are trapped in the silicon nitride layer. This particular structure has the advantage, when compared with the beam addressable MOS structure, of requiring much simpler equipment for performing the reading and writing operations in the memory device. There is a disadvantage associated with this particular structure, however, and that relates to the thin oxide layer. This oxide layer must be quite thin, on the order of about 20Å thick, in order to allow tunneling of the electrons or holes from the Si substrate. Reliability problems have been encountered with memory devices with this thin tunnel oxide layer because of the high fields across it during operation.
SUMMARY OF THE INVENTION
The present invention uses a graded band gap structure to make a charge storage device wherein injection of holes or electrons from one contact is possible without compensating injection of electrons or holes from the other contact. An example of a structure employing this band gap reduction is an MGOS FET to perform a memory function. More specifically, the MGOS structure employs hole trapping near the Si--SiO2 interface of the gate structure in a FET configuration. The "write" step involves hole injection from the gate electrode under moderate voltage bias and transport to the Si--SiO2 interface where some of the positively-charged holes are trapped in a very stable manner. The "erase" step involves electron injection from the gate electrode under moderate negative voltage bias and transport to the Si--SiO2 interface where the electrons would annihilate trapped holes very readily. The "read" operations uses the transconductance of the silicon surface to sense the charged state of the oxide region near the Si--SiO2 interface and uses low grade voltages to prevent further charging of this region.
The band gap graded structure may be fabricated by forming several pyrolytic or CVD SiO2 layers over a relatively thick thermal SiO2 layer with the pyrolytic SiO2 layers having sequentially increasing excess Si content. The structure may also be fabricated by controlled Si ion implantation in the thermal SiO2 layer.
BRIEF DESCRIPTION OF THE DRAWINGS
Other advantages, aspects and uses of the invention will become apparent from the following detailed description, taken in connection with the accompanying drawings, in which:
FIG. 1 is an energy band diagram of a conventional MOS structure;
FIG. 2 is an energy band diagram similar to that of FIG. 1, except that the band gap of the oxide continuously decreases toward the metal electrode interface;
FIG. 3 is an energy band diagram which is a stepped approximation the continuously graded energy band gap represented by FIG. 2;
FIG. 4 is a cross-sectional view of an MGOS structure which exhibits the characteristics of the energy band diagram shown in FIG. 3;
FIG. 5 is the energy band diagram of the MGOS structure of FIG. 4 for positive gate bias indicating hole injection and capture;
FIG. 6 is an energy band diagram of the MGOS structure of FIG. 4 for negative gate bias indicating electron injection and annihilation of a trapped hole; and
FIG. 7 is a generalized cross-sectional view of a MGOS FET structure according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In the energy band diagram of a conventional MOS structure shown in FIG. 1, the εv level is the valence level and the εc level is the conduction level in the silicon substrate. The conduction level εc is typically one electron volt higher than the valence level εv. The εf level is the fermi level of the metal electrode, in this case, aluminum. The fermi level εf in the energy diagram lies somewhere between the valence level εv and the conduction level εc of the silicon substrate. Between the silicon substrate and the aluminum contact is an insulator of thermal SiO2. In this insulator, the energy level difference between the valence level and the conduction level is on the order of nine electron volts. In addition, the difference between the fermi level εf of the aluminum contact and the conduction level in the thermal SiO2 is on the order of three electron volts. As a result, the thermal SiO2 represents a substantial barrier to conduction between the silicon substrate and the aluminum contact.
By reducing the band gap of the insulator layer of SiO2 near the Al--SiO2 interface, holes or electrons (depending on voltage bias) can be injected into the insulator under moderate electric field conditions from the aluminum contact at this interface. Simultaneously, electron or hole injection from the opposite Si--SiO2 interface is blocked due to the larger insulator band gap near this interface. This graded band gap structure is represented by the energy band diagram of FIG. 2. The continuous grading of the insulator band gap, as illustrated by FIG. 2, could be achieved by ion implantation of silicon, for example, at controlled depths adjacent to the Al--SiO2 interface.
According to a preferred embodiment of the invention, the continuous grading of the band gap of the insulator, as shown in FIG. 2, is a stepped approximation, as illustrated in FIG. 3. The specific structure which produces the energy band gap diagram, shown in FIG. 3, is shown in a generalized cross-sectional view in FIG. 4. Starting with a single crystal silicon substrate, a relatively thick thermal SiO2 insulator layer is grown. Over this thermal oxide insulator layer are deposited successive pyrolytic or chemical vapor deposition (CVD) SiO2 layers. In FIG. 4, three such layers are shown, but any number of layers may be used. Each pyrolytic oxide layer is relatively thin compared to the overall thermal oxide insulator layer; and each successive pyrolytic oxide layer has an increasing amount of excess silicon. It is known that pyrolytic oxide layers can be formed with excess silicon as described, for example, in U.S. Pat. No. 3,649,884. The number of pyrolytic layers, the thickness of each layer, and the amount of excess silicon in each successive layer is a matter of design choice. It will be understood by those skilled in the art, however, that a closer approximation to the continuously graded band gap, as represented by FIG. 2, may be achieved by many small steps. The thermal oxide layer, on the other hand, must be sufficiently thick when compared with the graded oxide layers to prevent any charge trapping or detrapping in the graded oxide layers from being sensed by the silicon substrate. This thick thermal oxide layer avoids the reliability problems encountered with memory devices with thin tunnel oxide layers like the MNOS structure.
FIG. 5 is an energy band diagram for a positive gate bias applied to the metal contact in the structure shown in FIG. 4. In other words, for a positive gate bias, the fermi level εf of the aluminum contact is substantially lowered with respect to the valence level εv of the silicon substrate. Under this condition for gate bias, holes represented by open circles tunnel from the gate electrode into the first pyrolytic oxide layer valence band, and then tunnel sequentially from one oxide layer to the next, as represented by the solid arrows. The hole is captured with about 50Å of the Si--SiO2 interface, as represented by the dashed arrows. An accumulation of holes at this interface provides a charge storage which can be used to perform a memory function. That is, the "write" step involves hole injection from the gate under moderate positive voltage bias and tunneling to the Si--SiO2 interface where some of the positively-charged holes are trapped in a very stable manner.
With the application of a negative gate bias, the fermi level εf of the aluminum contact is raised substantially above the conduction level εc of the silicon substrate, as shown in FIG. 6. Under this condition of negative bias, electrons are injected at the aluminum contact into the first pyrolytic oxide layer conduction band, and then tunnel sequentially from one oxide layer to the next. Once in the conduction band of the thermal oxide layer, the electrons may recombine with previously-trapped holes. Thus, this mechanism provides an "erase" step which involves electron injection from the gate under moderate negative voltage bias and tunneling to the Si--SiO2 interface where the electrons annihilate trapped holes very readily.
The "read" operation uses the transconductance of the silicon surface to sense the charge state of the oxide region near the Si--SiO2 interface at low gate voltages to prevent further charging of this region. Because of the thickness of the thermal oxide layer, charge trapping or detrapping in the graded pyrolytic oxide layers is not sensed by the silicon during the "read" operations. Also the magnitude of the applied field during the "read" operation is substantially smaller than the field applied for injection.
A MGOS FET device is shown in FIG. 7. The device employs a gate structure like that shown in FIG. 4 but is otherwise conventional. An array of these FET devices would provide for long-term storage, non-destructive readout and low voltage drive requirements.
While the invention has been described in terms of a preferred embodiment, those skilled in the art will understand that various modifications can be made in the practice of the invention without departing from the scope of the appended claims. For example, although the preferred embodiment of the invention has been described in terms of a MOS or MIS structure, the teachings of the invention are equally applicable to MIM or metal-insulator-metal structures. Moreover, while the gate structure of the preferred embodiment has been described as comprising an aluminum contact, those skilled in the art will recognize that other metals or semiconductors could be used. Specifically, polycrystalline silicon could be deposited over the pyrolytic oxide layers to form the gate electrode contact.

Claims (7)

We claim:
1. A metal-insulator-metal or metal-insulator-semiconductor structure .[.wherein the band gap of the insulator layer near one interface only is reduced.]..Iadd.comprising an insulator having a region of reduced band gap disposed near one insulator-metal interface only .Iaddend.to provide an injection region where holes or electrons, depending on voltage bias, can be injected into .[.the.]. .Iadd.said .Iaddend.insulator under moderate electric field conditions from the contact at .[.this.]. .Iadd.said one insulator-metal .Iaddend.interface while, simultaneously, electron or hole injection from the opposite interface is blocked due to the large insulator band gap near .[.this.]. .Iadd.said opposite .Iaddend.interface. .[.2. The structure of claim 1 comprising a silicon substrate having thereon a relatively thick thermal oxide insulator layer and a metal or semiconductor electrical contact on the thermal oxide insulator layer, said thermal oxide having a decreasing band gap in the vicinity of the electrical contact interface, said decreasing band gap being produced by ion implantation..]. .[.3. The structure recited in claim 1 comprising a silicon substrate having a first relatively thick thermal oxide insulator thereon over which is deposited a plurality of relatively thin pyrolytic oxide layers, each successively deposited pyrolytic oxide layer containing an increasing excess silicon content, and a metal or semiconductor contact on the last deposited pyrolytic oxide
layer..]. 4. A graded oxide metal-.Iadd.gate.Iaddend.-silicon dioxide.Iadd.gate-silicon.Iaddend.-silicon 14 substrate .[.MGOS.]. FET structure having an injection region adjacent to .[.the.]. .Iadd.said metal .Iaddend.gate .[.electrode.]., said injection region comprising a
.[.thin.]. .Iadd.region which exhibits a .Iaddend.graded band gap. 5. The .[.MGOS.]. FET structure as recited in claim 4 wherein .[.the.]. .Iadd.said .Iaddend.gate .[.structure.]. .Iadd.insulator .Iaddend.comprises a .[.relatively thick.]. thermal oxide formed on .[.a.]. .Iadd.said .Iaddend.silicon substrate and .Iadd.said injection region comprises .Iaddend.a plurality of .[.relatively thin.]. pyrolytic oxide layers formed over .[.the.]. .Iadd.said .Iaddend.thermal oxide, each successive pyrolytic oxide layer containing an increasing .[.excess.]. silicon content .Iadd.relative to the amount of silicon in the as grown
thermal oxide.Iaddend.. 6. In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions.[., the improvement wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface.]. .Iadd.comprising a region of reduced band gap forming a portion of said insulated gate structure disposed near the interface between the insulator and the gate electrode of said insulated gate structure .Iaddend.to provide an injection region wherein holes or electrons, depending on voltage bias, can be injected into .[.the.]. .Iadd.said .Iaddend.insulator under moderate electric field conditions from .[.the.]. .Iadd.said .Iaddend.gate .[.electrical contact.]. .Iadd.electrode .Iaddend.while, simultaneously, electron or hole injection from the .[.substrate.]. interface .Iadd.between said substrate and said insulator .Iaddend.is blocked due to the large insulator band gap at .[.this.]. .Iadd.said last mentioned
.Iaddend.interface. 7. The MOS FET device of claim 6 wherein .[.the insulator.]. .Iadd.said region of reduced band gap .Iaddend.comprises a .[.thermal oxide.]. .Iadd.region .Iaddend.having a decreasing band gap in the vicinity of the .[.gate electrical contact.]. interface.[., said decreasing band gap being produced by ion implantation.]. .Iadd.between
said gate electrode and said insulator.Iaddend.. 8. The MOS FET device of claim 6 wherein .[.the.]. .Iadd.said .Iaddend.insulator .[.comprises a first relatively thick.]. .Iadd.is a .Iaddend.thermal oxide .[.layer over which is deposited.]. .Iadd.and said region of reduced band gap is .Iaddend.a plurality of .[.relatively thin.]. pyrolytic oxide layers, each successively deposited pyrolytic oxide layer containing .[.an increasing silicon content.]. .Iadd.more silicon than the previously deposited layer and each of said layers containing more silicon than the as grown thermal oxide.Iaddend.. .Iadd.9. A metal-insulator-semiconductor structure comprising a silicon substrate having a thermal oxide insulator thereon over which is deposited at least one relatively thin oxide layer, each successively deposited oxide layer containing more silicon than the previously deposited oxide layer and each of said layers containing more silicon than the as grown thermal oxide insulator, and a metal or semiconductor contact on the last deposited oxide layer. .Iaddend. .Iadd.10. A graded oxide metal gate-silicon dioxide-silicon FET structure comprising a silicon substrate, a gate oxide of silicon dioxide disposed thereon and an injection region adjacent to said metal gate, said injection region comprising at least one relatively thin oxide layer formed over said gate oxide layer, each successive thin oxide layer containing more silicon than the previously formed oxide layer and each of said layers containing more silicon than said gate oxide. .Iaddend.
.Iadd. 1. In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate of one conductivity type, a pair of spaced apart regions of opposite conductivity type in said substrate and an insulated gate structure disposed between said pair of regions, the improvement wherein the insulator of said insulated gate structure comprises a first layer of silicon oxide over which is deposited at least one relatively thin oxide layer, each successively deposited oxide layer containing more silicon than the previously formed oxide layer and each of said layers containing more silicon than said first layer of silicon oxide. .Iaddend. .Iadd.12. The structure of claim 1 wherein said semiconductor is a silicon substrate, said insulator is a thermal oxide and said region of reduced band gap is a region of said insulator which exhibits a continuously decreasing band gap due to a continuously increasing content of silicon over that contained in the as grown thermal oxide as said region approaches said one insulator-metal interface and, a metal or semiconductor electrical contact disposed on said insulator. .Iaddend. .Iadd.13. The structure recited in claim 1 wherein said semiconductor is a silicon substrate, said insulator is a thermal oxide and said region of reduced band gap is a plurality of deposited pyrolytic oxide layers each successively deposited layer containing more silicon than the previously deposited layer and each of said layers containing more silicon than the as grown thermal oxide, and a metal or semiconductor contact deposited on the last deposited of said pyrolytic oxide layers. .Iaddend. .Iadd.14. A metal-insulator-semiconductor structure comprising a silicon substrate, a silicon oxide insulator disposed on said substrate and at least another silicon oxide layer disposed on said insulator having a silicon content therein in excess of that in said silicon oxide insulator, and a conductive contact on said at least another oxide layer. .Iaddend. .Iadd.15. A metal-insulator-semiconductor structure comprising a substrate of semiconductor material, a first layer of an oxide of said semiconductor material disposed on said substrate, at least another layer of an oxide of said semiconductor material having a semiconductor material content therein in excess of that in said first layer disposed on said first layer to reduce the band gap of said at least another layer, and a conductive contact on said at least another layer. .Iaddend. .Iadd.16. A metal-insulator-semiconductor structure according to claim 15 wherein said semiconductor material is silicon, said first layer of an oxide is silicon dioxide and, said at least another layer of oxide is silicon dioxide having a silicon content therein in excess of that in said first layer. .Iaddend.
US06/172,058 1977-06-21 1980-07-25 Moderate field hole and electron injection from one interface of MIM or MIS structures Expired - Lifetime USRE31734E (en)

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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104675A (en) * 1977-06-21 1978-08-01 International Business Machines Corporation Moderate field hole and electron injection from one interface of MIM or MIS structures
US4323910A (en) * 1977-11-28 1982-04-06 Rca Corporation MNOS Memory transistor
USRE31083E (en) * 1979-02-15 1982-11-16 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
US4217601A (en) * 1979-02-15 1980-08-12 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure
US4291328A (en) * 1979-06-15 1981-09-22 Texas Instruments Incorporated Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon
JPS5642375A (en) * 1979-08-31 1981-04-20 Fujitsu Ltd Semiconductor nonvolatile memory
US4334347A (en) * 1979-10-19 1982-06-15 Rca Corporation Method of forming an improved gate member for a gate injected floating gate memory device
US4253106A (en) * 1979-10-19 1981-02-24 Rca Corporation Gate injected floating gate memory device
EP0034653B1 (en) * 1980-02-25 1984-05-16 International Business Machines Corporation Dual electron injector structures
US4334292A (en) * 1980-05-27 1982-06-08 International Business Machines Corp. Low voltage electrically erasable programmable read only memory
US4336603A (en) * 1980-06-18 1982-06-22 International Business Machines Corp. Three terminal electrically erasable programmable read only memory
US4375085A (en) * 1981-01-02 1983-02-22 International Business Machines Corporation Dense electrically alterable read only memory
US4472726A (en) * 1981-05-06 1984-09-18 The United States Of America As Represented By The Secretary Of The Air Force Two carrier dual injector apparatus
DE3279138D1 (en) * 1981-12-14 1988-11-24 Ibm Dual electron injector structure and semiconductor memory device including a dual electron injector structure
US4665417A (en) * 1984-09-27 1987-05-12 International Business Machines Corporation Non-volatile dynamic random access memory cell
US4729115A (en) * 1984-09-27 1988-03-01 International Business Machines Corporation Non-volatile dynamic random access memory cell
JPS6180866A (en) * 1984-09-27 1986-04-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Non-volatile semiconductor memory cell
US4752812A (en) * 1987-01-12 1988-06-21 International Business Machines Corporation Permeable-base transistor
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
CA1276314C (en) * 1988-03-24 1990-11-13 Alexander Kalnitsky Silicon ion implanted semiconductor device
EP0472740B1 (en) * 1990-03-20 1995-02-08 Fujitsu Limited Electron device having a current channel of dielectric material
US5432749A (en) * 1994-04-26 1995-07-11 National Semiconductor Corporation Non-volatile memory cell having hole confinement layer for reducing band-to-band tunneling
TW374196B (en) * 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
TW335503B (en) * 1996-02-23 1998-07-01 Semiconductor Energy Lab Kk Semiconductor thin film and manufacturing method and semiconductor device and its manufacturing method
US6548825B1 (en) 1999-06-04 2003-04-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device including barrier layer having dispersed particles
US20090032861A1 (en) * 2007-07-30 2009-02-05 Zhong Dong Nonvolatile memories with charge trapping layers containing silicon nitride with germanium or phosphorus
US20090140318A1 (en) * 2007-12-03 2009-06-04 Zhong Dong Nonvolatile memories with higher conduction-band edge adjacent to charge-trapping dielectric
US20110039034A1 (en) * 2009-08-11 2011-02-17 Helen Maynard Pulsed deposition and recrystallization and tandem solar cell design utilizing crystallized/amorphous material

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3649884A (en) * 1969-06-06 1972-03-14 Nippon Electric Co Field effect semiconductor device with memory function
US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
US4047974A (en) * 1975-12-30 1977-09-13 Hughes Aircraft Company Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states
US4104675A (en) * 1977-06-21 1978-08-01 International Business Machines Corporation Moderate field hole and electron injection from one interface of MIM or MIS structures
US4217601A (en) * 1979-02-15 1980-08-12 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756782A (en) * 1969-10-03 1971-03-01 Western Electric Co MEMORY BODY HAVING A STRUCTURE CONTAINING TWO INSULATING LAYERS BETWEEN A SEMICONDUCTOR AND A METAL LAYER
GB1360770A (en) * 1972-05-30 1974-07-24 Westinghouse Electric Corp N-channel mos transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3649884A (en) * 1969-06-06 1972-03-14 Nippon Electric Co Field effect semiconductor device with memory function
US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
US4047974A (en) * 1975-12-30 1977-09-13 Hughes Aircraft Company Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states
US4104675A (en) * 1977-06-21 1978-08-01 International Business Machines Corporation Moderate field hole and electron injection from one interface of MIM or MIS structures
US4217601A (en) * 1979-02-15 1980-08-12 International Business Machines Corporation Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure

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