US9043517B1 - Multipass programming in buffers implemented in non-volatile data storage systems - Google Patents
Multipass programming in buffers implemented in non-volatile data storage systems Download PDFInfo
- Publication number
- US9043517B1 US9043517B1 US14/035,876 US201314035876A US9043517B1 US 9043517 B1 US9043517 B1 US 9043517B1 US 201314035876 A US201314035876 A US 201314035876A US 9043517 B1 US9043517 B1 US 9043517B1
- Authority
- US
- United States
- Prior art keywords
- storage medium
- bloom filter
- data storage
- volatile
- medium portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7202—Allocation control and policies
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99931—Database or file accessing
- Y10S707/99932—Access augmentation or optimizing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99931—Database or file accessing
- Y10S707/99933—Query processing, i.e. searching
Definitions
- the disclosed embodiments relate generally to memory systems, and in particular, to using non-volatile data storage systems to implement Bloom filters.
- Flash memory typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage.
- a flash memory cell for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value.
- Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. Non-volatile memory retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information.
- a host supplies an address and the data to be written.
- an address-targeted read from memory a host supplies an address from which to read.
- using address-targeted read and write methods to access memory is not ideal.
- a portion of memory e.g., a page in a block of a flash memory device
- a new location in the memory e.g., unused
- FIG. 1 is a block diagram illustrating an implementation of a data storage system, in accordance with some embodiments.
- FIG. 2 is a block diagram illustrating an implementation of a management module, in accordance with some embodiments.
- FIG. 3 is a prophetic diagram of voltage distributions that may be found in a single-level flash memory cell (SLC) over time, in accordance with some embodiments.
- SLC single-level flash memory cell
- FIGS. 4A-4E illustrate a flowchart representation of a method for data processing, in accordance with some embodiments.
- Bloom filter arrays can be implemented with dynamic random-access memory (DRAM), but this can become prohibitively expensive as the size of the set grows.
- DRAM dynamic random-access memory
- the various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). Some implementations include systems, methods and/or devices to integrate Bloom filter functionality in the non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to a new (e.g., unused) location in the memory.
- some implementations include a method for data processing.
- the method includes receiving from a host a plurality of requests that specify respective elements.
- the method further includes, for each respective element specified by the received requests, (1) generating a respective set of k bit positions in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2, and (2) setting the respective set of k bit positions in the Bloom filter, wherein the Bloom filter is stored in a non-volatile storage medium of the non-volatile data storage system.
- setting a respective bit position of the k bit positions in the Bloom filter includes (1) accessing usage information for a storage medium portion of the non-volatile storage medium that includes the respective bit position in the Bloom filter, (2) determining whether the usage information for the storage medium portion meets predefined multipass programming criteria, (3) if the usage information for the storage medium portion meets the predefined multipass programming criteria, setting the respective bit position in the Bloom filter in the storage medium portion, and (4) if the usage information for the storage medium portion does not meet the predefined multipass programming criteria, identifying a respective unused portion of the non-volatile storage medium, copying Bloom filter information in the storage medium portion to the identified portion of the non-volatile storage medium, and setting the respective bit position in the Bloom filter.
- the method includes generating the respective set of k bit positions in the Bloom filter using one or more processors of the non-volatile data storage system.
- the method includes generating the respective set of k bit positions in the Bloom filter using k parallel processors of the non-volatile data storage system.
- the method further includes scheduling erasure of the storage medium portion of the non-volatile storage medium.
- scheduling erasure of the storage medium portion is performed after setting the respective bit position in the Bloom filter.
- determining whether the usage information for the storage medium portion meets predefined multipass programming criteria includes (1) determining whether the usage information indicates the storage medium portion of the non-volatile data storage system has been programmed no more than m times, where m is an integer of at least 1000, (2) if the storage medium portion of the non-volatile data storage system has been programmed no more than m times, the usage information for the storage medium portion meets the predefined multipass programming criteria, and (3) if the storage medium portion of the non-volatile data storage system has been programmed more than m times, the usage information for the storage medium portion does not meet the predefined multipass programming criteria.
- setting the respective set of k bit positions in the storage medium includes out of order word line programming.
- the method further includes receiving an element for testing with respect to the Bloom filter.
- the method further includes testing whether the element is present in the Bloom filter, by (1) processing the element with the k distinct hash functions to generate a set of k bit positions, (2) reading the set of k bit positions from the Bloom filter, (3) returning a first result if all the k bit positions in the Bloom filter from the set are set, and (4) returning a second result if one or more of the k bit positions in the Bloom filter from the set are not set.
- the non-volatile storage medium includes one or more flash memory devices.
- the non-volatile data storage system is distinct from the host.
- the non-volatile data storage system is embedded in the host.
- the respective elements specified by the plurality of requests comprise a plurality of objects.
- the respective elements specified by the plurality of requests comprise n-bit fingerprints of a plurality of objects, where n is at least 64.
- any of the methods described above are performed by a non-volatile data storage system comprising (1) a non-volatile storage medium storing a Bloom filter, (2) one or more processors, and (3) memory storing one or more programs, which when executed by the one or more processors cause the non-volatile data storage system to perform any of the methods described above.
- a non-transitory computer readable storage medium stores one or more programs configured for execution by one or more processors of a non-volatile data storage system, the one or more programs comprising instructions for causing the non-volatile data storage system to perform any of the methods described above.
- a non-volatile data storage system is configured to process data in accordance with any of the methods described above.
- the non-volatile data storage system includes means for receiving from a host a plurality of requests that specify respective elements, and means for processing each respective element specified by the received requests, including (1) means for generating a respective set of k bit positions in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2, and (2) means for setting the respective set of k bit positions in the Bloom filter, wherein the Bloom filter is stored in a non-volatile storage medium of the non-volatile data storage system.
- the means for setting includes means for setting a respective bit position of the k bit positions in the Bloom filter, which includes (1) means for accessing usage information for a storage medium portion of the non-volatile storage medium that includes the respective bit position in the Bloom filter, (2) means for determining whether the usage information for the storage medium portion meets predefined multipass programming criteria, (3) means for setting the respective bit position in the Bloom filter in the storage medium portion if the usage information for the storage medium portion meets the predefined multipass programming criteria, and (4) means for identifying a respective unused portion of the non-volatile storage medium, copying Bloom filter information in the storage medium portion to the identified portion of the non-volatile storage medium, and setting the respective bit position in the Bloom filter, if the usage information for the storage medium portion does not meet the predefined multipass programming criteria.
- FIG. 1 is a diagram of an implementation of a data storage system 100 , in accordance with some embodiments. While some example features are illustrated, various other features have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the example implementations disclosed herein. To that end, as a non-limiting example, the data storage system 100 includes a memory controller 120 , and a storage medium 130 , and is used in conjunction with a computer system 110 .
- storage medium 130 is a single flash memory device while in other implementations storage medium 130 includes a plurality of flash memory devices.
- storage medium 130 is NAND-type flash memory or NOR-type flash memory.
- memory controller 120 is a solid-state drive (SSD) controller.
- SSD solid-state drive
- Computer system 110 is coupled to memory controller 120 through data connections 101 .
- computer system 110 includes memory controller 120 as a component and/or a sub-system.
- Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device.
- Computer system 110 is sometimes called a host or host system.
- computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch screen display, a mouse, a track-pad, a digital camera and/or any number of supplemental devices to add functionality.
- Storage medium 130 is coupled to memory controller 120 through connections 103 .
- Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 130 and data values read from storage medium 130 .
- memory controller 120 and storage medium 130 are included in the same device as components thereof.
- memory controller 120 and storage medium 130 are embedded in a host device, such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed by the embedded memory controller.
- Storage medium 130 may include any number (i.e., one or more) of memory devices including, without limitation, non-volatile semiconductor memory devices, such as flash memory.
- flash memory devices can be configured for enterprise storage suitable for applications such as cloud computing, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop and tablet computers. Furthermore, as discussed in more detail below, flash memory devices can be configured to implement data structures such as Bloom filter array(s) 131 .
- a Bloom filter (e.g., Bloom filter array(s) 131 ) is a probabilistic data structure used to determine if an element “x” is a member of a set “S” with high probability.
- a Bloom filter is constructed using an N-bit array that is initially cleared, and has hash functions where 0 ⁇ Hash (x,k) ⁇ N ⁇ 1. For each element “x” in set “S,” k hash functions are computed, and the k corresponding bits in the N-bit array are set.
- a Bloom filter is initially cleared by resetting the N-bit array to all zeros, and the k corresponding bits in the N-bit array are set to ones.
- a Bloom filter is initially cleared by resetting the N-bit array to all ones, and the k corresponding bits in the N-bit array are set to zeros. While the labeling of memory cell states as having specific data values is somewhat arbitrary, with respect to flash memory devices, memory cells that have been reset are typically said to represent ones, and memory cells that have been set are typically said to represent zeros. However, any labeling or mapping of memory cell states to data values can be used, as long as it is used consistently.
- the k hash functions are generated for element “w” and the k bit positions are tested. If the k bit positions are set, then the element “w” is most likely a member of set “S,” with a possibility of this membership being a “false positive.”
- a false positive is when the Bloom filter returns a result that an element is a member of the set “S,” when in actuality it is not. Bloom filters return fewer false positives when the number of elements in the set “S” is an order of magnitude smaller than the number of bits in the bit array.
- the probability of a false positive is given by equation (1): (1 ⁇ e ⁇ k(n+0.5)/(m ⁇ 1) ) k (1)
- k represents the number of hash functions per element
- m represents the number of bits in the Bloom filter
- n is the number of elements stored in the Bloom filter.
- Storage medium 130 is divided into a number of addressable and individually selectable blocks.
- the individually selectable blocks are the minimum size erasable units in a flash memory device.
- each block contains the minimum number of memory cells that can be erased simultaneously.
- Each block is usually further divided into a plurality of pages and/or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block.
- the smallest individually accessible unit of a data set is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for reading data from the flash memory device.
- one block comprises any number of pages, for example, 64 pages, 128 pages, 256 pages or another suitable number of pages.
- Blocks are typically grouped into a plurality of zones. Each block zone can be independently managed to some extent, which increases the degree of parallelism for parallel operations and simplifies management of storage medium 130 .
- memory controller 120 includes a management module 121 , a host interface 129 , a storage medium interface (I/O) 128 , and additional module(s) 125 .
- Memory controller 120 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure more pertinent features of the example implementations disclosed herein, and a different arrangement of features may be possible.
- Host interface 129 provides an interface to computer system 110 through data connections 101 .
- storage medium I/O 128 provides an interface to storage medium 130 though connections 103 .
- storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 130 (e.g., reading threshold voltages for NAND-type flash memory).
- management module 121 includes one or more processing units (CPUs, also sometimes called processors) 122 configured to execute instructions in one or more programs (e.g., in management module 121 ).
- the one or more CPUs 122 are shared by one or more components within, and in some cases, beyond the function of memory controller 120 .
- Management module 121 is coupled to host interface 129 , additional module(s) 125 and storage medium I/O 128 in order to coordinate the operation of these components.
- Additional module(s) 125 are coupled to storage medium I/O 128 , host interface 129 , and management module 121 .
- additional module(s) 125 may include an error control module to limit the number of uncorrectable errors inadvertently introduced into data during writes to memory or reads from memory.
- additional module(s) 125 are executed in software by the one or more CPUs 122 of management module 121 , and, in other embodiments, additional module(s) 125 are implemented in whole or in part using special purpose circuitry (e.g., to perform encoding and decoding functions).
- host interface 129 receives data to be stored in storage medium 130 from computer system 110 .
- the data held in host interface 129 is made available to an encoder (e.g., in additional module(s) 125 ), which encodes the data to produce one or more codewords.
- the one or more codewords are made available to storage medium I/O 128 , which transfers the one or more codewords to storage medium 130 in a manner dependent on the type of storage medium being utilized.
- An address-targeted read operation is initiated when computer system (host) 110 sends one or more host read commands on control line 111 to memory controller 120 requesting data from storage medium 130 .
- Memory controller 120 sends one or more read access commands to storage medium 130 , via storage medium I/O 128 , to obtain raw read data in accordance with memory locations (addresses) specified by the one or more host read commands.
- Storage medium I/O 128 provides the raw read data (e.g., comprising one or more codewords) to a decoder (e.g., in additional module(s) 125 ). If the decoding is successful, the decoded data is provided to host interface 129 , where the decoded data is made available to computer system 110 . In some implementations, if the decoding is not successful, memory controller 120 may resort to a number of remedial actions or provide an indication of an irresolvable error condition.
- Bloom filter implementations using address-targeted write and read operations would require transferring large amounts of data between computer system (host) 110 and data storage system 100 .
- computer system 110 would generate k hashes and then initiate k read-modify-write commands to data storage system 100 . In some examples, this would require the sensing, transfer, modification, and write back of k ⁇ 4 KB pages.
- computer system 110 would initiate k read commands.
- Bloom filter functionality is integrated in data storage system 100 , as described below and with reference to FIG. 2 .
- computer system 110 When Bloom filter functionality is integrated in data storage system 100 , computer system 110 is not required to generate k hashes and initiate k commands in order to add an object “X” to Bloom filter array(s) 131 . Instead, in some implementations, computer system 110 transfers object “X” directly to data storage system 100 as an element to add to Bloom filter array(s) 131 . In some implementations, computer system 110 generates a fingerprint of object “X” (e.g., an n-bit fingerprint of object “X,” where n is at least 64) and transfers the fingerprint of object “X” directly to data storage system 100 as an element to add to Bloom filter array(s) 131 .
- a fingerprint of object “X” e.g., an n-bit fingerprint of object “X,” where n is at least 64
- data storage system 100 For each element received from computer system 110 to add to Bloom filter array(s) 131 , data storage system 100 generates k bit positions in Bloom filter array(s) 131 , using k distinct hash functions, where k is an integer greater than 2. Further, data storage system 100 sets the k bit positions in Bloom filter array(s) 131 (e.g., using write circuitry in storage medium I/O 128 ). Thus, only a single host command (e.g., “Add Element”) is needed to add an element to Bloom filter array(s) 131 , reducing data transfers between computer system 110 and memory controller 120 .
- k is an integer greater than 2.
- computer system 110 when Bloom filter functionality is integrated in data storage system 100 , computer system 110 is not required to initiate k read commands in order to test whether an element is present in Bloom filter array(s) 131 . Instead, similar to the process described above for adding an element to Bloom filter array(s) 131 , in some implementations, computer system 110 transfers an element (e.g., object “X” or a fingerprint of object “X”) directly to data storage system 100 in order to test whether the element is present in Bloom filter array(s) 131 .
- an element e.g., object “X” or a fingerprint of object “X
- data storage system 100 For each element received from computer system 110 for testing, data storage system 100 processes the element with k distinct hash functions to generate k bit positions in Bloom filter array(s) 131 and reads the k bit positions from Bloom filter array(s) 131 (e.g., using read circuitry in storage medium I/O 128 ).
- data storage system 100 returns a first result in accordance with a determination that all the k bit positions are set (e.g., indicating that the element is present in Bloom filter array(s) 131 with high probability) or returns a second result in accordance with a determination that at least a predetermined number (e.g., one or more) of the k bit positions in the Bloom filter are not set (e.g., indicating that the element is not present in Bloom filter array(s) 131 ).
- a predetermined number e.g., one or more
- computer system 110 resets Bloom filter array(s) 131 with a single host command (e.g., “Reset Filter”).
- Data storage system 100 responds to a reset command by resetting Bloom filter array(s) 131 to an empty state.
- Bloom filter array(s) 131 is cleared by resetting the array to all zeros.
- Bloom filter array(s) 131 is cleared by resetting the array to all ones. As explained above, with respect to flash memory devices, memory cells that have been reset are typically said to represent ones.
- storage medium 130 is implemented using NAND flash memory.
- NAND flash memory devices have on-chip logical function capabilities with the ability to do simple bit-wise operations (e.g., AND, OR, INVERT, and XOR). Bloom filters require the ability to test and set single bits at a time. By using the NAND flash memory device's integrated logical function registers, these calculations are offloaded from the drive's processor(s) (e.g., CPUs 122 ), allowing for higher performance.
- Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages.
- Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on).
- the magnitude of the charge, and the corresponding threshold voltage the charge creates, is used to represent one or more data values.
- a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.
- cell voltage and “memory cell voltage,” in the context of flash memory cells, means the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current.
- reading threshold voltages sometimes also called reading signals and reading voltages
- gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage.
- the raw data value for that read operation is a “1,” and otherwise the raw data value is a “0.”
- FIG. 2 is a block diagram illustrating an exemplary management module 121 , in accordance with some embodiments.
- Management module 121 typically includes one or more processing units (CPUs) 122 for executing modules, programs and/or instructions stored in memory 206 and thereby performing processing operations, memory 206 , and one or more communication buses 208 for interconnecting these components.
- Communication buses 208 optionally include circuitry (sometimes called a chipset) that interconnects and controls communications between system components.
- Management module 121 is coupled to host interface 129 , additional module(s) 125 , and storage medium I/O 128 by communication buses 208 .
- Memory 206 includes high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. Memory 206 optionally includes one or more storage devices remotely located from the CPU(s) 122 . Memory 206 , or alternately the non-volatile memory device(s) within memory 206 , comprises a non-transitory computer readable storage medium. In some embodiments, memory 206 , or the computer readable storage medium of memory 206 stores the following programs, modules, and data structures, or a subset thereof:
- the add element module 218 optionally includes the following modules or sub-modules, or a subset thereof:
- test element module 224 optionally includes the following modules or sub-modules, or a subset thereof:
- the delete element module 232 optionally includes the following modules or sub-modules, or a subset thereof:
- Each of the above identified elements may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above.
- the above identified modules or programs i.e., sets of instructions
- memory 206 may store a subset of the modules and data structures identified above.
- memory 206 may store additional modules and data structures not described above.
- the programs, modules, and data structures stored in memory 206 , or the computer readable storage medium of memory 206 provide instructions for implementing any of the methods described below with reference to FIGS. 4A-4E .
- FIG. 2 shows a management module 121
- FIG. 2 is intended more as functional description of the various features which may be present in a management module than as a structural schematic of the embodiments described herein. In practice, and as recognized by those of ordinary skill in the art, items shown separately could be combined and some items could be separated.
- a single-level flash memory cell stores one bit (“0” or “1”).
- the storage density of a SLC memory device is one bit of information per memory cell.
- a multi-level flash memory cell can store two or more bits of information per cell by using different ranges within the total voltage range of the memory cell to represent a multi-bit bit-tuple.
- the storage density of a MLC memory device is multiple-bits per cell (e.g., two bits per memory cell).
- FIG. 3 is a simplified, prophetic diagram of voltage distributions 300 found in a single-level flash memory cell (SLC) over time, in accordance with some embodiments.
- the voltage distributions 300 shown in FIG. 3 have been simplified for illustrative purposes.
- the SLC's voltage range extends approximately from a voltage, V SS , at a source terminal of an NMOS transistor to a voltage, V DD , at a drain terminal of the NMOS transistor.
- voltage distributions 300 extend between V SS and V DD .
- Sequential voltage ranges 301 and 302 between source voltage V SS and drain voltage V DD are used to represent corresponding bit values “1” and “0,” respectively.
- Each voltage range 301 , 302 has a respective center voltage V 1 301 b , V 0 302 b .
- the memory cell current sensed in response to an applied reading threshold voltages is indicative of a memory cell voltage different from the respective center voltage V 1 301 b or V 0 302 b corresponding to the respective bit value written into the memory cell.
- Errors in cell voltage, and/or the cell voltage sensed when reading the memory cell can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the memory cell and the time a read operation is performed to read the data stored in the memory cell. For ease of discussion, these effects are collectively described as “cell voltage drift.”
- Each voltage range 301 , 302 also has a respective voltage distribution 301 a , 302 a that may occur as a result of any number of a combination of error-inducing factors, examples of which are identified above.
- a reading threshold voltage V R is applied between adjacent center voltages (e.g., applied proximate to the halfway region between adjacent center voltages V 1 301 b and V 0 302 b ).
- the reading threshold voltage is located between voltage ranges 301 and 302 .
- reading threshold voltage V R is applied in the region proximate to where the voltage distributions 301 a and 302 a overlap, which is not necessarily proximate to the halfway region between adjacent center voltages V 1 301 b and V 0 302 b.
- a SLC memory device stores one bit of information (“0” or “1”) per memory cell.
- a Bloom filter is implemented in a SLC memory device, and uses a single-level flash memory cell for each bit of the N-bit array of the Bloom filter.
- the Bloom filter is initially cleared by resetting each bit of the N-bit array to “1” and elements are added to the Bloom filter by setting the corresponding k bits generated from the k hash functions to “0.”
- the Bloom filter is initially cleared by resetting each bit of the N-bit array to “0” and elements are added to the Bloom filter by setting the corresponding k bits generated from the k hash functions to “1.”
- flash memory In order to increase storage density in flash memory, flash memory has developed from single-level (SLC) cell flash memory to multi-level cell (MLC) flash memory so that two or more bits can be stored by each memory cell.
- SLC single-level
- MLC multi-level cell
- a MLC flash memory device is used to store multiple bits by using voltage ranges within the total voltage range of the memory cell to represent different bit-tuples.
- a MLC flash memory device is typically more error-prone than a SLC flash memory device created using the same manufacturing process because the effective voltage difference between the voltages used to store different data values is smaller for a MLC flash memory device.
- a typical error includes a stored voltage level in a particular MLC being in a voltage range that is adjacent to the voltage range that would otherwise be representative of the correct storage of a particular bit-tuple.
- the impact of such errors can be reduced by gray-coding the data, such that adjacent voltage ranges represent single-bit changes between bit-tuples.
- a storage medium e.g., storage medium 130 , FIG. 1
- each block is optionally (but typically) further divided into a plurality of pages and/or word lines and/or sectors. While erasure of a storage medium is performed on a block basis, in many embodiments reading and programming of the storage medium is performed on a smaller subunit of a block (e.g., on a page basis, word line basis, or sector basis). In some embodiments, programming is performed on an entire page. In some embodiments, partial-page programming is used for writing smaller amounts of data.
- the number of operations is the maximum number of operations (e.g., the maximum number of times a partial page can be programmed) before an erase is required (e.g., erasure of the block containing the page).
- the maximum number of operations for SLC NAND memory devices is four and the maximum number of operations for MLC NAND memory devices is one.
- a partial page may be written at least 1000 times before an erase is required.
- a word line may be written at least 1000 times before an erase is required, where the “writes” involve setting single bits (e.g., setting a bit from “1” to “0”), rather than writing both ones and zeros to the entire word line.
- FIGS. 4A-4E illustrate a flowchart representation of a method 400 for data processing, in accordance with some embodiments.
- a host e.g., computer system 110 , FIG. 1 , sometimes called a host
- adds an element to a Bloom filter e.g., Bloom filter array(s) 131
- a Bloom filter e.g., Bloom filter array(s) 131
- the host sends a plurality of requests with respective elements to be added, which initiates performance of method 400 .
- method 400 is performed by a non-volatile data storage system (e.g., data storage system 100 , FIG. 1 ) or one or more components of the non-volatile data storage system (e.g., memory controller 120 and/or storage medium 130 , FIG. 1 ).
- method 400 is governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors of a device, such as the one or more processing units (CPUs) 122 of management module 121 , shown in FIGS. 1 and 2 .
- CPUs processing units
- a non-volatile data storage system receives ( 402 ) from a host (e.g., computer system 110 , FIG. 1 ) a plurality of requests that specify respective elements.
- the plurality of requests are requests to add respective elements to a Bloom filter (e.g., Bloom filter array(s) 131 , FIG. 1 ).
- a single host command e.g., “Add Element”
- the host would send three requests, the first request specifying the first element to be added to the Bloom filter, the second request specifying the second element to be added to the Bloom filter, and the third request specifying the third element to be added to the Bloom filter.
- the non-volatile data storage system is ( 404 ) distinct from the host.
- one or more components of the non-volatile data storage system e.g., memory controller 120 and storage medium 130 of data storage system 100 , FIG. 1
- a host e.g., computer system 110 , FIG. 1
- connections e.g., connections 101 and control line 111 , FIG. 1 .
- the non-volatile data storage system is ( 406 ) embedded in the host.
- one or more components of the non-volatile data storage system e.g., memory controller 120 and storage medium 130 of data storage system 100 , FIG. 1
- a device as components thereof.
- one or more components of the non-volatile data storage system e.g., memory controller 120 and storage medium 130 of data storage system 100 , FIG. 1
- a host device such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed by the embedded data storage system.
- the respective elements specified ( 408 ) by the plurality of requests comprise a plurality of objects.
- an object is a file (e.g., a 1 MB file).
- an object is an email attachment in a forwarded email message.
- an object is mapped into an n-bit fingerprint by the non-volatile data storage system (e.g., data storage system 100 , FIG. 1 ) before being processed for insertion in the Bloom filter.
- a fingerprint module e.g., fingerprint module 240 , FIG. 2
- n is at least 64, as described above with respect to FIG. 2 .
- the respective elements specified ( 410 ) by the plurality of requests comprise n-bit fingerprints of a plurality of objects, where n is at least 64.
- an object is mapped into an n-bit number by a host (e.g., computer system 110 , FIG. 1 , sometimes called a host).
- a 64-bit hash function is used to map data sets of variable length (e.g., a file or an email attachment) to data sets of a fixed length (e.g., 64 bits).
- the non-volatile data storage system For each respective element specified ( 412 ) by the received request, the non-volatile data storage system generates ( 414 ) a respective set of k bit positions (sometimes called a respective group of k bit positions) in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2. As an example, if k is equal to 16, for a respective element specified in the received request, the non-volatile data storage system uses 16 distinct hash functions to generate a respective set of 16 bit positions in the Bloom filter. In some implementations, the respective set of k bit positions in the Bloom filter is generated in firmware (e.g., in management module 121 , FIGS. 1 and 2 ).
- the respective set of k bit positions in the Bloom filter is generated in hardware (e.g., a hardware hash engine). In some implementations, the respective set of k bit positions in the Bloom filter is generated by a hash function generation module (e.g., hash function generation module 216 , FIG. 2 ) and/or an add element processing module (e.g., add element processing module 220 , FIG. 2 ), as described above with respect to FIG. 2 .
- a hash function generation module e.g., hash function generation module 216 , FIG. 2
- an add element processing module e.g., add element processing module 220 , FIG. 2
- the non-volatile data storage system generates ( 416 ) the respective set of k bit positions in the Bloom filter using one or more processors of the non-volatile data storage system (e.g., CPUs 122 , FIG. 1 ).
- processors of the non-volatile data storage system e.g., CPUs 122 , FIG. 1 .
- the non-volatile data storage system generates ( 418 ) the respective set of k bit positions in the Bloom filter using k parallel processors of the non-volatile data storage system. In some other embodiments, the non-volatile data storage system generates the respective set of k bit positions in the Bloom filter using at least k/2 parallel processors of the non-volatile data storage system, while in yet other embodiments, the non-volatile data storage system generates the respective set of k bit positions in the Bloom filter using at least k/4 parallel processors of the non-volatile data storage system. In some implementations, the aforementioned one or more processors of the non-volatile data storage system (e.g., CPUs 122 , FIG. 1 ) comprise parallel processors, and the respective set of k bit positions in the Bloom filter is generated using the parallel processors.
- the aforementioned one or more processors of the non-volatile data storage system e.g., CPUs 122 , FIG. 1
- the non-volatile data storage system sets ( 420 ) the respective set of k bit positions in the Bloom filter (e.g., Bloom filter array(s) 131 , FIG. 1 ), wherein the Bloom filter is stored in a non-volatile storage medium (e.g., storage medium 130 , FIG. 1 ) of the non-volatile data storage system.
- the Bloom filter e.g., Bloom filter array(s) 131 , FIG. 1
- a non-volatile storage medium e.g., storage medium 130 , FIG. 1
- the non-volatile storage medium comprises ( 422 ) one or more flash memory devices.
- the non-volatile storage medium e.g., storage medium 130 , FIG. 1
- the non-volatile storage medium is a single flash memory device, while in other implementations, the non-volatile storage medium includes a plurality of flash memory devices.
- the non-volatile storage medium e.g., storage medium 130 , FIG. 1
- setting ( 424 ) the respective set of k bit positions in the storage medium includes out of order word line programming.
- out of order word line programming includes setting one or more bits on a first word line, the first word line positioned earlier in a block, subsequent to setting one or more bits on a second word line, the second word line positioned later in the block. For example, if a block has 128 word lines (e.g., word line 0 through word line 127), in order word line programming usually involves writing word line 0, word line 1, word line 2, . . . , word line 126, and word line 127, in ascending order.
- An example of out of order word line programming includes writing word line 17 (e.g., setting one or more bits on word line 17) after writing word line 25 (e.g., setting one or more bits on word line 25).
- setting ( 426 ) a respective bit position of the k bit positions in the Bloom filter comprises accessing ( 428 ) usage information for a storage medium portion (e.g., a page, a word line, or a sector) of the non-volatile storage medium (e.g., storage medium 130 , FIG. 1 ) that includes the respective bit position in the Bloom filter (e.g., Bloom filter array(s) 131 , FIG. 1 ).
- usage information is a count of the number of times the storage medium portion has been programmed.
- a count of the number of bits that are “set” on the storage medium portion is the same as a count of the number of writes to the storage medium portion, since each write typically results in flipping only a single bit from “reset” to “set” (e.g., flipping a single bit from “1” to “0”).
- a counter could be kept in DRAM for each storage medium portion.
- setting ( 426 ) a respective bit position of the k bit positions in the Bloom filter further comprises determining ( 430 ) whether the usage information for the storage medium portion (e.g., a page, a word line, or a sector) meets predefined multipass programming criteria. For example, in some embodiments, if the respective bit position to be set in the Bloom filter is stored on word line 15, the non-volatile data storage system determines whether the usage information for word line 15 meets predefined multipass programming criteria.
- the storage medium portion e.g., a page, a word line, or a sector
- determining ( 430 ) whether the usage information for the storage medium portion meets predefined multipass programming criteria comprises determining ( 432 ) whether the usage information indicates the storage medium portion (e.g., a page, a word line, or a sector) of the non-volatile data storage system has been programmed no more than m times, where m is an integer of at least 1000.
- the term “no more than m” may be construed to mean “less than or equal to m.” For example, if m is equal to 1000, determining whether the usage information indicates the storage medium portion has been programmed no more than 1000 times is the same as determining whether the usage information indicates the storage medium portion has been programmed less than or equal to 1000 times.
- the usage information for the storage medium portion meets ( 434 ) the predefined multipass programming criteria.
- the predefined multipass programming criteria As an example, if m is equal to 1000 and the respective bit position is on word line 15, if the usage information for word line 15 indicates that word line 15 has been programmed 1000 times or less, then the usage information for word line 15 meets the predefined multipass programming criteria.
- the usage information for the storage medium portion does not meet ( 436 ) the predefined multipass programming criteria.
- the predefined multipass programming criteria As an example, if m is equal to 1000 and the respective bit position is on word line 15, if the usage information for word line 15 indicates that word line 15 has been programmed 1001 times or more, then the usage information for word line 15 does not meet the predefined multipass programming criteria.
- setting ( 426 ) a respective bit position of the k bit positions in the Bloom filter further comprises, in accordance with a determination that the usage information for the storage medium portion (e.g., a page, a word line, or a sector) meets the predefined multipass programming criteria, setting ( 440 ) the respective bit position in the Bloom filter in the storage medium portion.
- the respective bit position to be set is on word line 15 and if it is determined that the usage information for word line 15 meets the predefined multipass programming criteria (e.g., word line 15 has been programmed no more than m times), then the non-volatile data storage system sets the respective bit position on word line 15.
- setting a respective bit position of the k bit positions in the Bloom filter includes identifying the storage medium portion of the non-volatile storage medium that includes the respective bit position in the Bloom filter, and setting the respective bit position in the Bloom filter in the storage medium portion without resetting any other bit positions in the storage medium portion.
- setting ( 426 ) a respective bit position of the k bit positions in the Bloom filter further comprises, in accordance with a determination that the usage information for the storage medium portion (e.g., a page, a word line, or a sector) does not meet the predefined multipass programming criteria, identifying ( 442 ) a respective unused portion of the non-volatile storage medium, copying Bloom filter information in the storage medium portion to the identified portion of the non-volatile storage medium, and setting the respective bit position in the Bloom filter.
- the storage medium portion e.g., a page, a word line, or a sector
- the non-volatile data storage system identifies an unused word line, copies Bloom filter information from word line 15 to the identified unused word line, and sets the respective bit position in the Bloom filter.
- the non-volatile data storage system schedules ( 444 ) erasure of the storage medium portion of the non-volatile storage medium.
- the non-volatile data storage system schedules erasure of word line 15 (e.g., erasure of the block containing word line 15).
- scheduling ( 446 ) erasure of the storage medium portion is performed after setting the respective bit position in the Bloom filter.
- the non-volatile data storage system identifies an unused word line, copies Bloom filter information from word line 15 to the identified unused word line, sets the respective bit position in the Bloom filter, and in some embodiments, then schedules erasure of word line 15.
- erasure of the storage medium portion is scheduled after the copying but prior to setting the respective bit position in the Bloom filter.
- the non-volatile data storage system identifies an unused word line, copies Bloom filter information from word line 15 to the identified unused word line, schedules erasure of word line 15, and then sets the respective bit position in the Bloom filter.
- the non-volatile data storage system receives ( 448 ) an element (e.g., a first element) for testing with respect to the Bloom filter.
- a non-volatile data storage system e.g., data storage system 100 , FIG. 1
- receives an element for testing with respect to the Bloom filter e.g., Bloom filter array(s) 131 , FIG. 1
- a host e.g., computer system 110 , FIG. 1 , sometimes called a host.
- a host e.g., computer system 110 , FIG. 1 , sometimes called a host.
- only a single host command e.g., “Test Element” is needed to test whether the element is present in the Bloom filter.
- the non-volatile data storage system tests ( 450 ) whether the element is present in the Bloom filter by processing ( 452 ) the element with the k distinct hash functions to generate a set of k bit positions (sometimes called a group of k bit positions).
- the non-volatile data storage system e.g., data storage system 100 , FIG. 1
- processes the element with 16 distinct hash functions to generate a set of 16 bit positions in the Bloom filter e.g., Bloom filter array(s) 131 , FIG. 1
- the respective set of k bit positions in the Bloom filter is generated in firmware (e.g., in management module 121 , FIGS. 1 and 2 ).
- the respective set of k bit positions in the Bloom filter is generated in hardware (e.g., a hardware hash engine). In some implementations, the respective set of k bit positions in the Bloom filter is generated by a hash function generation module (e.g., hash function generation module 216 , FIG. 2 ) and/or a test element processing module (e.g., test element processing module 226 , FIG. 2 ), as described above with respect to FIG. 2 .
- a hash function generation module e.g., hash function generation module 216 , FIG. 2
- test element processing module e.g., test element processing module 226 , FIG. 2
- the non-volatile data storage system generates the respective set of k bit positions in the Bloom filter using one or more processors of the non-volatile data storage system (e.g., CPUs 122 , FIG. 1 ).
- the non-volatile data storage system generates the respective set of k bit positions in the Bloom filter using k parallel processors (or, alternatively, at least k/2 parallel processors, or at least k/4 parallel processors, as discussed above) of the non-volatile data storage system.
- the aforementioned one or more processors of the non-volatile data storage system e.g., CPUs 122 , FIG. 1
- the aforementioned one or more processors of the non-volatile data storage system comprise parallel processors, and the respective set of k bit positions in the Bloom filter is generated using the parallel processors.
- the non-volatile data storage system further tests ( 450 ) whether the element is present in the Bloom filter by reading ( 454 ) the set of k bit positions from the Bloom filter.
- the non-volatile data storage system reads the set of 16 bit positions from the Bloom filter (e.g., Bloom filter array(s) 131 , FIG. 1 ).
- the k bit positions are read from the Bloom filter using a bit reading module (e.g., bit reading module 228 , FIG. 2 ), as described above with respect to FIG. 2 .
- Testing ( 450 ) whether the element is present in the Bloom filter further includes returning ( 456 ) a first result in accordance with a determination that all the k bit positions in the Bloom filter from the set are set.
- the non-volatile data storage system e.g., data storage system 100 , FIG. 1
- the non-volatile data storage system returns a first result in accordance with a determination that all 16 bit positions in the Bloom filter (e.g., Bloom filter array(s) 131 , FIG. 1 ) from the set are set, indicating that the element is present in the Bloom filter with high probability.
- the first result is returned (e.g., in accordance with a determination that all the k bit positions in the Bloom filter from the set are set) using a test result module (e.g., test result module 230 , FIG. 2 ), as described above with respect to FIG. 2 .
- a test result module e.g., test result module 230 , FIG. 2
- testing ( 450 ) whether the element is present in the Bloom filter includes returning ( 458 ) a second result in accordance with a determination that one or more of the k bit positions in the Bloom filter from the set are not set.
- the non-volatile data storage system e.g., data storage system 100 , FIG. 1
- the second result is returned (e.g., in accordance with a determination that one or more of the k bit positions in the Bloom filter from the set are not set) using a test result module (e.g., test result module 230 , FIG. 2 ), as described above with respect to FIG. 2 .
- a test result module e.g., test result module 230 , FIG. 2
- the storage medium (e.g., storage medium 130 , FIG. 1 ) is a single flash memory device, while in other implementations, the storage medium (e.g., storage medium 130 , FIG. 1 ) includes a plurality of flash memory devices.
- a data storage system includes a non-volatile storage medium (e.g., storage medium 130 , FIG. 1 ), one or more processors (e.g., CPUs 122 , FIGS. 1 and 2 ) and memory (e.g., memory 206 , FIG. 2 ) storing one or more programs configured for execution by the one or more processors and configured to perform or control performance of any of the methods described above.
- a non-volatile storage medium e.g., storage medium 130 , FIG. 1
- processors e.g., CPUs 122 , FIGS. 1 and 2
- memory e.g., memory 206 , FIG. 2
- first first
- second second
- first contact first contact
- first contact second contact
- first contact second contact
- the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context.
- the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
Abstract
Description
(1−e −k(n+0.5)/(m−1))k (1)
-
- a hash
function generation module 216 that is used for processing an element with k distinct hash functions to generate k bit positions in a Bloom filter (e.g., Bloom filter array(s) 131,FIG. 1 ); - an
add element module 218 that is used for adding elements to the Bloom filter; - a
test element module 224 that is used for testing whether an element is present in the Bloom filter; - a
delete element module 232 that is used for deleting an element from the Bloom filter; - a
reset module 238 that is used for resetting the Bloom filter to an empty state; and - a
fingerprint module 240 that is used for generating an n-bit fingerprint of an object to be added to the Bloom filter, where n is at least 64.
- a hash
-
- an add
element processing module 220 that is used for processing the element to be added with k distinct hash functions to generate k bit positions in a Bloom filter and/or communicating with hashfunction generation module 216 to obtain the k bit positions; and - a
bit setting module 222 that is used for setting the k bit positions in the Bloom filter.
- an add
-
- a test
element processing module 226 that is used for processing the element to be tested with k distinct hash functions to generate k bit positions in a Bloom filter and/or communicating with hashfunction generation module 216 to obtain the k bit positions; - a
bit reading module 228 that is used for reading the k bit positions from the Bloom filter; and - a
test result module 230 that is used for returning a first result if all the k bit positions in the Bloom filter are set and returning a second result if at least a predetermined number (e.g., one or more) of the k bit positions in the Bloom filter are not set.
- a test
-
- a delete
element processing module 234 that is used for processing the element to be deleted with k distinct hash functions to generate k bit positions in a Bloom filter and/or communicating with hashfunction generation module 216 to obtain the k bit positions; and - a
bit resetting module 236 that is used for resetting the k bit positions in the Bloom filter.
- a delete
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/035,876 US9043517B1 (en) | 2013-07-25 | 2013-09-24 | Multipass programming in buffers implemented in non-volatile data storage systems |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361858528P | 2013-07-25 | 2013-07-25 | |
US14/035,876 US9043517B1 (en) | 2013-07-25 | 2013-09-24 | Multipass programming in buffers implemented in non-volatile data storage systems |
Publications (1)
Publication Number | Publication Date |
---|---|
US9043517B1 true US9043517B1 (en) | 2015-05-26 |
Family
ID=53176481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/035,876 Active 2033-11-28 US9043517B1 (en) | 2013-07-25 | 2013-09-24 | Multipass programming in buffers implemented in non-volatile data storage systems |
Country Status (1)
Country | Link |
---|---|
US (1) | US9043517B1 (en) |
Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9361221B1 (en) | 2013-08-26 | 2016-06-07 | Sandisk Technologies Inc. | Write amplification reduction through reliable writes during garbage collection |
US9367246B2 (en) | 2013-03-15 | 2016-06-14 | Sandisk Technologies Inc. | Performance optimization of data transfer for soft information generation |
US9384126B1 (en) * | 2013-07-25 | 2016-07-05 | Sandisk Technologies Inc. | Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems |
US9390021B2 (en) | 2014-03-31 | 2016-07-12 | Sandisk Technologies Llc | Efficient cache utilization in a tiered data structure |
US9436831B2 (en) | 2013-10-30 | 2016-09-06 | Sandisk Technologies Llc | Secure erase in a memory device |
US9443601B2 (en) | 2014-09-08 | 2016-09-13 | Sandisk Technologies Llc | Holdup capacitor energy harvesting |
US9442662B2 (en) | 2013-10-18 | 2016-09-13 | Sandisk Technologies Llc | Device and method for managing die groups |
US9448876B2 (en) | 2014-03-19 | 2016-09-20 | Sandisk Technologies Llc | Fault detection and prediction in storage devices |
US9448743B2 (en) | 2007-12-27 | 2016-09-20 | Sandisk Technologies Llc | Mass storage controller volatile memory containing metadata related to flash memory storage |
US9454448B2 (en) | 2014-03-19 | 2016-09-27 | Sandisk Technologies Llc | Fault testing in storage devices |
US9454420B1 (en) | 2012-12-31 | 2016-09-27 | Sandisk Technologies Llc | Method and system of reading threshold voltage equalization |
US9520162B2 (en) | 2013-11-27 | 2016-12-13 | Sandisk Technologies Llc | DIMM device controller supervisor |
US9520197B2 (en) | 2013-11-22 | 2016-12-13 | Sandisk Technologies Llc | Adaptive erase of a storage device |
US9524235B1 (en) | 2013-07-25 | 2016-12-20 | Sandisk Technologies Llc | Local hash value generation in non-volatile data storage systems |
US9582058B2 (en) | 2013-11-29 | 2017-02-28 | Sandisk Technologies Llc | Power inrush management of storage devices |
US9612948B2 (en) | 2012-12-27 | 2017-04-04 | Sandisk Technologies Llc | Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device |
US9626399B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Conditional updates for reducing frequency of data modification operations |
US9626400B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Compaction of information in tiered data structure |
US9639463B1 (en) | 2013-08-26 | 2017-05-02 | Sandisk Technologies Llc | Heuristic aware garbage collection scheme in storage systems |
US9652381B2 (en) | 2014-06-19 | 2017-05-16 | Sandisk Technologies Llc | Sub-block garbage collection |
US9699263B1 (en) | 2012-08-17 | 2017-07-04 | Sandisk Technologies Llc. | Automatic read and write acceleration of data accessed by virtual machines |
US9697267B2 (en) | 2014-04-03 | 2017-07-04 | Sandisk Technologies Llc | Methods and systems for performing efficient snapshots in tiered data structures |
US9703491B2 (en) | 2014-05-30 | 2017-07-11 | Sandisk Technologies Llc | Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device |
US9703636B2 (en) | 2014-03-01 | 2017-07-11 | Sandisk Technologies Llc | Firmware reversion trigger and control |
US9703816B2 (en) | 2013-11-19 | 2017-07-11 | Sandisk Technologies Llc | Method and system for forward reference logging in a persistent datastore |
US9870830B1 (en) | 2013-03-14 | 2018-01-16 | Sandisk Technologies Llc | Optimal multilevel sensing for reading data from a storage medium |
US10037164B1 (en) | 2016-06-29 | 2018-07-31 | EMC IP Holding Company LLC | Flash interface for processing datasets |
US10055351B1 (en) | 2016-06-29 | 2018-08-21 | EMC IP Holding Company LLC | Low-overhead index for a flash cache |
US10089025B1 (en) * | 2016-06-29 | 2018-10-02 | EMC IP Holding Company LLC | Bloom filters in a flash memory |
US10114557B2 (en) | 2014-05-30 | 2018-10-30 | Sandisk Technologies Llc | Identification of hot regions to enhance performance and endurance of a non-volatile storage device |
US10146448B2 (en) | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
US10146438B1 (en) | 2016-06-29 | 2018-12-04 | EMC IP Holding Company LLC | Additive library for data structures in a flash memory |
US10162748B2 (en) | 2014-05-30 | 2018-12-25 | Sandisk Technologies Llc | Prioritizing garbage collection and block allocation based on I/O history for logical address regions |
US20190044701A1 (en) * | 2017-08-04 | 2019-02-07 | Institute For Information Industry | Transmission apparatus, and transmission data protection method thereof |
US10261704B1 (en) | 2016-06-29 | 2019-04-16 | EMC IP Holding Company LLC | Linked lists in flash memory |
US10331561B1 (en) | 2016-06-29 | 2019-06-25 | Emc Corporation | Systems and methods for rebuilding a cache index |
US10372613B2 (en) | 2014-05-30 | 2019-08-06 | Sandisk Technologies Llc | Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device |
CN111159436A (en) * | 2018-11-07 | 2020-05-15 | 腾讯科技(深圳)有限公司 | Method and device for recommending multimedia content and computing equipment |
US10656842B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device |
US10656840B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Real-time I/O pattern recognition to enhance performance and endurance of a storage device |
US11410727B1 (en) | 2021-03-15 | 2022-08-09 | Sandisk Technologies Llc | Scalable search system design with single level cell NAND-based binary and ternary valued content addressable memory cells |
Citations (214)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916652A (en) | 1987-09-30 | 1990-04-10 | International Business Machines Corporation | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures |
US5270979A (en) | 1991-03-15 | 1993-12-14 | Sundisk Corporation | Method for optimum erasing of EEPROM |
US5519847A (en) | 1993-06-30 | 1996-05-21 | Intel Corporation | Method of pipelining sequential writes in a flash memory |
US5530705A (en) | 1995-02-08 | 1996-06-25 | International Business Machines Corporation | Soft error recovery system and method |
US5537555A (en) | 1993-03-22 | 1996-07-16 | Compaq Computer Corporation | Fully pipelined and highly concurrent memory controller |
US5551003A (en) | 1992-12-11 | 1996-08-27 | International Business Machines Corporation | System for managing log structured array (LSA) of DASDS by managing segment space availability and reclaiming regions of segments using garbage collection procedure |
US5657332A (en) | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
US5666114A (en) | 1994-11-22 | 1997-09-09 | International Business Machines Corporation | Method and means for managing linear mapped address spaces storing compressed data at the storage subsystem control unit or device level |
US5708849A (en) | 1994-01-26 | 1998-01-13 | Intel Corporation | Implementing scatter/gather operations in a direct memory access device on a personal computer |
US5765185A (en) | 1995-03-17 | 1998-06-09 | Atmel Corporation | EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles |
US5943692A (en) | 1997-04-30 | 1999-08-24 | International Business Machines Corporation | Mobile client computer system with flash memory management utilizing a virtual address map and variable length data |
US5982664A (en) | 1997-10-22 | 1999-11-09 | Oki Electric Industry Co., Ltd. | Semiconductor memory capable of writing and reading data |
US6000006A (en) | 1997-08-25 | 1999-12-07 | Bit Microsystems, Inc. | Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage |
US6016560A (en) | 1995-06-14 | 2000-01-18 | Hitachi, Ltd. | Semiconductor memory, memory device, and memory card |
US6018304A (en) | 1997-12-18 | 2000-01-25 | Texas Instruments Incorporated | Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability |
US6070074A (en) | 1998-04-24 | 2000-05-30 | Trw Inc. | Method for enhancing the performance of a regenerative satellite communications system |
US6138261A (en) | 1998-04-29 | 2000-10-24 | Trw Inc. | Concatenated coding system for satellite communications |
US6182264B1 (en) | 1998-05-22 | 2001-01-30 | Vlsi Technology, Inc. | Smart dynamic selection of error correction methods for DECT based data services |
US6192092B1 (en) | 1998-06-15 | 2001-02-20 | Intel Corp. | Method and apparatus for clock skew compensation |
US6295592B1 (en) | 1998-07-31 | 2001-09-25 | Micron Technology, Inc. | Method of processing memory requests in a pipelined memory controller |
US6311263B1 (en) | 1994-09-23 | 2001-10-30 | Cambridge Silicon Radio Limited | Data processing circuits and interfaces |
US20020024846A1 (en) | 1996-09-30 | 2002-02-28 | Takayuki Kawahara | Semiconductor integrated circuit and data processing system |
US6412042B1 (en) | 1999-11-17 | 2002-06-25 | Maxtor Corporation | System and method for improved disk drive performance and reliability |
US20020083299A1 (en) | 2000-12-22 | 2002-06-27 | International Business Machines Corporation | High speed remote storage controller |
US6442076B1 (en) | 2000-06-30 | 2002-08-27 | Micron Technology, Inc. | Flash memory with multiple status reading capability |
US6449625B1 (en) | 1999-04-20 | 2002-09-10 | Lucent Technologies Inc. | Use of a two-way stack approach to optimize flash memory management for embedded database systems |
JP2002532806A (en) | 1998-12-18 | 2002-10-02 | ユニシス コーポレーション | Computer system and method for operating multiple operating systems in different partitions of a computer system so that different partitions can communicate with each other via shared memory |
US20020152305A1 (en) | 2000-03-03 | 2002-10-17 | Jackson Gregory J. | Systems and methods for resource utilization analysis in information management environments |
US20020162075A1 (en) | 2001-04-30 | 2002-10-31 | Talagala Nisha D. | Storage array employing scrubbing operations at the disk-controller level |
US20020165896A1 (en) | 2001-05-02 | 2002-11-07 | Kim Jason Seung-Min | Multiprocessor communication system and method |
US6484224B1 (en) | 1999-11-29 | 2002-11-19 | Cisco Technology Inc. | Multi-interface symmetric multiprocessor |
US6516437B1 (en) | 2000-03-07 | 2003-02-04 | General Electric Company | Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates |
US20030041299A1 (en) | 2001-08-23 | 2003-02-27 | Fujitsu Limited | Memory controller for multilevel cell memory |
US20030043829A1 (en) | 2001-07-06 | 2003-03-06 | Abbas Rashid | Cross-bar switch employing a multiple entry point FIFO |
US20030088805A1 (en) | 2001-09-28 | 2003-05-08 | Tim Majni | Error indication in a raid memory system |
US20030093628A1 (en) | 2001-11-14 | 2003-05-15 | Matter Eugene P. | Memory adaptedt to provide dedicated and or shared memory to multiple processors and method therefor |
US20030188045A1 (en) | 2000-04-13 | 2003-10-02 | Jacobson Michael B. | System and method for distributing storage controller tasks |
US20030189856A1 (en) | 2002-04-04 | 2003-10-09 | Samsung Electronics Co., Ltd. | Multi-level flash memory with temperature compensation |
US20030198100A1 (en) | 2001-12-04 | 2003-10-23 | Hitachi, Ltd. | Method of controlling the operation of non-volatile semiconductor memory chips |
US20030212719A1 (en) | 2002-05-08 | 2003-11-13 | Hitachi, Ltd. | Method for heap memory management and computer system using the same method |
US6678788B1 (en) | 2000-05-26 | 2004-01-13 | Emc Corporation | Data type and topological data categorization and ordering for a mass storage system |
US20040024957A1 (en) | 2001-08-07 | 2004-02-05 | Chun-Hung Lin | Window-based flash memory storage system and management and access methods thereof |
US20040024963A1 (en) | 2002-08-05 | 2004-02-05 | Nisha Talagala | Method and system for striping data to accommodate integrity metadata |
US20040073829A1 (en) | 1998-07-16 | 2004-04-15 | Olarig Sompong P. | Fail-over of multiple memory blocks in multiple memory modules in computer system |
US6757768B1 (en) | 2001-05-17 | 2004-06-29 | Cisco Technology, Inc. | Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node |
US20040153902A1 (en) | 2003-01-21 | 2004-08-05 | Nexflash Technologies, Inc. | Serial flash integrated circuit having error detection and correction |
US6775792B2 (en) | 2001-01-29 | 2004-08-10 | Snap Appliance, Inc. | Discrete mapping of parity blocks |
US20040181734A1 (en) | 2003-03-14 | 2004-09-16 | Saliba George A. | Extended error correction codes |
EP1465203A1 (en) | 2003-04-03 | 2004-10-06 | Samsung Electronics Co., Ltd. | Nonvolatile memory with page copy capability and method thereof |
US20040199714A1 (en) | 1995-07-31 | 2004-10-07 | Petro Estakhri | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
US6810440B2 (en) | 1999-06-09 | 2004-10-26 | Qlogic Corporation | Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter |
US20040237018A1 (en) | 2003-05-23 | 2004-11-25 | Riley Dwight D. | Dual decode scheme |
US6836815B1 (en) | 2001-07-11 | 2004-12-28 | Pasternak Solutions Llc | Layered crossbar for interconnection of multiple processors and shared memories |
US6836808B2 (en) | 2002-02-25 | 2004-12-28 | International Business Machines Corporation | Pipelined packet processing |
US6842436B2 (en) | 1999-12-17 | 2005-01-11 | Siemens Aktiengesellschaft | Multiport-RAM memory device |
US20050060501A1 (en) | 2003-09-16 | 2005-03-17 | Denali Software, Inc. | Port independent data transaction interface for multi-port devices |
US20050060456A1 (en) | 2003-09-16 | 2005-03-17 | Denali Software, Inc. | Method and apparatus for multi-port memory controller |
US6871257B2 (en) | 2002-02-22 | 2005-03-22 | Sandisk Corporation | Pipelined parallel programming operation in a non-volatile memory system |
US6895464B2 (en) | 2002-06-03 | 2005-05-17 | Honeywell International Inc. | Flash memory management system and method utilizing multiple block list windows |
US20050114587A1 (en) | 2003-11-22 | 2005-05-26 | Super Talent Electronics Inc. | ExpressCard with On-Card Flash Memory with Shared Flash-Control Bus but Separate Ready Lines |
US20050172065A1 (en) | 2004-01-30 | 2005-08-04 | Micron Technology, Inc. | Data move method and apparatus |
US20050172207A1 (en) | 2004-01-30 | 2005-08-04 | Radke William H. | Error detection and correction scheme for a memory device |
US20050193161A1 (en) | 2004-02-26 | 2005-09-01 | Lee Charles C. | System and method for controlling flash memory |
US20050201148A1 (en) | 2004-03-12 | 2005-09-15 | Super Talent Electronics, Inc. | Flash memory device and architecture with multi level cells |
US20050231765A1 (en) | 2003-12-16 | 2005-10-20 | Matsushita Electric Industrial Co., Ltd. | Information recording medium, data processing apparatus and data processing method |
US20050257120A1 (en) | 2004-05-13 | 2005-11-17 | Gorobets Sergey A | Pipelined data relocation and improved chip architectures |
US20050273560A1 (en) | 2004-06-03 | 2005-12-08 | Hulbert Jared E | Method and apparatus to avoid incoherency between a cache memory and flash memory |
US6978343B1 (en) | 2002-08-05 | 2005-12-20 | Netlogic Microsystems, Inc. | Error-correcting content addressable memory |
US6981205B2 (en) | 2001-10-23 | 2005-12-27 | Lenovo (Singapore) Pte Ltd | Data storage apparatus, read data processor, and read data processing method |
US6980985B1 (en) | 2000-08-30 | 2005-12-27 | At&T Corp. | Distributed evalulation of directory queries using a topology cache |
US20050289314A1 (en) | 2004-06-23 | 2005-12-29 | Adusumilli Vijaya P | Simultaneous external read operation during internal programming in a flash memory device |
US6988171B2 (en) | 1999-03-03 | 2006-01-17 | International Business Machines Corporation | Method and system for recovery of meta data in a storage controller |
US20060039196A1 (en) | 2003-10-03 | 2006-02-23 | Gorobets Sergey A | Corrected data storage and handling methods |
US20060039227A1 (en) | 2004-08-17 | 2006-02-23 | Lawrence Lai | Memory device having staggered memory operations |
US20060053246A1 (en) | 2004-08-30 | 2006-03-09 | Lee Schweiray J | Systems and methods for providing nonvolatile memory management in wireless phones |
US7020017B2 (en) | 2004-04-06 | 2006-03-28 | Sandisk Corporation | Variable programming of non-volatile memory |
US7028165B2 (en) | 2000-12-06 | 2006-04-11 | Intel Corporation | Processor stalling |
US7032123B2 (en) | 2001-10-19 | 2006-04-18 | Sun Microsystems, Inc. | Error recovery |
US20060087893A1 (en) | 2004-10-27 | 2006-04-27 | Sony Corporation | Storage device and information processing system |
US7043505B1 (en) | 2003-01-28 | 2006-05-09 | Unisys Corporation | Method variation for collecting stability data from proprietary systems |
US20060136570A1 (en) | 2003-06-10 | 2006-06-22 | Pandya Ashish A | Runtime adaptable search processor |
US20060156177A1 (en) | 2004-12-29 | 2006-07-13 | Sailesh Kottapalli | Method and apparatus for recovering from soft errors in register files |
US20060195650A1 (en) | 2005-02-25 | 2006-08-31 | Su Zhiqiang J | Method to detect NAND-flash parameters by hardware automatically |
US7111293B1 (en) | 1998-06-03 | 2006-09-19 | Ants Software, Inc. | Method for increased concurrency in a computer system |
US20060259528A1 (en) | 2005-05-13 | 2006-11-16 | Microsoft Corporation | Implementation for collecting unmanaged memory |
US20070011413A1 (en) | 2004-01-29 | 2007-01-11 | Yusuke Nonaka | Storage system having a plurality of interfaces |
US20070058446A1 (en) | 2005-09-15 | 2007-03-15 | Hynix Semiconductor Inc. | Erase and Program Method of Flash Memory Device for Increasing Program Speed of Flash Memory Device |
US20070061597A1 (en) | 2005-09-14 | 2007-03-15 | Micky Holtzman | Secure yet flexible system architecture for secure devices with flash mass storage memory |
WO2007036834A2 (en) | 2005-09-27 | 2007-04-05 | Nxp B.V. | Error detection / correction circuit and corresponding method |
US20070076479A1 (en) | 2005-09-30 | 2007-04-05 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
US20070083697A1 (en) | 2005-10-07 | 2007-04-12 | Microsoft Corporation | Flash memory management |
US20070081408A1 (en) | 2005-10-06 | 2007-04-12 | Oh Suk Kwon | Multi-chip semiconductor memory device having internal power supply voltage generation circuit for decreasing current consumption |
US20070091677A1 (en) | 2005-10-25 | 2007-04-26 | M-Systems Flash Disk Pioneers Ltd. | Method for recovering from errors in flash memory |
US20070113019A1 (en) | 2005-11-17 | 2007-05-17 | International Business Machines Corporation | Fast path memory read request processing in a multi-level memory architecture |
US20070133312A1 (en) | 2000-05-10 | 2007-06-14 | Micron Technology, Inc. | Flash with consistent latency for read operations |
US20070147113A1 (en) | 2005-12-28 | 2007-06-28 | Nima Mokhlesi | Alternate sensing techniques for non-volatile memories |
US20070150790A1 (en) | 2005-12-27 | 2007-06-28 | Gross Stephen J | Method of storing downloadable firmware on bulk media |
US20070157064A1 (en) | 2005-12-27 | 2007-07-05 | D.S.P. Group Ltd. | Systems and methods for error corrections |
WO2007080586A2 (en) | 2006-01-10 | 2007-07-19 | Saifun Semiconductors Ltd. | Rd algorithm improvement for nrom technology |
US20070174579A1 (en) | 2006-01-20 | 2007-07-26 | Samsung Electronics Co., Ltd. | Apparatus for collecting garbage block of nonvolatile memory according to power state and method of collecting the same |
US20070180188A1 (en) | 2006-02-02 | 2007-08-02 | Akira Fujibayashi | Virtual path storage system and control method for the same |
US20070201274A1 (en) | 2000-01-06 | 2007-08-30 | Super Talent Electronics Inc. | Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory |
US20070234143A1 (en) | 2006-01-25 | 2007-10-04 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices |
US20070245061A1 (en) | 2006-04-13 | 2007-10-18 | Intel Corporation | Multiplexing a parallel bus interface and a flash memory interface |
US20070277036A1 (en) | 2003-05-23 | 2007-11-29 | Washington University, A Corporation Of The State Of Missouri | Intelligent data storage and processing using fpga devices |
US20070279988A1 (en) | 2006-05-17 | 2007-12-06 | Micron Technology, Inc. | Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices |
US20070291556A1 (en) | 2006-06-19 | 2007-12-20 | Teruhiko Kamei | Programming Differently Sized Margins and Sensing with Compensations at Select States for Improved Read Operations in Non-Volatile Memory |
US20070294496A1 (en) | 2006-06-19 | 2007-12-20 | Texas Instruments Incorporated | Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices |
US20070300130A1 (en) | 2006-05-17 | 2007-12-27 | Sandisk Corporation | Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices |
US20080022163A1 (en) | 2006-06-28 | 2008-01-24 | Hitachi, Ltd. | Storage system and data protection method therefor |
US20080019182A1 (en) | 2006-07-20 | 2008-01-24 | Kosuke Yanagidaira | Semiconductor memory device and control method of the same |
US7328377B1 (en) | 2004-01-27 | 2008-02-05 | Altera Corporation | Error correction for programmable logic integrated circuits |
US20080052446A1 (en) | 2006-08-28 | 2008-02-28 | Sandisk Il Ltd. | Logical super block mapping for NAND flash memory |
US20080056005A1 (en) | 2006-08-30 | 2008-03-06 | Micron Technology, Inc. | Non-volatile memory cell read failure reduction |
US20080077841A1 (en) | 2006-09-27 | 2008-03-27 | Gonzalez Carlos J | Methods of Cell Population Distribution Assisted Read Margining |
US20080077937A1 (en) | 2006-07-28 | 2008-03-27 | Samsung Electronics Co., Ltd. | Multipath accessible semiconductor memory device with host interface between processors |
US20080086677A1 (en) | 2006-10-10 | 2008-04-10 | Xueshi Yang | Adaptive systems and methods for storing and retrieving data to and from memory cells |
US20080144371A1 (en) | 2005-10-12 | 2008-06-19 | Macronix International Co., Ltd. | Systems and methods for programming a memory device |
US20080147998A1 (en) | 2006-12-18 | 2008-06-19 | Samsung Electronics Co., Ltd. | Method and apparatus for detecting static data area, wear-leveling, and merging data units in nonvolatile data storage device |
US20080148124A1 (en) | 2004-06-04 | 2008-06-19 | Yan Zhang | Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems |
US20080147964A1 (en) | 2004-02-26 | 2008-06-19 | Chow David Q | Using various flash memory cells to build usb data flash cards with multiple partitions and autorun function |
US20080168319A1 (en) | 2007-01-08 | 2008-07-10 | Samsung Electronics Co., Ltd. | Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems |
US20080168191A1 (en) | 2007-01-10 | 2008-07-10 | Giora Biran | Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device |
US20080170460A1 (en) | 2007-01-17 | 2008-07-17 | Samsung Electronics Co., Ltd | Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof |
US20080229000A1 (en) | 2007-03-12 | 2008-09-18 | Samsung Electronics Co., Ltd. | Flash memory device and memory system |
US20080229176A1 (en) | 2003-12-22 | 2008-09-18 | International Business Machines Corporation | Method for fast ecc memory testing by software including ecc check byte |
US20080229003A1 (en) | 2007-03-15 | 2008-09-18 | Nagamasa Mizushima | Storage system and method of preventing deterioration of write performance in storage system |
WO2008121577A1 (en) | 2007-03-31 | 2008-10-09 | Sandisk Corporation | Soft bit data transmission for error correction control in non-volatile memory |
WO2008121553A1 (en) | 2007-03-29 | 2008-10-09 | Sandisk Corporation | Non-volatile storage with decoding of data using reliability metrics based on multiple reads |
US20080270680A1 (en) | 2005-11-17 | 2008-10-30 | Chee Keng Chang | Controller for Non-Volatile Memories and Methods of Operating the Memory Controller |
EP1990921A2 (en) | 2007-05-07 | 2008-11-12 | Broadcom Corporation | Operational parameter adaptable LDPC (low density parity check) decoder |
US20080282128A1 (en) | 1999-08-04 | 2008-11-13 | Super Talent Electronics, Inc. | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance |
US20080285351A1 (en) | 2007-05-14 | 2008-11-20 | Mark Shlick | Measuring threshold voltage distribution in memory using an aggregate characteristic |
US20080313132A1 (en) * | 2007-06-15 | 2008-12-18 | Fang Hao | High accuracy bloom filter using partitioned hashing |
US20090003058A1 (en) | 2007-06-28 | 2009-01-01 | Samsung Electronics Co., Ltd. | Flash memory device and method for adjusting read voltage of flash memory device |
US20090037652A1 (en) | 2003-12-02 | 2009-02-05 | Super Talent Electronics Inc. | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules |
WO2009028281A1 (en) | 2007-08-31 | 2009-03-05 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of controlling the same |
WO2009032945A1 (en) | 2007-09-06 | 2009-03-12 | Siliconsystems, Inc. | Storage subsystem capable of adjusting ecc settings based on monitored conditions |
US7516292B2 (en) | 2003-05-09 | 2009-04-07 | Fujitsu Limited | Method for predicting and avoiding danger in execution environment |
US7523157B2 (en) | 2003-09-25 | 2009-04-21 | International Business Machines Corporation | Managing a plurality of processors as devices |
US7529466B2 (en) | 2001-08-06 | 2009-05-05 | Sony Corporation | Signal processing method and signal processing apparatus |
US7527466B2 (en) | 2003-04-03 | 2009-05-05 | Simmons Robert J | Building-erection structural member transporter |
WO2009058140A1 (en) | 2007-10-31 | 2009-05-07 | Agere Systems Inc. | Systematic error correction for multi-level flash memory |
US20090125671A1 (en) | 2006-12-06 | 2009-05-14 | David Flynn | Apparatus, system, and method for storage space recovery after reaching a read count limit |
US20090144598A1 (en) | 2007-11-30 | 2009-06-04 | Tony Yoon | Error correcting code predication system and method |
US20090172308A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories |
US20090172335A1 (en) | 2007-12-31 | 2009-07-02 | Anand Krishnamurthi Kulkarni | Flash devices with raid |
WO2009084724A1 (en) | 2007-12-28 | 2009-07-09 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20090193058A1 (en) | 2008-01-29 | 2009-07-30 | Denali Software, Inc. | System and method for providing copyback data integrity in a non-volatile memory system |
US7571277B2 (en) | 2006-11-06 | 2009-08-04 | Hitachi, Ltd. | Semiconductor memory system for flash memory |
US20090222708A1 (en) | 2008-03-01 | 2009-09-03 | Kabushiki Kaisha Toshiba | Error correcting device and error correcting method |
US20090228761A1 (en) | 2008-03-07 | 2009-09-10 | Anobit Technologies Ltd | Efficient readout from analog memory cells using data compression |
US7596643B2 (en) | 2007-02-07 | 2009-09-29 | Siliconsystems, Inc. | Storage subsystem with configurable buffer |
WO2009134576A1 (en) | 2008-04-30 | 2009-11-05 | Apple Inc. | Copyback optimization for memory system |
US20090292972A1 (en) | 2008-05-23 | 2009-11-26 | Samsung Electronics Co., Ltd. | Error correction apparatus, method thereof and memory device comprising the apparatus |
US20090296486A1 (en) | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20090296466A1 (en) | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20090319864A1 (en) | 2008-06-20 | 2009-12-24 | Denali Software, Inc. | Method and apparatus for dynamically configurable multi level error correction |
US20100002506A1 (en) | 2008-07-04 | 2010-01-07 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20100061151A1 (en) | 2008-09-11 | 2010-03-11 | Toru Miwa | Multi-pass programming for memory with reduced data storage requirement |
US7681106B2 (en) | 2006-03-29 | 2010-03-16 | Freescale Semiconductor, Inc. | Error correction device and methods thereof |
US7685494B1 (en) | 2006-05-08 | 2010-03-23 | Marvell International, Ltd. | Error correction coding for varying signal-to-noise ratio channels |
US20100091535A1 (en) | 2007-03-12 | 2010-04-15 | Anobit Technologies Ltd | Adaptive estimation of memory cell read thresholds |
US7707481B2 (en) | 2006-05-16 | 2010-04-27 | Pitney Bowes Inc. | System and method for efficient uncorrectable error detection in flash memory |
US20100103737A1 (en) | 2008-10-28 | 2010-04-29 | Ki Tae Park | Read Compensation Circuits and Apparatus Using Same |
US20100161936A1 (en) | 2008-12-22 | 2010-06-24 | Robert Royer | Method and system for queuing transfers of multiple non-contiguous address ranges with a single command |
US20100199125A1 (en) | 2009-02-04 | 2010-08-05 | Micron Technology, Inc. | Systems and Methods for Storing and Recovering Controller Data in Non-Volatile Memory Devices |
US20100202196A1 (en) | 2009-02-06 | 2010-08-12 | Sang Kyu Lee | Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method |
US20100208521A1 (en) | 2009-02-17 | 2010-08-19 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device |
US20100262889A1 (en) | 2006-06-30 | 2010-10-14 | Bains Kuljit S | Reliability, availability, and serviceability in a memory device |
US20100281342A1 (en) | 2009-04-30 | 2010-11-04 | Samsung Electronics Co., Ltd. | Memory controller and memory system |
US20100281207A1 (en) | 2009-04-30 | 2010-11-04 | Miller Steven C | Flash-based data archive storage system |
US7870326B2 (en) | 2006-07-28 | 2011-01-11 | Samsung Electronics Co., Ltd. | Multiprocessor system and method thereof |
US7890818B2 (en) | 2007-03-28 | 2011-02-15 | Samsung Electronics Co., Ltd. | Read level control apparatuses and methods |
WO2011024015A1 (en) | 2009-08-25 | 2011-03-03 | Sandisk Il Ltd. | Restoring data into a flash storage device |
US20110051513A1 (en) | 2009-08-25 | 2011-03-03 | Micron Technology, Inc. | Methods, devices, and systems for dealing with threshold voltage change in memory devices |
US7913022B1 (en) | 2007-02-14 | 2011-03-22 | Xilinx, Inc. | Port interface modules (PIMs) in a multi-port memory controller (MPMC) |
US20110083060A1 (en) | 2009-10-05 | 2011-04-07 | Kabushiki Kaisha Toshiba | Memory system and control method for the same |
US7925960B2 (en) | 2006-11-07 | 2011-04-12 | Macronix International Co., Ltd. | Memory and method for checking reading errors thereof |
US20110113281A1 (en) | 2009-11-12 | 2011-05-12 | Via Technologies, Inc. | Data storage system and method |
US7954041B2 (en) | 2005-10-31 | 2011-05-31 | Samsung Electronics Co., Ltd | Apparatus and method for transmitting/receiving a signal in a communication system using a low density parity check code |
US20110131444A1 (en) | 2009-12-02 | 2011-06-02 | Seagate Technology Llc | Systems and methods for low wear operation of solid state memory |
US7971112B2 (en) | 2008-02-05 | 2011-06-28 | Fujitsu Limited | Memory diagnosis method |
US7974368B2 (en) | 2006-09-25 | 2011-07-05 | Sunplus Technology Co., Ltd. | Decoding method and system for real-time wireless channel estimation |
US20110173378A1 (en) | 2009-08-24 | 2011-07-14 | Ocz Technology Group, Inc. | Computer system with backup function and method therefor |
US7996642B1 (en) | 2007-04-25 | 2011-08-09 | Marvell International Ltd. | Digital locked loop on channel tagged memory requests for memory optimization |
US20110199825A1 (en) | 2010-02-17 | 2011-08-18 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, operating method thereof, and memory system including the same |
US8006161B2 (en) | 2005-10-26 | 2011-08-23 | Samsung Electronics Co., Ltd | Apparatus and method for receiving signal in a communication system using a low density parity check code |
US20110205823A1 (en) | 2010-02-19 | 2011-08-25 | Gerrit Jan Hemink | Non-Volatile Storage With Temperature Compensation Based On Neighbor State Information |
US20110213920A1 (en) | 2009-08-11 | 2011-09-01 | Texas Memory Systems, Inc. | FLASH-based Memory System with Static or Variable Length Page Stripes Including Data Protection Information and Auxiliary Protection Stripes |
US20110228601A1 (en) | 2010-03-17 | 2011-09-22 | Olbrich Aaron K | Mlc self-raid flash data protection scheme |
US20110231600A1 (en) | 2006-03-29 | 2011-09-22 | Hitachi, Ltd. | Storage System Comprising Flash Memory Modules Subject to Two Wear - Leveling Process |
US8032724B1 (en) | 2007-04-04 | 2011-10-04 | Marvell International Ltd. | Demand-driven opportunistic garbage collection in memory components |
US8042011B2 (en) | 2009-04-28 | 2011-10-18 | Synopsys, Inc. | Runtime programmable BIST for testing a multi-port memory device |
US8069390B2 (en) | 2006-07-25 | 2011-11-29 | Commuications Coding Corporation | Universal error control coding scheme for digital communication and data storage systems |
US20120096217A1 (en) | 2010-10-15 | 2012-04-19 | Kyquang Son | File system-aware solid-state storage management system |
US20120110250A1 (en) | 2010-11-03 | 2012-05-03 | Densbits Technologies Ltd. | Meethod, system and computer readable medium for copy back |
US8190967B2 (en) | 2006-12-08 | 2012-05-29 | Samsung Electronics Co., Ltd. | Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method |
US20120151294A1 (en) | 2010-12-09 | 2012-06-14 | Samsung Electronics Co., Ltd. | Method and apparatus for correcting errors in memory device |
US20120151253A1 (en) | 2010-12-14 | 2012-06-14 | Western Digital Technologies, Inc. | System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss |
US20120151124A1 (en) | 2010-12-08 | 2012-06-14 | Sung Hoon Baek | Non-Volatile Memory Device, Devices Having the Same, and Method of Operating the Same |
US20120195126A1 (en) | 2008-01-22 | 2012-08-02 | Micron Technology, Inc. | Cell operation monitoring |
US8254181B2 (en) | 2008-11-24 | 2012-08-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and programming method |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US20120239976A1 (en) | 2010-07-09 | 2012-09-20 | Stec, Inc. | Apparatus and method for determining a read level of a flash memory after an inactive period of time |
US20120284587A1 (en) | 2008-06-18 | 2012-11-08 | Super Talent Electronics, Inc. | Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear |
US8312349B2 (en) | 2009-10-27 | 2012-11-13 | Micron Technology, Inc. | Error detection/correction based memory management |
US20130036418A1 (en) * | 2010-12-22 | 2013-02-07 | Vmware, Inc. | In-Place Snapshots of a Virtual Disk Configured with Sparse Extent |
US8412985B1 (en) | 2009-06-30 | 2013-04-02 | Micron Technology, Inc. | Hardwired remapped memory |
US20130179646A1 (en) | 2012-01-10 | 2013-07-11 | Sony Corporation | Storage control device, storage device, and control method for controlling storage control device |
US20130343131A1 (en) | 2012-06-26 | 2013-12-26 | Lsi Corporation | Fast tracking for flash channels |
US20140095775A1 (en) | 2012-01-12 | 2014-04-03 | Fusion-io-Inc. | Systems and methods for cache endurance |
US20140122818A1 (en) * | 2012-10-31 | 2014-05-01 | Hitachi Computer Peripherals Co., Ltd. | Storage apparatus and method for controlling storage apparatus |
US20140143505A1 (en) * | 2012-11-19 | 2014-05-22 | Advanced Micro Devices, Inc. | Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode |
-
2013
- 2013-09-24 US US14/035,876 patent/US9043517B1/en active Active
Patent Citations (236)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916652A (en) | 1987-09-30 | 1990-04-10 | International Business Machines Corporation | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures |
US5270979A (en) | 1991-03-15 | 1993-12-14 | Sundisk Corporation | Method for optimum erasing of EEPROM |
US5657332A (en) | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
US5551003A (en) | 1992-12-11 | 1996-08-27 | International Business Machines Corporation | System for managing log structured array (LSA) of DASDS by managing segment space availability and reclaiming regions of segments using garbage collection procedure |
US5537555A (en) | 1993-03-22 | 1996-07-16 | Compaq Computer Corporation | Fully pipelined and highly concurrent memory controller |
US5519847A (en) | 1993-06-30 | 1996-05-21 | Intel Corporation | Method of pipelining sequential writes in a flash memory |
US5708849A (en) | 1994-01-26 | 1998-01-13 | Intel Corporation | Implementing scatter/gather operations in a direct memory access device on a personal computer |
US6311263B1 (en) | 1994-09-23 | 2001-10-30 | Cambridge Silicon Radio Limited | Data processing circuits and interfaces |
US5666114A (en) | 1994-11-22 | 1997-09-09 | International Business Machines Corporation | Method and means for managing linear mapped address spaces storing compressed data at the storage subsystem control unit or device level |
US5530705A (en) | 1995-02-08 | 1996-06-25 | International Business Machines Corporation | Soft error recovery system and method |
US5765185A (en) | 1995-03-17 | 1998-06-09 | Atmel Corporation | EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles |
US6016560A (en) | 1995-06-14 | 2000-01-18 | Hitachi, Ltd. | Semiconductor memory, memory device, and memory card |
US20040199714A1 (en) | 1995-07-31 | 2004-10-07 | Petro Estakhri | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
US20020024846A1 (en) | 1996-09-30 | 2002-02-28 | Takayuki Kawahara | Semiconductor integrated circuit and data processing system |
US5943692A (en) | 1997-04-30 | 1999-08-24 | International Business Machines Corporation | Mobile client computer system with flash memory management utilizing a virtual address map and variable length data |
US6000006A (en) | 1997-08-25 | 1999-12-07 | Bit Microsystems, Inc. | Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage |
US5982664A (en) | 1997-10-22 | 1999-11-09 | Oki Electric Industry Co., Ltd. | Semiconductor memory capable of writing and reading data |
US6018304A (en) | 1997-12-18 | 2000-01-25 | Texas Instruments Incorporated | Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability |
US6070074A (en) | 1998-04-24 | 2000-05-30 | Trw Inc. | Method for enhancing the performance of a regenerative satellite communications system |
US6138261A (en) | 1998-04-29 | 2000-10-24 | Trw Inc. | Concatenated coding system for satellite communications |
US6182264B1 (en) | 1998-05-22 | 2001-01-30 | Vlsi Technology, Inc. | Smart dynamic selection of error correction methods for DECT based data services |
US7111293B1 (en) | 1998-06-03 | 2006-09-19 | Ants Software, Inc. | Method for increased concurrency in a computer system |
US6192092B1 (en) | 1998-06-15 | 2001-02-20 | Intel Corp. | Method and apparatus for clock skew compensation |
US20040073829A1 (en) | 1998-07-16 | 2004-04-15 | Olarig Sompong P. | Fail-over of multiple memory blocks in multiple memory modules in computer system |
US6295592B1 (en) | 1998-07-31 | 2001-09-25 | Micron Technology, Inc. | Method of processing memory requests in a pipelined memory controller |
JP2002532806A (en) | 1998-12-18 | 2002-10-02 | ユニシス コーポレーション | Computer system and method for operating multiple operating systems in different partitions of a computer system so that different partitions can communicate with each other via shared memory |
US6988171B2 (en) | 1999-03-03 | 2006-01-17 | International Business Machines Corporation | Method and system for recovery of meta data in a storage controller |
US6449625B1 (en) | 1999-04-20 | 2002-09-10 | Lucent Technologies Inc. | Use of a two-way stack approach to optimize flash memory management for embedded database systems |
US6810440B2 (en) | 1999-06-09 | 2004-10-26 | Qlogic Corporation | Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter |
US20080282128A1 (en) | 1999-08-04 | 2008-11-13 | Super Talent Electronics, Inc. | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance |
US6412042B1 (en) | 1999-11-17 | 2002-06-25 | Maxtor Corporation | System and method for improved disk drive performance and reliability |
US6484224B1 (en) | 1999-11-29 | 2002-11-19 | Cisco Technology Inc. | Multi-interface symmetric multiprocessor |
US6842436B2 (en) | 1999-12-17 | 2005-01-11 | Siemens Aktiengesellschaft | Multiport-RAM memory device |
US20070201274A1 (en) | 2000-01-06 | 2007-08-30 | Super Talent Electronics Inc. | Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory |
US20020152305A1 (en) | 2000-03-03 | 2002-10-17 | Jackson Gregory J. | Systems and methods for resource utilization analysis in information management environments |
US6516437B1 (en) | 2000-03-07 | 2003-02-04 | General Electric Company | Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates |
US20030188045A1 (en) | 2000-04-13 | 2003-10-02 | Jacobson Michael B. | System and method for distributing storage controller tasks |
US20070133312A1 (en) | 2000-05-10 | 2007-06-14 | Micron Technology, Inc. | Flash with consistent latency for read operations |
US6678788B1 (en) | 2000-05-26 | 2004-01-13 | Emc Corporation | Data type and topological data categorization and ordering for a mass storage system |
US6442076B1 (en) | 2000-06-30 | 2002-08-27 | Micron Technology, Inc. | Flash memory with multiple status reading capability |
US6980985B1 (en) | 2000-08-30 | 2005-12-27 | At&T Corp. | Distributed evalulation of directory queries using a topology cache |
US7028165B2 (en) | 2000-12-06 | 2006-04-11 | Intel Corporation | Processor stalling |
US20020083299A1 (en) | 2000-12-22 | 2002-06-27 | International Business Machines Corporation | High speed remote storage controller |
US6775792B2 (en) | 2001-01-29 | 2004-08-10 | Snap Appliance, Inc. | Discrete mapping of parity blocks |
US20020162075A1 (en) | 2001-04-30 | 2002-10-31 | Talagala Nisha D. | Storage array employing scrubbing operations at the disk-controller level |
US20020165896A1 (en) | 2001-05-02 | 2002-11-07 | Kim Jason Seung-Min | Multiprocessor communication system and method |
US6757768B1 (en) | 2001-05-17 | 2004-06-29 | Cisco Technology, Inc. | Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node |
US7184446B2 (en) | 2001-07-06 | 2007-02-27 | Juniper Networks, Inc. | Cross-bar switch employing a multiple entry point FIFO |
US20030043829A1 (en) | 2001-07-06 | 2003-03-06 | Abbas Rashid | Cross-bar switch employing a multiple entry point FIFO |
US20070208901A1 (en) | 2001-07-11 | 2007-09-06 | Purcell Stephen C | Layered crossbar for interconnection of multiple processors and shared memories |
US6836815B1 (en) | 2001-07-11 | 2004-12-28 | Pasternak Solutions Llc | Layered crossbar for interconnection of multiple processors and shared memories |
US7529466B2 (en) | 2001-08-06 | 2009-05-05 | Sony Corporation | Signal processing method and signal processing apparatus |
US20040024957A1 (en) | 2001-08-07 | 2004-02-05 | Chun-Hung Lin | Window-based flash memory storage system and management and access methods thereof |
US20030041299A1 (en) | 2001-08-23 | 2003-02-27 | Fujitsu Limited | Memory controller for multilevel cell memory |
US20060085671A1 (en) | 2001-09-28 | 2006-04-20 | Tim Majni | Error indication in a raid memory system |
US20030088805A1 (en) | 2001-09-28 | 2003-05-08 | Tim Majni | Error indication in a raid memory system |
US7032123B2 (en) | 2001-10-19 | 2006-04-18 | Sun Microsystems, Inc. | Error recovery |
US6981205B2 (en) | 2001-10-23 | 2005-12-27 | Lenovo (Singapore) Pte Ltd | Data storage apparatus, read data processor, and read data processing method |
US20030093628A1 (en) | 2001-11-14 | 2003-05-15 | Matter Eugene P. | Memory adaptedt to provide dedicated and or shared memory to multiple processors and method therefor |
US20030198100A1 (en) | 2001-12-04 | 2003-10-23 | Hitachi, Ltd. | Method of controlling the operation of non-volatile semiconductor memory chips |
US6871257B2 (en) | 2002-02-22 | 2005-03-22 | Sandisk Corporation | Pipelined parallel programming operation in a non-volatile memory system |
US6836808B2 (en) | 2002-02-25 | 2004-12-28 | International Business Machines Corporation | Pipelined packet processing |
US20030189856A1 (en) | 2002-04-04 | 2003-10-09 | Samsung Electronics Co., Ltd. | Multi-level flash memory with temperature compensation |
US20030212719A1 (en) | 2002-05-08 | 2003-11-13 | Hitachi, Ltd. | Method for heap memory management and computer system using the same method |
US6895464B2 (en) | 2002-06-03 | 2005-05-17 | Honeywell International Inc. | Flash memory management system and method utilizing multiple block list windows |
US20040024963A1 (en) | 2002-08-05 | 2004-02-05 | Nisha Talagala | Method and system for striping data to accommodate integrity metadata |
US6978343B1 (en) | 2002-08-05 | 2005-12-20 | Netlogic Microsystems, Inc. | Error-correcting content addressable memory |
US20040153902A1 (en) | 2003-01-21 | 2004-08-05 | Nexflash Technologies, Inc. | Serial flash integrated circuit having error detection and correction |
US7043505B1 (en) | 2003-01-28 | 2006-05-09 | Unisys Corporation | Method variation for collecting stability data from proprietary systems |
US7162678B2 (en) | 2003-03-14 | 2007-01-09 | Quantum Corporation | Extended error correction codes |
US20040181734A1 (en) | 2003-03-14 | 2004-09-16 | Saliba George A. | Extended error correction codes |
EP1465203A1 (en) | 2003-04-03 | 2004-10-06 | Samsung Electronics Co., Ltd. | Nonvolatile memory with page copy capability and method thereof |
US20080163030A1 (en) | 2003-04-03 | 2008-07-03 | Samsung Electronics Co., Ltd. | Nonvolatile memory with error correction for page copy operation and method thereof |
US7527466B2 (en) | 2003-04-03 | 2009-05-05 | Simmons Robert J | Building-erection structural member transporter |
US7516292B2 (en) | 2003-05-09 | 2009-04-07 | Fujitsu Limited | Method for predicting and avoiding danger in execution environment |
US20040237018A1 (en) | 2003-05-23 | 2004-11-25 | Riley Dwight D. | Dual decode scheme |
US20070277036A1 (en) | 2003-05-23 | 2007-11-29 | Washington University, A Corporation Of The State Of Missouri | Intelligent data storage and processing using fpga devices |
US20060136570A1 (en) | 2003-06-10 | 2006-06-22 | Pandya Ashish A | Runtime adaptable search processor |
US20050060501A1 (en) | 2003-09-16 | 2005-03-17 | Denali Software, Inc. | Port independent data transaction interface for multi-port devices |
US20050060456A1 (en) | 2003-09-16 | 2005-03-17 | Denali Software, Inc. | Method and apparatus for multi-port memory controller |
US7100002B2 (en) | 2003-09-16 | 2006-08-29 | Denali Software, Inc. | Port independent data transaction interface for multi-port devices |
US7523157B2 (en) | 2003-09-25 | 2009-04-21 | International Business Machines Corporation | Managing a plurality of processors as devices |
US7173852B2 (en) | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
US20060039196A1 (en) | 2003-10-03 | 2006-02-23 | Gorobets Sergey A | Corrected data storage and handling methods |
US20050114587A1 (en) | 2003-11-22 | 2005-05-26 | Super Talent Electronics Inc. | ExpressCard with On-Card Flash Memory with Shared Flash-Control Bus but Separate Ready Lines |
US20090037652A1 (en) | 2003-12-02 | 2009-02-05 | Super Talent Electronics Inc. | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules |
US20050231765A1 (en) | 2003-12-16 | 2005-10-20 | Matsushita Electric Industrial Co., Ltd. | Information recording medium, data processing apparatus and data processing method |
US20080229176A1 (en) | 2003-12-22 | 2008-09-18 | International Business Machines Corporation | Method for fast ecc memory testing by software including ecc check byte |
US7328377B1 (en) | 2004-01-27 | 2008-02-05 | Altera Corporation | Error correction for programmable logic integrated circuits |
US20070011413A1 (en) | 2004-01-29 | 2007-01-11 | Yusuke Nonaka | Storage system having a plurality of interfaces |
US20050172207A1 (en) | 2004-01-30 | 2005-08-04 | Radke William H. | Error detection and correction scheme for a memory device |
US20050172065A1 (en) | 2004-01-30 | 2005-08-04 | Micron Technology, Inc. | Data move method and apparatus |
US20050193161A1 (en) | 2004-02-26 | 2005-09-01 | Lee Charles C. | System and method for controlling flash memory |
US20080147964A1 (en) | 2004-02-26 | 2008-06-19 | Chow David Q | Using various flash memory cells to build usb data flash cards with multiple partitions and autorun function |
US20050201148A1 (en) | 2004-03-12 | 2005-09-15 | Super Talent Electronics, Inc. | Flash memory device and architecture with multi level cells |
US7020017B2 (en) | 2004-04-06 | 2006-03-28 | Sandisk Corporation | Variable programming of non-volatile memory |
US20050257120A1 (en) | 2004-05-13 | 2005-11-17 | Gorobets Sergey A | Pipelined data relocation and improved chip architectures |
US20050273560A1 (en) | 2004-06-03 | 2005-12-08 | Hulbert Jared E | Method and apparatus to avoid incoherency between a cache memory and flash memory |
US20080148124A1 (en) | 2004-06-04 | 2008-06-19 | Yan Zhang | Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems |
US20050289314A1 (en) | 2004-06-23 | 2005-12-29 | Adusumilli Vijaya P | Simultaneous external read operation during internal programming in a flash memory device |
US20060039227A1 (en) | 2004-08-17 | 2006-02-23 | Lawrence Lai | Memory device having staggered memory operations |
US20060053246A1 (en) | 2004-08-30 | 2006-03-09 | Lee Schweiray J | Systems and methods for providing nonvolatile memory management in wireless phones |
US20060087893A1 (en) | 2004-10-27 | 2006-04-27 | Sony Corporation | Storage device and information processing system |
US20060156177A1 (en) | 2004-12-29 | 2006-07-13 | Sailesh Kottapalli | Method and apparatus for recovering from soft errors in register files |
US20060195650A1 (en) | 2005-02-25 | 2006-08-31 | Su Zhiqiang J | Method to detect NAND-flash parameters by hardware automatically |
US20060259528A1 (en) | 2005-05-13 | 2006-11-16 | Microsoft Corporation | Implementation for collecting unmanaged memory |
US20070061597A1 (en) | 2005-09-14 | 2007-03-15 | Micky Holtzman | Secure yet flexible system architecture for secure devices with flash mass storage memory |
US20090207660A1 (en) | 2005-09-15 | 2009-08-20 | Hynix Semiconductor Inc. | Program method of flash memory device |
US20070058446A1 (en) | 2005-09-15 | 2007-03-15 | Hynix Semiconductor Inc. | Erase and Program Method of Flash Memory Device for Increasing Program Speed of Flash Memory Device |
WO2007036834A2 (en) | 2005-09-27 | 2007-04-05 | Nxp B.V. | Error detection / correction circuit and corresponding method |
US20070076479A1 (en) | 2005-09-30 | 2007-04-05 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
US20070081408A1 (en) | 2005-10-06 | 2007-04-12 | Oh Suk Kwon | Multi-chip semiconductor memory device having internal power supply voltage generation circuit for decreasing current consumption |
US20070083697A1 (en) | 2005-10-07 | 2007-04-12 | Microsoft Corporation | Flash memory management |
US20080144371A1 (en) | 2005-10-12 | 2008-06-19 | Macronix International Co., Ltd. | Systems and methods for programming a memory device |
US20070091677A1 (en) | 2005-10-25 | 2007-04-26 | M-Systems Flash Disk Pioneers Ltd. | Method for recovering from errors in flash memory |
US8006161B2 (en) | 2005-10-26 | 2011-08-23 | Samsung Electronics Co., Ltd | Apparatus and method for receiving signal in a communication system using a low density parity check code |
US7954041B2 (en) | 2005-10-31 | 2011-05-31 | Samsung Electronics Co., Ltd | Apparatus and method for transmitting/receiving a signal in a communication system using a low density parity check code |
US20080270680A1 (en) | 2005-11-17 | 2008-10-30 | Chee Keng Chang | Controller for Non-Volatile Memories and Methods of Operating the Memory Controller |
US20070113019A1 (en) | 2005-11-17 | 2007-05-17 | International Business Machines Corporation | Fast path memory read request processing in a multi-level memory architecture |
US20070157064A1 (en) | 2005-12-27 | 2007-07-05 | D.S.P. Group Ltd. | Systems and methods for error corrections |
US20070150790A1 (en) | 2005-12-27 | 2007-06-28 | Gross Stephen J | Method of storing downloadable firmware on bulk media |
US20070147113A1 (en) | 2005-12-28 | 2007-06-28 | Nima Mokhlesi | Alternate sensing techniques for non-volatile memories |
WO2007080586A2 (en) | 2006-01-10 | 2007-07-19 | Saifun Semiconductors Ltd. | Rd algorithm improvement for nrom technology |
US7774390B2 (en) | 2006-01-20 | 2010-08-10 | Samsung Electronics Co., Ltd. | Apparatus for collecting garbage block of nonvolatile memory according to power state and method of collecting the same |
US20070174579A1 (en) | 2006-01-20 | 2007-07-26 | Samsung Electronics Co., Ltd. | Apparatus for collecting garbage block of nonvolatile memory according to power state and method of collecting the same |
US20070234143A1 (en) | 2006-01-25 | 2007-10-04 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices |
US20070180188A1 (en) | 2006-02-02 | 2007-08-02 | Akira Fujibayashi | Virtual path storage system and control method for the same |
US7681106B2 (en) | 2006-03-29 | 2010-03-16 | Freescale Semiconductor, Inc. | Error correction device and methods thereof |
US20110231600A1 (en) | 2006-03-29 | 2011-09-22 | Hitachi, Ltd. | Storage System Comprising Flash Memory Modules Subject to Two Wear - Leveling Process |
US20070245061A1 (en) | 2006-04-13 | 2007-10-18 | Intel Corporation | Multiplexing a parallel bus interface and a flash memory interface |
US7685494B1 (en) | 2006-05-08 | 2010-03-23 | Marvell International, Ltd. | Error correction coding for varying signal-to-noise ratio channels |
US7707481B2 (en) | 2006-05-16 | 2010-04-27 | Pitney Bowes Inc. | System and method for efficient uncorrectable error detection in flash memory |
US20070300130A1 (en) | 2006-05-17 | 2007-12-27 | Sandisk Corporation | Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices |
US20070279988A1 (en) | 2006-05-17 | 2007-12-06 | Micron Technology, Inc. | Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices |
US20070294496A1 (en) | 2006-06-19 | 2007-12-20 | Texas Instruments Incorporated | Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices |
US20070291556A1 (en) | 2006-06-19 | 2007-12-20 | Teruhiko Kamei | Programming Differently Sized Margins and Sensing with Compensations at Select States for Improved Read Operations in Non-Volatile Memory |
US7574554B2 (en) | 2006-06-28 | 2009-08-11 | Hitachi, Ltd. | Storage system and data protection method therefor |
US20080022163A1 (en) | 2006-06-28 | 2008-01-24 | Hitachi, Ltd. | Storage system and data protection method therefor |
US20100262889A1 (en) | 2006-06-30 | 2010-10-14 | Bains Kuljit S | Reliability, availability, and serviceability in a memory device |
US20080019182A1 (en) | 2006-07-20 | 2008-01-24 | Kosuke Yanagidaira | Semiconductor memory device and control method of the same |
US8069390B2 (en) | 2006-07-25 | 2011-11-29 | Commuications Coding Corporation | Universal error control coding scheme for digital communication and data storage systems |
US20080077937A1 (en) | 2006-07-28 | 2008-03-27 | Samsung Electronics Co., Ltd. | Multipath accessible semiconductor memory device with host interface between processors |
US7870326B2 (en) | 2006-07-28 | 2011-01-11 | Samsung Electronics Co., Ltd. | Multiprocessor system and method thereof |
US20080052446A1 (en) | 2006-08-28 | 2008-02-28 | Sandisk Il Ltd. | Logical super block mapping for NAND flash memory |
US20080056005A1 (en) | 2006-08-30 | 2008-03-06 | Micron Technology, Inc. | Non-volatile memory cell read failure reduction |
US7974368B2 (en) | 2006-09-25 | 2011-07-05 | Sunplus Technology Co., Ltd. | Decoding method and system for real-time wireless channel estimation |
US20080077841A1 (en) | 2006-09-27 | 2008-03-27 | Gonzalez Carlos J | Methods of Cell Population Distribution Assisted Read Margining |
US20080086677A1 (en) | 2006-10-10 | 2008-04-10 | Xueshi Yang | Adaptive systems and methods for storing and retrieving data to and from memory cells |
US7571277B2 (en) | 2006-11-06 | 2009-08-04 | Hitachi, Ltd. | Semiconductor memory system for flash memory |
US7925960B2 (en) | 2006-11-07 | 2011-04-12 | Macronix International Co., Ltd. | Memory and method for checking reading errors thereof |
US20090125671A1 (en) | 2006-12-06 | 2009-05-14 | David Flynn | Apparatus, system, and method for storage space recovery after reaching a read count limit |
US8190967B2 (en) | 2006-12-08 | 2012-05-29 | Samsung Electronics Co., Ltd. | Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method |
US20080147998A1 (en) | 2006-12-18 | 2008-06-19 | Samsung Electronics Co., Ltd. | Method and apparatus for detecting static data area, wear-leveling, and merging data units in nonvolatile data storage device |
US20080168319A1 (en) | 2007-01-08 | 2008-07-10 | Samsung Electronics Co., Ltd. | Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems |
US20080168191A1 (en) | 2007-01-10 | 2008-07-10 | Giora Biran | Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device |
US7840762B2 (en) | 2007-01-17 | 2010-11-23 | Samsung Electronics Co., Ltd | Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof |
US20080170460A1 (en) | 2007-01-17 | 2008-07-17 | Samsung Electronics Co., Ltd | Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof |
US7596643B2 (en) | 2007-02-07 | 2009-09-29 | Siliconsystems, Inc. | Storage subsystem with configurable buffer |
US7913022B1 (en) | 2007-02-14 | 2011-03-22 | Xilinx, Inc. | Port interface modules (PIMs) in a multi-port memory controller (MPMC) |
US20100091535A1 (en) | 2007-03-12 | 2010-04-15 | Anobit Technologies Ltd | Adaptive estimation of memory cell read thresholds |
US20080229000A1 (en) | 2007-03-12 | 2008-09-18 | Samsung Electronics Co., Ltd. | Flash memory device and memory system |
US7761655B2 (en) | 2007-03-15 | 2010-07-20 | Hitachi, Ltd. | Storage system and method of preventing deterioration of write performance in storage system |
US20080229003A1 (en) | 2007-03-15 | 2008-09-18 | Nagamasa Mizushima | Storage system and method of preventing deterioration of write performance in storage system |
US7890818B2 (en) | 2007-03-28 | 2011-02-15 | Samsung Electronics Co., Ltd. | Read level control apparatuses and methods |
WO2008121553A1 (en) | 2007-03-29 | 2008-10-09 | Sandisk Corporation | Non-volatile storage with decoding of data using reliability metrics based on multiple reads |
WO2008121577A1 (en) | 2007-03-31 | 2008-10-09 | Sandisk Corporation | Soft bit data transmission for error correction control in non-volatile memory |
US8032724B1 (en) | 2007-04-04 | 2011-10-04 | Marvell International Ltd. | Demand-driven opportunistic garbage collection in memory components |
US7996642B1 (en) | 2007-04-25 | 2011-08-09 | Marvell International Ltd. | Digital locked loop on channel tagged memory requests for memory optimization |
EP1990921A2 (en) | 2007-05-07 | 2008-11-12 | Broadcom Corporation | Operational parameter adaptable LDPC (low density parity check) decoder |
US20080285351A1 (en) | 2007-05-14 | 2008-11-20 | Mark Shlick | Measuring threshold voltage distribution in memory using an aggregate characteristic |
US20080313132A1 (en) * | 2007-06-15 | 2008-12-18 | Fang Hao | High accuracy bloom filter using partitioned hashing |
US20090003058A1 (en) | 2007-06-28 | 2009-01-01 | Samsung Electronics Co., Ltd. | Flash memory device and method for adjusting read voltage of flash memory device |
WO2009028281A1 (en) | 2007-08-31 | 2009-03-05 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of controlling the same |
WO2009032945A1 (en) | 2007-09-06 | 2009-03-12 | Siliconsystems, Inc. | Storage subsystem capable of adjusting ecc settings based on monitored conditions |
WO2009058140A1 (en) | 2007-10-31 | 2009-05-07 | Agere Systems Inc. | Systematic error correction for multi-level flash memory |
US20090144598A1 (en) | 2007-11-30 | 2009-06-04 | Tony Yoon | Error correcting code predication system and method |
US20090172258A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc | Flash memory controller garbage collection operations performed independently in multiple flash memory groups |
US20090172308A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories |
US7934052B2 (en) | 2007-12-27 | 2011-04-26 | Pliant Technology, Inc. | System and method for performing host initiated mass storage commands using a hierarchy of data structures |
US20090172499A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Patrol function used in flash storage controller to detect data errors |
US7978516B2 (en) | 2007-12-27 | 2011-07-12 | Pliant Technology, Inc. | Flash memory controller having reduced pinout |
US20090172262A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Metadata rebuild in a flash memory controller following a loss of power |
US20090168525A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Flash memory controller having reduced pinout |
US20090172259A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Mass storage controller volatile memory containing metadata related to flash memory storage |
US20090172261A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Multiprocessor storage controller |
US20090172260A1 (en) | 2007-12-27 | 2009-07-02 | Pliant Technology, Inc. | Flash memory controller and system including data pipelines incorporating multiple buffers |
US20100037012A1 (en) | 2007-12-28 | 2010-02-11 | Hirokuni Yano | Semiconductor Storage Device, Method of Controlling the Same, Controller and Information Processing Apparatus |
WO2009084724A1 (en) | 2007-12-28 | 2009-07-09 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20090172335A1 (en) | 2007-12-31 | 2009-07-02 | Anand Krishnamurthi Kulkarni | Flash devices with raid |
US20120195126A1 (en) | 2008-01-22 | 2012-08-02 | Micron Technology, Inc. | Cell operation monitoring |
US20090193058A1 (en) | 2008-01-29 | 2009-07-30 | Denali Software, Inc. | System and method for providing copyback data integrity in a non-volatile memory system |
US7971112B2 (en) | 2008-02-05 | 2011-06-28 | Fujitsu Limited | Memory diagnosis method |
US20090222708A1 (en) | 2008-03-01 | 2009-09-03 | Kabushiki Kaisha Toshiba | Error correcting device and error correcting method |
US20090228761A1 (en) | 2008-03-07 | 2009-09-10 | Anobit Technologies Ltd | Efficient readout from analog memory cells using data compression |
WO2009134576A1 (en) | 2008-04-30 | 2009-11-05 | Apple Inc. | Copyback optimization for memory system |
US20090292972A1 (en) | 2008-05-23 | 2009-11-26 | Samsung Electronics Co., Ltd. | Error correction apparatus, method thereof and memory device comprising the apparatus |
US20090296466A1 (en) | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20090296486A1 (en) | 2008-05-28 | 2009-12-03 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20120284587A1 (en) | 2008-06-18 | 2012-11-08 | Super Talent Electronics, Inc. | Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear |
US20090319864A1 (en) | 2008-06-20 | 2009-12-24 | Denali Software, Inc. | Method and apparatus for dynamically configurable multi level error correction |
US20100002506A1 (en) | 2008-07-04 | 2010-01-07 | Samsung Electronics Co., Ltd. | Memory device and memory programming method |
US20100061151A1 (en) | 2008-09-11 | 2010-03-11 | Toru Miwa | Multi-pass programming for memory with reduced data storage requirement |
US20100103737A1 (en) | 2008-10-28 | 2010-04-29 | Ki Tae Park | Read Compensation Circuits and Apparatus Using Same |
US8254181B2 (en) | 2008-11-24 | 2012-08-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and programming method |
US20100161936A1 (en) | 2008-12-22 | 2010-06-24 | Robert Royer | Method and system for queuing transfers of multiple non-contiguous address ranges with a single command |
US20100199125A1 (en) | 2009-02-04 | 2010-08-05 | Micron Technology, Inc. | Systems and Methods for Storing and Recovering Controller Data in Non-Volatile Memory Devices |
US20100202196A1 (en) | 2009-02-06 | 2010-08-12 | Sang Kyu Lee | Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method |
US20100208521A1 (en) | 2009-02-17 | 2010-08-19 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8042011B2 (en) | 2009-04-28 | 2011-10-18 | Synopsys, Inc. | Runtime programmable BIST for testing a multi-port memory device |
US20100281342A1 (en) | 2009-04-30 | 2010-11-04 | Samsung Electronics Co., Ltd. | Memory controller and memory system |
US20100281207A1 (en) | 2009-04-30 | 2010-11-04 | Miller Steven C | Flash-based data archive storage system |
US8412985B1 (en) | 2009-06-30 | 2013-04-02 | Micron Technology, Inc. | Hardwired remapped memory |
US20110213920A1 (en) | 2009-08-11 | 2011-09-01 | Texas Memory Systems, Inc. | FLASH-based Memory System with Static or Variable Length Page Stripes Including Data Protection Information and Auxiliary Protection Stripes |
US20110173378A1 (en) | 2009-08-24 | 2011-07-14 | Ocz Technology Group, Inc. | Computer system with backup function and method therefor |
US20110051513A1 (en) | 2009-08-25 | 2011-03-03 | Micron Technology, Inc. | Methods, devices, and systems for dealing with threshold voltage change in memory devices |
WO2011024015A1 (en) | 2009-08-25 | 2011-03-03 | Sandisk Il Ltd. | Restoring data into a flash storage device |
US20110083060A1 (en) | 2009-10-05 | 2011-04-07 | Kabushiki Kaisha Toshiba | Memory system and control method for the same |
US8312349B2 (en) | 2009-10-27 | 2012-11-13 | Micron Technology, Inc. | Error detection/correction based memory management |
US20110113281A1 (en) | 2009-11-12 | 2011-05-12 | Via Technologies, Inc. | Data storage system and method |
US20110131444A1 (en) | 2009-12-02 | 2011-06-02 | Seagate Technology Llc | Systems and methods for low wear operation of solid state memory |
US20110199825A1 (en) | 2010-02-17 | 2011-08-18 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, operating method thereof, and memory system including the same |
US20110205823A1 (en) | 2010-02-19 | 2011-08-25 | Gerrit Jan Hemink | Non-Volatile Storage With Temperature Compensation Based On Neighbor State Information |
US20110228601A1 (en) | 2010-03-17 | 2011-09-22 | Olbrich Aaron K | Mlc self-raid flash data protection scheme |
US20120239976A1 (en) | 2010-07-09 | 2012-09-20 | Stec, Inc. | Apparatus and method for determining a read level of a flash memory after an inactive period of time |
US20120096217A1 (en) | 2010-10-15 | 2012-04-19 | Kyquang Son | File system-aware solid-state storage management system |
US20120110250A1 (en) | 2010-11-03 | 2012-05-03 | Densbits Technologies Ltd. | Meethod, system and computer readable medium for copy back |
US20120151124A1 (en) | 2010-12-08 | 2012-06-14 | Sung Hoon Baek | Non-Volatile Memory Device, Devices Having the Same, and Method of Operating the Same |
US20120151294A1 (en) | 2010-12-09 | 2012-06-14 | Samsung Electronics Co., Ltd. | Method and apparatus for correcting errors in memory device |
US20120151253A1 (en) | 2010-12-14 | 2012-06-14 | Western Digital Technologies, Inc. | System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss |
US20130036418A1 (en) * | 2010-12-22 | 2013-02-07 | Vmware, Inc. | In-Place Snapshots of a Virtual Disk Configured with Sparse Extent |
US20130179646A1 (en) | 2012-01-10 | 2013-07-11 | Sony Corporation | Storage control device, storage device, and control method for controlling storage control device |
US20140095775A1 (en) | 2012-01-12 | 2014-04-03 | Fusion-io-Inc. | Systems and methods for cache endurance |
US20130343131A1 (en) | 2012-06-26 | 2013-12-26 | Lsi Corporation | Fast tracking for flash channels |
US20140122818A1 (en) * | 2012-10-31 | 2014-05-01 | Hitachi Computer Peripherals Co., Ltd. | Storage apparatus and method for controlling storage apparatus |
US20140143505A1 (en) * | 2012-11-19 | 2014-05-22 | Advanced Micro Devices, Inc. | Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode |
Non-Patent Citations (40)
Title |
---|
Barr, Introduction to Watchdog Timers, Oct. 2001, 3 pgs. |
Canim, Buffered Bloom ilters on Solid State Storage, ADMS* 10, Singapore, Sep. 13-17, 2010, 8 pgs. |
International Search Report and Written Opinion dated Jul. 25, 2014, received in International Patent Application No. PCT/US2014/029453, which corresponds to U.S. Appl. No. 13/963,444, 9 pages (Frayer). |
International Search Report and Written Opinion dated Mar. 24, 2014, received in International Patent Application No. PCT/US2013/074777, which corresponds to U.S. Appl. No. 13/831,308, 10 pages (George). |
International Search Report and Written Opinion dated Mar. 7, 2014, received in International Patent Application No. PCT/US2013/074772, which corresponds to U.S. Appl. No. 13/831,218, 10 pages (George). |
International Search Report and Written Opinion dated Mar. 7, 2014, received in International Patent Application No. PCT/US2013/074779, which corresponds to U.S. Appl. No. 13/831,374, 8 pages (George). |
Kang, A Multi-Channel Architecture for High-Performance NAND Flash-Based Storage System, J. Syst. Archit., 53, 9, Sep. 2007, 15 pgs. |
Kim, A Space-Efficient Flash Translation Layer for CompactFlash Systems, May 2002, 10 pgs. |
Lu, A Forest-structured Bloom Filter with Flash Memory, MSST 2011, Denver, CO, May 23-27, 2011, article, 6 pgs. |
Lu, A Forest-structured Bloom Filter with Flash Memory, MSST 2011, Denver, CO, May 23-27, 2011, presentation slides, 25 pgs. |
McLean, Information Technology-AT Attachment with Packet Interface Extension, Aug. 19, 1998, 339 pgs. |
McLean, Information Technology—AT Attachment with Packet Interface Extension, Aug. 19, 1998, 339 pgs. |
Park, A High Performance Controller for NAND Flash-Based Solid State Disk (NSSD), Feb. 12 16, 2006, 4 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88133, Mar. 19, 2009, 7 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88136, Mar. 19, 2009, 7 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88146, Feb. 26, 2009, 10 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88154, Feb. 27, 2009, 8 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88164, Feb. 13, 2009, 6 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88206, Feb. 18, 2009, 8 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88217, Feb. 19, 2009, 7 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88229, Feb. 13, 2009, 7 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88232, Feb. 19, 2009, 8 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US08/88236, Feb. 19, 2009, 7 pgs. |
Pliant Technology, International Search Report / Written Opinion, PCT/US2011/028637, Oct. 27, 2011, 11 pgs. |
Pliant Technology, Supplementary ESR, 08866997.3, Feb. 23, 2012, 6 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/042764, Aug. 31, 2012, 12 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/042771, Mar. 4, 2013, 14 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/042775, Sep. 26, 2012, 8 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/059447, Jun. 6, 2013, 12 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/059453, Jun. 6, 2013, 12 pgs. |
Sandisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/059459, Feb. 14, 2013, 9 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/065914, May 23, 2013, 7 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/065916, Apr. 5, 2013, 7 pgs. |
SanDisk Enterprise IP LLC, International Search Report / Written Opinion, PCT/US2012/065919, Jun. 17, 2013, 8 pgs. |
SanDisk Enterprise IP LLC, Notification of the Decision to Grant a Patent Right for Patent for Invention, CN 200880127623.8, Jul. 4, 2013, 1 pg. |
SanDisk Enterprise IP LLC, Office Action, CN 200880127623.8, Apr. 18, 2012, 12 pgs. |
SanDisk Enterprise IP LLC, Office Action, CN 200880127623.8, Dec. 31, 2012, 9 pgs. |
SanDisk Enterprise IP LLC, Office Action, JP 2010-540863, Jul. 24 2012, 3 pgs. |
Watchdog Timer and Power Savin Modes, Microchip Technology Inc., 2005, 14 pgs. |
Zeidman, 1999 Verilog Designer's Library, 9 pgs. |
Cited By (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9448743B2 (en) | 2007-12-27 | 2016-09-20 | Sandisk Technologies Llc | Mass storage controller volatile memory containing metadata related to flash memory storage |
US9483210B2 (en) | 2007-12-27 | 2016-11-01 | Sandisk Technologies Llc | Flash storage controller execute loop |
US9699263B1 (en) | 2012-08-17 | 2017-07-04 | Sandisk Technologies Llc. | Automatic read and write acceleration of data accessed by virtual machines |
US9612948B2 (en) | 2012-12-27 | 2017-04-04 | Sandisk Technologies Llc | Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device |
US9454420B1 (en) | 2012-12-31 | 2016-09-27 | Sandisk Technologies Llc | Method and system of reading threshold voltage equalization |
US9870830B1 (en) | 2013-03-14 | 2018-01-16 | Sandisk Technologies Llc | Optimal multilevel sensing for reading data from a storage medium |
US9367246B2 (en) | 2013-03-15 | 2016-06-14 | Sandisk Technologies Inc. | Performance optimization of data transfer for soft information generation |
US9524235B1 (en) | 2013-07-25 | 2016-12-20 | Sandisk Technologies Llc | Local hash value generation in non-volatile data storage systems |
US9384126B1 (en) * | 2013-07-25 | 2016-07-05 | Sandisk Technologies Inc. | Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems |
US9361221B1 (en) | 2013-08-26 | 2016-06-07 | Sandisk Technologies Inc. | Write amplification reduction through reliable writes during garbage collection |
US9639463B1 (en) | 2013-08-26 | 2017-05-02 | Sandisk Technologies Llc | Heuristic aware garbage collection scheme in storage systems |
US9442662B2 (en) | 2013-10-18 | 2016-09-13 | Sandisk Technologies Llc | Device and method for managing die groups |
US9436831B2 (en) | 2013-10-30 | 2016-09-06 | Sandisk Technologies Llc | Secure erase in a memory device |
US9703816B2 (en) | 2013-11-19 | 2017-07-11 | Sandisk Technologies Llc | Method and system for forward reference logging in a persistent datastore |
US9520197B2 (en) | 2013-11-22 | 2016-12-13 | Sandisk Technologies Llc | Adaptive erase of a storage device |
US9520162B2 (en) | 2013-11-27 | 2016-12-13 | Sandisk Technologies Llc | DIMM device controller supervisor |
US9582058B2 (en) | 2013-11-29 | 2017-02-28 | Sandisk Technologies Llc | Power inrush management of storage devices |
US9703636B2 (en) | 2014-03-01 | 2017-07-11 | Sandisk Technologies Llc | Firmware reversion trigger and control |
US9448876B2 (en) | 2014-03-19 | 2016-09-20 | Sandisk Technologies Llc | Fault detection and prediction in storage devices |
US9454448B2 (en) | 2014-03-19 | 2016-09-27 | Sandisk Technologies Llc | Fault testing in storage devices |
US9626399B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Conditional updates for reducing frequency of data modification operations |
US9626400B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Compaction of information in tiered data structure |
US9390021B2 (en) | 2014-03-31 | 2016-07-12 | Sandisk Technologies Llc | Efficient cache utilization in a tiered data structure |
US9697267B2 (en) | 2014-04-03 | 2017-07-04 | Sandisk Technologies Llc | Methods and systems for performing efficient snapshots in tiered data structures |
US9703491B2 (en) | 2014-05-30 | 2017-07-11 | Sandisk Technologies Llc | Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device |
US10656840B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Real-time I/O pattern recognition to enhance performance and endurance of a storage device |
US10372613B2 (en) | 2014-05-30 | 2019-08-06 | Sandisk Technologies Llc | Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device |
US10656842B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device |
US10114557B2 (en) | 2014-05-30 | 2018-10-30 | Sandisk Technologies Llc | Identification of hot regions to enhance performance and endurance of a non-volatile storage device |
US10146448B2 (en) | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
US10162748B2 (en) | 2014-05-30 | 2018-12-25 | Sandisk Technologies Llc | Prioritizing garbage collection and block allocation based on I/O history for logical address regions |
US9652381B2 (en) | 2014-06-19 | 2017-05-16 | Sandisk Technologies Llc | Sub-block garbage collection |
US9443601B2 (en) | 2014-09-08 | 2016-09-13 | Sandisk Technologies Llc | Holdup capacitor energy harvesting |
US10055351B1 (en) | 2016-06-29 | 2018-08-21 | EMC IP Holding Company LLC | Low-overhead index for a flash cache |
US11106373B2 (en) | 2016-06-29 | 2021-08-31 | EMC IP Holding Company LLC | Flash interface for processing dataset |
US11182083B2 (en) | 2016-06-29 | 2021-11-23 | EMC IP Holding Company LLC | Bloom filters in a flash memory |
US10261704B1 (en) | 2016-06-29 | 2019-04-16 | EMC IP Holding Company LLC | Linked lists in flash memory |
US10318201B2 (en) | 2016-06-29 | 2019-06-11 | EMC IP Holding Company LLC | Flash interface for processing datasets |
US10331561B1 (en) | 2016-06-29 | 2019-06-25 | Emc Corporation | Systems and methods for rebuilding a cache index |
US10353607B2 (en) * | 2016-06-29 | 2019-07-16 | EMC IP Holding Company LLC | Bloom filters in a flash memory |
US10353820B2 (en) | 2016-06-29 | 2019-07-16 | EMC IP Holding Company LLC | Low-overhead index for a flash cache |
US10146438B1 (en) | 2016-06-29 | 2018-12-04 | EMC IP Holding Company LLC | Additive library for data structures in a flash memory |
US10521123B2 (en) | 2016-06-29 | 2019-12-31 | EMC IP Holding Company LLC | Additive library for data structures in a flash memory |
US11113199B2 (en) | 2016-06-29 | 2021-09-07 | EMC IP Holding Company LLC | Low-overhead index for a flash cache |
US11106362B2 (en) | 2016-06-29 | 2021-08-31 | EMC IP Holding Company LLC | Additive library for data structures in a flash memory |
US11106586B2 (en) | 2016-06-29 | 2021-08-31 | EMC IP Holding Company LLC | Systems and methods for rebuilding a cache index |
US10089025B1 (en) * | 2016-06-29 | 2018-10-02 | EMC IP Holding Company LLC | Bloom filters in a flash memory |
US10037164B1 (en) | 2016-06-29 | 2018-07-31 | EMC IP Holding Company LLC | Flash interface for processing datasets |
US10936207B2 (en) | 2016-06-29 | 2021-03-02 | EMC IP Holding Company LLC | Linked lists in flash memory |
US20190044701A1 (en) * | 2017-08-04 | 2019-02-07 | Institute For Information Industry | Transmission apparatus, and transmission data protection method thereof |
TWI686072B (en) * | 2017-08-04 | 2020-02-21 | 財團法人資訊工業策進會 | Transmission apparatus, and transmission data protection method thereof |
US10530570B2 (en) * | 2017-08-04 | 2020-01-07 | Institute For Information Industry | Transmission apparatus, and transmission data protection method thereof |
CN109391465A (en) * | 2017-08-04 | 2019-02-26 | 财团法人资讯工业策进会 | transmission device and transmission data protection method thereof |
CN109391465B (en) * | 2017-08-04 | 2022-01-21 | 财团法人资讯工业策进会 | Transmission device and transmission data protection method thereof |
CN111159436A (en) * | 2018-11-07 | 2020-05-15 | 腾讯科技(深圳)有限公司 | Method and device for recommending multimedia content and computing equipment |
CN111159436B (en) * | 2018-11-07 | 2023-12-12 | 腾讯科技(深圳)有限公司 | Method, device and computing equipment for recommending multimedia content |
US11410727B1 (en) | 2021-03-15 | 2022-08-09 | Sandisk Technologies Llc | Scalable search system design with single level cell NAND-based binary and ternary valued content addressable memory cells |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9043517B1 (en) | Multipass programming in buffers implemented in non-volatile data storage systems | |
US9384126B1 (en) | Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems | |
US10579537B2 (en) | Memory having a static cache and a dynamic cache | |
US20210165832A1 (en) | Proactive corrective actions in memory based on a probabilistic data structure | |
US9524235B1 (en) | Local hash value generation in non-volatile data storage systems | |
US9442662B2 (en) | Device and method for managing die groups | |
US9053808B2 (en) | Flash memory with targeted read scrub algorithm | |
US20160118132A1 (en) | Low Impact Read Disturb Handling | |
US10714186B2 (en) | Method and apparatus for dynamically determining start program voltages for a memory device | |
US9639463B1 (en) | Heuristic aware garbage collection scheme in storage systems | |
US9990149B2 (en) | Memory device for internally performing read-verify operation, method of operating the same, and memory system including the same | |
US10902924B2 (en) | Memory system varying pass voltage based on erase count of target memory block and operating method thereof | |
US10324785B2 (en) | Decoder using low-density parity-check code and memory controller including the same | |
US10133645B2 (en) | Data recovery in three dimensional non-volatile memory array after word line short | |
US11373709B2 (en) | Memory system for performing a read operation and an operating method thereof | |
CN112542201A (en) | Storage device and method of operating the same | |
US20170091243A1 (en) | Reduction of Write Amplification in Object Store | |
CN115731971A (en) | Cross-die temperature management on a memory device | |
KR20130087936A (en) | Memory device, memory system and program method of the same | |
CN114579040A (en) | Apparatus and method for maintaining data stored in a memory system | |
US10817187B2 (en) | Balancing the block wearing leveling for optimum SSD endurance | |
US20200327069A1 (en) | Data storage device and operation method thereof, controller using the same | |
US20160306569A1 (en) | Memory system | |
CN116010157A (en) | Memory device and memory system for programming data | |
US20160062688A1 (en) | Flash memory device, flash memory system, and operating method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SANDISK ENTERPRISE IP LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SPROUSE, STEVEN;LI, YAN;REEL/FRAME:031553/0740 Effective date: 20130920 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK ENTERPRISE IP LLC;REEL/FRAME:038295/0225 Effective date: 20160324 |
|
AS | Assignment |
Owner name: SANDISK TECHNOLOGIES LLC, TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:SANDISK TECHNOLOGIES INC;REEL/FRAME:038807/0948 Effective date: 20160516 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |