US8679957B2 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
US8679957B2
US8679957B2 US13/602,517 US201213602517A US8679957B2 US 8679957 B2 US8679957 B2 US 8679957B2 US 201213602517 A US201213602517 A US 201213602517A US 8679957 B2 US8679957 B2 US 8679957B2
Authority
US
United States
Prior art keywords
silicon carbide
carbide substrate
implanted
ions
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US13/602,517
Other versions
US20130237042A1 (en
Inventor
Johji Nishio
Chiharu Ota
Takashi Shinohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NISHIO, JOHJI, OTA, CHIHARU, SHINOHE, TAKASHI
Publication of US20130237042A1 publication Critical patent/US20130237042A1/en
Application granted granted Critical
Publication of US8679957B2 publication Critical patent/US8679957B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments described herein relate generally to a method of manufacturing a semiconductor device.
  • Silicon carbide has been drawing attention as a suitable material of a semiconductor device for attaining a high breakdown voltage and a high current capacity.
  • a silicon carbide film is formed on a bulk silicon carbide substrate of a hexagonal system by epitaxial growth, and a pn junction region is formed in the silicon carbide film.
  • BPD basal plane dislocation
  • a device having the BPD therein is known to have an increased on-resistance when supplied with electricity.
  • the mechanism is considered to: easily disintegrate the BPD into partial dislocations with supplied electricity; and form a high-resistance layer by a stacking fault on a plane between the disintegrated partial dislocations.
  • step-flow growth of the silicon carbide film is important in order to obtain a smooth surface on an epitaxially grown film.
  • the silicon carbide substrate used for realizing satisfactory step-flow growth is usually off-cut by few degrees from a (0001) plane (a basal plane).
  • the proportion of the BPD in the substrate directly propagated into the epitaxially grown film is considered to decrease remarkably compared with the case where the substrate with the off-cut angle of 8 degrees is used. There is also a reported case where only 3% of the BPD is propagated.
  • the surface of the epitaxial film would have the BPD density of 30 cm ⁇ 2 when the BPD density in the bulk silicon carbide substrate is approximately 1000 cm ⁇ 2 .
  • FIG. 1 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device of a first embodiment
  • FIG. 2 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment
  • FIG. 3 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment
  • FIG. 4 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment
  • FIG. 5 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device of a second embodiment
  • FIG. 6 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the second embodiment
  • FIG. 7 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the second embodiment.
  • FIGS. 8A and 8B are process cross-sectional views illustrating the method of manufacturing a semiconductor device of the second embodiment.
  • a method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
  • a method of manufacturing a semiconductor device of the present embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
  • the method of manufacturing a semiconductor device of the present embodiment can suppress propagation or extension of a BPD within the silicon carbide substrate into the silicon carbide film that is an epitaxially grown film. Consequently, a semiconductor device can be manufactured in which performance deterioration caused by the BPD is prevented.
  • FIGS. 1 to 4 are process cross-sectional views illustrating the method of manufacturing a semiconductor device of the present embodiment.
  • the semiconductor device will be described with an example of a mesa-type PiN diode with a high breakdown voltage that is one kind of a silicon carbide bipolar power device.
  • a silicon carbide substrate 10 with an n + -type (0001) plane of a 4H silicon carbide bulk single crystal of a hexagonal system is prepared as shown in FIG. 1 . It is preferable that the silicon carbide substrate 10 be off-cut so that the surface thereof would have an off angle of 1 degree or greater and 8 degrees or less with respect to the (0001) plane, in terms of realizing satisfactory step-flow growth when performing epitaxial growth at a later stage.
  • ions of an impurity are implanted throughout the silicon carbide substrate 10 to form an ion-implanted region 12 .
  • phosphorus (P) that is an n-type impurity is implanted with a dose of 1 ⁇ 10 17 cm ⁇ 2 and an accelerating voltage of 380 keV.
  • This ion-implanted region 12 can suppress the propagation of the BPD within the silicon carbide substrate 10 into the epitaxial film when performing epitaxial growth at a later stage.
  • a silicon carbide film 14 is formed, by epitaxial growth, on the silicon carbide substrate 10 into which the ions have been implanted.
  • the silicon carbide film 14 includes: an n-type silicon carbide film 14 a as a drift layer; a p-type silicon carbide film 14 b as a p-type layer; and a p + -type silicon carbide film 14 c as a p-type contact layer.
  • the n-type silicon carbide film 14 a is formed by epitaxial growth in a furnace for n-type growth such that the film would have a thickness of 26 ⁇ m and a carrier concentration of 4 ⁇ 10 15 cm ⁇ 3 . Thereafter, the p-type silicon carbide film 14 b and the p + -type silicon carbide film 14 c are formed by epitaxial growth in a furnace for p-type growth.
  • An alignment mark 16 is then formed in the silicon carbide film 14 by dry etching.
  • a pattern is formed by a resist or the like with the alignment mark 16 as a fiducial mark, and a groove 18 is formed by dry etching, thereby forming a mesa-type electrode part surrounded by the groove 18 .
  • the width of the mesa-type electrode part is approximately 1 mm, for example.
  • the p-type silicon carbide film 14 b is etched so that it is entirely removed in a depth direction.
  • the depth of dry etching can be controlled by managing an etching time, for example.
  • ions of aluminum (Al) that is a p-type impurity are selectively implanted, for example.
  • a p-type layer 20 being a junction termination structure is formed as shown in FIG. 4 .
  • the implanted ionic species (the impurity) is activated by high-temperature annealing.
  • the high-temperature annealing is performed at a temperature of 1600° C. to 1900° C. under an inert gas atmosphere of argon (Ar) or the like, for example.
  • a cathode electrode 22 is formed on the back surface of the silicon carbide substrate 10 .
  • the cathode electrode 22 is formed by vapor-depositing nickel (Ni) on the entire back surface of the silicon carbide substrate 10 , sintering it, and sputtering titanium (Ti), nickel (Ni), and gold (Au) in this order, for example.
  • an anode electrode 24 is formed on the p + -type silicon carbide film 14 c serving as the p-type contact layer of the mesa-type electrode part.
  • the anode electrode 24 is formed by sputtering aluminum (Al) on the p + -type silicon carbide film 14 c and patterning thereafter, for example.
  • the mesa-type PiN diode with a high breakdown voltage of the present embodiment is formed.
  • the ion-implanted region 12 is formed by implanting ions of the impurity into the silicon carbide substrate 10 before forming the silicon carbide film 14 on the silicon carbide substrate 10 by epitaxial growth. An area including a number of dislocations or sub-boundaries is formed in this ion-implanted region, where the crystalline structure of the silicon carbide is destroyed due to damage done by the ion implantation.
  • This ion-implanted region serves as a dislocation-blocking layer for suppressing propagation of the BPD within the silicon carbide substrate 10 into the silicon carbide film 14 .
  • the BPD is terminated by the interaction between the BPD and a dislocation having a Burgers vector directed oppositely from the BPD, or a dislocation loop is formed with the sub-boundaries being the surface thereof. It is confirmed that, as a result of the above, the BPD would not be propagated into the silicon carbide film 14 that is the epitaxial film.
  • the surface of the ion-implanted region 12 be undamaged by the ion implantation as much as possible, in order to ensure epitaxial growth with superior crystallinity on the ion-implanted region 12 .
  • the ions be directly implanted into the silicon carbide substrate 10 with the surface thereof exposed, without forming a film such as an insulating film, what is called a through film, on the silicon carbide substrate 10 .
  • the ions be implanted under a condition that the impurity concentration on the surface of the silicon carbide substrate 10 right after the ion implantation would be lower by one order of magnitude or more than the maximum impurity concentration when the ion-implanted region is viewed in a depth direction.
  • the ions be implanted with a temperature of the silicon carbide substrate 10 of 100° C. or less, at which little is recovered from the damage caused by the ion implantation.
  • the ions are preferably implanted at room temperature.
  • the ion implantation at room temperature implies the ion implantation during which the silicon carbide substrate 10 is not heated.
  • the ionic species (impurity) being implanted is not particularly limited as long as it effectively causes damage to the silicon carbide substrate 10 .
  • phosphorus (P), nitrogen (N), boron (B), and aluminum (Al) can be used.
  • the ionic species with a large ionic radius and large mass such as P (phosphorus).
  • the ionic species of the conductivity type identical to that of the silicon carbide substrate 10 be implanted.
  • a dose of the ions implanted is preferably 1E15 cm ⁇ 2 or greater and 1E17 cm ⁇ 2 or less. If the dose falls below this range, the silicon carbide substrate 10 may not receive enough damage. If the dose exceeds this range, on the other hand, the ion-implanted region 12 may obstruct the device operation as the high-resistance layer, or excess damage done to the surface of the silicon carbide substrate 10 may obstruct epitaxial growth with superior crystallinity.
  • an off direction namely, a crystal orientation of the maximum angle of inclination of the silicon carbide substrate 10 with respect to the (0001) plane is preferably in a direction of ⁇ 21-30> ⁇ 5 degrees. This is to inhibit the stacking fault from being generated by the BPD propagated into the epitaxial film.
  • the off direction in the direction of ⁇ 21-30> ⁇ 5 degrees the deterioration in device characteristics due to the stacking fault generated from the BPD can be suppressed even if there exists the BPD, the propagation of which into the silicon carbide film 14 could not be obstructed by the ion-implanted region 12 .
  • a second embodiment is similar to the first embodiment except that ions are selectively implanted into the silicon carbide substrate, and that a region formed by shifting the pn junction region used for device operation by d/tan ⁇ toward an upstream side in a step-flow direction of the silicon carbide film, which is grown by epitaxial growth, is included in an ion-implanted region, where d denotes the thickness of the silicon carbide film and a denotes an off angle of the silicon carbide substrate with respect to a (0001) plane.
  • FIGS. 5 to 8B are process cross-sectional views illustrating a method of manufacturing a semiconductor device of the present embodiment.
  • a silicon carbide substrate 10 with an n + -type (0001) plane of a 4H silicon carbide bulk single crystal of a hexagonal system is prepared as shown in FIG. 5 .
  • the silicon carbide substrate 10 is off-cut so that the surface thereof would have an off angle of 1 degree or greater and 8 degrees or less with respect to the (0001) plane, for example.
  • an alignment mark 26 is formed on the silicon carbide substrate 10 by dry etching.
  • a pattern is then formed by a resistor the like with the alignment mark 26 as a fiducial mark, and ions are selectively implanted into a predetermined region of the silicon carbide substrate 10 to form an ion-implanted region 12 .
  • a silicon carbide film 14 is formed, by epitaxial growth, on the silicon carbide substrate 10 into which the ions have been implanted.
  • the silicon carbide film 14 includes: an n-type silicon carbide film 14 a as a drift layer; a p-type silicon carbide film 14 b as a p-type layer; and a p + -type silicon carbide film 14 c as a p-type contact layer.
  • an alignment mark 16 is formed in the silicon carbide film 14 by dry etching.
  • a pattern of the alignment mark 16 is formed with the alignment mark 26 as a fiducial mark.
  • the depth of the alignment mark 16 would not affect the reading and positioning even when the alignment mark 16 is formed shallower than the depth of the alignment mark 26 .
  • a pattern is formed by a resist or the like with the alignment mark 16 as the fiducial mark, and a groove 18 is formed by dry etching, thereby forming a mesa-type electrode part surrounded by the groove 18 .
  • ions of aluminum (Al) that is a p-type impurity are selectively implanted, for example.
  • Al aluminum
  • the p ⁇ -type layer 20 being the junction termination structure is formed as shown in FIG. 8 .
  • the implanted ionic species (the impurity) is activated by high-temperature annealing.
  • the cathode electrode 22 is formed on the back surface of the silicon carbide substrate 10 .
  • the anode electrode 24 is formed on the p + -type silicon carbide film 14 c serving as the p-type contact layer of the mesa-type electrode part.
  • the mesa-type PiN diode with a high breakdown voltage of the present embodiment is formed.
  • the ion-implanted region 12 would obstruct the device operation as a high-resistance layer. It is thus preferred not to form it as much as possible in a region where it is not necessary, considering the device characteristics.
  • the range of the ion-implanted region 12 is set so as to ensure, at a bare minimum, that the BPD would not geometrically reach the pn junction region even if it is propagated into the silicon carbide film 14 .
  • the ion-implanted region 12 is set to include the region formed by shifting the pn junction region used for device operation by d/tan ⁇ toward the upstream side in the step-flow direction of the silicon carbide film 14 , which is grown by epitaxial growth, where d denotes the thickness of the silicon carbide film 14 and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane.
  • FIG. 8A is a cross-sectional view of the semiconductor device of the present embodiment
  • FIG. 8B is a top view of the semiconductor device of the present embodiment.
  • A indicates the pn junction region
  • A′ indicates the region formed by shifting the pn junction region by d/tan ⁇ toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth.
  • B indicates the ion-implanted region 12 .
  • the pn junction region is the region including: the pn junction between the p-type silicon carbide film 14 b of the mesa-type electrode part and the n ⁇ -type silicon carbide film 14 a ; and the pn junction between the p ⁇ -type layer 20 and the n ⁇ -type silicon carbide film 14 a.
  • the BPD When the BPD is propagated into the silicon carbide film 14 , it is geometrically propagated in the step-flow direction or, for example, in the ⁇ 21-30> direction on the (0001) plane, in the present embodiment. Therefore, by setting the ion-implanted region 12 as described in the present embodiment, it is ensured that the BPD propagated into the silicon carbide film 14 would not reach the pn junction region.
  • the ion-implanted region 12 is formed to the minimum extent in the region considered not necessary in terms of device characteristics, in addition to the effects of the first embodiment. This can thereby prevent the ion-implanted region 12 being the high-resistance layer from possibly obstructing the device operation.
  • the pn junction region used for the device operation is shifted by d/tan ⁇ toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth, where d denotes the thickness of the silicon carbide film 14 and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane.
  • the pn junction surface is provided closer to the n ⁇ -type silicon carbide film 14 a than to the boundary surface between the p-type silicon carbide film 14 b and the n ⁇ -type silicon carbide film 14 a .
  • the BPD would not reach the pn junction region if the pn junction region used for the device operation is shifted by d′/tan ⁇ toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth, where d′ denotes the thickness of the n ⁇ -type silicon carbide film 14 a being the drift layer ( FIG. 8A ), and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane.
  • n + -type silicon carbide substrate of the 4H silicon carbide bulk single crystal as an example; however, the embodiments can also be applied to a p + -type silicon carbide substrate of a 4H silicon carbide bulk single crystal, an n + -type silicon carbide substrate of a 6H silicon carbide bulk single crystal, and a p + -type silicon carbide substrate of a 6H silicon carbide bulk single crystal, for example.
  • the embodiments have been described with an example of the mesa-type PiN diode with a high breakdown voltage as the semiconductor device; however, the embodiments can also be applied to a semiconductor device manufactured by epitaxially growing the silicon carbide film on the silicon carbide substrate of a hexagonal system.
  • the embodiments can be applied to a vertical IGBT and a MOSFET.

Abstract

A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-046503, filed on Mar. 2, 2012, the entire contents of which are incorporated herein by reference.
FIELD
Embodiments described herein relate generally to a method of manufacturing a semiconductor device.
BACKGROUND
Silicon carbide has been drawing attention as a suitable material of a semiconductor device for attaining a high breakdown voltage and a high current capacity. For example, when manufacturing a bipolar power device with a silicon carbide material, a silicon carbide film is formed on a bulk silicon carbide substrate of a hexagonal system by epitaxial growth, and a pn junction region is formed in the silicon carbide film.
There exists a dislocation referred to as a basal plane dislocation (BPD) in the silicon carbide substrate, and this BPD may be propagated or extended into the silicon carbide film formed by epitaxial growth. A device having the BPD therein is known to have an increased on-resistance when supplied with electricity. The mechanism is considered to: easily disintegrate the BPD into partial dislocations with supplied electricity; and form a high-resistance layer by a stacking fault on a plane between the disintegrated partial dislocations.
On the other hand, step-flow growth of the silicon carbide film is important in order to obtain a smooth surface on an epitaxially grown film. The silicon carbide substrate used for realizing satisfactory step-flow growth is usually off-cut by few degrees from a (0001) plane (a basal plane).
When the silicon carbide substrate with an off-cut angle of 4 degrees is used, the proportion of the BPD in the substrate directly propagated into the epitaxially grown film is considered to decrease remarkably compared with the case where the substrate with the off-cut angle of 8 degrees is used. There is also a reported case where only 3% of the BPD is propagated.
Even with this proportion, the surface of the epitaxial film would have the BPD density of 30 cm−2 when the BPD density in the bulk silicon carbide substrate is approximately 1000 cm−2. Thus, this would be a problem in terms of the manufacturing yield when a power device of a large area is to be formed for attaining high capacity.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device of a first embodiment;
FIG. 2 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment;
FIG. 3 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment;
FIG. 4 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the first embodiment;
FIG. 5 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device of a second embodiment;
FIG. 6 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the second embodiment;
FIG. 7 is a process cross-sectional view illustrating the method of manufacturing a semiconductor device of the second embodiment; and
FIGS. 8A and 8B are process cross-sectional views illustrating the method of manufacturing a semiconductor device of the second embodiment.
 DETAILED DESCRIPTION
A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
First Embodiment
A method of manufacturing a semiconductor device of the present embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
By the above configuration, the method of manufacturing a semiconductor device of the present embodiment can suppress propagation or extension of a BPD within the silicon carbide substrate into the silicon carbide film that is an epitaxially grown film. Consequently, a semiconductor device can be manufactured in which performance deterioration caused by the BPD is prevented.
FIGS. 1 to 4 are process cross-sectional views illustrating the method of manufacturing a semiconductor device of the present embodiment. In the present embodiment, the semiconductor device will be described with an example of a mesa-type PiN diode with a high breakdown voltage that is one kind of a silicon carbide bipolar power device.
First, a silicon carbide substrate 10 with an n+-type (0001) plane of a 4H silicon carbide bulk single crystal of a hexagonal system is prepared as shown in FIG. 1. It is preferable that the silicon carbide substrate 10 be off-cut so that the surface thereof would have an off angle of 1 degree or greater and 8 degrees or less with respect to the (0001) plane, in terms of realizing satisfactory step-flow growth when performing epitaxial growth at a later stage.
Then, ions of an impurity are implanted throughout the silicon carbide substrate 10 to form an ion-implanted region 12. For example, phosphorus (P) that is an n-type impurity is implanted with a dose of 1×1017 cm−2 and an accelerating voltage of 380 keV. This ion-implanted region 12 can suppress the propagation of the BPD within the silicon carbide substrate 10 into the epitaxial film when performing epitaxial growth at a later stage.
Next, as shown in FIG. 2, a silicon carbide film 14 is formed, by epitaxial growth, on the silicon carbide substrate 10 into which the ions have been implanted. The silicon carbide film 14 includes: an n-type silicon carbide film 14 a as a drift layer; a p-type silicon carbide film 14 b as a p-type layer; and a p+-type silicon carbide film 14 c as a p-type contact layer.
For example, the n-type silicon carbide film 14 a is formed by epitaxial growth in a furnace for n-type growth such that the film would have a thickness of 26 μm and a carrier concentration of 4×1015 cm−3. Thereafter, the p-type silicon carbide film 14 b and the p+-type silicon carbide film 14 c are formed by epitaxial growth in a furnace for p-type growth.
An alignment mark 16 is then formed in the silicon carbide film 14 by dry etching.
Next, as shown in FIG. 3, a pattern is formed by a resist or the like with the alignment mark 16 as a fiducial mark, and a groove 18 is formed by dry etching, thereby forming a mesa-type electrode part surrounded by the groove 18. The width of the mesa-type electrode part is approximately 1 mm, for example.
At this time, the p-type silicon carbide film 14 b is etched so that it is entirely removed in a depth direction. The depth of dry etching can be controlled by managing an etching time, for example.
Next, ions of aluminum (Al) that is a p-type impurity are selectively implanted, for example. By this ion implantation, a p-type layer 20 being a junction termination structure is formed as shown in FIG. 4.
After implanting the ions, the implanted ionic species (the impurity) is activated by high-temperature annealing. The high-temperature annealing is performed at a temperature of 1600° C. to 1900° C. under an inert gas atmosphere of argon (Ar) or the like, for example.
Then, a cathode electrode 22 is formed on the back surface of the silicon carbide substrate 10. The cathode electrode 22 is formed by vapor-depositing nickel (Ni) on the entire back surface of the silicon carbide substrate 10, sintering it, and sputtering titanium (Ti), nickel (Ni), and gold (Au) in this order, for example.
Then, an anode electrode 24 is formed on the p+-type silicon carbide film 14 c serving as the p-type contact layer of the mesa-type electrode part. The anode electrode 24 is formed by sputtering aluminum (Al) on the p+-type silicon carbide film 14 c and patterning thereafter, for example.
By the manufacturing method above, the mesa-type PiN diode with a high breakdown voltage of the present embodiment is formed.
According to the present embodiment, the ion-implanted region 12 is formed by implanting ions of the impurity into the silicon carbide substrate 10 before forming the silicon carbide film 14 on the silicon carbide substrate 10 by epitaxial growth. An area including a number of dislocations or sub-boundaries is formed in this ion-implanted region, where the crystalline structure of the silicon carbide is destroyed due to damage done by the ion implantation. This ion-implanted region serves as a dislocation-blocking layer for suppressing propagation of the BPD within the silicon carbide substrate 10 into the silicon carbide film 14.
According to microscopic observations by the inventor, the BPD is terminated by the interaction between the BPD and a dislocation having a Burgers vector directed oppositely from the BPD, or a dislocation loop is formed with the sub-boundaries being the surface thereof. It is confirmed that, as a result of the above, the BPD would not be propagated into the silicon carbide film 14 that is the epitaxial film.
Moreover, it is preferred that the surface of the ion-implanted region 12 be undamaged by the ion implantation as much as possible, in order to ensure epitaxial growth with superior crystallinity on the ion-implanted region 12. From this point of view, it is preferred to implant the ions under a condition that a projected range (Rp), at which the ion concentration would be the maximum, falls within the silicon carbide substrate 10.
Therefore, for example, it is preferred that the ions be directly implanted into the silicon carbide substrate 10 with the surface thereof exposed, without forming a film such as an insulating film, what is called a through film, on the silicon carbide substrate 10. Moreover, it is preferred that the ions be implanted under a condition that the impurity concentration on the surface of the silicon carbide substrate 10 right after the ion implantation would be lower by one order of magnitude or more than the maximum impurity concentration when the ion-implanted region is viewed in a depth direction.
Furthermore, it is preferred not to recover from the damage caused by the ion implantation as much as possible in view of suppressing the propagation of the BPD. Therefore, it is preferred that the ions be implanted with a temperature of the silicon carbide substrate 10 of 100° C. or less, at which little is recovered from the damage caused by the ion implantation. The ions are preferably implanted at room temperature. Here, the ion implantation at room temperature implies the ion implantation during which the silicon carbide substrate 10 is not heated.
The ionic species (impurity) being implanted is not particularly limited as long as it effectively causes damage to the silicon carbide substrate 10. For example, phosphorus (P), nitrogen (N), boron (B), and aluminum (Al) can be used.
In terms of increasing damage to the silicon carbide substrate 10, it is preferable to use the ionic species with a large ionic radius and large mass such as P (phosphorus).
In addition, in terms of inhibiting the ion-implanted region 12 as a high-resistance layer from obstructing the device operation, it is preferred that the ionic species of the conductivity type identical to that of the silicon carbide substrate 10 be implanted. As in the present embodiment, for example, it is preferred to implant ions of an n-type impurity such as phosphorus (P) and nitrogen (N) when the substrate is an n+-type semiconductor substrate.
Moreover, a dose of the ions implanted is preferably 1E15 cm−2 or greater and 1E17 cm−2 or less. If the dose falls below this range, the silicon carbide substrate 10 may not receive enough damage. If the dose exceeds this range, on the other hand, the ion-implanted region 12 may obstruct the device operation as the high-resistance layer, or excess damage done to the surface of the silicon carbide substrate 10 may obstruct epitaxial growth with superior crystallinity.
With regards to the silicon carbide substrate 10, an off direction, namely, a crystal orientation of the maximum angle of inclination of the silicon carbide substrate 10 with respect to the (0001) plane is preferably in a direction of <21-30>±5 degrees. This is to inhibit the stacking fault from being generated by the BPD propagated into the epitaxial film.
That is, by having the off direction in the <21-30> direction, a portion of the BPD that is within the silicon carbide substrate 10 and extending in the <21-30> direction would be propagated into the silicon carbide film 14. As a result, it would be unlikely for the BPD to be disintegrated into a Shockley partial dislocation which is parallel to a <11-20> or <10-10> direction bearing one side of the stacking fault. Therefore, the generation of the stacking fault caused by supplying electricity can likely be avoided even when the BPD within the silicon carbide substrate 10 is propagated as the BPD into the silicon carbide film 14.
As a result, by having the off direction in the direction of <21-30>±5 degrees, the deterioration in device characteristics due to the stacking fault generated from the BPD can be suppressed even if there exists the BPD, the propagation of which into the silicon carbide film 14 could not be obstructed by the ion-implanted region 12.
Second Embodiment
A second embodiment is similar to the first embodiment except that ions are selectively implanted into the silicon carbide substrate, and that a region formed by shifting the pn junction region used for device operation by d/tan α toward an upstream side in a step-flow direction of the silicon carbide film, which is grown by epitaxial growth, is included in an ion-implanted region, where d denotes the thickness of the silicon carbide film and a denotes an off angle of the silicon carbide substrate with respect to a (0001) plane. Thus, description of the contents overlapping the first embodiment will be partly omitted.
FIGS. 5 to 8B are process cross-sectional views illustrating a method of manufacturing a semiconductor device of the present embodiment.
First, a silicon carbide substrate 10 with an n+-type (0001) plane of a 4H silicon carbide bulk single crystal of a hexagonal system is prepared as shown in FIG. 5. The silicon carbide substrate 10 is off-cut so that the surface thereof would have an off angle of 1 degree or greater and 8 degrees or less with respect to the (0001) plane, for example.
Then, an alignment mark 26 is formed on the silicon carbide substrate 10 by dry etching. A pattern is then formed by a resistor the like with the alignment mark 26 as a fiducial mark, and ions are selectively implanted into a predetermined region of the silicon carbide substrate 10 to form an ion-implanted region 12.
Next, as shown in FIG. 6, a silicon carbide film 14 is formed, by epitaxial growth, on the silicon carbide substrate 10 into which the ions have been implanted. The silicon carbide film 14 includes: an n-type silicon carbide film 14 a as a drift layer; a p-type silicon carbide film 14 b as a p-type layer; and a p+-type silicon carbide film 14 c as a p-type contact layer.
Thereafter, an alignment mark 16 is formed in the silicon carbide film 14 by dry etching. At this time, a pattern of the alignment mark 16 is formed with the alignment mark 26 as a fiducial mark. Here, the depth of the alignment mark 16 would not affect the reading and positioning even when the alignment mark 16 is formed shallower than the depth of the alignment mark 26.
Next, as shown in FIG. 7, a pattern is formed by a resist or the like with the alignment mark 16 as the fiducial mark, and a groove 18 is formed by dry etching, thereby forming a mesa-type electrode part surrounded by the groove 18.
Then, ions of aluminum (Al) that is a p-type impurity are selectively implanted, for example. By this ion implantation, the p−-type layer 20 being the junction termination structure is formed as shown in FIG. 8.
After implanting the ions, the implanted ionic species (the impurity) is activated by high-temperature annealing.
Then, the cathode electrode 22 is formed on the back surface of the silicon carbide substrate 10. Moreover, the anode electrode 24 is formed on the p+-type silicon carbide film 14 c serving as the p-type contact layer of the mesa-type electrode part.
By the manufacturing method above, the mesa-type PiN diode with a high breakdown voltage of the present embodiment is formed.
There is a possibility that the ion-implanted region 12 would obstruct the device operation as a high-resistance layer. It is thus preferred not to form it as much as possible in a region where it is not necessary, considering the device characteristics.
The deliberation by the inventor has manifested that, even if the BPD is propagated into the silicon carbide film 14, the device characteristics would not be deteriorated as long as the BPD does not reach the pn junction region geometrically. Accordingly, in the present embodiment, the range of the ion-implanted region 12 is set so as to ensure, at a bare minimum, that the BPD would not geometrically reach the pn junction region even if it is propagated into the silicon carbide film 14.
Specifically, the ion-implanted region 12 is set to include the region formed by shifting the pn junction region used for device operation by d/tan α toward the upstream side in the step-flow direction of the silicon carbide film 14, which is grown by epitaxial growth, where d denotes the thickness of the silicon carbide film 14 and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane.
FIG. 8A is a cross-sectional view of the semiconductor device of the present embodiment, and FIG. 8B is a top view of the semiconductor device of the present embodiment. In FIG. 8B, A indicates the pn junction region, and A′ indicates the region formed by shifting the pn junction region by d/tan α toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth. In addition, B indicates the ion-implanted region 12. In the present embodiment, the pn junction region is the region including: the pn junction between the p-type silicon carbide film 14 b of the mesa-type electrode part and the n−-type silicon carbide film 14 a; and the pn junction between the p−-type layer 20 and the n−-type silicon carbide film 14 a.
When the BPD is propagated into the silicon carbide film 14, it is geometrically propagated in the step-flow direction or, for example, in the <21-30> direction on the (0001) plane, in the present embodiment. Therefore, by setting the ion-implanted region 12 as described in the present embodiment, it is ensured that the BPD propagated into the silicon carbide film 14 would not reach the pn junction region.
Thus, according to the present embodiment, the ion-implanted region 12 is formed to the minimum extent in the region considered not necessary in terms of device characteristics, in addition to the effects of the first embodiment. This can thereby prevent the ion-implanted region 12 being the high-resistance layer from possibly obstructing the device operation.
Here, the pn junction region used for the device operation is shifted by d/tan α toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth, where d denotes the thickness of the silicon carbide film 14 and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane. In the present embodiment, the pn junction surface is provided closer to the n−-type silicon carbide film 14 a than to the boundary surface between the p-type silicon carbide film 14 b and the n−-type silicon carbide film 14 a. Therefore, the BPD would not reach the pn junction region if the pn junction region used for the device operation is shifted by d′/tan α toward the upstream side in the step-flow direction of the silicon carbide film 14 that is grown by epitaxial growth, where d′ denotes the thickness of the n−-type silicon carbide film 14 a being the drift layer (FIG. 8A), and a denotes the off angle of the silicon carbide substrate 10 with respect to the (0001) plane.
For example, when the thickness d′ of the n−-type silicon carbide film 14 a as the drift layer is 26 μm and the off angle α is 4 degrees, a mask for ion implantation is designed so that a pattern formed by shifting the pattern of the pn junction region by d′/tan α=372 μm is included in the ion-implanted region 12.
The embodiments have been described with the n+-type silicon carbide substrate of the 4H silicon carbide bulk single crystal as an example; however, the embodiments can also be applied to a p+-type silicon carbide substrate of a 4H silicon carbide bulk single crystal, an n+-type silicon carbide substrate of a 6H silicon carbide bulk single crystal, and a p+-type silicon carbide substrate of a 6H silicon carbide bulk single crystal, for example.
Furthermore, the embodiments have been described with an example of the mesa-type PiN diode with a high breakdown voltage as the semiconductor device; however, the embodiments can also be applied to a semiconductor device manufactured by epitaxially growing the silicon carbide film on the silicon carbide substrate of a hexagonal system. For example, the embodiments can be applied to a vertical IGBT and a MOSFET.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the method of manufacturing a semiconductor device described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (8)

What is claimed is:
1. A method of manufacturing a semiconductor device, comprising:
preparing a silicon carbide substrate of a hexagonal system;
implanting ions into the silicon carbide substrate;
forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and
forming a pn junction region in the silicon carbide film,
wherein the ions are implanted into the silicon carbide substrate such that a region formed by shifting the pn junction region used for device operation by d/tan α toward an upstream side in a step-flow direction of the silicon carbide film, which is grown by epitaxial growth, is included in an ion-implanted region, where d denotes a thickness of the silicon carbide film and α denotes an off angle of the silicon carbide substrate with respect to a (0001) plane.
2. The method according to claim 1, wherein the ions are implanted into the silicon carbide substrate with a temperature of the silicon carbide substrate of 100° C. or less.
3. The method according to claim 1, wherein the ions are implanted into the silicon carbide substrate, a conductivity type of the impurity being identical to a conductivity type of the silicon carbide substrate.
4. The method according to claim 1, wherein the ions are implanted into the silicon carbide substrate with a surface thereof exposed without forming a film on the silicon carbide substrate.
5. The method according to claim 1, wherein the ions are selectively implanted into a predetermined region of the silicon carbide substrate.
6. The method according to claim 1, wherein the silicon carbide substrate is n-type, and
ions of phosphorus or nitrogen are implanted into the silicon carbide substrate.
7. The method according to claim 1, wherein a dose of the ions implanted into the silicon carbide substrate is 1E15 cm−2 or greater and 1E17 cm−2 or less.
8. The method according to claim 1, wherein a surface of the silicon carbide substrate has an off angle of 1 degree or greater and 8 degrees or less with respect to a (0001) plane in a direction of <21-30>±5 degrees.
US13/602,517 2012-03-02 2012-09-04 Method of manufacturing semiconductor device Expired - Fee Related US8679957B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012046503A JP5717674B2 (en) 2012-03-02 2012-03-02 Manufacturing method of semiconductor device
JP2012-046503 2012-03-02

Publications (2)

Publication Number Publication Date
US20130237042A1 US20130237042A1 (en) 2013-09-12
US8679957B2 true US8679957B2 (en) 2014-03-25

Family

ID=49096567

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/602,517 Expired - Fee Related US8679957B2 (en) 2012-03-02 2012-09-04 Method of manufacturing semiconductor device

Country Status (3)

Country Link
US (1) US8679957B2 (en)
JP (1) JP5717674B2 (en)
CN (1) CN103295884A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9263347B2 (en) * 2014-04-17 2016-02-16 Sumitomo Electric Industries, Ltd. Method of manufacturing silicon carbide semiconductor device
CN109192770A (en) * 2018-08-23 2019-01-11 无锡光磊电子科技有限公司 A kind of PN junction terminal manufacturing process
RU2710479C1 (en) * 2019-04-05 2019-12-26 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Method of forming hexagonal silicon phase by implanting krypton ions in a film of silicon oxide on a monocrystalline silicon wafer

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928320B (en) * 2014-04-21 2016-08-24 西安电子科技大学 The preparation method of trench gate carborundum insulated gate bipolar transistor
WO2016038833A1 (en) * 2014-09-08 2016-03-17 パナソニックＩｐマネジメント株式会社 Semiconductor device and method for manufacturing same
CN107768245A (en) * 2016-08-16 2018-03-06 北大方正集团有限公司 The preparation method and PIN diode of PIN diode
CN107068539B (en) * 2016-12-15 2019-11-22 中国电子科技集团公司第五十五研究所 The method for reducing silicon carbide epitaxy base plane dislocation density
JP6782263B2 (en) * 2018-02-07 2020-11-11 株式会社東芝 Semiconductor device, substrate, method of manufacturing semiconductor device, and method of manufacturing substrate
WO2019230206A1 (en) * 2018-05-30 2019-12-05 住友電気工業株式会社 Method for producing silicon carbide semiconductor device
JP7263740B2 (en) * 2018-11-06 2023-04-25 富士電機株式会社 Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP7331590B2 (en) * 2019-09-27 2023-08-23 株式会社デンソー Silicon carbide semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040149993A1 (en) * 2003-01-30 2004-08-05 Cree, Inc. Methods of Treating a Silicon Carbide Substrate for Improved Epitaxial Deposition and Resulting Structures and Devices
JP2006066722A (en) 2004-08-27 2006-03-09 Shikusuon:Kk EPITAXIAL SiC FILM, MANUFACTURING METHOD THEREFOR AND SiC SEMICONDUCTOR DEVICE
US7018554B2 (en) 2003-09-22 2006-03-28 Cree, Inc. Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices
US20100221917A1 (en) * 2006-01-30 2010-09-02 Sumitomo Electric Industries, Ltd. Method of manufacturing silicon carbide semiconductor device
US20110193101A1 (en) * 2010-02-10 2011-08-11 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003210882A1 (en) * 2002-02-08 2003-09-02 Cree, Inc. Methods of treating a silicon carbide substrate for improved epitaxial deposition
US7153983B2 (en) * 2002-03-25 2006-12-26 Council Of Scientific And Industrial Research Chemo-enzymatic process for the preparation of opticaly enriched β-benzyl-γ-butyrolactones
CN100474533C (en) * 2005-12-13 2009-04-01 上海华虹Nec电子有限公司 Production of extra-high resistance on surface of active zone
JP2007246350A (en) * 2006-03-16 2007-09-27 Mitsubishi Materials Corp METHOD FOR PRODUCING SiC SUBSTRATE, SiC SUBSTRATE, AND SEMICONDUCTOR DEVICE
JP5411422B2 (en) * 2007-01-31 2014-02-12 関西電力株式会社 Bipolar semiconductor device, method for manufacturing the same, and method for controlling zener voltage
JP4412335B2 (en) * 2007-02-23 2010-02-10 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
JP2009088223A (en) * 2007-09-28 2009-04-23 Hitachi Cable Ltd Silicon carbide semiconductor substrate and silicon carbide semiconductor device using the same
JP5343889B2 (en) * 2010-02-19 2013-11-13 株式会社デンソー Method for manufacturing silicon carbide substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040149993A1 (en) * 2003-01-30 2004-08-05 Cree, Inc. Methods of Treating a Silicon Carbide Substrate for Improved Epitaxial Deposition and Resulting Structures and Devices
US7018554B2 (en) 2003-09-22 2006-03-28 Cree, Inc. Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices
JP2006066722A (en) 2004-08-27 2006-03-09 Shikusuon:Kk EPITAXIAL SiC FILM, MANUFACTURING METHOD THEREFOR AND SiC SEMICONDUCTOR DEVICE
US20100221917A1 (en) * 2006-01-30 2010-09-02 Sumitomo Electric Industries, Ltd. Method of manufacturing silicon carbide semiconductor device
US20110193101A1 (en) * 2010-02-10 2011-08-11 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9263347B2 (en) * 2014-04-17 2016-02-16 Sumitomo Electric Industries, Ltd. Method of manufacturing silicon carbide semiconductor device
CN109192770A (en) * 2018-08-23 2019-01-11 无锡光磊电子科技有限公司 A kind of PN junction terminal manufacturing process
RU2710479C1 (en) * 2019-04-05 2019-12-26 Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" Method of forming hexagonal silicon phase by implanting krypton ions in a film of silicon oxide on a monocrystalline silicon wafer

Also Published As

Publication number Publication date
US20130237042A1 (en) 2013-09-12
JP2013183064A (en) 2013-09-12
CN103295884A (en) 2013-09-11
JP5717674B2 (en) 2015-05-13

Similar Documents

Publication Publication Date Title
US8679957B2 (en) Method of manufacturing semiconductor device
TWI229421B (en) Minimizing degradation of SiC bipolar semiconductor devices
CN107430993B (en) Method for manufacturing epitaxial wafer, method for manufacturing semiconductor device, and semiconductor device
JP5011493B2 (en) Method for manufacturing silicon carbide semiconductor element
JP6706767B2 (en) Semiconductor device
JP5164319B2 (en) Deactivated protective ring for semiconductor devices
US10312330B2 (en) Method for fabricating semiconductor substrate, semiconductor substrate, and semiconductor device
WO2011046020A1 (en) Silicon carbide substrate manufacturing method, silicon carbide substrate, and semiconductor device
JP4879507B2 (en) Bipolar semiconductor device forward voltage recovery method, stacking fault reduction method, and bipolar semiconductor device
JP4463448B2 (en) SiC substrate and method of manufacturing SiC semiconductor device
US20110284871A1 (en) Silicon carbide substrate, semiconductor device, and method for manufacturing silicon carbide substrate
US9318324B2 (en) Manufacturing method of SiC epitaxial substrate, manufacturing method of semiconductor device, and semiconductor device
CN108886063B (en) Nitride semiconductor substrate, semiconductor device, and method for manufacturing nitride semiconductor substrate
US20100084663A1 (en) Silicon Carbide Zener Diode
CA2768285A1 (en) Silicon carbide substrate fabrication method, semiconductor device fabrication method, silicon carbide substrate, and semiconductor device
US20110306181A1 (en) Method of manufacturing silicon carbide substrate
WO2008015766A1 (en) Method for recovering forward voltage of bipolar semiconductor device, method for reducing lamination defect and bipolar semiconductor device
JP2007027630A (en) Bipolar semiconductor device and its manufacturing method
US9450054B2 (en) Dislocation in SiC semiconductor substrate
US20180012957A1 (en) Silicon carbide semiconductor device
US20230299173A1 (en) Forming an electronic device, such as a jbs or mps diode, based on 3c-sic, and 3c-sic electronic device
JP7331393B2 (en) Method for manufacturing silicon carbide semiconductor device
JP2006237125A (en) Method of operating bipolar type semiconductor device, and bipolar type semiconductor device
JP2023068113A (en) Silicon carbide semiconductor device
WO2011158535A1 (en) Method for producing composite substrate and composite substrate

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NISHIO, JOHJI;OTA, CHIHARU;SHINOHE, TAKASHI;REEL/FRAME:029208/0375

Effective date: 20120928

CC Certificate of correction
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20180325