US8658520B2 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- US8658520B2 US8658520B2 US13/415,628 US201213415628A US8658520B2 US 8658520 B2 US8658520 B2 US 8658520B2 US 201213415628 A US201213415628 A US 201213415628A US 8658520 B2 US8658520 B2 US 8658520B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 49
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 34
- 239000013078 crystal Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims description 8
- 239000007790 solid phase Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 13
- 230000005855 radiation Effects 0.000 description 10
- 230000002159 abnormal effect Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000004913 activation Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- -1 hafnium silicon oxide nitride Chemical class 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- Embodiments of the invention relate to a method of manufacturing a semiconductor device.
- transistors are miniaturized mainly by a logic device
- memory devices which are miniaturized by one generation about every two years
- transistors having a performance higher than the logic device have been requested.
- a thin source/drain region such as, for example, a source/drain region having a thickness of 10 nm or less is formed. Even in the transistors, since it is necessary to reduce a parasitic resistance of the transistors, a nickel silicide film is formed on the source/drain region by self-alignment, and a resistance of the source/drain region is reduced by the nickel silicide films.
- FIGS. 1A to 1D are views which explain a method of manufacturing a semiconductor device according to a first embodiment
- FIG. 2 is a view schematically showing a manufacturing apparatus of the first embodiment and a second embodiment
- FIGS. 3A to 3E are views which explain a mechanism in the first and second embodiments
- FIG. 4 is a sectional view of a semiconductor device according to a modification of the first embodiment.
- FIGS. 5A to 5E are views which explain a method of manufacturing a semiconductor device according to the second embodiment.
- a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers by radiating microwaves to the amorphous regions and the nickel films.
- FIGS. 1A to 1D correspond to a cross-section of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) along a channel direction and shows manufacturing steps of the MOSFET disposed on a silicon substrate 101 .
- a left side is a P-type MOSFET region 10 where a P-type MOSFET is formed
- a right side is an N-type MOSFET region 11 where an N-type MOSFET is formed.
- a method of manufacturing the MOSFET is explained as an example, the invention is not limited to the method of manufacturing the semiconductor device and may be a method of manufacturing other semiconductor device.
- a gate insulation film 105 which is composed of a silicon oxide film (SiO 2 ), a hafnium silicon oxide nitride film (HfSiON), and the like, is formed on each of a channel region of an N-type diffusion layer 103 in the P-type MOSFET region 10 and a channel region of a P-type diffusion layer 104 in the N-type MOSFET region 11 on the silicon substrate 101 with STIs (Shallow Trench Isolation) 102 .
- a metal film 106 which controls a work function of TiN and the like and a polycrystalline silicon film 107 are deposited on each of the gate insulation films 105 , and these films are processed as gate electrodes 12 .
- extension diffusion layers 108 , 109 are formed by injecting impurities to two portions of a front surface of the silicon substrate 101 that sandwiches the respective channel regions along the channel direction.
- the P-type extension diffusion layer 108 is formed in the P-type MOSFET region 10
- the N-type extension diffusion layer 109 is formed in the N-type MOSFET region 11 .
- gate side wall films 110 which are composed of, for example, a silicon oxide film and a silicon nitride film (SiN) or a laminated structure of these films and cover side walls of the gate electrodes 12 are formed.
- a source/drain region 111 that is a P-type layer is formed in the P-type MOSFET region 10
- a source/drain region 112 that is an N-type layer is formed in the N-type MOSFET region 11 .
- Halo ion implantation and PTS (Punch Through Stopper) injection that are ordinarily executed when the MOSFET is formed is omitted.
- the source/drain regions 111 , 112 having a depth of 10 nm is formed after the extension diffusion layers 108 , 109 having a depth of, for example, 6 nm from the front surface of the silicon substrate 101 are formed.
- the present embodiment is not limited thereto and, for example, the side walls 110 are removed after the source/drain regions 111 , 112 having a depth of 10 nm are formed, and then the extension diffusion layers 108 , 109 having a depth of 6 nm may be formed and thereafter the side walls 110 may be formed again.
- amorphous regions 113 , 114 , 115 are formed on upper surfaces of the source/drain regions 111 , 112 and on upper surfaces of polycrystalline silicon films 107 that constitute parts of the gate electrodes 12 by executing a plasma process in an atmosphere of Xe, Kr, Ar, GeH 4 and the like while applying a bias to the silicon substrate 101 . Crystal defects can be reduced by using the plasma process as described above. At the time, it is preferable to form a depth of the amorphous regions 113 , 114 formed on the upper surfaces of the source/drain regions 111 , 112 so that the depth does not exceed the depth of the source/drain regions 111 , 112 .
- a nickel film 117 containing 5 to 10% of platinum and having a thickness of 5 to 7 nm is deposited on the silicon substrate 101 , in particular, so as to cover the source/drain regions 111 , 112 and the gate electrodes 12 using PVD (Physical Vapor Deposition).
- the nickel film 117 can be formed also using CVD (Chemical Vapor Deposition).
- the nickel film 117 may contain impurities such as cobalt to improve a heat resistance, a resistance value, and the like or may not contain the impurities.
- microwaves of 5.80 GHz are radiated at a power of 10 W/cm 2 to 1000 W/cm 2 .
- the microwaves are radiated for 30 seconds to 15 minutes at a power by which a substrate temperature of the silicon substrate 101 is saturated at 150 to 350° C. and preferably at 200 to 300° C.
- upper portions of the amorphous regions 113 , 114 , 115 in contact with the nickel film 117 and the nickel film 117 cause a silicidation reaction, and nickel silicide films 118 , 119 are formed on the upper surfaces of the source/drain regions 111 , 112 and on upper surfaces of the polycrystalline silicon films 107 .
- nickel silicide films 118 , 119 are formed as films composed of a low resistant nickel monosilicide (NiSi) by causing the reaction at a low temperature using the microwaves as described above. Then, at the same time, lower portions of the amorphous regions 113 , 114 in contact with the source/drain regions 111 , 112 are crystalized (solid-phase grown) using the source/drain regions 111 , 112 as a growth nucleus, and impurities contained in the amorphous regions 113 , 114 are activated.
- NiSi nickel monosilicide
- the lower portions of the amorphous regions 113 , 114 in contact with the source/drain regions 111 , 112 are made to single crystal layers containing the activated impurities by radiating the microwaves, and further the nickel silicide films 118 are formed on the single crystal layers.
- the single crystal layers have a crystal orientation in accordance with a crystal structure of the source/drain regions 111 , 112 .
- the nickel silicide films 118 do not pass through the source/drain regions 111 , 112 , in other words, the nickel silicide films 118 are formed on lower surfaces of the amorphous regions in contact with the source/drain regions 111 , 112 (in FIG.
- the substrate temperature of the silicon substrate 101 at the time can be confirmed using a thermocouple disposed on a back surface of the silicon substrate 101 or a radiation thermometer installed to a microwave radiation apparatus.
- a radiation power of the microwaves is preferably configured as described below.
- a manufacturing apparatus 20 used when the microwaves are radiated has one or plural waveguides 21 (for example, in FIG. 2 , the manufacturing apparatus 20 has four waveguides 21 ).
- the waveguides 21 are used to guide the microwaves Wn (in FIG. 2 , W 1 to W 4 ) output from a microwave oscillator (not illustrated) such as a magnetron into the manufacturing apparatus 20 to which the silicon substrate 101 is installed.
- the sum total ⁇ (PWn/Sn) of quotients obtained by dividing radiation powers of the microwaves in particular, powers PWn of respective microwaves Wn output from the respective waveguides 21 by cross-sectional areas Sn of the waveguides 21 corresponding to the powers PWn so that the sum total ⁇ (PWn/Sn) becomes 10 W/cm 2 to 1000 W/cm 2 .
- This will be explained using, for example, the manufacturing apparatus 20 having the four waveguides 21 shown in FIG. 2 .
- the radiation powers of the microwaves defined as described above increase as the number of the waveguides 21 provided with the increase of the manufacturing apparatus 20 .
- the microwaves that mainly have a frequency band of 5.80 GHz are used, this is because that since the frequency band is designated to ISM (Industry-Science-Medical Band), the magnetron can easily obtain the microwaves, and the present embodiment can be embodied likewise even by microwaves that mainly have a frequency band of from 2.45 GHz to 25 GHz.
- ISM Industry-Science-Medical Band
- an increase of the substrate temperature may be suppressed by cooling the silicon substrate 101 by blowing N 2 gas, He gas, and the like to the substrate or placing the silicon substrate 101 on a quartz plate simultaneously with the radiation of the microwaves.
- the radiation powers of the microwaves can be more increased by suppressing the increase of the substrate temperature of the silicon substrate 101 and thereby the silicidation reaction and the activation of the impurities can be easily executed.
- the nickel silicide films 118 , 119 remain on the upper surfaces of the source/drain regions 111 , 112 and on the upper surfaces of the polycrystalline silicon films 107 .
- a temperature of about 300° C. to 500° C. is necessary.
- nickel silicide film when a very thin nickel silicide film is formed on the source/drain regions by RTA, since the nickel silicide films are very thin, aggregation occurs by heat applied after the nickel silicide films are formed and a sheet resistance of the nickel silicide films increases. In contrast, when a thick nickel silicide film is formed on the source/drain regions by RTA, there is a possibility that the nickel silicide film causes an abnormal growth and the like toward a depth direction (toward a direction opposite to the front surface of the silicon substrate), further passes through the source/drain regions, and increases a junction leak.
- the abnormal growth of the nickel silicide films 118 , 119 as described above can be avoided by using the microwaves.
- the microwaves have such a property that they have a long wavelength of about 5 cm in comparison with ultraviolet rays, visible light, infrared rays, and the like and a high permeability into a film.
- both the formation of the nickel silicide films 118 , 119 and the activation of the impurities contained in the source/drain regions 111 , 112 can be executed while suppressing the aggregation and the abnormal growth due to the heat by that the microwaves having the property deliver energy to necessary portions and dipoles existing in an interface between the nickel film 117 and the amorphous regions 113 , 114 , 115 are rotated. Further, in the RTA and the like, even in a low temperature region in which nickel rich silicide is formed, since the nickel silicide films 118 , 119 that contain a lot of nickel monosilicide and have a low resistance can be formed by radiating the microwaves, a parasitic resistance of a transistor can be more reduced.
- the nickel silicide films 118 pass through the source/drain regions 111 , 112 by suppressing the abnormal growth of the nickel silicide films 118 . That is, the nickel silicide films 118 can be formed thin. Accordingly, a transistor in which a junction leak current is suppressed can be formed. For example, smooth nickel silicide films 118 can be obtained in which an interface between the nickel silicide films 118 and the source/drain regions 111 , 112 have a roughness of 1 nm or less.
- FIGS. 3A to 3E correspond to FIGS. 1C to 1D and show a process in which an amorphous region 203 ( 113 , 114 , 115 in FIGS. 1C and 1D ) and a nickel film 204 ( 117 in FIGS. 1C and 1D ) cause a silicidation reaction and a nickel silicide film 205 ( 118 , 119 in FIGS. 1C and 1D ) is formed.
- the nickel film 204 causes the silicidation reaction with a part of the amorphous region 203 by radiating the microwaves.
- the silicidation reaction proceeds in a depth direction (toward a silicon substrate 201 ).
- a crystallization of amorphous silicon that is, a solid-phase growth of silicon using the silicon substrate 201 as a growth nucleus (seed) proceeds in a direction opposite to a direction in which the silicidation reaction proceeds, and a part of the amorphous region 203 becomes a single crystal layer 202 .
- the silicidation reaction stops once in an interface between the amorphous region 203 and the single crystal layer 202 due to solid-phase growth.
- the microwaves are used at about 200° C.
- a speed of the silicidation reaction is faster than a speed of the solid-phase growth
- the silicidation reaction in the depth direction stops once in the interface between the single crystal layer 202 and the amorphous region 203
- the silicidation reaction proceeds in a lateral direction along the interface.
- FIG. 3D when the silicidation in the amorphous region 203 in the lateral direction is completed, the silicidation reaction in the depth direction resumes as shown in FIG. 3E .
- the nickel silicide films 118 are formed on a front surface side of the silicon substrate 101 rather than bottom portions of the source/drain regions 111 , 112 positioned far from the front surface of the silicon substrate 101 by finishing the silicidation reaction at a stage that the silicidation reaction in the lateral direction as in FIG. 3D is completed, it can be avoided that the nickel silicide films 118 pass through the source/drain regions 111 , 112 and thereby the transistor in which the junction leak current is sufficiently suppressed can be formed.
- the present embodiment can be applied to a structure without the extension diffusion layers 108 , 109 as shown in FIG. 4 .
- FIGS. 5A to 5E A method of manufacturing a Fin-type transistor (FinFET) according to a second embodiment will be explained using FIGS. 5A to 5E .
- the FinFET is a MOSFET configured such that a projection-like region is formed by cutting a silicon substrate in a thin strip state (the projection-like region is called a Fin), and a gate electrode is caused to three-dimensionally intersect with the projection-like region and thereby an upper surface and a side surface of the cut projection-like region is used as a channel.
- the invention is not limited to the method of manufacturing the semiconductor device and may be a method of manufacturing other semiconductor device and a P-type Fin FET.
- FIGS. 5A to 5E correspond to a cross-section of a Fin in a source/drain region (not illustrated) in the Fin in a FinFET and shows manufacturing steps of a P-type FinFET. Note that, although not shown in FIGS. 5A to 5E , the FinFET may include an extension diffusion layer, and a gate side wall film.
- a silicon substrate 301 on which plural Fins 304 having a width of, for example, 12 nm are formed, is prepared, and an STI 302 is formed by burying an insulation film between the Fins 304 . Further, after side wall films 303 are formed so as to cover the Fins 304 , the side wall films 303 that cover upper portions of the Fins 304 are removed by reactive Ion etching. As described above, the Fins 304 whose lower portions are covered with the side wall films 303 and whose upper portions are exposed are formed as shown in FIG. 5A are formed.
- amorphous regions 306 containing phosphorus (P) are formed on the front surfaces of the Fins 304 on which the epitaxial silicon layers 305 are formed by using a plasma doping process in an atmosphere containing a doping gas such as PH 3 and an inert gas such as He, Ne, Ar, Kr, and Xe.
- a thickness of the amorphous regions 306 is preferably made to, for example, 10 nm so that single crystal portions 307 remain to central portions of the Fins 304 . This is because when all of the Fins 304 are amorphousized, it becomes difficult to execute recrystallization at a next step.
- the number of crystal defects can be reduced by executing doping by plasma having a smaller amount of energy of particles than ion implantation.
- the plasma doping process is preferably used to the three-dimensional structure such as the Fins 304 .
- nickel films 308 containing 5 to 40% of cobalt are deposited in a thickness of 5 to 7 nm on the silicon substrate 301 by CVD, in particular, so as to cover the Fins 304 .
- CVD chemical vapor deposition
- impurities such as carbon are liable to be contained in the nickel films 308 .
- hydrogen is preferably used at a next step.
- the nickel films 308 containing cobalt are used, the nickel films 308 may or may not contain impurities such as phosphorus.
- microwaves of 5.80 GHz are radiated at a power of 10 W/cm 2 to 1000 W/cm 2 in an atmosphere containing H 2 , N 2 , or Ar.
- the microwaves are radiated for 30 seconds to 15 minutes at a power by which a substrate temperature of the silicon substrate 301 is saturated at 200 to 350° C. and preferably at 250 to 300° C.
- the substrate temperature of the silicon substrate 301 at the time can be confirmed using a thermocouple disposed on a back surface of the silicon substrate 301 like the first embodiment.
- NiSi nickel monosilicide
- central portions of the amorphous regions 306 in contact with the single crystal portions 307 of central portions of the Fins 304 are crystalized (solid-phase grown) using the single crystal portions 307 of the central portions of the Fins 304 as a growth nucleus, and impurities contained in the central portions of the amorphous regions 306 are activated. That is, like the mechanism of the first embodiment explained previously using FIGS.
- the single crystal portions 307 existing in the central portions of the Fins 304 act as a growth nucleus (seed) for recrystallization, the amorphous regions 306 are solid-phase grown and crystal layers are formed thereby, and impurities contained in the crystal layers are activated. Accordingly, like the first embodiment, it can be avoided that the nickel silicide films 309 pass through source/drain regions (not illustrated) by suppressing an abnormal growth of the nickel silicide films 309 .
- the same definition of a radiation power of the microwaves as that of the first embodiment is used, and further, as to also a frequency, like the first embodiment, the present embodiment can also be embodied by microwaves having a frequency band of mainly from 2.45 GHz to 25 GHz.
- an increase of the substrate temperature may be suppressed by cooling the silicon substrate 301 by blowing N 2 gas, He gas, and the like to the substrate or placing the silicon substrate 301 on a quartz plate simultaneously with the radiation of the microwaves.
- a film thickness of the nickel silicide films 309 is, for example, 7 to 8 nm.
- both the formation of the nickel silicide films 309 and the activation of the impurities can be executed at the same time while suppressing aggregation and abnormal growth due to heat by using the microwaves. Further, since the formation and the activation can be executed at a low temperature, the nickel silicide films 309 that contain nickel monosilicide in a large amount and a low resistance can be formed and thereby a parasitic resistance of a transistor can be reduced. In addition, there can be formed a transistor in which the abnormal growth of the nickel silicide films 309 is suppressed and it is avoided that nickel silicide films 309 pass through the source/drain regions and thereby a junction leak current is sufficiently suppressed.
- the present embodiment can be applied also to the P-type FinFET, and, in the case, it is sufficient to change the doping gas used in the plasma doping process from PH 3 and the like to B 2 H 6 and the like.
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