US8566379B2 - Systems and methods for self tuning target adaptation - Google Patents
Systems and methods for self tuning target adaptation Download PDFInfo
- Publication number
- US8566379B2 US8566379B2 US12/947,931 US94793110A US8566379B2 US 8566379 B2 US8566379 B2 US 8566379B2 US 94793110 A US94793110 A US 94793110A US 8566379 B2 US8566379 B2 US 8566379B2
- Authority
- US
- United States
- Prior art keywords
- output
- circuit
- data
- noise
- equalizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03993—Noise whitening
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03445—Time domain
- H04L2025/03471—Tapped delay lines
- H04L2025/03484—Tapped delay lines time-recursive
- H04L2025/03503—Tapped delay lines time-recursive as a combination of feedback and prediction filters
Definitions
- the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptive data processing.
- a synchronization mark is identified based upon a threshold comparison.
- a threshold comparison approach depends highly upon determining an appropriate threshold for comparison. Where the selected threshold is too high, sync marks will be missed. Alternatively, where the selected threshold is too low, sync marks may be incorrectly identified. Either case is problematic for proper data processing.
- the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptive data processing.
- Various embodiments of the present inventions provide methods for data processing that include: receiving a data input; equalizing the data input based on an equalizer coefficient to yield an equalized output; performing a data detection on a derivative of the equalized output to yield a detected output; reconstructing the detected output based on a target polynomial to yield a reconstructed output; aligning the equalized output with the reconstructed output to yield a delayed output; calculating a difference between the reconstructed output and the delayed output to yield an error value; filtering the error value based at least in part on a filter coefficient to yield a filtered output; and using the filtered output to adapt the filter coefficient, the target polynomial, and the equalizer coefficient.
- the data input is received from an analog to digital converter circuit, and the method further includes receiving an analog input, and converting the analog input signal into a digital output, wherein the digital output is the data input.
- the data input is derived from a storage medium or a transfer medium.
- the data input is initially a known data input, and subsequently an unknown data input.
- the target polynomial may be fixed to a value adaptively determined during processing the known data input.
- using the filter output to adapt the target polynomial is done by minimizing a noise whitened and squared version of the error value, and using the filter output to adapt the equalizer coefficient is done by minimizing a noise whitened and squared version of the error value.
- Such data processing circuits include: an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit.
- the equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient.
- the noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient.
- the data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output.
- the data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.
- the adaptation circuit is operable to adaptively calculate the equalizer coefficient, the noise predictive filter coefficient and the target polynomial.
- the adaptation circuit includes a summation circuit operable to subtract the reconstructed output from the equalized output to yield an error value.
- the adaptation circuit further includes an equalizer adaptation circuit operable to minimize the noise whitened and squared version of the error value, and a target adaptation circuit operable to minimize a noise whitened and squared version of the error value.
- FIG. 1 depicts a data processing circuit including an adaptive feedback noise processing, equalization and targeting circuit in accordance with some embodiments of the present invention
- FIG. 2 a is a flow diagram showing a process in accordance with some embodiments of the present invention for adaptively adjusting noise processing, equalization and targeting in a data processing circuit to establish a baseline;
- FIG. 2 b is a flow diagram showing a process in accordance with some embodiments of the present invention for using the baseline established in the method of FIG. 2 a to adaptively adjusting noise processing, equalization and targeting in a data processing circuit;
- FIG. 3 shows a storage system including an adaptive feedback noise processing, equalization and targeting circuit in accordance with some embodiments of the present invention.
- FIG. 4 depicts a communication system including an adaptive feedback noise processing, equalization and targeting circuit in accordance with different embodiments of the present invention.
- the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptive data processing.
- Data processing circuit 100 includes an analog to digital conversion circuit 110 that receives a data input 105 .
- Data input 105 is an analog signal representing information that may be received from a variety of sources including, but not limited to, a storage medium or a data transfer medium in a communication device. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources for data input 105 .
- Analog to digital converter circuit 110 samples data input 105 and provides the samples as a series of digital values 112 . Digital values 112 are generally referred to herein as y samples.
- a ten tap filter length is used to implement equalizer adaptation circuit 190 .
- Noise predictive filter circuit 130 may be any noise predictive filter circuit known in the art.
- noise predictive filter 130 has a three tap filter length that is used to implement noise predictive filter circuit 130 .
- Noise whitened output 132 is provided to a data detector circuit 140 that performs a data detection on the received input to yield a data output 142 .
- Data output 142 includes both hard decision data and soft decision data.
- the soft decision data indicates a likelihood that the corresponding hard decision data is correctly selected.
- the operation of data detector circuit 140 is governed by a target polynomial 164 (i.e., target coefficients) provided by a filter adaptation circuit 160 .
- Data detector circuit may be any data detector circuit known in the art. In one particular embodiment of the present invention, data detector circuit 140 is a maximum a posteriori data detector circuit as is known in the art.
- the hard decision portion of data output 142 is provided to both filter adaptation circuit 180 and target adaptation circuit 160 .
- a data reconstruction circuit 150 operates on the hard decision portion of data output 142 to reconstruct a data set corresponding to equalized output 122 and provide a reconstructed output 152 .
- Data reconstruction circuit 150 may be any circuit known in the art that is capable of regenerating an original input based on a received detected output.
- Reconstructed output 152 is generally referred to herein as ⁇ samples.
- Reconstructed output 152 is provided to a summation circuit 195 where it is subtracted from a delayed equalized output 172 received from a delay circuit 170 .
- delay circuit 172 receives equalized output 122 and delays it in time to align with the bit positions of reconstructed output 152 corresponding to equalized output 122 .
- An error value 194 is provided from summation circuit 195 in accordance with the following equation:
- the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine.
- the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine.
- the aforementioned is an ideal equation that may be modified to account for mis-equalization ( ⁇ [cond]) that may be considered as part of the target adaptation process discussed below.
- the modified equation accounting for mis-equalization is as follows:
- Error value 194 is provided to equalizer adaptation circuit 190 , filter adaptation circuit 180 and target adaptation circuit 160 .
- Filter adaptation circuit 180 adaptively calculates noise predictive coefficients 182 using any adaptive calculation process known in the art. In particular, filter adaptation circuit 180 adaptively calculates noise predictive coefficients 182 based on error value 194 , equalized output 122 and a target feedback value 162 .
- the noise predictive filter is a three tap filter length in which case t is equal to three.
- Target adaptation circuit 160 adaptively calculates target polynomial 164 to minimize a noise whitened and squared version of the error value. Minimizing noise whitened and squared version of the error value by changing target polynomial 164 to drive the following gradient the following gradient of the squared error (i.e.,
- data processing circuit 100 receives a known data set as data input 105 for processing.
- filter adaptation circuit 180 adaptively calculates noise predictive coefficients 182 using a standard adaptive calculation process known in the art.
- equalization adaptation circuit 190 adaptively calculates equalizer coefficients 192 to minimize a noise whitened and squared version of the error value
- target adaptation circuit 160 adaptively calculates target polynomial 164 to minimize a noise whitened and squared version of the error value. Once a minimum occurs, target polynomial is fixed and stored for use during regular data processing.
- a regular data input i.e., an unknown data input
- Target polynomial 164 equalizer coefficients 192
- noise predictive coefficients 182 are initially applied.
- filter adaptation circuit 180 adaptively calculates noise predictive coefficients 182 using a standard adaptive calculation process known in the art
- equalization adaptation circuit 190 adaptively calculates equalizer coefficients 192 to minimize a noise whitened and squared version of the error value.
- a flow diagram 200 shows a process in accordance with some embodiments of the present invention for adaptively adjusting noise processing, equalization and targeting in a data processing circuit to establish a baseline.
- a known data input is received (block 205 ).
- the data input is a defined, known analog signal representing informational bits at various times or bit locations. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the known data input.
- An analog to digital conversion is applied to the data input to yield a series of digital samples corresponding to respective sample periods (block 210 ).
- the resulting digital samples are generally referred to herein as x samples.
- the analog to digital conversion may be applied using any analog to digital conversion approach known in the art.
- the resulting series of digital samples are provided to an equalization circuit where they are equalized to an equalization target (block 215 ).
- the equalizer circuit is initialized with coefficients that are expected to be close to the final adapted equalizer coefficients.
- the equalization may be done using any equalization process known in the art.
- the equalization is done using a finite impulse response filter with operation governed by one or more filter taps as is known in the art.
- the resulting equalized data samples are provided to a noise predictive filter circuit that performs noise predictive filtering to yield a noise whitened output (block 225 ).
- the noise predictive filtering may be done using any noise predictive filtering circuit governed based on one or more filter taps as is known in the art.
- the noise whitened output is provided to a data detector circuit where a data detection algorithm is applied to the received sample in an effort to recover the originally written data (block 230 ).
- This data detection process may be any data detection process known in the art.
- the data detection process may be a maximum a posteriori data detection process as is known in the art.
- the resulting detected output is used to reconstruct the data input for comparison purposes (block 235 ).
- the resulting reconstructed output is generally referred to herein as ⁇ samples.
- the equalized output (block 215 ) is delayed in time to align it with the corresponding reconstructed data (block 220 ).
- the delayed equalized output and the reconstructed output are combined to calculate a target error (block 245 ) in accordance with the following equation:
- the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine.
- the aforementioned is an ideal equation that may be modified to account for mis-equalization ( ⁇ [cond]) that may be considered as part of the target adaptation process discussed below.
- the modified equation accounting for mis-equalization is as follows:
- the determined error is then noise whitened to yield a whitened error term (block 250 ) in accordance with the following equation:
- the noise predictive filter is a three tap filter length in which case t is equal to two.
- the existing noise predictive filter coefficients, equalization coefficients and target coefficients are modified to adaptively minimize the squared error term (block 270 ).
- the resulting adapted values are used in processing a newly received data input.
- the adapted values are calculated using any approach known in the art for optimizing noise predictive coefficients (i.e., f[cond][m]). Using the aforementioned f[cond][m], the following gradient of the squared error (i.e.,
- a flow diagram 203 shows a process in accordance with some embodiments of the present invention for using the baseline established using the process of flow diagram 200 of FIG. 2 a to adaptively adjust noise processing, equalization and targeting in a data processing circuit.
- the baseline i.e., the value established for the target which accounts for the mis-equalization term
- the baseline is fixed for the specific zone over which it was calculated and stored to a table.
- a known data input is received (block 208 ).
- the process of flow diagram 203 is used to process unknown data inputs.
- Such data inputs are an analog signals representing informational bits at various times or bit locations.
- the data input may be received from a variety of sources including, but not limited to, a storage medium or a data transfer medium in a communication device. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources for such data inputs.
- An analog to digital conversion is applied to the data input to yield a series of digital samples corresponding to respective sample periods (block 211 ).
- the resulting digital samples are generally referred to herein as x samples.
- the analog to digital conversion may be applied using any analog to digital conversion approach known in the art.
- the resulting series of digital samples are provided to an equalization circuit where they are equalized to an equalization target (block 214 ).
- the equalizer circuit is initialized with the equalizer coefficients developed in the process of flow diagram 200 .
- the equalization may be done using any equalization process known in the art.
- the equalization is done using a finite impulse response filter with operation governed by one or more filter taps as is known in the art.
- the resulting equalized data samples are provided to a noise predictive filter circuit that performs noise predictive filtering to yield a noise whitened output (block 223 ).
- the noise predictive filtering may be done using any noise predictive filtering circuit governed based on one or more filter taps as is known in the art.
- the noise whitened output is provided to a data detector circuit where a data detection algorithm is applied to the received sample in an effort to recover the originally written data (block 226 ).
- This data detection process may be any data detection process known in the art.
- the data detection process may be a maximum a posteriori data detection process as is known in the art.
- the resulting detected output is provided as a circuit output (block 232 ).
- This detected output may be provided, for example, to a down stream data decoding circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will appreciate a variety of uses for the resulting detected output.
- the resulting detected output is used to reconstruct the data input for comparison purposes (block 229 ).
- the resulting reconstructed output is generally referred to herein as ⁇ samples.
- the equalized output (block 214 ) is delayed in time to align it with the corresponding reconstructed data (block 217 ).
- the delayed equalized output and the reconstructed output are combined to calculate a target error (block 238 ) in accordance with the following equation:
- the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine.
- the aforementioned is an ideal equation that may be modified to account for mis-equalization ( ⁇ [cond]) that may be considered as part of the target adaptation process discussed below.
- the modified equation accounting for mis-equalization is as follows:
- the determined error is then noise whitened to yield a whitened error term (block 241 ) in accordance with the following equation:
- the noise predictive filter is a three tap filter length in which case t is equal to two.
- the existing noise predictive filter coefficients, equalization coefficients are modified to adaptively minimize the squared error term (block 263 ).
- the resulting adapted values are used in processing a newly received data input.
- the adapted values are calculated using any approach known in the art for optimizing noise predictive coefficients (i.e., f[cond][m]). Using the aforementioned f[cond] [m], the following gradient of the squared error (i.e.,
- Storage system 300 may be, for example, a hard disk drive.
- Storage system 300 also includes a preamplifier 370 , an interface controller 320 , a hard disk controller 366 , a motor controller 368 , a spindle motor 372 , a disk platter 378 , and a read/write head 376 .
- Interface controller 320 controls addressing and timing of data to/from disk platter 378 .
- the data on disk platter 378 consists of groups of magnetic signals that may be detected by read/write head assembly 376 when the assembly is properly positioned over disk platter 378 .
- disk platter 378 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.
- read/write head assembly 376 is accurately positioned by motor controller 368 over a desired data track on disk platter 378 .
- Motor controller 368 both positions read/write head assembly 376 in relation to disk platter 378 and drives spindle motor 372 by moving read/write head assembly to the proper data track on disk platter 378 under the direction of hard disk controller 366 .
- Spindle motor 372 spins disk platter 378 at a determined spin rate (RPMs).
- the sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 378 .
- This minute analog signal is transferred from read/write head assembly 376 to read channel module 364 via preamplifier 370 .
- Preamplifier 370 is operable to amplify the minute analog signals accessed from disk platter 378 .
- read channel circuit 310 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 378 .
- This data is provided as read data 303 to a receiving circuit.
- read channel circuit 310 performs an adaptive feedback noise processing, equalization and targeting circuit. Such an adaptive circuit may be implemented similar to that described above in relation to FIG.
- a write operation is substantially the opposite of the preceding read operation with write data 301 being provided to read channel circuit 310 . This data is then encoded and written to disk platter 378 .
- storage system 300 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system 300 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.
- RAID redundant array of inexpensive disks or redundant array of independent disks
- Communication system 400 includes a transmitter 410 that is operable to transmit encoded information via a transfer medium 430 as is known in the art.
- the encoded data is received from transfer medium 430 by receiver 420 .
- Receiver 420 incorporates an adaptive feedback noise processing, equalization and targeting circuit.
- Such an adaptive circuit may be implemented similar to that described above in relation to FIG. 1 , and/or may operate similar to the method discussed above in relation to FIG. 2 .
- Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
Abstract
Description
y=ax,
where a corresponds to
where j indicates one of the equalizer coefficients. In one embodiment of the present invention, the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other equalizer circuits lengths that may be used in accordance with different embodiments of the present invention. Of note, the aforementioned is an ideal equation that may be modified to account for mis-equalization (μ[cond]) that may be considered as part of the target adaptation process discussed below. The modified equation accounting for mis-equalization is as follows:
Squared Error=(ErrorTerm)2,
where the ErrorTerm is defined by the following equation:
where m represents each filter tap on a noise predictive filter that performs the f[cond][m] processing. In one particular embodiment of the present invention, the noise predictive filter is a three tap filter length in which case t is equal to three. Minimizing noise whitened and squared version of the error value by changing the equalizer coefficients 192 (an) to drive the following gradient (i.e.,
of the Squared Error to zero for each coefficient:
where e[k−m] is short for the difference between the reconstructed output and the target error shown in the following equation:
is set equal to zero to determine an optimal value for the target which accounts for the mis-equalization term:
Again, e[k−m] is short for the difference between the reconstructed output and the target error shown in the following equation:
y=ax,
where a corresponds to the equalization target. The equalization may be done using any equalization process known in the art. For example, in one embodiment of the present invention, the equalization is done using a finite impulse response filter with operation governed by one or more filter taps as is known in the art. The resulting equalized data samples are provided to a noise predictive filter circuit that performs noise predictive filtering to yield a noise whitened output (block 225). The noise predictive filtering may be done using any noise predictive filtering circuit governed based on one or more filter taps as is known in the art.
where j indicates one of the equalizer coefficients. In one embodiment of the present invention, the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other equalizer circuits lengths that may be used in accordance with different embodiments of the present invention. Of note, the aforementioned is an ideal equation that may be modified to account for mis-equalization (μ[cond]) that may be considered as part of the target adaptation process discussed below. The modified equation accounting for mis-equalization is as follows:
where m represents each filter tap on a noise predictive filter that performs the f[cond][m] processing. In one particular embodiment of the present invention, the noise predictive filter is a three tap filter length in which case t is equal to two. The error term is then squared (block 255) in accordance with the following equation:
Squared Error=(ErrorTerm)2.
is set equal to zero to determine an optimal value for the equalizer coefficients (an) for each coefficient:
where e[k−m] is short for the difference between the reconstructed output and the target error shown in the following equation:
Similarly, using the aforementioned f[cond][m], the following gradient of the squared error (i.e.,
is set equal to zero to determine an optimal value for the target which accounts for the mis-equalization term:
Again, e[k−m] is short for the difference between the reconstructed output and the target error shown in the following equation:
y=ax,
where a corresponds to the equalization target. The equalization may be done using any equalization process known in the art. For example, in one embodiment of the present invention, the equalization is done using a finite impulse response filter with operation governed by one or more filter taps as is known in the art. The resulting equalized data samples are provided to a noise predictive filter circuit that performs noise predictive filtering to yield a noise whitened output (block 223). The noise predictive filtering may be done using any noise predictive filtering circuit governed based on one or more filter taps as is known in the art.
where j indicates one of the equalizer coefficients. In one embodiment of the present invention, the equalizer circuit is a ten tap equalizer filter in which case the value of z is nine. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other equalizer circuits lengths that may be used in accordance with different embodiments of the present invention. Of note, the aforementioned is an ideal equation that may be modified to account for mis-equalization (μ[cond]) that may be considered as part of the target adaptation process discussed below. The modified equation accounting for mis-equalization is as follows:
where m represents each filter tap on a noise predictive filter that performs the f[cond][m] processing. In one particular embodiment of the present invention, the noise predictive filter is a three tap filter length in which case t is equal to two. The error term is then squared (block 244) in accordance with the following equation:
Squared Error=(ErrorTerm)2.
is set equal to zero to determine an optimal value for the equalizer coefficients (an) for each coefficient:
where e[k−m] is short for the difference between the reconstructed output and the target error shown in the following equation:
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/947,931 US8566379B2 (en) | 2010-11-17 | 2010-11-17 | Systems and methods for self tuning target adaptation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/947,931 US8566379B2 (en) | 2010-11-17 | 2010-11-17 | Systems and methods for self tuning target adaptation |
Publications (2)
Publication Number | Publication Date |
---|---|
US20120124119A1 US20120124119A1 (en) | 2012-05-17 |
US8566379B2 true US8566379B2 (en) | 2013-10-22 |
Family
ID=46048786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/947,931 Expired - Fee Related US8566379B2 (en) | 2010-11-17 | 2010-11-17 | Systems and methods for self tuning target adaptation |
Country Status (1)
Country | Link |
---|---|
US (1) | US8566379B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130016846A1 (en) * | 2011-07-11 | 2013-01-17 | Lsi Corporation | Systems and Methods for Area Efficient Noise Predictive Filter Calibration |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8996597B2 (en) | 2011-10-12 | 2015-03-31 | Lsi Corporation | Nyquist constrained digital finite impulse response filter |
US8604960B2 (en) | 2011-10-28 | 2013-12-10 | Lsi Corporation | Oversampled data processing circuit with multiple detectors |
US8719682B2 (en) | 2012-06-15 | 2014-05-06 | Lsi Corporation | Adaptive calibration of noise predictive finite impulse response filter |
US8654474B2 (en) | 2012-06-15 | 2014-02-18 | Lsi Corporation | Initialization for decoder-based filter calibration |
US8819519B2 (en) | 2012-06-28 | 2014-08-26 | Lsi Corporation | Systems and methods for enhanced accuracy NPML calibration |
US8908304B2 (en) | 2012-07-17 | 2014-12-09 | Lsi Corporation | Systems and methods for channel target based CBD estimation |
US8854750B2 (en) | 2012-07-30 | 2014-10-07 | Lsi Corporation | Saturation-based loop control assistance |
US8824076B2 (en) | 2012-08-28 | 2014-09-02 | Lsi Corporation | Systems and methods for NPML calibration |
US8730606B1 (en) | 2012-11-20 | 2014-05-20 | Lsi Corporation | Read channel error correction using multiple calibrators |
US8861113B2 (en) | 2013-02-15 | 2014-10-14 | Lsi Corporation | Noise predictive filter adaptation for inter-track interference cancellation |
US8922934B2 (en) | 2013-03-15 | 2014-12-30 | Lsi Corporation | Systems and methods for transition based equalization |
US8867154B1 (en) | 2013-05-09 | 2014-10-21 | Lsi Corporation | Systems and methods for processing data with linear phase noise predictive filter |
US9324363B2 (en) | 2013-06-05 | 2016-04-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Systems and methods for floating variance branch metric calculation |
US8929010B1 (en) | 2013-08-21 | 2015-01-06 | Lsi Corporation | Systems and methods for loop pulse estimation |
US9129647B2 (en) | 2013-12-19 | 2015-09-08 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Servo channel with equalizer adaptation |
US9214185B1 (en) | 2014-06-29 | 2015-12-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Adaptive filter-based narrowband interference detection, estimation and cancellation |
CN107911322B (en) * | 2017-11-28 | 2019-10-29 | 中国电子科技集团公司第五十四研究所 | A kind of Decision-Feedback Equalization of low complex degree |
Citations (125)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0522578A2 (en) | 1991-07-12 | 1993-01-13 | Pioneer Electronic Corporation | Noise removing circuit |
US5278703A (en) | 1991-06-21 | 1994-01-11 | Digital Equipment Corp. | Embedded servo banded format for magnetic disks for use with a data processing system |
US5278846A (en) | 1990-06-11 | 1994-01-11 | Matsushita Electric Industrial Co., Ltd. | Digital signal decoder |
US5325402A (en) | 1991-04-30 | 1994-06-28 | Nec Corporation | Method and arrangement for estimating data sequences transmsitted using Viterbi algorithm |
US5392299A (en) | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
EP0631277A3 (en) | 1993-06-22 | 1995-02-22 | Quantum Corp | ID-less data sector format and data controller for disk drive. |
US5471500A (en) | 1994-03-08 | 1995-11-28 | At&T Ipm Corp. | Soft symbol decoding |
US5523903A (en) | 1993-12-23 | 1996-06-04 | International Business Machines Corporation | Sector architecture for fixed block disk drive |
US5550870A (en) | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
US5612964A (en) | 1991-04-08 | 1997-03-18 | Haraszti; Tegze P. | High performance, fault tolerant orthogonal shuffle memory and method |
US5701314A (en) | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
US5710784A (en) | 1993-09-24 | 1998-01-20 | Qualcomm Incorporated | Multirate serial viterbi decoder for code division multiple access system applications |
US5712861A (en) | 1994-07-12 | 1998-01-27 | Mitsubishi Denki Kabushiki Kaisha | Error correcting method and decoder with improved reliability |
US5717706A (en) | 1994-03-04 | 1998-02-10 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US5802118A (en) | 1996-07-29 | 1998-09-01 | Cirrus Logic, Inc. | Sub-sampled discrete time read channel for computer storage systems |
US5844945A (en) | 1994-04-12 | 1998-12-01 | Goldstar Co., Ltd. | Viterbi decoder for a high definition television |
US5898710A (en) | 1995-06-06 | 1999-04-27 | Globespan Technologies, Inc. | Implied interleaving, a family of systematic interleavers and deinterleavers |
US5923713A (en) | 1996-02-28 | 1999-07-13 | Sony Corporation | Viterbi decoder |
US5978414A (en) | 1996-07-03 | 1999-11-02 | Matsushita Electric Industrial Co., Ltd. | Transmission rate judging unit |
US5983383A (en) | 1997-01-17 | 1999-11-09 | Qualcom Incorporated | Method and apparatus for transmitting and receiving concatenated code data |
US6005897A (en) | 1997-12-16 | 1999-12-21 | Mccallister; Ronald D. | Data communication system and method therefor |
US6023783A (en) | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US6029264A (en) | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6065149A (en) | 1996-11-21 | 2000-05-16 | Matsushita Electric Industrial Co., Ltd. | Error correction device for a communication system |
US6145110A (en) | 1998-06-22 | 2000-11-07 | Ericsson Inc. | Digital data decoder that derives codeword estimates from soft data |
US6216249B1 (en) | 1999-03-03 | 2001-04-10 | Cirrus Logic, Inc. | Simplified branch metric for reducing the cost of a trellis sequence detector in a sampled amplitude read channel |
US6216251B1 (en) | 1999-04-30 | 2001-04-10 | Motorola Inc | On-chip error detection and correction system for an embedded non-volatile memory array and method of operation |
US6229467B1 (en) | 1999-05-28 | 2001-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Correction static errors in a/d-converter |
US6266795B1 (en) | 1999-05-28 | 2001-07-24 | Lucent Technologies Inc. | Turbo code termination |
US6317472B1 (en) | 1997-08-07 | 2001-11-13 | Samsung Electronics Co., Ltd. | Viterbi decoder |
US6351832B1 (en) | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US6377610B1 (en) | 1997-04-25 | 2002-04-23 | Deutsche Telekom Ag | Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation |
US6381726B1 (en) | 1999-01-04 | 2002-04-30 | Maxtor Corporation | Architecture for soft decision decoding of linear block error correcting codes |
US6438717B1 (en) | 1999-05-26 | 2002-08-20 | 3Com Corporation | High speed parallel bit error rate tester |
US6473878B1 (en) | 1999-05-28 | 2002-10-29 | Lucent Technologies Inc. | Serial-concatenated turbo codes |
US6476989B1 (en) | 1996-07-09 | 2002-11-05 | International Business Machines Corporation | Radial self-propagation pattern generation for disk file servowriting |
US20030063405A1 (en) | 2001-10-02 | 2003-04-03 | Ming Jin | Method and apparatus for detecting media defects |
US20030081693A1 (en) | 2001-07-11 | 2003-05-01 | Raghavan Sreen A. | Low complexity high-speed communications transceiver |
US20030087634A1 (en) | 2001-07-11 | 2003-05-08 | Raghavan Sreen A. | 10165368High-speed multi-channel communications transceiver with inter-channel interference filter |
US20030112896A1 (en) | 2001-07-11 | 2003-06-19 | Raghavan Sreen A. | Multi-channel communications transceiver |
US6625775B1 (en) | 1998-12-10 | 2003-09-23 | Samsung Electronics Co., Ltd. | Encoder/decoder with serial concatenated structure in communication system |
US6657803B1 (en) | 1999-11-22 | 2003-12-02 | Seagate Technology Llc | Method and apparatus for data error recovery using defect threshold detector and viterbi gain |
US6671404B1 (en) | 1997-02-14 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and apparatus for recognizing patterns |
US20040071206A1 (en) | 2002-08-13 | 2004-04-15 | Fujitsu Limited. | Digital filter adaptively learning filter coefficient |
US20040098659A1 (en) | 2002-11-18 | 2004-05-20 | Bjerke Bjorn A. | Rate-compatible LDPC codes |
US6748034B2 (en) | 1997-12-19 | 2004-06-08 | Sony Corporation | Viterbi decoding apparatus and viterbi decoding method |
US6757862B1 (en) | 2000-08-21 | 2004-06-29 | Handspring, Inc. | Method and apparatus for digital data error correction coding |
US6785863B2 (en) | 2002-09-18 | 2004-08-31 | Motorola, Inc. | Method and apparatus for generating parity-check bits from a symbol set |
US6788654B1 (en) | 1998-01-29 | 2004-09-07 | Nippon Hoso Kyokai | Digital data receiver |
US6810502B2 (en) | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US20050010855A1 (en) | 2003-07-09 | 2005-01-13 | Itay Lusky | Reduced complexity decoding for trellis coded modulation |
US20050078399A1 (en) | 2003-10-10 | 2005-04-14 | Seagate Technology Llc | Using data compression to achieve lower linear bit densities on a storage medium |
US20050111540A1 (en) | 2001-11-21 | 2005-05-26 | David Modrie | Adaptive equalizer operating at a sampling rate asynchronous to the data rate |
US20050157780A1 (en) | 2003-12-17 | 2005-07-21 | Werner Carl W. | Signaling system with selectively-inhibited adaptive equalization |
US20050195749A1 (en) | 2004-03-05 | 2005-09-08 | Elmasry George F. | Method and system for capacity analysis for On The Move adhoc wireless packet-switched networks |
US20050216819A1 (en) | 2004-02-19 | 2005-09-29 | Trellisware Technologies, Inc. | Method and apparatus for communications using turbo like codes |
US20050273688A1 (en) | 2004-06-02 | 2005-12-08 | Cenk Argon | Data communication system with multi-dimensional error-correction product codes |
US6980382B2 (en) | 2001-11-09 | 2005-12-27 | Fujitsu Limited | Magnetic disk drive system |
US6986098B2 (en) | 2001-11-20 | 2006-01-10 | Lsi Logic Corporation | Method of reducing miscorrections in a post-processor using column parity checks |
US20060020872A1 (en) | 2004-07-21 | 2006-01-26 | Tom Richardson | LDPC encoding methods and apparatus |
US20060031737A1 (en) | 2004-02-19 | 2006-02-09 | Trellisware Technologies, Inc. | Method and apparatus for communications using improved turbo like codes |
US7010051B2 (en) | 2000-03-24 | 2006-03-07 | Sony Corporation | Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein |
US7047474B2 (en) | 2002-12-23 | 2006-05-16 | Do-Jun Rhee | Decoding concatenated codes via parity bit recycling |
US7058873B2 (en) | 2002-11-07 | 2006-06-06 | Carnegie Mellon University | Encoding method using a low density parity check code with a column weight of two |
US20060123285A1 (en) | 2004-11-16 | 2006-06-08 | De Araujo Daniel F | Dynamic threshold scaling in a communication system |
US20060140311A1 (en) | 2004-12-23 | 2006-06-29 | Agere Systems Inc. | Composite data detector and a method for detecting data |
US7073118B2 (en) | 2001-09-17 | 2006-07-04 | Digeo, Inc. | Apparatus and method for saturating decoder values |
US20060168493A1 (en) | 2005-01-24 | 2006-07-27 | Agere Systems Inc. | Data detection and decoding system and method |
US7093179B2 (en) | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US20060195772A1 (en) | 2005-02-28 | 2006-08-31 | Nils Graef | Method and apparatus for evaluating performance of a read channel |
US20060210002A1 (en) | 2005-03-03 | 2006-09-21 | Xueshi Yang | Timing recovery in a parallel channel communication system |
US7113356B1 (en) | 2002-09-10 | 2006-09-26 | Marvell International Ltd. | Method for checking the quality of servo gray codes |
US20060248435A1 (en) | 2005-04-29 | 2006-11-02 | Haratsch Erich F | Method and apparatus for iterative error-erasure decoding |
US7136244B1 (en) | 2002-02-22 | 2006-11-14 | Western Digital Technologies, Inc. | Disk drive employing data averaging techniques during retry operations to facilitate data recovery |
US20060256670A1 (en) | 2005-05-16 | 2006-11-16 | Samsung Electronics Co., Ltd. | Signal-to-noise ratio measurement apparatus and method for signal read out of optical disc |
US20070011569A1 (en) | 2005-06-20 | 2007-01-11 | The Regents Of The University Of California | Variable-rate low-density parity check codes with constant blocklength |
US7173783B1 (en) | 2001-09-21 | 2007-02-06 | Maxtor Corporation | Media noise optimized detector for magnetic recording |
US7184486B1 (en) | 2000-04-27 | 2007-02-27 | Marvell International Ltd. | LDPC encoder and decoder and method thereof |
US20070047635A1 (en) | 2005-08-24 | 2007-03-01 | Stojanovic Vladimir M | Signaling system with data correlation detection |
US20070047121A1 (en) | 2005-08-26 | 2007-03-01 | Eleftheriou Evangelos S | Read channel apparatus for asynchronous sampling and synchronous equalization |
US7191378B2 (en) | 2002-07-03 | 2007-03-13 | The Directv Group, Inc. | Method and system for providing low density parity check (LDPC) encoding |
US7203015B2 (en) | 2003-07-31 | 2007-04-10 | Kabushiki Kaisha Toshiba | Method and apparatus for decoding sync marks in a disk |
US20070110200A1 (en) | 2005-11-15 | 2007-05-17 | Gokhan Mergen | Equalizer for a receiver in a wireless communication system |
US7257764B2 (en) | 2003-11-03 | 2007-08-14 | Broadcom Corporation | FEC (Forward Error Correction) decoder with dynamic parameters |
US20070230407A1 (en) | 2006-03-31 | 2007-10-04 | Petrie Michael C | Dynamic, adaptive power control for a half-duplex wireless communication system |
US7298570B1 (en) * | 2004-10-27 | 2007-11-20 | Marvell International Ltd. | Asymmetry correction in read signal |
US20070286270A1 (en) | 2001-09-05 | 2007-12-13 | Mediatek Inc. | Read channel apparatus and method for an optical storage system |
US7313750B1 (en) | 2003-08-06 | 2007-12-25 | Ralink Technology, Inc. | Efficient soft decision demapper to minimize viterbi decoder complexity |
US20080049825A1 (en) | 2006-08-25 | 2008-02-28 | Broadcom Corporation | Equalizer with reorder |
US20080055122A1 (en) | 2006-07-31 | 2008-03-06 | Agere Systems Inc. | Systems and Methods for Code Based Error Reduction |
US20080065970A1 (en) | 2006-07-31 | 2008-03-13 | Agere Systems Inc. | Systems and Methods for Code Dependency Reduction |
US20080069373A1 (en) | 2006-09-20 | 2008-03-20 | Broadcom Corporation | Low frequency noise reduction circuit architecture for communications applications |
US7370258B2 (en) | 2005-04-28 | 2008-05-06 | Sandbridge Technologies Inc. | Iterative concatenated convolutional Reed-Solomon decoding method |
US20080168330A1 (en) | 2007-01-08 | 2008-07-10 | Agere Systems Inc. | Systems and methods for prioritizing error correction data |
US7430256B2 (en) | 2003-09-26 | 2008-09-30 | Samsung Electronics Co., Ltd. | Method and apparatus for providing channel state information |
US20080276156A1 (en) | 2007-05-01 | 2008-11-06 | Texas A&M University System | Low density parity check decoder for regular ldpc codes |
EP1814108B1 (en) | 2005-09-12 | 2008-11-26 | Sony Corporation | Noise reducing apparatus, method and program and sound pickup apparatus for electronic equipment |
US7502189B2 (en) | 2000-10-23 | 2009-03-10 | Hitachi Global Storage Technologies Japan, Ltd. | Apparatus, signal-processing circuit and device for magnetic recording system |
US7505537B1 (en) | 2003-03-25 | 2009-03-17 | Marvell International Ltd. | System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter |
US7511910B1 (en) * | 2004-10-27 | 2009-03-31 | Marvell International Ltd. | Asymmetry correction in read signal |
US7509927B2 (en) | 2006-01-25 | 2009-03-31 | Comfort-Sinusverteiler Gmbh | Hydraulic header for a heating system |
US7523375B2 (en) | 2005-09-21 | 2009-04-21 | Distribution Control Systems | Set of irregular LDPC codes with random structure and low encoding complexity |
US20090185643A1 (en) | 2008-01-22 | 2009-07-23 | Fitzpatrick Kelly K | Methods and Apparatus for Map Detection with Reduced Complexity |
US20090199071A1 (en) | 2008-02-05 | 2009-08-06 | Agere Systems Inc. | Systems and Methods for Low Cost LDPC Decoding |
US20090235116A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Regenerating Data from a Defective Medium |
US20090235146A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Using Intrinsic Data for Regenerating Data from a Defective Medium |
US20090259915A1 (en) | 2004-10-12 | 2009-10-15 | Michael Livshitz | Structured low-density parity-check (ldpc) code |
US20090274247A1 (en) | 2008-04-30 | 2009-11-05 | Richard Leo Galbraith | Detection of synchronization mark from output of matched filter upstream of viterbi detector |
US20090273492A1 (en) | 2008-05-02 | 2009-11-05 | Lsi Corporation | Systems and Methods for Queue Based Data Detection and Decoding |
US20100042890A1 (en) | 2008-08-15 | 2010-02-18 | Lsi Corporation | Error-floor mitigation of ldpc codes using targeted bit adjustments |
US20100042877A1 (en) | 2007-10-01 | 2010-02-18 | Weijun Tan | Systems and Methods for Media Defect Detection |
US20100050043A1 (en) | 2006-12-01 | 2010-02-25 | Commissariat A L'energie Atomique | Method and device for decoding ldpc codes and communication apparatus including such device |
US20100061492A1 (en) | 2008-09-05 | 2010-03-11 | Lsi Corporation | Reduced Frequency Data Processing Using a Matched Filter Set Front End |
US20100070837A1 (en) | 2008-09-17 | 2010-03-18 | LSI Corporatrion | Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such |
US7702989B2 (en) | 2006-09-27 | 2010-04-20 | Agere Systems Inc. | Systems and methods for generating erasure flags |
US7712008B2 (en) | 2006-01-26 | 2010-05-04 | Agere Systems Inc. | Systems and methods for error reduction associated with information transfer |
US7738201B2 (en) | 2006-08-18 | 2010-06-15 | Seagate Technology Llc | Read error recovery using soft information |
US20100164764A1 (en) | 2008-05-19 | 2010-07-01 | Ratnakar Aravind Nayak | Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop |
US7752523B1 (en) | 2006-02-13 | 2010-07-06 | Marvell International Ltd. | Reduced-complexity decoding of parity check codes |
US20100185914A1 (en) | 2007-09-28 | 2010-07-22 | Weijun Tan | Systems and Methods for Reduced Complexity Data Processing |
US20110075569A1 (en) | 2008-04-18 | 2011-03-31 | Link_A_Media Devices Corporation | Obtaining parameters for minimizing an error event probability |
US20110080211A1 (en) | 2008-11-20 | 2011-04-07 | Shaohua Yang | Systems and Methods for Noise Reduced Data Detection |
US20110167246A1 (en) | 2010-01-04 | 2011-07-07 | Lsi Corporation | Systems and Methods for Data Detection Including Dynamic Scaling |
US7982985B1 (en) * | 2009-04-17 | 2011-07-19 | Marvell International Ltd. | Method and apparatus for adapting a finite impulse response equalizer in a hard disk drive read channel |
US8416520B1 (en) * | 2007-05-18 | 2013-04-09 | Marvell International Ltd. | Equalization and detection |
-
2010
- 2010-11-17 US US12/947,931 patent/US8566379B2/en not_active Expired - Fee Related
Patent Citations (139)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5278846A (en) | 1990-06-11 | 1994-01-11 | Matsushita Electric Industrial Co., Ltd. | Digital signal decoder |
US5612964A (en) | 1991-04-08 | 1997-03-18 | Haraszti; Tegze P. | High performance, fault tolerant orthogonal shuffle memory and method |
US5325402A (en) | 1991-04-30 | 1994-06-28 | Nec Corporation | Method and arrangement for estimating data sequences transmsitted using Viterbi algorithm |
US5278703A (en) | 1991-06-21 | 1994-01-11 | Digital Equipment Corp. | Embedded servo banded format for magnetic disks for use with a data processing system |
EP0522578A2 (en) | 1991-07-12 | 1993-01-13 | Pioneer Electronic Corporation | Noise removing circuit |
US5392299A (en) | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
EP0631277A3 (en) | 1993-06-22 | 1995-02-22 | Quantum Corp | ID-less data sector format and data controller for disk drive. |
US5710784A (en) | 1993-09-24 | 1998-01-20 | Qualcomm Incorporated | Multirate serial viterbi decoder for code division multiple access system applications |
US5523903A (en) | 1993-12-23 | 1996-06-04 | International Business Machines Corporation | Sector architecture for fixed block disk drive |
US5768044A (en) | 1993-12-23 | 1998-06-16 | International Business Machines Corporation | Zoned recording embedded servo disk drive having no data identification fields and reduced rotational latency |
US5550870A (en) | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
US5717706A (en) | 1994-03-04 | 1998-02-10 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US6041432A (en) | 1994-03-04 | 2000-03-21 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US5471500A (en) | 1994-03-08 | 1995-11-28 | At&T Ipm Corp. | Soft symbol decoding |
US5844945A (en) | 1994-04-12 | 1998-12-01 | Goldstar Co., Ltd. | Viterbi decoder for a high definition television |
US5712861A (en) | 1994-07-12 | 1998-01-27 | Mitsubishi Denki Kabushiki Kaisha | Error correcting method and decoder with improved reliability |
US5898710A (en) | 1995-06-06 | 1999-04-27 | Globespan Technologies, Inc. | Implied interleaving, a family of systematic interleavers and deinterleavers |
US5701314A (en) | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
US5923713A (en) | 1996-02-28 | 1999-07-13 | Sony Corporation | Viterbi decoder |
US6023783A (en) | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US5978414A (en) | 1996-07-03 | 1999-11-02 | Matsushita Electric Industrial Co., Ltd. | Transmission rate judging unit |
US6476989B1 (en) | 1996-07-09 | 2002-11-05 | International Business Machines Corporation | Radial self-propagation pattern generation for disk file servowriting |
US5802118A (en) | 1996-07-29 | 1998-09-01 | Cirrus Logic, Inc. | Sub-sampled discrete time read channel for computer storage systems |
US6065149A (en) | 1996-11-21 | 2000-05-16 | Matsushita Electric Industrial Co., Ltd. | Error correction device for a communication system |
US5983383A (en) | 1997-01-17 | 1999-11-09 | Qualcom Incorporated | Method and apparatus for transmitting and receiving concatenated code data |
US6671404B1 (en) | 1997-02-14 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and apparatus for recognizing patterns |
US6377610B1 (en) | 1997-04-25 | 2002-04-23 | Deutsche Telekom Ag | Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation |
US6029264A (en) | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6317472B1 (en) | 1997-08-07 | 2001-11-13 | Samsung Electronics Co., Ltd. | Viterbi decoder |
US6005897A (en) | 1997-12-16 | 1999-12-21 | Mccallister; Ronald D. | Data communication system and method therefor |
US6097764A (en) | 1997-12-16 | 2000-08-01 | Sicom, Inc. | Pragmatic trellis-coded modulation system and method therefor |
US6748034B2 (en) | 1997-12-19 | 2004-06-08 | Sony Corporation | Viterbi decoding apparatus and viterbi decoding method |
US6788654B1 (en) | 1998-01-29 | 2004-09-07 | Nippon Hoso Kyokai | Digital data receiver |
US6145110A (en) | 1998-06-22 | 2000-11-07 | Ericsson Inc. | Digital data decoder that derives codeword estimates from soft data |
US6625775B1 (en) | 1998-12-10 | 2003-09-23 | Samsung Electronics Co., Ltd. | Encoder/decoder with serial concatenated structure in communication system |
US6381726B1 (en) | 1999-01-04 | 2002-04-30 | Maxtor Corporation | Architecture for soft decision decoding of linear block error correcting codes |
US6216249B1 (en) | 1999-03-03 | 2001-04-10 | Cirrus Logic, Inc. | Simplified branch metric for reducing the cost of a trellis sequence detector in a sampled amplitude read channel |
US6216251B1 (en) | 1999-04-30 | 2001-04-10 | Motorola Inc | On-chip error detection and correction system for an embedded non-volatile memory array and method of operation |
US6438717B1 (en) | 1999-05-26 | 2002-08-20 | 3Com Corporation | High speed parallel bit error rate tester |
US6473878B1 (en) | 1999-05-28 | 2002-10-29 | Lucent Technologies Inc. | Serial-concatenated turbo codes |
US6229467B1 (en) | 1999-05-28 | 2001-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Correction static errors in a/d-converter |
US6266795B1 (en) | 1999-05-28 | 2001-07-24 | Lucent Technologies Inc. | Turbo code termination |
US6351832B1 (en) | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US6657803B1 (en) | 1999-11-22 | 2003-12-02 | Seagate Technology Llc | Method and apparatus for data error recovery using defect threshold detector and viterbi gain |
US7310768B2 (en) | 2000-01-28 | 2007-12-18 | Conexant Systems, Inc. | Iterative decoder employing multiple external code error checks to lower the error floor |
US6810502B2 (en) | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US7010051B2 (en) | 2000-03-24 | 2006-03-07 | Sony Corporation | Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein |
US7184486B1 (en) | 2000-04-27 | 2007-02-27 | Marvell International Ltd. | LDPC encoder and decoder and method thereof |
US6757862B1 (en) | 2000-08-21 | 2004-06-29 | Handspring, Inc. | Method and apparatus for digital data error correction coding |
US7502189B2 (en) | 2000-10-23 | 2009-03-10 | Hitachi Global Storage Technologies Japan, Ltd. | Apparatus, signal-processing circuit and device for magnetic recording system |
US7093179B2 (en) | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US20100002795A1 (en) | 2001-07-11 | 2010-01-07 | Entropic Communications, Inc. | Low Complexity High-Speed Communications Transceiver |
US7403752B2 (en) | 2001-07-11 | 2008-07-22 | Vativ Technologies, Inc. | Multi-channel communications transceiver |
US20030112896A1 (en) | 2001-07-11 | 2003-06-19 | Raghavan Sreen A. | Multi-channel communications transceiver |
US20030134607A1 (en) | 2001-07-11 | 2003-07-17 | Raghavan Sreeen A. | Multi-channel communications transceiver |
US7590168B2 (en) | 2001-07-11 | 2009-09-15 | Entropic Communications, Inc. | Low complexity high-speed communications transceiver |
US7236757B2 (en) | 2001-07-11 | 2007-06-26 | Vativ Technologies, Inc. | High-speed multi-channel communications transceiver with inter-channel interference filter |
US20030087634A1 (en) | 2001-07-11 | 2003-05-08 | Raghavan Sreen A. | 10165368High-speed multi-channel communications transceiver with inter-channel interference filter |
US20030081693A1 (en) | 2001-07-11 | 2003-05-01 | Raghavan Sreen A. | Low complexity high-speed communications transceiver |
US20070286270A1 (en) | 2001-09-05 | 2007-12-13 | Mediatek Inc. | Read channel apparatus and method for an optical storage system |
US7073118B2 (en) | 2001-09-17 | 2006-07-04 | Digeo, Inc. | Apparatus and method for saturating decoder values |
US7173783B1 (en) | 2001-09-21 | 2007-02-06 | Maxtor Corporation | Media noise optimized detector for magnetic recording |
US20030063405A1 (en) | 2001-10-02 | 2003-04-03 | Ming Jin | Method and apparatus for detecting media defects |
US6980382B2 (en) | 2001-11-09 | 2005-12-27 | Fujitsu Limited | Magnetic disk drive system |
US6986098B2 (en) | 2001-11-20 | 2006-01-10 | Lsi Logic Corporation | Method of reducing miscorrections in a post-processor using column parity checks |
US20050111540A1 (en) | 2001-11-21 | 2005-05-26 | David Modrie | Adaptive equalizer operating at a sampling rate asynchronous to the data rate |
US7136244B1 (en) | 2002-02-22 | 2006-11-14 | Western Digital Technologies, Inc. | Disk drive employing data averaging techniques during retry operations to facilitate data recovery |
US7203887B2 (en) | 2002-07-03 | 2007-04-10 | The Directtv Group, Inc. | Method and system for routing in low density parity check (LDPC) decoders |
US7191378B2 (en) | 2002-07-03 | 2007-03-13 | The Directv Group, Inc. | Method and system for providing low density parity check (LDPC) encoding |
US20040071206A1 (en) | 2002-08-13 | 2004-04-15 | Fujitsu Limited. | Digital filter adaptively learning filter coefficient |
US7113356B1 (en) | 2002-09-10 | 2006-09-26 | Marvell International Ltd. | Method for checking the quality of servo gray codes |
US6785863B2 (en) | 2002-09-18 | 2004-08-31 | Motorola, Inc. | Method and apparatus for generating parity-check bits from a symbol set |
US7058873B2 (en) | 2002-11-07 | 2006-06-06 | Carnegie Mellon University | Encoding method using a low density parity check code with a column weight of two |
US20040098659A1 (en) | 2002-11-18 | 2004-05-20 | Bjerke Bjorn A. | Rate-compatible LDPC codes |
US7047474B2 (en) | 2002-12-23 | 2006-05-16 | Do-Jun Rhee | Decoding concatenated codes via parity bit recycling |
US7505537B1 (en) | 2003-03-25 | 2009-03-17 | Marvell International Ltd. | System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter |
US20050010855A1 (en) | 2003-07-09 | 2005-01-13 | Itay Lusky | Reduced complexity decoding for trellis coded modulation |
US7203015B2 (en) | 2003-07-31 | 2007-04-10 | Kabushiki Kaisha Toshiba | Method and apparatus for decoding sync marks in a disk |
US7313750B1 (en) | 2003-08-06 | 2007-12-25 | Ralink Technology, Inc. | Efficient soft decision demapper to minimize viterbi decoder complexity |
US7430256B2 (en) | 2003-09-26 | 2008-09-30 | Samsung Electronics Co., Ltd. | Method and apparatus for providing channel state information |
US20050078399A1 (en) | 2003-10-10 | 2005-04-14 | Seagate Technology Llc | Using data compression to achieve lower linear bit densities on a storage medium |
US7257764B2 (en) | 2003-11-03 | 2007-08-14 | Broadcom Corporation | FEC (Forward Error Correction) decoder with dynamic parameters |
US20050157780A1 (en) | 2003-12-17 | 2005-07-21 | Werner Carl W. | Signaling system with selectively-inhibited adaptive equalization |
US20050216819A1 (en) | 2004-02-19 | 2005-09-29 | Trellisware Technologies, Inc. | Method and apparatus for communications using turbo like codes |
US20060031737A1 (en) | 2004-02-19 | 2006-02-09 | Trellisware Technologies, Inc. | Method and apparatus for communications using improved turbo like codes |
US20050195749A1 (en) | 2004-03-05 | 2005-09-08 | Elmasry George F. | Method and system for capacity analysis for On The Move adhoc wireless packet-switched networks |
US20050273688A1 (en) | 2004-06-02 | 2005-12-08 | Cenk Argon | Data communication system with multi-dimensional error-correction product codes |
US20060020872A1 (en) | 2004-07-21 | 2006-01-26 | Tom Richardson | LDPC encoding methods and apparatus |
US20090259915A1 (en) | 2004-10-12 | 2009-10-15 | Michael Livshitz | Structured low-density parity-check (ldpc) code |
US7298570B1 (en) * | 2004-10-27 | 2007-11-20 | Marvell International Ltd. | Asymmetry correction in read signal |
US7511910B1 (en) * | 2004-10-27 | 2009-03-31 | Marvell International Ltd. | Asymmetry correction in read signal |
US20060123285A1 (en) | 2004-11-16 | 2006-06-08 | De Araujo Daniel F | Dynamic threshold scaling in a communication system |
US20060140311A1 (en) | 2004-12-23 | 2006-06-29 | Agere Systems Inc. | Composite data detector and a method for detecting data |
US20060168493A1 (en) | 2005-01-24 | 2006-07-27 | Agere Systems Inc. | Data detection and decoding system and method |
US20060195772A1 (en) | 2005-02-28 | 2006-08-31 | Nils Graef | Method and apparatus for evaluating performance of a read channel |
US20060210002A1 (en) | 2005-03-03 | 2006-09-21 | Xueshi Yang | Timing recovery in a parallel channel communication system |
US7370258B2 (en) | 2005-04-28 | 2008-05-06 | Sandbridge Technologies Inc. | Iterative concatenated convolutional Reed-Solomon decoding method |
US7587657B2 (en) | 2005-04-29 | 2009-09-08 | Agere Systems Inc. | Method and apparatus for iterative error-erasure decoding |
US20060248435A1 (en) | 2005-04-29 | 2006-11-02 | Haratsch Erich F | Method and apparatus for iterative error-erasure decoding |
US20060256670A1 (en) | 2005-05-16 | 2006-11-16 | Samsung Electronics Co., Ltd. | Signal-to-noise ratio measurement apparatus and method for signal read out of optical disc |
US20070011569A1 (en) | 2005-06-20 | 2007-01-11 | The Regents Of The University Of California | Variable-rate low-density parity check codes with constant blocklength |
US20070047635A1 (en) | 2005-08-24 | 2007-03-01 | Stojanovic Vladimir M | Signaling system with data correlation detection |
US20070047121A1 (en) | 2005-08-26 | 2007-03-01 | Eleftheriou Evangelos S | Read channel apparatus for asynchronous sampling and synchronous equalization |
EP1814108B1 (en) | 2005-09-12 | 2008-11-26 | Sony Corporation | Noise reducing apparatus, method and program and sound pickup apparatus for electronic equipment |
US7523375B2 (en) | 2005-09-21 | 2009-04-21 | Distribution Control Systems | Set of irregular LDPC codes with random structure and low encoding complexity |
US20070110200A1 (en) | 2005-11-15 | 2007-05-17 | Gokhan Mergen | Equalizer for a receiver in a wireless communication system |
US7509927B2 (en) | 2006-01-25 | 2009-03-31 | Comfort-Sinusverteiler Gmbh | Hydraulic header for a heating system |
US7712008B2 (en) | 2006-01-26 | 2010-05-04 | Agere Systems Inc. | Systems and methods for error reduction associated with information transfer |
US7752523B1 (en) | 2006-02-13 | 2010-07-06 | Marvell International Ltd. | Reduced-complexity decoding of parity check codes |
US20070230407A1 (en) | 2006-03-31 | 2007-10-04 | Petrie Michael C | Dynamic, adaptive power control for a half-duplex wireless communication system |
US20080065970A1 (en) | 2006-07-31 | 2008-03-13 | Agere Systems Inc. | Systems and Methods for Code Dependency Reduction |
US7802163B2 (en) | 2006-07-31 | 2010-09-21 | Agere Systems Inc. | Systems and methods for code based error reduction |
US20080055122A1 (en) | 2006-07-31 | 2008-03-06 | Agere Systems Inc. | Systems and Methods for Code Based Error Reduction |
US7801200B2 (en) | 2006-07-31 | 2010-09-21 | Agere Systems Inc. | Systems and methods for code dependency reduction |
US7738201B2 (en) | 2006-08-18 | 2010-06-15 | Seagate Technology Llc | Read error recovery using soft information |
US20080049825A1 (en) | 2006-08-25 | 2008-02-28 | Broadcom Corporation | Equalizer with reorder |
US20080069373A1 (en) | 2006-09-20 | 2008-03-20 | Broadcom Corporation | Low frequency noise reduction circuit architecture for communications applications |
US7702989B2 (en) | 2006-09-27 | 2010-04-20 | Agere Systems Inc. | Systems and methods for generating erasure flags |
US20100050043A1 (en) | 2006-12-01 | 2010-02-25 | Commissariat A L'energie Atomique | Method and device for decoding ldpc codes and communication apparatus including such device |
US20080168330A1 (en) | 2007-01-08 | 2008-07-10 | Agere Systems Inc. | Systems and methods for prioritizing error correction data |
US20080276156A1 (en) | 2007-05-01 | 2008-11-06 | Texas A&M University System | Low density parity check decoder for regular ldpc codes |
US20080301521A1 (en) | 2007-05-01 | 2008-12-04 | Texas A&M University System | Low density parity check decoder for irregular ldpc codes |
US8416520B1 (en) * | 2007-05-18 | 2013-04-09 | Marvell International Ltd. | Equalization and detection |
US20100185914A1 (en) | 2007-09-28 | 2010-07-22 | Weijun Tan | Systems and Methods for Reduced Complexity Data Processing |
US20100042877A1 (en) | 2007-10-01 | 2010-02-18 | Weijun Tan | Systems and Methods for Media Defect Detection |
US20090185643A1 (en) | 2008-01-22 | 2009-07-23 | Fitzpatrick Kelly K | Methods and Apparatus for Map Detection with Reduced Complexity |
US20090199071A1 (en) | 2008-02-05 | 2009-08-06 | Agere Systems Inc. | Systems and Methods for Low Cost LDPC Decoding |
US20090235146A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Using Intrinsic Data for Regenerating Data from a Defective Medium |
US20090235116A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Regenerating Data from a Defective Medium |
US20110075569A1 (en) | 2008-04-18 | 2011-03-31 | Link_A_Media Devices Corporation | Obtaining parameters for minimizing an error event probability |
US20090274247A1 (en) | 2008-04-30 | 2009-11-05 | Richard Leo Galbraith | Detection of synchronization mark from output of matched filter upstream of viterbi detector |
US20090273492A1 (en) | 2008-05-02 | 2009-11-05 | Lsi Corporation | Systems and Methods for Queue Based Data Detection and Decoding |
US20100164764A1 (en) | 2008-05-19 | 2010-07-01 | Ratnakar Aravind Nayak | Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop |
US20100042890A1 (en) | 2008-08-15 | 2010-02-18 | Lsi Corporation | Error-floor mitigation of ldpc codes using targeted bit adjustments |
US20100061492A1 (en) | 2008-09-05 | 2010-03-11 | Lsi Corporation | Reduced Frequency Data Processing Using a Matched Filter Set Front End |
US20100070837A1 (en) | 2008-09-17 | 2010-03-18 | LSI Corporatrion | Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such |
US20110080211A1 (en) | 2008-11-20 | 2011-04-07 | Shaohua Yang | Systems and Methods for Noise Reduced Data Detection |
US7982985B1 (en) * | 2009-04-17 | 2011-07-19 | Marvell International Ltd. | Method and apparatus for adapting a finite impulse response equalizer in a hard disk drive read channel |
US20110167246A1 (en) | 2010-01-04 | 2011-07-07 | Lsi Corporation | Systems and Methods for Data Detection Including Dynamic Scaling |
Non-Patent Citations (56)
Title |
---|
Amer et al "Design Issues for a Shingled Write Disk System" MSST IEEE 26th Symposium May 2010. |
Bahl, et al "Optimal decoding of linear codes for Minimizing symbol error rate", IEEE Trans. Inform. Theory, vol. 20, pp. 284-287, Mar. 1974. |
Casado et al., Multiple-rate low-denstiy parity-check codes with constant blocklength, IEEE Transations on communications, Jan. 2009, vol. 57, pp. 75-83. |
Collins and Hizlan, "Determinate State Convolutional Codes" IEEE Transactions on Communications, Dec. 1993. |
Eleftheriou, E. et al., "Low Density Parity-Check Codes for Digital Subscriber Lines", Proc ICC 2002, pp. 1752-1757. |
Fisher, R et al., "Adaptive Thresholding"[online] 2003 [retrieved on May 28, 2010] Retrieved from the Internet <URL:http://homepages.inf.ed.ac.uk/rbf/HIPR2/adpthrsh.htm. |
Fossnorier, Marc P.C. "Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Maricies" IEEE Transactions on Information Theory, vol. 50, No. 8 Aug. 8, 2004. |
Gibson et al "Directions for Shingled-Write and Two-Dimensional Magnetic Recording System" Architectures: Synergies with Solid-State Disks Carnegie Mellon Univ. May 1, 2009. |
Hagenauer, J. et al. A Viterbi Algorithm with Soft-Decision Outputs and its Applications in Proc. IEEE Globecom, pp. 47. 11-47 Dallas, TX Nov. 1989. |
Han and Ryan, "Pinning Techniques for Low-Floor Detection/Decoding of LDPC-Coded Partial Response Channels", 5th International Symposium on Turbo Codes &Related Topics, 2008. |
K. Gunnam "Area and Energy Efficient VLSI Architectures for Low-Density Parity-Check Decoders Using an On-The-Fly Computation" dissertation at Texas A&M University, Dec. 2006. |
K. Gunnam et al., "Next Generation iterative LDPC solutions for magnetic recording storage", invited paper. The Asilomar Conference on Signals, Systems, and Computers, Nov. 2008. |
K. Gunnam et al., "Value-Reuse Properties of Min-Sum for GF(q)" (dated Oct. 2006) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. |
K. Gunnam et al., "Value-Reuse Properties of Min-Sum for GF(q)"(dated Jul. 2008) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. |
Lee et al., "Partial Zero-Forcing Adaptive MMSE Receiver for DS-CDMA Uplink in Multicell Environments" IEEE Transactions on Vehicular Tech. vol. 51, No. 5, Sep. 2002. |
Lin et al "An efficient VLSI Architecture for non binary LDPC decoders"-IEEE Transaction on Circuits and Systems II vol. 57, Issue 1 (Jan. 2010) pp. 51-55. |
Mohsenin et al., "Split Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture", pp. 1-6, printed from www.ece.ucdavis.edu on Jul. 9, 2007. |
Moon et al, "Pattern-dependent noise prediction in signal-dependent Noise," IEEE JSAC, vol. 19, No. 4 pp. 730-743, Apr. 2001. |
Perisa et al "Frequency Offset Estimation Based on Phase Offsets Between Sample Correlations" Dept. of Info. Tech. University of Ulm 2005. |
Sari H et al., "Transmission Techniques for Digital Terrestrial TV Broadcasting" IEEE Communications Magazine, IEEE Service Center Ny, NY vol. 33, No. 2 Feb. 1995. |
Selvarathinam, A.: "Low Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels" IEEE International Conference on Computer Design (ICCD '03) 2003. |
Shu Lin, Ryan, "Channel Codes, Classical and Modern" 2009, Cambridge University Press, pp. 213-222. |
U.S. Appl. No. 11/461,026, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 11/461,198, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 11/461,283, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 12/540,283, filed Aug. 13, 2009, Liu, et al. |
U.S. Appl. No. 12/652,201, filed Jan. 5, 2010, Mathew, et al. |
U.S. Appl. No. 12/763,050, filed Apr. 19, 2010, Ivkovic, et al. |
U.S. Appl. No. 12/792,555, filed Jun. 2, 2010, Liu, et al. |
U.S. Appl. No. 12/887,317, filed Sep. 2, 2010, Xia et al. |
U.S. Appl. No. 12/887,330, filed Sep. 21, 2010, Zhang, et al. |
U.S. Appl. No. 12/887,369, filed Sep. 21, 2010, Liu et al. |
U.S. Appl. No. 12/901,742, filed Oct. 11, 2010, Yang. |
U.S. Appl. No. 12/901,816, filed Oct. 11, 2010, Li et al. |
U.S. Appl. No. 12/917,756, filed Nov. 2, 2010, Miladinovic et al. |
U.S. Appl. No. 12/947,931, filed Nov. 17, 2010, Yang, Shaohua. |
U.S. Appl. No. 12/947,942, filed Dec. 20, 2010, Liao et al. |
U.S. Appl. No. 12/947,947, filed Nov. 17, 2010, Ivkovic et al. |
U.S. Appl. No. 12/992,948, filed Nov. 16, 2010, Yang et al. |
Unknown, "Auto threshold and Auto Local Threshold" [online] [retrieved May 28, 2010] Retrieved from the Internet: <URL:http://www. density.bham.ac.uk/landinig/software/autot. |
Vasic, B., "High-Rate Girth-Eight Codes on Rectangular Integer Lattices", IEEE Trans. Communications, vol. 52, Aug. 2004, pp. 1248-1252. |
Vasic, B., "High-Rate Low-Density Parity-Check Codes Based on Anti-Pasch Affine Geometries," Proc ICC 2002, pp. 1332-1336. |
Wang Y et al., "A Soft Decision Decoding Scheme for Wireless COFDM With Application to DVB-T" IEEE Trans. on Consumer elec., IEEE Service Center, NY,NY vo. 50, No. 1 Feb. 2004. |
Weon-Cheol Lee et al., "Vitierbi Decoding Method Using Channel State Info. in COFDM System" IEEE Trans. on Consumer Elect., IEEE Service Center, NY, NY vol. 45, No. 3 Aug. 1999. |
Xia et al, "A Chase-GMD algorithm of Reed-Solomon codes on perpendicular channels", IEEE Transactions on Magnetics, vol. 42 pp. 2603-2605, Oct. 2006. |
Xia et al, "Reliability-based Reed-Solomon decoding for magnetic recording channels", IEEE International Conference on Communication pp. 1977-1981, May 2008. |
Yeo et al., "VLSI Architecture for Iterative Decoders in Magnetic Storage Channels", Mar. 2001, pp. 748-755, IEEE trans. Magnetics, vol. 37, No. 2. |
Youn, et al. "BER Perform. Due to Irrreg. of Row-Weight Distrib. of the Parity-Chk. Matrix in Irreg. LDPC Codes for 10-Gb/s Opt. Signls" Jrnl of Lightwave Tech., vol. 23, Sep. 2005. |
Zhong et al., "Area-Efficient Min-Sum Decoder VLSI Architecture for High-Rate QC-LDPC Codes in Magnetic Recording", pp. 1-15, Submitted 2006, not yet published. |
Zhong et al., "Design of VLSI Implementation-Oriented LDPC Codes", IEEE, pp. 670-673, 2003. |
Zhong et al., "High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor", ISCAS, IEEE pp. 3546-3549, May 2006. |
Zhong et al., "Iterative MAX-LOG-MAP and LDPC Detector/Decoder Hardware Implementation for Magnetic Read Channel", SRC TECHRON, pp. 1-4, Oct. 2005. |
Zhong et al., "Joint Code-Encoder Design for LPDC Coding System VLSI Implementation", ISCAS, IEEE pp. 389-392, May 2004. |
Zhong et al., "Quasi Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VSLI Implementation", IEEE Transactions on Magnetics, v. 43, pp. 1118-1123, Mar. 2007. |
Zhong, "Block-LDPC: A Practical LDPC Coding System Design Approach", IEEE Trans. on Circuits, Regular Papers, vol. 5, No. 4, pp. 766-775, Apr. 2005. |
Zhong, "VLSI Architecture of LDPC Based Signal Detection and Coding System for Magnetic Recording Channel", Thesis, RPI, Troy, NY, pp. 1-95, May 2006. |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130016846A1 (en) * | 2011-07-11 | 2013-01-17 | Lsi Corporation | Systems and Methods for Area Efficient Noise Predictive Filter Calibration |
US8762440B2 (en) * | 2011-07-11 | 2014-06-24 | Lsi Corporation | Systems and methods for area efficient noise predictive filter calibration |
Also Published As
Publication number | Publication date |
---|---|
US20120124119A1 (en) | 2012-05-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8566379B2 (en) | Systems and methods for self tuning target adaptation | |
US8611033B2 (en) | Systems and methods for selective decoder input data processing | |
US8670955B2 (en) | Systems and methods for reliability assisted noise predictive filtering | |
US8261171B2 (en) | Systems and methods for diversity combined data detection | |
US8667039B2 (en) | Systems and methods for variance dependent normalization for branch metric calculation | |
US8699167B2 (en) | Systems and methods for data detection using distance based tuning | |
US9026572B2 (en) | Systems and methods for anti-causal noise predictive filtering in a data channel | |
US8749908B2 (en) | Systems and methods for sync mark detection | |
US8614858B2 (en) | Systems and methods for sync mark detection metric computation | |
US8539328B2 (en) | Systems and methods for noise injection driven parameter selection | |
US7872823B2 (en) | AGC loop with weighted zero forcing and LMS error sources and methods for using such | |
US8693119B2 (en) | Energy-based inter-track interference cancellation | |
US8767333B2 (en) | Systems and methods for pattern dependent target adaptation | |
US8604960B2 (en) | Oversampled data processing circuit with multiple detectors | |
US8762440B2 (en) | Systems and methods for area efficient noise predictive filter calibration | |
US20130024163A1 (en) | Systems and Methods for Early Stage Noise Compensation in a Detection Channel | |
US8630053B2 (en) | Systems and methods for parameter modification during data processing retry | |
US8904070B2 (en) | Systems and methods for digital MRA compensation | |
US8929017B2 (en) | Systems and methods for SNR measurement using equalized data | |
US8838660B2 (en) | Systems and methods for reducing filter sensitivities | |
US9553739B1 (en) | Loop adaptation control with pattern detection | |
US8976471B1 (en) | Systems and methods for two stage tone reduction | |
US8908304B2 (en) | Systems and methods for channel target based CBD estimation | |
US20130335844A1 (en) | Systems and Methods for Hybrid MRA Compensation | |
US9472237B1 (en) | Systems and methods for side-track aided data recovery |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LSI CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YANG, SHAOHUA;REEL/FRAME:025381/0165 Effective date: 20101110 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388 Effective date: 20140814 |
|
AS | Assignment |
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047230/0910 Effective date: 20180509 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047351/0384 Effective date: 20180905 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:049248/0558 Effective date: 20180905 |
|
AS | Assignment |
Owner name: BROADCOM INTERNATIONAL PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED;REEL/FRAME:053771/0901 Effective date: 20200826 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20211022 |