US8501543B1 - Direct-write wafer level chip scale package - Google Patents

Direct-write wafer level chip scale package Download PDF

Info

Publication number
US8501543B1
US8501543B1 US13/472,961 US201213472961A US8501543B1 US 8501543 B1 US8501543 B1 US 8501543B1 US 201213472961 A US201213472961 A US 201213472961A US 8501543 B1 US8501543 B1 US 8501543B1
Authority
US
United States
Prior art keywords
dielectric layer
conductive layer
layer
conductive
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/472,961
Inventor
Christopher John Berry
Ronald Patrick Huemoeller
David Jon Hiner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amkor Technology Singapore Holding Pte Ltd
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/810,799 external-priority patent/US7723210B2/en
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Priority to US13/472,961 priority Critical patent/US8501543B1/en
Application granted granted Critical
Publication of US8501543B1 publication Critical patent/US8501543B1/en
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. PATENT SECURITY AGREEMENT Assignors: AMKOR TECHNOLOGY, INC.
Assigned to BANK OF AMERICA, N.A., AS AGENT reassignment BANK OF AMERICA, N.A., AS AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. reassignment AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314Guiding structures outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Definitions

  • the present invention relates to the field of integrated circuit packaging and, in particular, to wafer level chip scale packaging processes and structures.
  • wafer level chip scale packaging techniques typically involved adding various layers to integrated circuit wafers and then patterning the layers using a complex series of masking and photo etching steps.
  • additive layers were spun-on, sprayed-on as a vapor, or printed on the integrated circuit wafers.
  • prior art techniques also typically required the use of photoimagable materials such as CyclotoneTM products or polyimides and the use of extensive photo-definition processes, i.e., masking and photo-etching of the layers.
  • the prior art photoimagable materials had to be of specific and limited thickness for the prior art processes to work, and be practical. In the prior art, these thicknesses were typically limited to less than twenty (20) microns. Consequently, the resulting structures typically offered limited flexibility and opportunity for “compliance” between interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
  • a method and structure according to one embodiment of the invention provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings.
  • DWWLCSP Direct Write Wafer Level Chip Scale Package
  • a Direct Write Wafer Level Chip Scale Package is created by first preparing a silicon wafer and then a dielectric layer is attached directly to the wafer.
  • the dielectric layer is a layer of InterVia® 8000 or a similar material.
  • the dielectric layer is then ablated to form vias and trench patterns.
  • the surface of the dielectric layer is then plated with a conductive layer, such as copper, or another suitable metal, to fill in all of the related via and trench patterns and thereby form conductive patterns and connections to the die pads.
  • the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads. In one embodiment of the invention, these patterns are then processed through standard solder application techniques such as solder masking and/or other solder application methods known in the art.
  • the dielectric layer is ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed.
  • This particular structure provides a cushion of dielectric material between sub-vias for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • a Direct Write Wafer Level Chip Scale Package is created by first preparing a silicon wafer and then a dielectric layer is attached to the wafer using an adhesive layer. The dielectric layer is then ablated to form via and trench patterns. The surface of the dielectric layer is then plated with a conductive layer, such as copper or another suitable conductive material, to fill in all of via and trench patterns and thereby form conductor patterns and connections to the die pads. According to one embodiment of the invention, the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads. In one embodiment of the invention, these patterns are then processed through any standard solder application techniques, such as solder masking and/or other solder application methods known in the art.
  • the dielectric and conductive layers of the invention can be laminated, which enables the creation of multilayer Direct Write Wafer Level Chip Scale Package structures at lower costs, and with improved reliability of the finished Direct Write Wafer Level Chip Scale Packaged electronic component.
  • the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric and conductive materials applied directly onto the wafer surface.
  • the dielectric layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of indirect materials required for the masking and etching steps.
  • the dielectric layers can be attached to the wafer with an adhesive layer and this adhesive layer need not be patterned using standard techniques.
  • the conductive layer building process is solely additive, using the ablated dielectric layer as its mask. Consequently, the need for subsequent patterning and etching is eliminated.
  • the materials used need not be photoimagable materials, the materials need not be of the prior art specified limited thickness. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • the dielectric layer is ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. This particular structure provides a cushion of dielectric material between sub-vias for thermal expansion and therefore provides better compliance properties.
  • FIG. 1A shows a silicon wafer, including one or more electronic components such as integrated circuits;
  • FIG. 1B shows the silicon wafer of FIG. 1A , including a dielectric layer applied to the silicon wafer in accordance with the principles of one embodiment of the present invention
  • FIG. 1C shows the silicon wafer of FIG. 1B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention
  • FIG. 1D shows a layer of conductive material applied to the structure of FIG. 1C in accordance with the principles of one embodiment of the present invention
  • FIG. 1E shows the structure of FIG. 1D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention
  • FIG. 1F shows the structure of FIG. 1E with solder bumps attached to points on the conductive layer in accordance with the principles of one embodiment of the present invention
  • FIG. 1G shows the structure of FIG. 1F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention
  • FIG. 1H shows a singulated Direct Write Wafer Level Chip Scale Package in accordance with the principles of one embodiment of the present invention
  • FIG. 2A shows a silicon wafer, including an adhesive layer applied in to the silicon wafer in accordance with the principles of one embodiment of the present invention
  • FIG. 2B shows the structure of FIG. 2A , including a dielectric layer applied to the silicon wafer using the adhesive layer of FIG. 2A in accordance with the principles of one embodiment of the present invention
  • FIG. 2C shows the structure of FIG. 2B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention
  • FIG. 2D shows a layer of conductive material applied to the structure of FIG. 2C in accordance with the principles of one embodiment of the present invention
  • FIG. 2E shows the structure of FIG. 2D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention
  • FIG. 2F shows the structure of FIG. 2E with solder bumps attached to points on the conductive layer in accordance with the principles of one embodiment of the present invention
  • FIG. 2G shows the structure of FIG. 2F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention
  • FIG. 2H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component in accordance with the principles of one embodiment of the present invention
  • FIG. 3A shows the silicon wafer, including an adhesive layer applied in to the silicon wafer in accordance with the principles of one embodiment of the present invention
  • FIG. 3B shows the structure of FIG. 3A , including a dielectric layer applied to the silicon wafer using the adhesive layer of FIG. 3A in accordance with the principles of one embodiment of the present invention
  • FIG. 3C shows the structure of FIG. 3B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention
  • FIG. 3D shows a layer of conductive material applied to the structure of FIG. 3C in accordance with the principles of one embodiment of the present invention
  • FIG. 3E shows the structure of FIG. 3D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention
  • FIG. 3F shows the structure of FIG. 3E , including a second dielectric layer applied in accordance with the principles of one embodiment of the present invention
  • FIG. 3G shows the structure of FIG. 3F after the second dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention
  • FIG. 3H shows a second layer of conductive material applied to the structure of FIG. 3G in accordance with the principles of one embodiment of the present invention
  • FIG. 3I shows the structure of FIG. 3H after the second layer of conductive material has been etched using a controlled etching process in accordance with the principles of one embodiment of the present invention
  • FIG. 3J shows the structure of FIG. 3I with solder bumps attached to points on the second conductive layer in accordance with the principles of one embodiment of the present invention
  • FIG. 3K shows the structure of FIG. 3J being singulated into multi-layer Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention
  • FIG. 3L shows a singulated multi-layer Direct Write Wafer Level Chip Scale Packaged electronic component in accordance with the principles of one embodiment of the present invention
  • FIG. 3M shows the singulated multi-layer Direct Write Wafer Level Chip Scale Packaged electronic component of FIG. 3L in detail in accordance with the principles of one embodiment of the present invention
  • FIG. 4A shows a detail portion of a Direct Write Wafer Level Chip Scale Packaged electronic component wherein a dielectric layer has been ablated in such a way as to form patterned vias;
  • FIG. 4B shows a detail portion of a Direct Write Wafer Level Chip Scale Packaged electronic component wherein a metal buildup region is formed on bonding points of a conductive layer second surface.
  • a method and structure according to one embodiment of the invention provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent coatings/layers and direct write techniques to pattern these coatings/layers.
  • DWWLCSP Direct Write Wafer Level Chip Scale Package
  • a Direct Write Wafer Level Chip Scale Package ( 121 in FIG. 1H ) is created by first preparing a silicon wafer ( 100 in FIG. 1A ) and then a dielectric layer, also called a first dielectric layer, ( 107 in FIG. 1B ) is attached directly to the wafer. The dielectric layer is then ablated to form vias and trench patterns ( 104 in FIG. 1C ). In one embodiment of the invention, the dielectric layer ( 407 in FIG. 4B ) is ablated in such a way as to form patterned vias ( 411 in FIG. 4B ) to the die pads ( 498 in FIG. 4B ). The vias can be patterned in any way that the user of the invention deems necessary.
  • a pattern of multiple smaller cylindrical or rectangular sub-vias ( 416 A, 416 B, 416 C in FIG. 4A ) are formed.
  • This particular structure provides a cushion of dielectric material ( 407 A and 407 B) between sub-vias for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • the surface of the dielectric layer is then plated with a conductive layer, also called a first conductive layer, ( 111 in FIG.
  • a Direct Write Wafer Level Chip Scale Package ( 221 in FIG. 2H ) is created by first preparing a silicon wafer ( 200 in FIG. 2A ) and then a dielectric layer, also called a first dielectric layer, ( 207 in FIG. 2B ) is attached to the wafer using an adhesive ( 204 in FIG. 2B ). The dielectric layer is then ablated to form via and trench patterns ( FIG. 2C ). In one embodiment of the invention, the dielectric layer is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary.
  • a pattern of multiple smaller cylindrical or rectangular vias are formed.
  • this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • the surface of the dielectric layer is then plated with a conductive layer, also called a first conductive layer, ( 211 in FIG. 2D ), such as copper or another suitable conductive material, to fill in all of via and trench patterns and thereby form conductor patterns and connections to the die pads ( FIG. 2D ).
  • the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads ( FIG. 2E ). In one embodiment of the invention, these patterns are then processed through any standard solder application techniques ( FIG. 2F ).
  • the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric and conductive materials applied directly onto the wafer surface.
  • the dielectric layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention.
  • the materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of the masking and etching steps.
  • FIG. 1A shows a silicon wafer 100 that has been prepared for the packaging process and includes bonding locations, or pads, 105 .
  • silicon wafer 100 has a silicon wafer first surface 101 and a silicon wafer second surface 103 .
  • Silicon wafers are well known to those of skill in the art and typically include one or more electronic components, such as integrated circuits, (not shown) formed in, or on, silicon wafer 100 by methods well known to those of skill in the art.
  • FIG. 1B shows silicon wafer 100 of FIG. 1A including a dielectric layer, also called a first dielectric layer, 107 applied directly to silicon wafer second surface 103 of silicon wafer 100 in accordance with the principles of one embodiment of the present invention.
  • a dielectric layer first surface 110 of dielectric layer 107 is applied directly to silicon wafer second surface 103 of silicon wafer 100 .
  • dielectric layer 107 is a polymer layer.
  • dielectric layer 107 is made of InterVia® 8000 material and has a thickness of approximately forty (40) microns.
  • InterVia® 8000 material has a thickness of approximately forty (40) microns.
  • those of skill in the art will readily recognize, in light of this disclosure, that many different types of materials and thicknesses can be used for dielectric layer 107 .
  • dielectric layer 107 is then ablated, using a laser or other ablation means, to form various predetermined patterns 104 in dielectric layer 107 .
  • FIG. 1C shows the structure of FIG. 1B after dielectric layer 107 has been ablated to form vias and trenches 104 in accordance with the principles of one embodiment of the present invention.
  • dielectric layer 107 is ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary.
  • a pattern or multiple smaller cylindrical or rectangular vias are formed.
  • this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric layer 107 laminated directly onto the silicon wafer second surface 103 and the dielectric layer 107 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
  • a conductive layer, also called a first conductive layer, 111 is then applied to silicon wafer second surface 103 and dielectric layer second surface 109 .
  • conductive layer 111 is copper, or another suitable metal, and is applied to an approximate thickness of approximately five (5) microns above dielectric layer second surface 109 .
  • conductive layer 111 includes a conductive layer first surface 115 that is in electrical contact with bonding locations 105 and a conductive layer second surface 113 .
  • conductive layer 111 is then etched away in a controlled etch process that results in conductive layer second surface 113 being made level with dielectric layer second surface 109 .
  • electrically conductive traces and vias 116 are formed As discussed in more detail below with respect to FIG.
  • portions of conductive layer second surface 113 can, in one embodiment of the invention, be left higher that dielectric layer second surface 109 to facilitate better bonding and compliance.
  • FIG. 1E shows the structure of FIG. 1D after conductive layer 111 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention.
  • Depth controlled etching processes such as that used to bring conductive layer second surface 113 level with, or with potions slightly raised above, dielectric layer second surface 109 are well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
  • the conductive layer 111 building process is solely additive using the ablated dielectric layer 107 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
  • the materials used for dielectric layer 107 need not be photoimagable materials, the materials need not be of the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
  • FIG. 1F shows the structure of FIG. 1E with solder bumps 119 attached to selected bonding points 198 on conductive layer 111 using standard bumping techniques in accordance with the principles of one embodiment of the present invention.
  • FIG. 1G shows the structure of FIG. 1F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components 121 , 123 and 125 using a standard cutting means 127 such as a saw.
  • FIG. 1H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component 121 in accordance with the principles of one embodiment of the present invention.
  • a silicon wafer 200 is first prepared for the packaging process, as discussed above.
  • silicon wafer 200 includes a silicon wafer first surface 201 , a silicon wafer second surface 203 , and bonding locations, or pads, 205 .
  • an adhesive layer 204 is applied to silicon wafer second surface 203 using methods well known to those of skill in the art such as spinning or spraying.
  • FIG. 2B shows the structure of FIG. 2A , including a dielectric layer, also called a first dielectric layer, 207 applied to silicon wafer second surface 203 using adhesive layer 204 of FIG. 2A .
  • dielectric layer 207 is then ablated, using a laser or other ablation means, to form various predetermined patterns 206 in dielectric layer 207 .
  • dielectric layer 207 is ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary.
  • FIG. 2C shows silicon wafer 200 of FIG. 2B after dielectric layer 207 and adhesive layer 204 have been ablated to form vias and trenches 206 in accordance with the principles of one embodiment of the present invention.
  • the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric layer 207 applied onto the silicon wafer second surface 203 and dielectric layer 207 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
  • a conductive layer also called a first conductive layer, 211 is then applied to silicon wafer second surface 203 and dielectric layer second surface 209 .
  • conductive layer 211 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns above dielectric layer second surface 209 .
  • conductive layer 211 includes a conductive layer first surface 215 that is in electrical contact with bonding locations 205 and a conductive layer second surface 213 . According to the principles of one embodiment of the invention, conductive layer 211 is then etched away in a controlled etch process that results in conductive layer second surface 213 being made level with dielectric layer second surface 209 . In this way electrically conductive traces and vias 216 are formed. As discussed in more detail below with respect to FIG.
  • portions of conductive layer second surface 213 can, in one embodiment of the invention, be left higher than dielectric layer second surface 209 to facilitate better bonding and compliance.
  • FIG. 2E shows the structure of FIG. 2D after conductive layer 211 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention.
  • Depth controlled etching processes such as that used to bring conductive layer second surface 213 level with, or with selected portions raised above, dielectric layer second surface 209 are well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
  • the conductive layer 211 building process is solely additive using the ablated dielectric layer 207 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
  • the materials used for dielectric layer 207 need not be photoimagable materials, the materials need not be of the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
  • FIG. 2F shows the structure of FIG. 2E with solder bumps 219 attached to selected bonding points 298 on conductive layer 211 using standard bumping techniques in accordance with the principles of one embodiment of the present invention.
  • FIG. 2G shows the structure of FIG. 2F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components 221 , 223 and 225 using a standard cutting means 227 such as a saw.
  • FIG. 2H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component 221 in accordance with the principles of one embodiment of the present invention.
  • the permanent layers of the invention i.e., the dielectric and conductive layers 107 , 207 and 111 , 211 respectively can be laminated or glued, which enables the creation of multilayer Direct Write Wafer Level Chip Scale Packaged electronic components at lower costs, and with improved reliability of the finished package.
  • FIGS. 3A to 3M show the process and structure for a multilayer Direct Write Wafer Level Chip Scale Package in which a first dielectric layer is attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H , and a second dielectric layer is directly attached, such as discussed above with respect to FIGS. 1A to 1H .
  • a silicon wafer 300 is first prepared for the packaging process, as discussed above.
  • silicon wafer 300 includes a silicon wafer first surface 301 , a silicon wafer second surface 303 , and bonding locations or pads 305 .
  • an adhesive layer 304 is applied to silicon wafer second surface 303 using methods well known to those of skill in the art such as spinning or spraying.
  • FIG. 3B shows the structure of FIG. 3A , including a first dielectric layer 307 applied to silicon wafer second surface 303 using adhesive layer 304 of FIG. 3A .
  • first dielectric layer 307 is then ablated, using a laser or other ablation means, to form various predetermined patterns 306 in first dielectric layer 307 .
  • FIG. 3C shows silicon wafer 300 of FIG. 3B after first dielectric layer 307 has been ablated to form vias and trenches 306 in accordance with the principles of one embodiment of the present invention.
  • one embodiment of the multilayer Direct Write Wafer Level Chip Scale Packages of the invention includes first dielectric layer 307 laminated directly onto the silicon wafer second surface 303 and first dielectric layer 307 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
  • first layer of conductive material 311 is then applied to silicon wafer second surface 303 and first dielectric layer second surface 309 of first dielectric layer 307 .
  • first conductive layer 311 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns above first dielectric layer second surface 309 of first dielectric layer 307 .
  • first conductive layer 311 includes a first conductive layer first surface 315 that is in electrical contact with bonding locations 305 and a first conductive layer second surface 313 .
  • first conductive layer 311 is then etched away in a controlled etch process that results in first conductive layer second surface 313 of first conductive layer 311 being made level with first dielectric layer second surface 309 of first dielectric layer 307 .
  • FIG. 3E shows the structure of FIG. 3D after first conductive layer 311 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention.
  • Depth controlled etching processes can be used to bring first conductive layer second surface 313 of first conductive layer 311 level with first dielectric layer second surface 309 of first dielectric layer 307 as well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
  • the conductive layer 311 building process is solely additive using the ablated first dielectric layer 307 as its mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated using the present invention.
  • FIG. 3F shows the structure of FIG. 3E including a second dielectric layer 337 .
  • a second dielectric layer first surface 336 of second dielectric layer 337 is applied directly to first dielectric layer second surface 309 of first dielectric layer 307 and first conductive layer second surface 313 of first conductive layer 311 in accordance with the principles of one embodiment of the present invention.
  • second dielectric layer 337 is a polymer layer of InterVia® 8000, or a similar material having a thickness of forty (40) microns.
  • InterVia® 8000 or a similar material having a thickness of forty (40) microns.
  • second dielectric layer 337 is then ablated, using a laser or other ablation means, to form various predetermined patterns 344 in dielectric layer 337 .
  • dielectric layer 337 is ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed.
  • FIG. 3G shows the structure of FIG. 3F after second dielectric layer 337 has been ablated to form vias and trenches 344 in accordance with the principles of one embodiment of the present invention.
  • a second conductive layer 345 is then applied to second dielectric layer second surface 339 of second dielectric layer 337 .
  • second conductive layer 345 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns or less.
  • second conductive layer 345 includes a second conductive layer first surface 346 that is in electrical contact with bonding locations 305 and a second conductive layer second surface 353 .
  • second conductive layer 345 is then etched away in a controlled etch process that results in second conductive layer second surface 353 of second conductive layer 345 being made level with second dielectric layer second surface 339 of second dielectric layer 337 .
  • FIG. 3I shows the structure of FIG. 3H after second conductive layer 345 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention.
  • the second conductive layer 345 building process is solely additive using the ablated second dielectric layer 337 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
  • the materials used for second dielectric layer 337 need not be photoimagable materials, the materials need not limited to the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
  • FIG. 3J shows the structure of FIG. 3I with solder bumps 319 attached to selected points on second conductive layer 345 using standard techniques in accordance with the principles of one embodiment of the present invention.
  • FIG. 3K shows the structure of FIG. 3J being singulated into individual multilayer Direct Write Wafer Level Chip Scale Packaged electronic components 321 , 323 and 325 using a standard cutting means 327 , such as a saw.
  • FIG. 3L shows a singulated multilayer Direct Write Wafer Level Chip Scale Packaged electronic component 321 in accordance with the principles of one embodiment of the present invention.
  • FIG. 3M shows the singulated multilayer Direct Write Wafer Level Chip Scale Packaged electronic component 321 of FIG. 3L in more detail.
  • FIGS. 3A to 3M The process and structure shown in FIGS. 3A to 3M is for a multilayer Direct Write Wafer Level Chip Scale Package 321 in which a first dielectric layer is attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H , and a second dielectric layer is directly attached, such as discussed above with respect to FIGS. 1A to 1H .
  • a first dielectric layer is attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H
  • a second dielectric layer is directly attached, such as discussed above with respect to FIGS. 1A to 1H .
  • the multilayer Direct Write Wafer Level Chip Scale Packages of the invention can also be formed where all dielectric layers are attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H , or all dielectric layers are directly attached, such as discussed above with respect to FIGS. 1A to 1H .
  • the dielectric layers such as dielectric layer 107 , dielectric layer 207 , and dielectric layer 337 are ablated in such a way as to form patterned vias to the die pads.
  • the vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. This particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
  • FIG. 4A shows a detail portion 400 A, such as portion 299 of FIG. 2F , of a Direct Write Wafer Level Chip Scale Packaged electronic component of the invention, such as Direct Write Wafer Level Chip Scale Packaged electronic component 121 or 221 discussed above, wherein a dielectric layer 407 , such as dielectric layer 107 or dielectric layer 207 discussed above, has it's dielectric layer second surface 409 A ablated in such a way as to form a patterned via 416 A, such as electrically conductive vias 116 and 216 discussed above, between bonding location or pad 405 , such as bonding locations or pads 105 and 205 discussed above, and bonding point 498 , such as bonding points 198 and 298 discussed above.
  • a dielectric layer 407 such as dielectric layer 107 or dielectric layer 207 discussed above
  • a patterned via 416 A such as electrically conductive vias 116 and 216 discussed above
  • patterned via 416 includes multiple sub-vias 416 A, 416 B and 416 C as opposed to a single cylindrical or rectangular opening.
  • This particular structure allows for better thermal expansion by providing dielectric columns 407 A and 407 B to absorb thermal expansion of sub-vias 416 A, 416 B and 416 C. Consequently, this particular embodiment of the invention provides better compliance properties between solder bump 419 and bonding point 498 and bonding location or pad 405 on the surfaces of the dies comprising the silicon wafers (not shown).
  • portions of conductive layer second surfaces 113 , 213 such as bonding points 198 and 298 for solder bumps 119 and 219 discussed above, and other interconnections, are be left higher that dielectric layer second surfaces 109 , 209 , respectively, to facilitate better bonding and compliance.
  • FIG. 4B shows detail portion 400 B, such as portion 299 of FIG. 2F , of a Direct Write Wafer Level Chip Scale Packaged electronic component of the invention, such as Direct Write Wafer Level Chip Scale Packaged electronic component 121 or 221 discussed above, wherein bonding point 498 includes a metal buildup region 451 that extends a height “h” above dielectric second surface 409 B.
  • Metal buildup region 451 is formed by either selective etching away of conductive layer second surfaces 113 , 213 (see FIGS. 1D and 1E and FIGS. 2D and 2E ) or by an additive process wherein metal buildup region 451 is applied after conductive layer second surface 113 or 213 is etched away.
  • the present invention provides a method and structure for Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings.
  • DWWLCSP Direct Write Wafer Level Chip Scale Package
  • the Direct Write Wafer Level Chip Scale Packages of the invention include materials laminated directly onto the wafer surface. The layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of the masking steps.
  • the dielectric layers can be attached to the wafer with an adhesive layer and this adhesive layer need not be patterned using standard techniques.
  • the metal layer building process is solely additive using the ablated dielectric layer as its mask. Consequently, the need for subsequent patterning and etching is eliminated.
  • the materials used need not be photoimagable materials, the materials need not be limited to the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.

Abstract

A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.

Description

RELATED APPLICATIONS
This application is a divisional of Berry et al., U.S. patent application Ser. No. 12/661,597, filed on Mar. 19, 2010, entitled “DIRECT-WRITE WAFER LEVEL CHIP SCALE PACKAGE”, now U.S. Pat. No. 8,188,584, issued May 29, 2012, which is a divisional of Berry et al., U.S. patent application Ser. No. 11/810,799, filed on Jun. 6, 2007, entitled “DIRECT-WRITE WAFER LEVEL CHIP SCALE PACKAGE”, now U.S. Pat. No. 7,723,210, issued on May 25, 2010, which is a continuation of Berry et al., U.S. patent application Ser. No. 11/289,826, filed on Nov. 29, 2005, entitled “DIRECT-WRITE WAFER LEVEL CHIP SCALE PACKAGE”, now abandoned, which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuit packaging and, in particular, to wafer level chip scale packaging processes and structures.
2. Description of Related Art
In the prior art, wafer level chip scale packaging techniques typically involved adding various layers to integrated circuit wafers and then patterning the layers using a complex series of masking and photo etching steps. Typically, additive layers were spun-on, sprayed-on as a vapor, or printed on the integrated circuit wafers. As noted above, prior art techniques also typically required the use of photoimagable materials such as Cyclotone™ products or polyimides and the use of extensive photo-definition processes, i.e., masking and photo-etching of the layers.
In the prior art, many of the coatings or layers discussed above, such as photoresist, were not permanent, and did not remain part of the finished product. Rather, many layers were used as temporary masks and were later removed. Consequently, the prior art techniques required multiple steps and significant amounts of discarded/wasted materials. In addition, the process of depositing the prior art layers described above, and then subsequently photo-patterning and photo-etching the layers, was inherently expensive and labor intensive as well as time consuming and complicated.
In addition, the prior art photoimagable materials had to be of specific and limited thickness for the prior art processes to work, and be practical. In the prior art, these thicknesses were typically limited to less than twenty (20) microns. Consequently, the resulting structures typically offered limited flexibility and opportunity for “compliance” between interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
What is needed is a wafer level chip scale packaging method and structure that is not dependent on photolithography and therefore eliminates the need for photoimagable materials, non-permanent layers and the wasteful photo-definition process and makes feasible structures that would be impractical using prior art methods.
SUMMARY OF THE INVENTION
A method and structure according to one embodiment of the invention provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings.
According to one embodiment of the invention, a Direct Write Wafer Level Chip Scale Package is created by first preparing a silicon wafer and then a dielectric layer is attached directly to the wafer. In one embodiment of the invention, the dielectric layer is a layer of InterVia® 8000 or a similar material. The dielectric layer is then ablated to form vias and trench patterns. The surface of the dielectric layer is then plated with a conductive layer, such as copper, or another suitable metal, to fill in all of the related via and trench patterns and thereby form conductive patterns and connections to the die pads. According to one embodiment of the invention, the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads. In one embodiment of the invention, these patterns are then processed through standard solder application techniques such as solder masking and/or other solder application methods known in the art.
In one embodiment of the invention, the dielectric layer is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. This particular structure provides a cushion of dielectric material between sub-vias for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
According to another embodiment of the invention, a Direct Write Wafer Level Chip Scale Package is created by first preparing a silicon wafer and then a dielectric layer is attached to the wafer using an adhesive layer. The dielectric layer is then ablated to form via and trench patterns. The surface of the dielectric layer is then plated with a conductive layer, such as copper or another suitable conductive material, to fill in all of via and trench patterns and thereby form conductor patterns and connections to the die pads. According to one embodiment of the invention, the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads. In one embodiment of the invention, these patterns are then processed through any standard solder application techniques, such as solder masking and/or other solder application methods known in the art.
According to one embodiment of the invention, because of the flexible thicknesses of the dielectric available using the methods and structures of the invention, the dielectric and conductive layers of the invention can be laminated, which enables the creation of multilayer Direct Write Wafer Level Chip Scale Package structures at lower costs, and with improved reliability of the finished Direct Write Wafer Level Chip Scale Packaged electronic component.
As noted above, the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric and conductive materials applied directly onto the wafer surface. The dielectric layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of indirect materials required for the masking and etching steps.
In addition, using the methods and structures of the present invention, the dielectric layers can be attached to the wafer with an adhesive layer and this adhesive layer need not be patterned using standard techniques. In addition, according to the method and structure of the invention, the conductive layer building process is solely additive, using the ablated dielectric layer as its mask. Consequently, the need for subsequent patterning and etching is eliminated.
In, addition, since using the method and structure of the present invention, the materials used need not be photoimagable materials, the materials need not be of the prior art specified limited thickness. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
In addition, as discussed above, according to one embodiment of the invention, the dielectric layer is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. This particular structure provides a cushion of dielectric material between sub-vias for thermal expansion and therefore provides better compliance properties.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows a silicon wafer, including one or more electronic components such as integrated circuits;
FIG. 1B shows the silicon wafer of FIG. 1A, including a dielectric layer applied to the silicon wafer in accordance with the principles of one embodiment of the present invention;
FIG. 1C shows the silicon wafer of FIG. 1B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention;
FIG. 1D shows a layer of conductive material applied to the structure of FIG. 1C in accordance with the principles of one embodiment of the present invention;
FIG. 1E shows the structure of FIG. 1D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention;
FIG. 1F shows the structure of FIG. 1E with solder bumps attached to points on the conductive layer in accordance with the principles of one embodiment of the present invention;
FIG. 1G shows the structure of FIG. 1F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention;
FIG. 1H shows a singulated Direct Write Wafer Level Chip Scale Package in accordance with the principles of one embodiment of the present invention;
FIG. 2A shows a silicon wafer, including an adhesive layer applied in to the silicon wafer in accordance with the principles of one embodiment of the present invention;
FIG. 2B shows the structure of FIG. 2A, including a dielectric layer applied to the silicon wafer using the adhesive layer of FIG. 2A in accordance with the principles of one embodiment of the present invention;
FIG. 2C shows the structure of FIG. 2B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention;
FIG. 2D shows a layer of conductive material applied to the structure of FIG. 2C in accordance with the principles of one embodiment of the present invention;
FIG. 2E shows the structure of FIG. 2D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention;
FIG. 2F shows the structure of FIG. 2E with solder bumps attached to points on the conductive layer in accordance with the principles of one embodiment of the present invention;
FIG. 2G shows the structure of FIG. 2F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention;
FIG. 2H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component in accordance with the principles of one embodiment of the present invention;
FIG. 3A shows the silicon wafer, including an adhesive layer applied in to the silicon wafer in accordance with the principles of one embodiment of the present invention;
FIG. 3B shows the structure of FIG. 3A, including a dielectric layer applied to the silicon wafer using the adhesive layer of FIG. 3A in accordance with the principles of one embodiment of the present invention;
FIG. 3C shows the structure of FIG. 3B after the dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention;
FIG. 3D shows a layer of conductive material applied to the structure of FIG. 3C in accordance with the principles of one embodiment of the present invention;
FIG. 3E shows the structure of FIG. 3D after the layer of conductive material is etched using a controlled etching process in accordance with the principles of one embodiment of the present invention;
FIG. 3F shows the structure of FIG. 3E, including a second dielectric layer applied in accordance with the principles of one embodiment of the present invention;
FIG. 3G shows the structure of FIG. 3F after the second dielectric layer has been ablated to form vias and trenches in accordance with the principles of one embodiment of the present invention;
FIG. 3H shows a second layer of conductive material applied to the structure of FIG. 3G in accordance with the principles of one embodiment of the present invention;
FIG. 3I shows the structure of FIG. 3H after the second layer of conductive material has been etched using a controlled etching process in accordance with the principles of one embodiment of the present invention;
FIG. 3J shows the structure of FIG. 3I with solder bumps attached to points on the second conductive layer in accordance with the principles of one embodiment of the present invention;
FIG. 3K shows the structure of FIG. 3J being singulated into multi-layer Direct Write Wafer Level Chip Scale Packaged electronic components, in accordance with the principles of one embodiment of the present invention;
FIG. 3L shows a singulated multi-layer Direct Write Wafer Level Chip Scale Packaged electronic component in accordance with the principles of one embodiment of the present invention;
FIG. 3M shows the singulated multi-layer Direct Write Wafer Level Chip Scale Packaged electronic component of FIG. 3L in detail in accordance with the principles of one embodiment of the present invention;
FIG. 4A shows a detail portion of a Direct Write Wafer Level Chip Scale Packaged electronic component wherein a dielectric layer has been ablated in such a way as to form patterned vias; and
FIG. 4B shows a detail portion of a Direct Write Wafer Level Chip Scale Packaged electronic component wherein a metal buildup region is formed on bonding points of a conductive layer second surface.
Common reference numerals are used throughout the drawings and detailed description to indicate like elements.
DETAILED DESCRIPTION
A method and structure according to one embodiment of the invention provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent coatings/layers and direct write techniques to pattern these coatings/layers.
According to one embodiment of the invention, a Direct Write Wafer Level Chip Scale Package (121 in FIG. 1H) is created by first preparing a silicon wafer (100 in FIG. 1A) and then a dielectric layer, also called a first dielectric layer, (107 in FIG. 1B) is attached directly to the wafer. The dielectric layer is then ablated to form vias and trench patterns (104 in FIG. 1C). In one embodiment of the invention, the dielectric layer (407 in FIG. 4B) is ablated in such a way as to form patterned vias (411 in FIG. 4B) to the die pads (498 in FIG. 4B). The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular sub-vias (416A, 416B, 416C in FIG. 4A) are formed. This particular structure provides a cushion of dielectric material (407A and 407B) between sub-vias for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers. The surface of the dielectric layer is then plated with a conductive layer, also called a first conductive layer, (111 in FIG. 1D), such as copper, or another suitable metal, to fill in all of related via and trench patterns and thereby form conductor patterns and connections to the die pads (FIG. 1D). According to one embodiment of the invention, the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads (FIG. 1E). In one embodiment of the invention, these patterns are then processed through standard solder application techniques (FIG. 1F).
According to another embodiment of the invention, a Direct Write Wafer Level Chip Scale Package (221 in FIG. 2H) is created by first preparing a silicon wafer (200 in FIG. 2A) and then a dielectric layer, also called a first dielectric layer, (207 in FIG. 2B) is attached to the wafer using an adhesive (204 in FIG. 2B). The dielectric layer is then ablated to form via and trench patterns (FIG. 2C). In one embodiment of the invention, the dielectric layer is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. As discussed above, this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers. The surface of the dielectric layer is then plated with a conductive layer, also called a first conductive layer, (211 in FIG. 2D), such as copper or another suitable conductive material, to fill in all of via and trench patterns and thereby form conductor patterns and connections to the die pads (FIG. 2D). According to one embodiment of the invention, the conductive layer is then partially removed through a controlled etching process, leaving only the conductor patterns and connections to the die pads (FIG. 2E). In one embodiment of the invention, these patterns are then processed through any standard solder application techniques (FIG. 2F).
According to one embodiment of the invention, because of the flexible thicknesses available using the methods and structures of the invention, the dielectric and conductive layers of the invention can be laminated (FIGS. 3A to 3M), which enables the creation of multilayer Direct Write Wafer Level Chip Scale Package structures (FIG. 3M) at lower costs, and with improved reliability of the finished Direct Write Wafer Level Chip Scale Package.
As noted above, the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric and conductive materials applied directly onto the wafer surface. The dielectric layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention. The materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of the masking and etching steps.
In addition, using the methods and structures of the present invention, the dielectric layers can be attached to the wafer with an adhesive layer and this adhesive layer need not be patterned using standard techniques. In addition, according to the method and structure of the invention, the conductive layer building process is solely additive using the ablated dielectric layer as its mask. Consequently, the need for subsequent patterning and etching is eliminated.
In, addition, since using the method and structure of the present invention, the materials used need not be photoimagable materials, the materials need not be of the prior art predetermined and specified thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers. In addition, since using the method and structure of the present invention, the materials used need not be photoimagable materials, any one of numerous known adhesives and intermediate layer materials can be used with the method and structure of the invention.
In particular, FIG. 1A shows a silicon wafer 100 that has been prepared for the packaging process and includes bonding locations, or pads, 105. As shown in FIG. 1A, silicon wafer 100 has a silicon wafer first surface 101 and a silicon wafer second surface 103. Silicon wafers are well known to those of skill in the art and typically include one or more electronic components, such as integrated circuits, (not shown) formed in, or on, silicon wafer 100 by methods well known to those of skill in the art.
Once silicon wafer 100 is prepared, according to a first embodiment of the invention, a dielectric layer 107 is applied directly to silicon wafer second surface 103 of silicon wafer 100. FIG. 1B shows silicon wafer 100 of FIG. 1A including a dielectric layer, also called a first dielectric layer, 107 applied directly to silicon wafer second surface 103 of silicon wafer 100 in accordance with the principles of one embodiment of the present invention. As shown in FIG. 1B, a dielectric layer first surface 110 of dielectric layer 107 is applied directly to silicon wafer second surface 103 of silicon wafer 100.
According to the principles of one embodiment of the present invention, dielectric layer 107 is a polymer layer. In one embodiment of the invention, dielectric layer 107 is made of InterVia® 8000 material and has a thickness of approximately forty (40) microns. However, those of skill in the art will readily recognize, in light of this disclosure, that many different types of materials and thicknesses can be used for dielectric layer 107.
According to the principles of the invention, dielectric layer 107 is then ablated, using a laser or other ablation means, to form various predetermined patterns 104 in dielectric layer 107. FIG. 1C shows the structure of FIG. 1B after dielectric layer 107 has been ablated to form vias and trenches 104 in accordance with the principles of one embodiment of the present invention. As discussed in more detail below with respect to FIGS. 4A and 4B, in one embodiment of the invention, dielectric layer 107 is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern or multiple smaller cylindrical or rectangular vias are formed. As discussed in more detail below, this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
As noted above, in one embodiment of the invention, the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric layer 107 laminated directly onto the silicon wafer second surface 103 and the dielectric layer 107 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
As shown in FIG. 1D, according to the principles of the invention, a conductive layer, also called a first conductive layer, 111 is then applied to silicon wafer second surface 103 and dielectric layer second surface 109. In one embodiment of the invention conductive layer 111 is copper, or another suitable metal, and is applied to an approximate thickness of approximately five (5) microns above dielectric layer second surface 109.
According to the principles of one embodiment of the invention, conductive layer 111 includes a conductive layer first surface 115 that is in electrical contact with bonding locations 105 and a conductive layer second surface 113. According to the principles of one embodiment of the invention, conductive layer 111 is then etched away in a controlled etch process that results in conductive layer second surface 113 being made level with dielectric layer second surface 109. By this process electrically conductive traces and vias 116 are formed As discussed in more detail below with respect to FIG. 4B, using controlled etching, and the methods of the present invention, portions of conductive layer second surface 113, such as bonding points 198 for solder balls and other interconnections, can, in one embodiment of the invention, be left higher that dielectric layer second surface 109 to facilitate better bonding and compliance.
FIG. 1E shows the structure of FIG. 1D after conductive layer 111 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention. Depth controlled etching processes such as that used to bring conductive layer second surface 113 level with, or with potions slightly raised above, dielectric layer second surface 109 are well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
As shown above, according to the method and structure of the invention, the conductive layer 111 building process is solely additive using the ablated dielectric layer 107 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
Since using the method and structure of the present invention, the materials used for dielectric layer 107 need not be photoimagable materials, the materials need not be of the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
FIG. 1F shows the structure of FIG. 1E with solder bumps 119 attached to selected bonding points 198 on conductive layer 111 using standard bumping techniques in accordance with the principles of one embodiment of the present invention.
FIG. 1G shows the structure of FIG. 1F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components 121, 123 and 125 using a standard cutting means 127 such as a saw.
FIG. 1H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component 121 in accordance with the principles of one embodiment of the present invention.
Referring to FIG. 2A, according to one embodiment of the invention, a silicon wafer 200 is first prepared for the packaging process, as discussed above. In this embodiment of the invention silicon wafer 200 includes a silicon wafer first surface 201, a silicon wafer second surface 203, and bonding locations, or pads, 205. In addition, an adhesive layer 204 is applied to silicon wafer second surface 203 using methods well known to those of skill in the art such as spinning or spraying.
FIG. 2B shows the structure of FIG. 2A, including a dielectric layer, also called a first dielectric layer, 207 applied to silicon wafer second surface 203 using adhesive layer 204 of FIG. 2A. According to the principles of the invention, dielectric layer 207 is then ablated, using a laser or other ablation means, to form various predetermined patterns 206 in dielectric layer 207. As discussed in more detail below with respect to FIGS. 4A and 4B, in one embodiment of the invention, dielectric layer 207 is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. As discussed below, this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers. FIG. 2C shows silicon wafer 200 of FIG. 2B after dielectric layer 207 and adhesive layer 204 have been ablated to form vias and trenches 206 in accordance with the principles of one embodiment of the present invention.
As noted above, the Direct Write Wafer Level Chip Scale Packages of the invention include dielectric layer 207 applied onto the silicon wafer second surface 203 and dielectric layer 207 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
As shown in FIG. 2D, according to the principles of the invention, a conductive layer, also called a first conductive layer, 211 is then applied to silicon wafer second surface 203 and dielectric layer second surface 209. In one embodiment of the invention conductive layer 211 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns above dielectric layer second surface 209.
According to the principles of one embodiment of the invention, conductive layer 211 includes a conductive layer first surface 215 that is in electrical contact with bonding locations 205 and a conductive layer second surface 213. According to the principles of one embodiment of the invention, conductive layer 211 is then etched away in a controlled etch process that results in conductive layer second surface 213 being made level with dielectric layer second surface 209. In this way electrically conductive traces and vias 216 are formed. As discussed in more detail below with respect to FIG. 4B, using controlled etching, and the methods of the present invention, portions of conductive layer second surface 213, such as bonding locations for solder balls and other interconnections, can, in one embodiment of the invention, be left higher than dielectric layer second surface 209 to facilitate better bonding and compliance.
FIG. 2E shows the structure of FIG. 2D after conductive layer 211 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention. Depth controlled etching processes such as that used to bring conductive layer second surface 213 level with, or with selected portions raised above, dielectric layer second surface 209 are well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
As shown above, according to the method and structure of the invention, the conductive layer 211 building process is solely additive using the ablated dielectric layer 207 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
Since using the method and structure of the present invention the materials used for dielectric layer 207 need not be photoimagable materials, the materials need not be of the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
FIG. 2F shows the structure of FIG. 2E with solder bumps 219 attached to selected bonding points 298 on conductive layer 211 using standard bumping techniques in accordance with the principles of one embodiment of the present invention.
FIG. 2G shows the structure of FIG. 2F being singulated into individual Direct Write Wafer Level Chip Scale Packaged electronic components 221, 223 and 225 using a standard cutting means 227 such as a saw.
FIG. 2H shows a singulated Direct Write Wafer Level Chip Scale Packaged electronic component 221 in accordance with the principles of one embodiment of the present invention.
Using the methods and structure of the present invention the permanent layers of the invention, i.e., the dielectric and conductive layers 107, 207 and 111, 211 respectively can be laminated or glued, which enables the creation of multilayer Direct Write Wafer Level Chip Scale Packaged electronic components at lower costs, and with improved reliability of the finished package.
FIGS. 3A to 3M show the process and structure for a multilayer Direct Write Wafer Level Chip Scale Package in which a first dielectric layer is attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H, and a second dielectric layer is directly attached, such as discussed above with respect to FIGS. 1A to 1H.
Referring to FIG. 3A, according to one embodiment of the invention, a silicon wafer 300 is first prepared for the packaging process, as discussed above. In this embodiment of the invention, silicon wafer 300 includes a silicon wafer first surface 301, a silicon wafer second surface 303, and bonding locations or pads 305. In addition, an adhesive layer 304 is applied to silicon wafer second surface 303 using methods well known to those of skill in the art such as spinning or spraying.
FIG. 3B shows the structure of FIG. 3A, including a first dielectric layer 307 applied to silicon wafer second surface 303 using adhesive layer 304 of FIG. 3A.
According to the principles of the invention, first dielectric layer 307 is then ablated, using a laser or other ablation means, to form various predetermined patterns 306 in first dielectric layer 307. FIG. 3C shows silicon wafer 300 of FIG. 3B after first dielectric layer 307 has been ablated to form vias and trenches 306 in accordance with the principles of one embodiment of the present invention.
As noted above, one embodiment of the multilayer Direct Write Wafer Level Chip Scale Packages of the invention includes first dielectric layer 307 laminated directly onto the silicon wafer second surface 303 and first dielectric layer 307 is then ablated, as opposed to imaged using the photolithography techniques of the prior art. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials.
As shown in FIG. 3D, according to the principles of the invention, a first layer of conductive material 311 is then applied to silicon wafer second surface 303 and first dielectric layer second surface 309 of first dielectric layer 307. In one embodiment of the invention first conductive layer 311 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns above first dielectric layer second surface 309 of first dielectric layer 307.
According to the principles of one embodiment of the invention, first conductive layer 311 includes a first conductive layer first surface 315 that is in electrical contact with bonding locations 305 and a first conductive layer second surface 313. According to the principles of one embodiment of the invention, first conductive layer 311 is then etched away in a controlled etch process that results in first conductive layer second surface 313 of first conductive layer 311 being made level with first dielectric layer second surface 309 of first dielectric layer 307. FIG. 3E shows the structure of FIG. 3D after first conductive layer 311 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention. Depth controlled etching processes can be used to bring first conductive layer second surface 313 of first conductive layer 311 level with first dielectric layer second surface 309 of first dielectric layer 307 as well known to those of skill in the art and are therefore not discussed in further detail herein to avoid detracting from the present invention.
As shown above, according to the method and structure of the invention, the conductive layer 311 building process is solely additive using the ablated first dielectric layer 307 as its mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated using the present invention.
According to this embodiment of the invention a second dielectric layer is now applied to the structure of FIG. 3E. FIG. 3F shows the structure of FIG. 3E including a second dielectric layer 337. As shown in FIG. 3F, a second dielectric layer first surface 336 of second dielectric layer 337 is applied directly to first dielectric layer second surface 309 of first dielectric layer 307 and first conductive layer second surface 313 of first conductive layer 311 in accordance with the principles of one embodiment of the present invention. According to the principles of one embodiment of the present invention, second dielectric layer 337 is a polymer layer of InterVia® 8000, or a similar material having a thickness of forty (40) microns. However, those of skill in the art will readily recognize, in light of this disclosure, that many different types of materials and thicknesses can be used for second dielectric layer 337.
According to the principles of the invention, second dielectric layer 337 is then ablated, using a laser or other ablation means, to form various predetermined patterns 344 in dielectric layer 337. As discussed in more detail below with respect to FIGS. 4A and 4B, in one embodiment of the invention, dielectric layer 337 is ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. As discussed in more detail below, this particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers. FIG. 3G shows the structure of FIG. 3F after second dielectric layer 337 has been ablated to form vias and trenches 344 in accordance with the principles of one embodiment of the present invention.
As shown in FIG. 3H, according to the principles of the invention, a second conductive layer 345 is then applied to second dielectric layer second surface 339 of second dielectric layer 337. In one embodiment of the invention second conductive layer 345 is copper, or another suitable metal, and is applied to an approximate thickness of five (5) microns or less.
According to the principles of one embodiment of the invention, second conductive layer 345 includes a second conductive layer first surface 346 that is in electrical contact with bonding locations 305 and a second conductive layer second surface 353. According to the principles of one embodiment of the invention, second conductive layer 345 is then etched away in a controlled etch process that results in second conductive layer second surface 353 of second conductive layer 345 being made level with second dielectric layer second surface 339 of second dielectric layer 337. As discussed in more detail below with respect to FIG. 4B, using controlled etching, and the methods of the present invention, portions of conductive layer second surface 353, such as bonding locations for solder balls and other interconnections, can, in one embodiment of the invention, be left higher that dielectric layer second surface 339 to facilitate better bonding and compliance. FIG. 3I shows the structure of FIG. 3H after second conductive layer 345 is etched using the controlled etching process in accordance with the principles of one embodiment of the present invention.
As shown above, according to the method and structure of the invention, the second conductive layer 345 building process is solely additive using the ablated second dielectric layer 337 as a mask. Consequently, the need for subsequent masks, patterning, and etching, as required in the prior art, is eliminated.
Since using the method and structure of the present invention, the materials used for second dielectric layer 337 need not be photoimagable materials, the materials need not limited to the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
FIG. 3J shows the structure of FIG. 3I with solder bumps 319 attached to selected points on second conductive layer 345 using standard techniques in accordance with the principles of one embodiment of the present invention.
FIG. 3K shows the structure of FIG. 3J being singulated into individual multilayer Direct Write Wafer Level Chip Scale Packaged electronic components 321, 323 and 325 using a standard cutting means 327, such as a saw.
FIG. 3L shows a singulated multilayer Direct Write Wafer Level Chip Scale Packaged electronic component 321 in accordance with the principles of one embodiment of the present invention. FIG. 3M shows the singulated multilayer Direct Write Wafer Level Chip Scale Packaged electronic component 321 of FIG. 3L in more detail.
The process and structure shown in FIGS. 3A to 3M is for a multilayer Direct Write Wafer Level Chip Scale Package 321 in which a first dielectric layer is attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H, and a second dielectric layer is directly attached, such as discussed above with respect to FIGS. 1A to 1H. However, those of skill in the art will readily recognize, in light of this disclosure, that the multilayer Direct Write Wafer Level Chip Scale Packages of the invention can also be formed where all dielectric layers are attached using an adhesive layer, such as discussed above with respect to FIGS. 2A to 2H, or all dielectric layers are directly attached, such as discussed above with respect to FIGS. 1A to 1H.
As discussed above, in some embodiments of the invention, the dielectric layers, such as dielectric layer 107, dielectric layer 207, and dielectric layer 337 are ablated in such a way as to form patterned vias to the die pads. The vias can be patterned in any way that the user of the invention deems necessary. For instance, in one embodiment of the invention, rather than simply ablating a single cylindrical or rectangular via to the die pads, a pattern of multiple smaller cylindrical or rectangular vias are formed. This particular structure provides for thermal expansion and therefore provides better compliance properties between solder bumps, or other interconnections, and the surfaces of the dies comprising the silicon wafers.
FIG. 4A shows a detail portion 400A, such as portion 299 of FIG. 2F, of a Direct Write Wafer Level Chip Scale Packaged electronic component of the invention, such as Direct Write Wafer Level Chip Scale Packaged electronic component 121 or 221 discussed above, wherein a dielectric layer 407, such as dielectric layer 107 or dielectric layer 207 discussed above, has it's dielectric layer second surface 409A ablated in such a way as to form a patterned via 416A, such as electrically conductive vias 116 and 216 discussed above, between bonding location or pad 405, such as bonding locations or pads 105 and 205 discussed above, and bonding point 498, such as bonding points 198 and 298 discussed above.
As shown in FIG. 4A, in one embodiment, patterned via 416 includes multiple sub-vias 416A, 416B and 416C as opposed to a single cylindrical or rectangular opening. This particular structure allows for better thermal expansion by providing dielectric columns 407A and 407B to absorb thermal expansion of sub-vias 416A, 416B and 416C. Consequently, this particular embodiment of the invention provides better compliance properties between solder bump 419 and bonding point 498 and bonding location or pad 405 on the surfaces of the dies comprising the silicon wafers (not shown).
Those of skill in the art will readily recognize that many different patterns can be ablated in dielectric layer 407 to form many different vias 416A depending on the needs of the designer.
As discussed above, in some embodiments of the invention, portions of conductive layer second surfaces 113, 213 such as bonding points 198 and 298 for solder bumps 119 and 219 discussed above, and other interconnections, are be left higher that dielectric layer second surfaces 109, 209, respectively, to facilitate better bonding and compliance.
FIG. 4B shows detail portion 400B, such as portion 299 of FIG. 2F, of a Direct Write Wafer Level Chip Scale Packaged electronic component of the invention, such as Direct Write Wafer Level Chip Scale Packaged electronic component 121 or 221 discussed above, wherein bonding point 498 includes a metal buildup region 451 that extends a height “h” above dielectric second surface 409B. Metal buildup region 451 is formed by either selective etching away of conductive layer second surfaces 113, 213 (see FIGS. 1D and 1E and FIGS. 2D and 2E) or by an additive process wherein metal buildup region 451 is applied after conductive layer second surface 113 or 213 is etched away.
As shown above, the present invention provides a method and structure for Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings.
As noted above, the Direct Write Wafer Level Chip Scale Packages of the invention include materials laminated directly onto the wafer surface. The layers are then ablated, as opposed to imaged using photolithography. Consequently, using the method and structure of the present invention, the materials used need not be photoimagable materials, thus saving the cost of the materials themselves and the cost of the masking steps.
In addition, using the methods and structures of the present invention, the dielectric layers can be attached to the wafer with an adhesive layer and this adhesive layer need not be patterned using standard techniques. In addition, according to the method and structure of the invention, the metal layer building process is solely additive using the ablated dielectric layer as its mask. Consequently, the need for subsequent patterning and etching is eliminated.
In addition, since using the method and structure of the present invention, the materials used need not be photoimagable materials, the materials need not be limited to the prior art predetermined and specific thicknesses. Consequently, the resulting structures of the invention provide the opportunity for greater flexibility and “compliance” between solder bumps, or other interconnections, and the surfaces of the dies comprising the integrated circuit wafers.
This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Consequently, numerous variations, whether explicitly provided for by the specification or implied by the specification or not, may be implemented by one of skill in the art in view of this disclosure.

Claims (20)

What is claimed is:
1. A method for packaging an electronic component comprising:
providing a silicon wafer, the silicon wafer having a silicon wafer first surface and a silicon wafer second surface, opposite the silicon wafer first surface;
applying a first dielectric layer, the first dielectric layer having a first dielectric layer first surface and a first dielectric layer second surface, opposite the first dielectric layer first surface, the first dielectric layer first surface being applied to the silicon wafer second surface;
ablating patterns in the first dielectric layer to create vias extending vertically in the first dielectric layer and trenches extending horizontally in the first dielectric layer;
applying a first conductive layer, the first conductive layer having a first conductive layer first surface and a first conductive layer second surface, opposite the first conductive layer first surface, the first conductive layer being applied directly to the first dielectric layer second surface, the first conductive layer completely filling the patterns ablated in the first dielectric layer such that the first conductive layer second surface is at least substantially co-planar with the first dielectric layer second surface to create conductive vias extending vertically in the first dielectric layer and traces extending horizontally in the first dielectric layer; and
singulating the silicon wafer with the applied first dielectric layer and the applied first conductive layer into individual packaged electronic components.
2. The method for packaging an electronic component of claim 1, wherein:
the first dielectric layer first surface is directly applied to the silicon wafer second surface by lamination.
3. The method for packaging an electronic component of claim 2, wherein:
ablating patterns in the first dielectric layer to create vias and trenches is performed by LASER ablation of portions of the first dielectric layer.
4. The method for packaging an electronic component of claim 1, wherein:
the first dielectric layer first surface is applied to the silicon wafer second surface by an adhesive.
5. The method for packaging an electronic component of claim 4, wherein:
ablating patterns in the first dielectric layer to create vias and trenches is performed by LASER ablation of portions of the first dielectric layer.
6. The method for packaging an electronic component of claim 1, wherein:
the first conductive layer is applied such that the first conductive layer completely fills the patterns ablated in the first dielectric layer and covers the first dielectric layer second surface; further wherein,
at least a portion of the first conductive layer is removed such that the first conductive layer second surface is substantially co-planar with the first dielectric layer second surface to create the conductive vias and traces.
7. A method for packaging an electronic component comprising:
providing a silicon wafer;
applying a first dielectric layer to the silicon wafer;
ablating patterns in the first dielectric layer to create vias extending vertically in the first dielectric layer and trenches extending horizontally in the first dielectric layer;
applying a first conductive layer directly to the first dielectric layer, the first conductive layer filling the patterns ablated in the first dielectric layer to create conductive vias extending vertically in the first dielectric layer and traces extending horizontally in the first dielectric layer; and
singulating the silicon wafer with the applied first dielectric layer and the applied first conductive layer into individual packaged electronic components.
8. The method for packaging an electronic component of claim 7, wherein:
the first dielectric layer is directly applied to the silicon wafer by lamination.
9. The method for packaging an electronic component of claim 7, wherein:
ablating patterns in the first dielectric layer to create vias and trenches is performed by LASER ablation of portions of the first dielectric layer.
10. The method for packaging an electronic component of claim 7, wherein:
the first dielectric layer is applied to the silicon wafer by an adhesive.
11. The method for packaging an electronic component of claim 10, wherein:
ablating patterns in the first dielectric layer to create vias and trenches is performed by LASER ablation of portions of the first dielectric layer.
12. The method for packaging an electronic component of claim 7, wherein the first dielectric layer comprise:
a first dielectric layer first surface; and
a first dielectric layer second surface, and wherein the first conductive layer comprises:
a first conductive layer first surface; and
a first conductive layer second surface.
13. The method for packaging an electronic component of claim 12, wherein:
the first conductive layer is applied such that the first conductive layer covers the first dielectric layer; further wherein,
at least a portion of the first conductive layer is removed such that the first conductive layer second surface is substantially co-planar with the first dielectric layer second surface.
14. A method for packaging an electronic component comprising:
providing a silicon wafer;
applying a first dielectric layer to the silicon wafer;
ablating patterns in the first dielectric layer;
filling the patterns ablated in the first dielectric layer with a first conductive layer to create conductive vias extending vertically in the first dielectric layer and traces extending horizontally in the first dielectric layer in the patterns;
applying a second dielectric layer to the first dielectric layer and the first conductive layer;
ablating patterns in the second dielectric layer; and
filling the patterns ablated in the second dielectric layer with a second conductive layer to create conductive vias and traces in the patterns in the second dielectric layer.
15. The method for packaging an electronic component of claim 14 further comprising:
singulating the silicon wafer, the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer into individual packaged electronic components.
16. The method of claim 14 wherein the first dielectric layer comprises a non photoimagable material.
17. The method of claim 14 wherein the second dielectric layer comprises a non photoimagable material.
18. The method for packaging an electronic component of claim 14, wherein the first dielectric layer is applied to the silicon wafer by an adhesive.
19. The method for packaging an electronic component of claim 14, wherein the first dielectric layer comprises:
a first dielectric layer first surface; and
a first dielectric layer second surface, and wherein the first conductive layer comprises:
a first conductive layer first surface; and
a first conductive layer second surface, the first conductive layer second surface being substantially co-planar with the first dielectric layer second surface.
20. The method for packaging an electronic component of claim 14, wherein the second dielectric layer comprises:
a second dielectric layer first surface; and
a second dielectric layer second surface, and wherein the second conductive layer comprises:
a second conductive layer first surface; and
a second conductive layer second surface, the second conductive layer second surface being substantially co-planar with the second dielectric layer second surface.
US13/472,961 2002-11-08 2012-05-16 Direct-write wafer level chip scale package Active US8501543B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/472,961 US8501543B1 (en) 2002-11-08 2012-05-16 Direct-write wafer level chip scale package

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/291,050 US6905914B1 (en) 2002-11-08 2002-11-08 Wafer level package and fabrication method
US28982605A 2005-11-26 2005-11-26
US11/810,799 US7723210B2 (en) 2002-11-08 2007-06-06 Direct-write wafer level chip scale package
US12/661,597 US8188584B1 (en) 2002-11-08 2010-03-19 Direct-write wafer level chip scale package
US13/472,961 US8501543B1 (en) 2002-11-08 2012-05-16 Direct-write wafer level chip scale package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/661,597 Division US8188584B1 (en) 2002-11-08 2010-03-19 Direct-write wafer level chip scale package

Publications (1)

Publication Number Publication Date
US8501543B1 true US8501543B1 (en) 2013-08-06

Family

ID=34632671

Family Applications (18)

Application Number Title Priority Date Filing Date
US10/291,050 Expired - Lifetime US6905914B1 (en) 2002-11-08 2002-11-08 Wafer level package and fabrication method
US11/047,848 Expired - Lifetime US7247523B1 (en) 2002-11-08 2005-01-31 Two-sided wafer escape package
US11/123,605 Expired - Lifetime US7192807B1 (en) 2002-11-08 2005-05-05 Wafer level package and fabrication method
US11/605,740 Active 2024-10-08 US7714431B1 (en) 2002-11-08 2006-11-28 Electronic component package comprising fan-out and fan-in traces
US11/784,979 Expired - Lifetime US7420272B1 (en) 2002-11-08 2007-04-09 Two-sided wafer escape package
US12/221,797 Expired - Lifetime US7692286B1 (en) 2002-11-08 2008-08-05 Two-sided fan-out wafer escape package
US12/661,604 Expired - Fee Related US7932595B1 (en) 2002-11-08 2010-03-19 Electronic component package comprising fan-out traces
US13/065,296 Expired - Lifetime US8119455B1 (en) 2002-11-08 2011-03-18 Wafer level package fabrication method
US13/358,947 Expired - Lifetime US8298866B1 (en) 2002-11-08 2012-01-26 Wafer level package and fabrication method
US13/472,961 Active US8501543B1 (en) 2002-11-08 2012-05-16 Direct-write wafer level chip scale package
US13/627,815 Expired - Lifetime US8486764B1 (en) 2002-11-08 2012-09-26 Wafer level package and fabrication method
US13/918,307 Expired - Lifetime US8691632B1 (en) 2002-11-08 2013-06-14 Wafer level package and fabrication method
US14/019,136 Expired - Lifetime US8710649B1 (en) 2002-11-08 2013-09-05 Wafer level package and fabrication method
US14/264,970 Expired - Lifetime US8952522B1 (en) 2002-11-08 2014-04-29 Wafer level package and fabrication method
US14/586,263 Expired - Fee Related US9054117B1 (en) 2002-11-08 2014-12-30 Wafer level package and fabrication method
US14/734,192 Expired - Lifetime US9406645B1 (en) 2002-11-08 2015-06-09 Wafer level package and fabrication method
US15/225,284 Expired - Lifetime US9871015B1 (en) 2002-11-08 2016-08-01 Wafer level package and fabrication method
US15/872,397 Expired - Lifetime US10665567B1 (en) 2002-11-08 2018-01-16 Wafer level package and fabrication method

Family Applications Before (9)

Application Number Title Priority Date Filing Date
US10/291,050 Expired - Lifetime US6905914B1 (en) 2002-11-08 2002-11-08 Wafer level package and fabrication method
US11/047,848 Expired - Lifetime US7247523B1 (en) 2002-11-08 2005-01-31 Two-sided wafer escape package
US11/123,605 Expired - Lifetime US7192807B1 (en) 2002-11-08 2005-05-05 Wafer level package and fabrication method
US11/605,740 Active 2024-10-08 US7714431B1 (en) 2002-11-08 2006-11-28 Electronic component package comprising fan-out and fan-in traces
US11/784,979 Expired - Lifetime US7420272B1 (en) 2002-11-08 2007-04-09 Two-sided wafer escape package
US12/221,797 Expired - Lifetime US7692286B1 (en) 2002-11-08 2008-08-05 Two-sided fan-out wafer escape package
US12/661,604 Expired - Fee Related US7932595B1 (en) 2002-11-08 2010-03-19 Electronic component package comprising fan-out traces
US13/065,296 Expired - Lifetime US8119455B1 (en) 2002-11-08 2011-03-18 Wafer level package fabrication method
US13/358,947 Expired - Lifetime US8298866B1 (en) 2002-11-08 2012-01-26 Wafer level package and fabrication method

Family Applications After (8)

Application Number Title Priority Date Filing Date
US13/627,815 Expired - Lifetime US8486764B1 (en) 2002-11-08 2012-09-26 Wafer level package and fabrication method
US13/918,307 Expired - Lifetime US8691632B1 (en) 2002-11-08 2013-06-14 Wafer level package and fabrication method
US14/019,136 Expired - Lifetime US8710649B1 (en) 2002-11-08 2013-09-05 Wafer level package and fabrication method
US14/264,970 Expired - Lifetime US8952522B1 (en) 2002-11-08 2014-04-29 Wafer level package and fabrication method
US14/586,263 Expired - Fee Related US9054117B1 (en) 2002-11-08 2014-12-30 Wafer level package and fabrication method
US14/734,192 Expired - Lifetime US9406645B1 (en) 2002-11-08 2015-06-09 Wafer level package and fabrication method
US15/225,284 Expired - Lifetime US9871015B1 (en) 2002-11-08 2016-08-01 Wafer level package and fabrication method
US15/872,397 Expired - Lifetime US10665567B1 (en) 2002-11-08 2018-01-16 Wafer level package and fabrication method

Country Status (1)

Country Link
US (18) US6905914B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
US10886232B2 (en) 2019-05-10 2021-01-05 Applied Materials, Inc. Package structure and fabrication methods
US11064615B2 (en) 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package
US11063169B2 (en) 2019-05-10 2021-07-13 Applied Materials, Inc. Substrate structuring methods

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7326629B2 (en) * 2004-09-10 2008-02-05 Agency For Science, Technology And Research Method of stacking thin substrates by transfer bonding
TWI250629B (en) * 2005-01-12 2006-03-01 Ind Tech Res Inst Electronic package and fabricating method thereof
US7572681B1 (en) * 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
CN101449375B (en) * 2006-06-29 2012-01-18 英特尔公司 A device, a system and a method applied to the connection without leads in the encapsulation of an integrate circuit
US20080001297A1 (en) * 2006-06-30 2008-01-03 Stefanie Lotz Laser patterning and conductive interconnect/materials forming techniques for fine line and space features
US8237259B2 (en) * 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
FR2923081B1 (en) * 2007-10-26 2009-12-11 3D Plus PROCESS FOR VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS.
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8343809B2 (en) 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US9318441B2 (en) * 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
CN101364760B (en) * 2008-07-31 2010-11-10 卢旻 Electricity generator, motor and electric automobile, electric boat
JP2012506156A (en) * 2008-10-17 2012-03-08 オッカム ポートフォリオ リミテッド ライアビリティ カンパニー Flexible circuit assembly and manufacturing method without using solder
TWI456715B (en) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng Chip package structure and manufacturing method thereof
TWI466259B (en) 2009-07-21 2014-12-21 Advanced Semiconductor Eng Semiconductor package, manufacturing method thereof and manufacturing method for chip-redistribution encapsulant
TWI405306B (en) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng Semiconductor package, manufacturing method thereof and chip-redistribution encapsulant
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8334202B2 (en) * 2009-11-03 2012-12-18 Infineon Technologies Ag Device fabricated using an electroplating process
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8327532B2 (en) * 2009-11-23 2012-12-11 Freescale Semiconductor, Inc. Method for releasing a microelectronic assembly from a carrier substrate
TWI497679B (en) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US9754835B2 (en) 2010-02-16 2017-09-05 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US20110198762A1 (en) * 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric
US8421226B2 (en) * 2010-02-25 2013-04-16 Infineon Technologies Ag Device including an encapsulated semiconductor chip and manufacturing method thereof
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
TWI411075B (en) * 2010-03-22 2013-10-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US20110316140A1 (en) * 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8535961B1 (en) * 2010-12-09 2013-09-17 Amkor Technology, Inc. Light emitting diode (LED) package and method
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US10204879B2 (en) 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
US8492203B2 (en) * 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US8828802B1 (en) 2011-11-01 2014-09-09 Amkor Technology, Inc. Wafer level chip scale package and method of fabricating wafer level chip scale package
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US20130154106A1 (en) * 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9147610B2 (en) * 2012-06-22 2015-09-29 Infineon Technologies Ag Monitor structures and methods of formation thereof
KR101429344B1 (en) 2012-08-08 2014-08-12 앰코 테크놀로지 코리아 주식회사 Semiconductor Package and Manufacturing Methode thereof
US8941223B2 (en) 2012-09-10 2015-01-27 Invensense, Inc. MEMS device package with conductive shell
US9735087B2 (en) * 2012-09-20 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level embedded heat spreader
KR20140038116A (en) 2012-09-20 2014-03-28 제이앤제이 패밀리 주식회사 Led lamp
KR101438915B1 (en) * 2012-11-02 2014-09-11 엘지이노텍 주식회사 The printed circuit board and the method for manufacturing the same
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (en) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
KR101488590B1 (en) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
KR101607981B1 (en) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 Interposer and method for manufacturing the same, and semiconductor package using the same
JP2017073472A (en) * 2015-10-07 2017-04-13 株式会社ディスコ Semiconductor device manufacturing method
US10055631B1 (en) 2015-11-03 2018-08-21 Synaptics Incorporated Semiconductor package for sensor applications
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10269728B2 (en) * 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with shielding structure for cross-talk reduction
DE102018109028B4 (en) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a shield structure for reducing crosstalk and method of manufacturing the same
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
US11164804B2 (en) 2019-07-23 2021-11-02 International Business Machines Corporation Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste
KR102543996B1 (en) * 2019-09-20 2023-06-16 주식회사 네패스 Semiconductor package and manufacturing method thereof
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
CN114649286B (en) * 2022-05-19 2022-09-27 甬矽电子(宁波)股份有限公司 Fan-out type packaging structure and fan-out type packaging method

Citations (394)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2596993A (en) 1949-01-13 1952-05-20 United Shoe Machinery Corp Method and mold for covering of eyelets by plastic injection
US3435815A (en) 1966-07-15 1969-04-01 Micro Tech Mfg Inc Wafer dicer
US3734660A (en) 1970-01-09 1973-05-22 Tuthill Pump Co Apparatus for fabricating a bearing device
US3781596A (en) 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US3838984A (en) 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US4054238A (en) 1976-03-23 1977-10-18 Western Electric Company, Inc. Method, apparatus and lead frame for assembling leads with terminals on a substrate
US4189342A (en) 1971-10-07 1980-02-19 U.S. Philips Corporation Semiconductor device comprising projecting contact layers
US4258381A (en) 1977-12-07 1981-03-24 Steag, Kernergie Gmbh Lead frame for a semiconductor device suitable for mass production
US4289922A (en) 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
US4301464A (en) 1978-08-02 1981-11-17 Hitachi, Ltd. Lead frame and semiconductor device employing the same with improved arrangement of supporting leads for securing the semiconductor supporting member
US4332537A (en) 1978-07-17 1982-06-01 Dusan Slepcevic Encapsulation mold with removable cavity plates
US4417266A (en) 1981-08-14 1983-11-22 Amp Incorporated Power and ground plane structure for chip carrier
US4451224A (en) 1982-03-25 1984-05-29 General Electric Company Mold device for making plastic articles from resin
US4530152A (en) 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
US4541003A (en) 1978-12-27 1985-09-10 Hitachi, Ltd. Semiconductor device including an alpha-particle shield
US4646710A (en) 1982-09-22 1987-03-03 Crystal Systems, Inc. Multi-wafer slicing with a fixed abrasive
US4707724A (en) 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
US4729061A (en) 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US4727633A (en) 1985-08-08 1988-03-01 Tektronix, Inc. Method of securing metallic members together
US4737839A (en) 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
US4756080A (en) 1986-01-27 1988-07-12 American Microsystems, Inc. Metal foil semiconductor interconnection method
US4812896A (en) 1986-11-13 1989-03-14 Olin Corporation Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant
US4862245A (en) 1985-04-18 1989-08-29 International Business Machines Corporation Package semiconductor chip
US4862246A (en) 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
US4907067A (en) 1988-05-11 1990-03-06 Texas Instruments Incorporated Thermally efficient power device package
US4920074A (en) 1987-02-25 1990-04-24 Hitachi, Ltd. Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US4935803A (en) 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US4942454A (en) 1987-08-05 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
US4987475A (en) 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US5018003A (en) 1988-10-20 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Lead frame and semiconductor device
US5029386A (en) 1990-09-17 1991-07-09 Hewlett-Packard Company Hierarchical tape automated bonding method
US5041902A (en) 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
US5057900A (en) 1988-10-17 1991-10-15 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5059379A (en) 1987-07-20 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Method of resin sealing semiconductor devices
US5065223A (en) 1989-05-31 1991-11-12 Fujitsu Vlsi Limited Packaged semiconductor device
US5070039A (en) 1989-04-13 1991-12-03 Texas Instruments Incorporated Method of making an integrated circuit using a pre-served dam bar to reduce mold flash and to facilitate flash removal
US5087961A (en) 1987-01-28 1992-02-11 Lsi Logic Corporation Semiconductor device package
US5091341A (en) 1989-05-22 1992-02-25 Kabushiki Kaisha Toshiba Method of sealing semiconductor device with resin by pressing a lead frame to a heat sink using an upper mold pressure member
US5096852A (en) 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
US5118298A (en) 1991-04-04 1992-06-02 Advanced Interconnections Corporation Through hole mounting of integrated circuit adapter leads
US5122860A (en) 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
US5134773A (en) 1989-05-26 1992-08-04 Gerard Lemaire Method for making a credit card containing a microprocessor chip
US5151039A (en) 1990-04-06 1992-09-29 Advanced Interconnections Corporation Integrated circuit adapter having gullwing-shaped leads
US5157475A (en) 1988-07-08 1992-10-20 Oki Electric Industry Co., Ltd. Semiconductor device having a particular conductive lead structure
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5168368A (en) 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5172213A (en) 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5172214A (en) 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5175060A (en) 1989-07-01 1992-12-29 Ibiden Co., Ltd. Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same
US5200809A (en) 1991-09-27 1993-04-06 Vlsi Technology, Inc. Exposed die-attach heatsink package
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5214845A (en) 1992-05-11 1993-06-01 Micron Technology, Inc. Method for producing high speed integrated circuits
US5216278A (en) 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5218231A (en) 1989-08-30 1993-06-08 Kabushiki Kaisha Toshiba Mold-type semiconductor device
US5221642A (en) 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
US5250841A (en) 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5252853A (en) 1991-09-19 1993-10-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device having tab tape and particular power distribution lead structure
US5258094A (en) 1991-09-18 1993-11-02 Nec Corporation Method for producing multilayer printed wiring boards
US5266834A (en) 1989-03-13 1993-11-30 Hitachi Ltd. Semiconductor device and an electronic device with the semiconductor devices mounted thereon
US5268310A (en) 1992-11-25 1993-12-07 M/A-Com, Inc. Method for making a mesa type PIN diode
US5277972A (en) 1988-09-29 1994-01-11 Tomoegawa Paper Co., Ltd. Adhesive tapes
US5278446A (en) 1992-07-06 1994-01-11 Motorola, Inc. Reduced stress plastic package
US5279029A (en) 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5281849A (en) 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
US5294897A (en) 1992-07-20 1994-03-15 Mitsubishi Denki Kabushiki Kaisha Microwave IC package
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
US5332864A (en) 1991-12-27 1994-07-26 Vlsi Technology, Inc. Integrated circuit package having an interposer
US5336931A (en) 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
US5335771A (en) 1990-09-25 1994-08-09 R. H. Murphy Company, Inc. Spacer trays for stacking storage trays with integrated circuits
US5343076A (en) 1990-07-21 1994-08-30 Mitsui Petrochemical Industries, Ltd. Semiconductor device with an airtight space formed internally within a hollow package
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5358905A (en) 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking
US5365106A (en) 1992-10-27 1994-11-15 Kabushiki Kaisha Toshiba Resin mold semiconductor device
US5381042A (en) 1992-03-31 1995-01-10 Amkor Electronics, Inc. Packaged integrated circuit including heat slug having an exposed surface
EP0393997B1 (en) 1989-04-20 1995-02-01 Honeywell Inc. Method of providing a variable-pitch leadframe assembly
US5391439A (en) 1990-09-27 1995-02-21 Dai Nippon Printing Co., Ltd. Leadframe adapted to support semiconductor elements
US5394303A (en) 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5406124A (en) 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
US5410180A (en) 1992-07-28 1995-04-25 Shinko Electric Industries Co., Ltd. Metal plane support for multi-layer lead frames and a process for manufacturing such frames
US5414299A (en) 1993-09-24 1995-05-09 Vlsi Technology, Inc. Semi-conductor device interconnect package assembly for improved package performance
US5417905A (en) 1989-05-26 1995-05-23 Esec (Far East) Limited Method of making a card having decorations on both faces
US5428248A (en) 1992-08-21 1995-06-27 Goldstar Electron Co., Ltd. Resin molded semiconductor package
US5432677A (en) 1993-02-09 1995-07-11 Texas Instruments Incorporated Multi-chip integrated circuit module
US5435057A (en) 1990-10-30 1995-07-25 International Business Machines Corporation Interconnection method and structure for organic circuit boards
US5444301A (en) 1993-06-23 1995-08-22 Goldstar Electron Co. Ltd. Semiconductor package and method for manufacturing the same
US5452511A (en) 1993-11-04 1995-09-26 Chang; Alexander H. C. Composite lead frame manufacturing method
US5454905A (en) 1994-08-09 1995-10-03 National Semiconductor Corporation Method for manufacturing fine pitch lead frame
US5454904A (en) 1993-01-04 1995-10-03 General Electric Company Micromachining methods for making micromechanical moving structures including multiple contact switching system
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5484274A (en) 1992-11-24 1996-01-16 Neu Dynamics Corp. Encapsulation molding equipment
US5493151A (en) 1993-07-15 1996-02-20 Kabushiki Kaisha Toshiba Semiconductor device, lead frame and method for manufacturing semiconductor devices
US5508556A (en) 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
US5517056A (en) 1993-09-30 1996-05-14 Motorola, Inc. Molded carrier ring leadframe having a particular resin injecting area design for gate removal and semiconductor device employing the same
US5521429A (en) 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
US5528076A (en) 1995-02-01 1996-06-18 Motorola, Inc. Leadframe having metal impregnated silicon carbide mounting area
US5534467A (en) 1993-03-18 1996-07-09 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
US5539251A (en) 1992-05-11 1996-07-23 Micron Technology, Inc. Tie bar over chip lead frame design
US5543657A (en) 1994-10-07 1996-08-06 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5545923A (en) 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5544412A (en) 1994-05-24 1996-08-13 Motorola, Inc. Method for coupling a power lead to a bond pad in an electronic module
US5576517A (en) 1994-05-23 1996-11-19 General Electric Company Low Dielectric constant materials for high speed electronics
US5578525A (en) 1993-12-13 1996-11-26 Fujitsu Limited Semiconductor device and a fabrication process thereof
US5581122A (en) 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
US5592025A (en) 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5592019A (en) 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
US5594274A (en) 1993-07-01 1997-01-14 Nec Corporation Lead frame for use in a semiconductor device and method of manufacturing the semiconductor device using the same
US5595934A (en) 1995-05-17 1997-01-21 Samsung Electronics Co., Ltd. Method for forming oxide protective film on bonding pads of semiconductor chips by UV/O3 treatment
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
US5608267A (en) 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
US5608265A (en) 1993-03-17 1997-03-04 Hitachi, Ltd. Encapsulated semiconductor device package having holes for electrically conductive material
US5619068A (en) 1995-04-28 1997-04-08 Lucent Technologies Inc. Externally bondable overmolded package arrangements
US5625222A (en) 1993-11-18 1997-04-29 Fujitsu Limited Semiconductor device in a resin package housed in a frame having high thermal conductivity
US5633528A (en) 1994-05-25 1997-05-27 Texas Instruments Incorporated Lead frame structure for IC devices with strengthened encapsulation adhesion
US5640047A (en) 1995-09-25 1997-06-17 Mitsui High-Tec, Inc. Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding function
US5639990A (en) 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same
US5641997A (en) 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5643433A (en) 1992-12-23 1997-07-01 Shinko Electric Industries Co., Ltd. Lead frame and method for manufacturing same
US5644169A (en) 1993-03-04 1997-07-01 Goldstar Electron Co., Ltd. Mold and method for manufacturing a package for a semiconductor chip and the package manufactured thereby
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5661088A (en) 1996-01-11 1997-08-26 Motorola, Inc. Electronic component and method of packaging
US5665996A (en) 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
EP0794572A2 (en) 1996-03-07 1997-09-10 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
US5673479A (en) 1993-12-20 1997-10-07 Lsi Logic Corporation Method for mounting a microelectronic circuit peripherally-leaded package including integral support member with spacer
US5683806A (en) 1988-09-29 1997-11-04 Tomoegawa Paper Co., Ltd. Adhesive tapes
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5701034A (en) 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
US5703407A (en) 1995-02-14 1997-12-30 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device
US5710064A (en) 1994-08-16 1998-01-20 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor package
US5723899A (en) 1994-08-30 1998-03-03 Amkor Electronics, Inc. Semiconductor lead frame having connection bar and guide rings
US5724233A (en) 1993-07-09 1998-03-03 Fujitsu Limited Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag
US5726493A (en) 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure
US5736432A (en) 1996-09-20 1998-04-07 National Semiconductor Corporation Lead frame with lead finger locking feature and method for making same
US5736448A (en) 1995-12-04 1998-04-07 General Electric Company Fabrication method for thin film capacitors
US5745984A (en) 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5753977A (en) 1996-03-22 1998-05-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and lead frame therefor
US5753532A (en) 1995-08-30 1998-05-19 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor chip package
US5766972A (en) 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
US5770888A (en) 1995-12-29 1998-06-23 Lg Semicon Co., Ltd. Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US5769989A (en) 1995-09-19 1998-06-23 International Business Machines Corporation Method and system for reworkable direct chip attach (DCA) structure with thermal enhancement
US5776798A (en) 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US5783861A (en) 1994-03-29 1998-07-21 Lg Semicon Co., Ltd. Semiconductor package and lead frame
US5786238A (en) 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates
US5801440A (en) 1995-10-10 1998-09-01 Acc Microelectronics Corporation Chip package board having utility rings
US5814883A (en) 1995-10-04 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor chip
US5814881A (en) 1996-12-20 1998-09-29 Lsi Logic Corporation Stacked integrated chip package and method of making same
US5814884A (en) 1996-10-24 1998-09-29 International Rectifier Corporation Commonly housed diverse semiconductor die
US5817540A (en) 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
US5818105A (en) 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
US5821457A (en) 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US5821615A (en) 1995-12-06 1998-10-13 Lg Semicon Co., Ltd. Semiconductor chip package having clip-type outlead and fabrication method of same
US5834830A (en) 1995-12-18 1998-11-10 Lg Semicon Co., Ltd. LOC (lead on chip) package and fabricating method thereof
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5844306A (en) 1995-09-28 1998-12-01 Mitsubishi Denki Kabushiki Kaisha Die pad structure for solder bonding
US5856911A (en) 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US5859475A (en) 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5859471A (en) 1992-11-17 1999-01-12 Shinko Electric Industries Co., Ltd. Semiconductor device having tab tape lead frame with reinforced outer leads
US5866939A (en) 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5871782A (en) 1995-12-30 1999-02-16 Lg Semicon Co. Ltd. Transfer molding apparatus having laminated chase block
US5874784A (en) 1995-10-25 1999-02-23 Sharp Kabushiki Kaisha Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
US5874770A (en) 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
US5877043A (en) 1996-02-01 1999-03-02 International Business Machines Corporation Electronic package with strain relief means and method of making
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US5886398A (en) 1997-09-26 1999-03-23 Lsi Logic Corporation Molded laminate package with integral mold gate
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5897339A (en) 1996-09-11 1999-04-27 Samsung Electronics Co., Ltd. Lead-on-chip semiconductor device package having an adhesive layer formed from liquid adhesive and method for manufacturing the same
US5900676A (en) 1996-08-19 1999-05-04 Samsung Electronics Co., Ltd. Semiconductor device package structure having column leads and a method for production thereof
US5903050A (en) 1998-04-30 1999-05-11 Lsi Logic Corporation Semiconductor package having capacitive extension spokes and method for making the same
US5903049A (en) 1997-10-29 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor module comprising semiconductor packages
US5915998A (en) 1996-06-19 1999-06-29 Erico International Corporation Electrical connector and method of making
US5917242A (en) 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5937324A (en) 1996-08-26 1999-08-10 Motorola, Inc. Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits
US5939779A (en) 1996-05-17 1999-08-17 Lg Semicon Co., Ltd. Bottom lead semiconductor chip stack package
US5942794A (en) 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
KR100220154B1 (en) 1996-04-01 1999-09-01 김규현 Method manufacture of semiconductor package
US5951305A (en) 1998-07-09 1999-09-14 Tessera, Inc. Lidless socket and method of making same
US5959356A (en) 1995-11-25 1999-09-28 Samsung Electronics Co., Ltd. Solder ball grid array carrier package with heat sink
US5969426A (en) 1994-12-14 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Substrateless resin encapsulated semiconductor device
US5973388A (en) 1998-01-26 1999-10-26 Motorola, Inc. Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe
EP0844665A3 (en) 1996-11-21 1999-10-27 Texas Instruments Incorporated Wafer level packaging
US5977630A (en) 1997-08-15 1999-11-02 International Rectifier Corp. Plural semiconductor die housed in common package with split heat sink
US5977615A (en) 1996-12-24 1999-11-02 Matsushita Electronics Corporation Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5982632A (en) 1995-01-24 1999-11-09 Intel Corporation Short power signal path integrated circuit package
US5981314A (en) 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US5986333A (en) 1997-02-27 1999-11-16 Oki Electric Industry Co., Ltd. Semiconductor apparatus and method for fabricating the same
US5986885A (en) 1997-04-08 1999-11-16 Integrated Device Technology, Inc. Semiconductor package with internal heatsink and assembly method
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6013947A (en) 1997-06-27 2000-01-11 Trimecs Co., Ltd. Substrate having gate recesses or slots and molding device and molding method thereof
US6018189A (en) 1997-03-31 2000-01-25 Nec Corporation Lead frame for face-down bonding
US6020625A (en) 1998-03-27 2000-02-01 Mitsubishi Denki Kabushiki Kaisha Lead frame including hanging leads and hanging lead reinforcement in a semiconductor device including the lead frame
US6025640A (en) 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US6031279A (en) 1996-09-02 2000-02-29 Siemens Aktiengesellschaft Power semiconductor component
US6034423A (en) 1998-04-02 2000-03-07 National Semiconductor Corporation Lead frame design for increased chip pinout
USRE36613E (en) 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
US6040626A (en) 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US6043430A (en) 1997-03-14 2000-03-28 Lg Semicon Co., Ltd. Bottom lead semiconductor chip package
US6060768A (en) 1995-05-09 2000-05-09 Fujitsu Limited Semiconductor device, method of manufacturing the semiconductor device, and method of manufacturing lead frame
JP2000150765A (en) 1998-10-21 2000-05-30 Amkor Technology Inc Semiconductor integrated circuit plastic package, ultra- compact lead frame for manufacture thereof, and its manufacture
US6072228A (en) 1996-10-25 2000-06-06 Micron Technology, Inc. Multi-part lead frame with dissimilar materials and method of manufacturing
US6075284A (en) 1998-06-30 2000-06-13 Hyundai Electronics Industries Co., Ltd. Stack package
US6081029A (en) 1998-03-12 2000-06-27 Matsushita Electronics Corporation Resin encapsulated semiconductor device having a reduced thickness and improved reliability
US6084310A (en) 1997-04-21 2000-07-04 Nec Corporation Semiconductor device, lead frame, and lead bonding
US6087715A (en) 1997-04-22 2000-07-11 Kabushiki Kaisha Toshiba Semiconductor device, and manufacturing method of the same
US6087722A (en) 1998-05-28 2000-07-11 Samsung Electronics Co., Ltd. Multi-chip package
US6097089A (en) 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US6100594A (en) 1998-01-14 2000-08-08 Sharp Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6113474A (en) 1997-10-01 2000-09-05 Cummins Engine Company, Inc. Constant force truing and dressing apparatus and method
US6114752A (en) 1998-11-10 2000-09-05 Siliconware Precision Industries Co., Ltd. Semiconductor package having lead frame with an exposed base pad
US6118184A (en) 1997-07-18 2000-09-12 Sharp Kabushiki Kaisha Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow
US6118174A (en) 1996-12-28 2000-09-12 Lg Semicon Co., Ltd. Bottom lead frame and bottom lead semiconductor package using the same
US6127633A (en) 1995-04-28 2000-10-03 Victor Company Of Japan, Ltd. Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production
US6130473A (en) 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
USRE36907E (en) 1992-12-07 2000-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
US6133623A (en) 1996-07-03 2000-10-17 Seiko Epson Corporation Resin sealing type semiconductor device that includes a plurality of leads and method of making the same
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6169329B1 (en) 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6177718B1 (en) 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US6181002B1 (en) 1998-12-22 2001-01-30 Sharp Kabushiki Kaisha Semiconductor device having a plurality of semiconductor chips
US6184573B1 (en) 1999-05-13 2001-02-06 Siliconware Precision Industries Co., Ltd. Chip packaging
US6184465B1 (en) 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6194777B1 (en) 1998-06-27 2001-02-27 Texas Instruments Incorporated Leadframes with selective palladium plating
US6197615B1 (en) 1997-04-04 2001-03-06 Samsung Electronics Co., Ltd. Method of producing lead frame having uneven surfaces
US6198171B1 (en) 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
JP2001060648A (en) 1999-08-23 2001-03-06 Dainippon Printing Co Ltd Lead frame, manufacture thereof and semiconductor device
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6201186B1 (en) 1998-06-29 2001-03-13 Motorola, Inc. Electronic component assembly and method of making the same
US6204554B1 (en) 1996-09-05 2001-03-20 International Rectifier Corporation Surface mount semiconductor package
US6208020B1 (en) 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
US6208021B1 (en) 1996-03-27 2001-03-27 Oki Electric Industry Co., Ltd. Semiconductor device, manufacturing method thereof and aggregate type semiconductor device
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
US6211462B1 (en) 1998-11-05 2001-04-03 Texas Instruments Incorporated Low inductance power package for integrated circuits
US6214525B1 (en) 1996-09-06 2001-04-10 International Business Machines Corp. Printed circuit board with circuitized cavity and methods of producing same
US6217987B1 (en) 1996-11-20 2001-04-17 Ibiden Co. Ltd. Solder resist composition and printed circuit boards
US6218731B1 (en) 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6222258B1 (en) 1996-11-11 2001-04-24 Fujitsu Limited Semiconductor device and method for producing a semiconductor device
US6221754B1 (en) 1998-08-21 2001-04-24 United Microelectronics Corp. Method of fabricating a plug
US6222259B1 (en) 1998-09-15 2001-04-24 Hyundai Electronics Industries Co., Ltd. Stack package and method of fabricating the same
JP2001118947A (en) 1999-10-19 2001-04-27 Nec Corp Semiconductor device and method of manufacturing package therefor
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6229205B1 (en) 1997-06-30 2001-05-08 Samsung Electronics Co., Ltd. Semiconductor device package having twice-bent tie bar and small die pad
US6239384B1 (en) 1995-09-18 2001-05-29 Tessera, Inc. Microelectric lead structures with plural conductors
US6239367B1 (en) 1999-01-29 2001-05-29 United Microelectronics Corp. Multi-chip chip scale package
US6256200B1 (en) 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6258192B1 (en) 1999-02-10 2001-07-10 International Business Machines Corporation Multi-thickness, multi-layer green sheet processing
US6258629B1 (en) 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
US6261918B1 (en) 1999-10-04 2001-07-17 Conexant Systems, Inc. Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture
US20010008305A1 (en) 1998-06-10 2001-07-19 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US20010011654A1 (en) 1998-07-16 2001-08-09 The University Of Texas System Method for rapid drying of coated materials with close capture of vapors
US20010012704A1 (en) 1998-07-13 2001-08-09 Benjamin N. Eldridge Interconnect assemblies and methods
US20010014538A1 (en) 1998-06-10 2001-08-16 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
EP0459493B1 (en) 1990-06-01 2001-08-16 Kabushiki Kaisha Toshiba A semiconductor device comprising a TAB tape and its manufacturing method
US6282095B1 (en) 1999-02-02 2001-08-28 Compaq Computer Corporation Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures
US6281566B1 (en) 1996-09-30 2001-08-28 Sgs-Thomson Microelectronics S.R.L. Plastic package for electronic devices
US6285075B1 (en) 1998-11-02 2001-09-04 Asat, Limited Integrated circuit package with bonding planes on a ceramic ring using an adhesive assembly
US6291273B1 (en) 1996-12-26 2001-09-18 Hitachi, Ltd. Plastic molded type semiconductor device and fabrication process thereof
US6291271B1 (en) 1999-09-14 2001-09-18 Advanced Semiconductor Engineering, Inc. Method of making semiconductor chip package
US20010022396A1 (en) 1994-07-07 2001-09-20 Distefano Thomas H. Fan-out semiconductor chip assembly
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US6295977B1 (en) 1998-11-05 2001-10-02 Wacker Chemie Gmbh Method and device for simultaneously cutting off a multiplicity of wafers from a workpiece
US6303997B1 (en) 1998-04-08 2001-10-16 Anam Semiconductor, Inc. Thin, stackable semiconductor packages
US6303984B1 (en) 1997-08-12 2001-10-16 Micron Technology, Inc. Lead frame including angle iron tie bar
US6307272B1 (en) 1998-05-27 2001-10-23 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
US20010032738A1 (en) 1999-07-15 2001-10-25 Dibene Joseph Ted Method and apparatus for providing power to a microprocessor with integrated thermal and EMI management
US6309909B1 (en) 1998-07-02 2001-10-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6316822B1 (en) 1998-09-16 2001-11-13 Texas Instruments Incorporated Multichip assembly semiconductor
US6316838B1 (en) 1999-10-29 2001-11-13 Fujitsu Limited Semiconductor device
US6323550B1 (en) 1995-06-06 2001-11-27 Analog Devices, Inc. Package for sealing an integrated circuit die
US6326244B1 (en) 1998-09-03 2001-12-04 Micron Technology, Inc. Method of making a cavity ball grid array apparatus
US6326243B1 (en) 1995-08-15 2001-12-04 Kabushiki Kaisha Toshiba Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin
US6326678B1 (en) 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US6335564B1 (en) 1998-05-06 2002-01-01 Conexant Systems, Inc. Single Paddle having a semiconductor device and a passive electronic component
US6337510B1 (en) 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
US6339255B1 (en) 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
JP2002043497A (en) 2000-07-27 2002-02-08 Mitsubishi Electric Corp Semiconductor device
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US20020024122A1 (en) 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US20020027297A1 (en) 2000-09-04 2002-03-07 Chikao Ikenaga Semiconductor package
US6355502B1 (en) 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
US6365974B1 (en) 1999-03-23 2002-04-02 Texas Instruments Incorporated Flex circuit substrate for an integrated circuit package
US6369447B2 (en) 1998-04-20 2002-04-09 Mitsubishi Denki Kabushiki Kaisha Plastic-packaged semiconductor device including a plurality of chips
US6369454B1 (en) 1998-12-31 2002-04-09 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6373127B1 (en) 1998-09-29 2002-04-16 Texas Instruments Incorporated Integrated capacitor on the back of a chip
US6380048B1 (en) 2001-08-02 2002-04-30 St Assembly Test Services Pte Ltd Die paddle enhancement for exposed pad in semiconductor packaging
US6384472B1 (en) 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US6388336B1 (en) 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
US20020061642A1 (en) 1999-09-02 2002-05-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6396153B2 (en) 1999-10-04 2002-05-28 General Electric Company Circuit chip package and fabrication method
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6400004B1 (en) 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
US6410979B2 (en) 1998-12-21 2002-06-25 Nec Corporation Ball-grid-array semiconductor device with protruding terminals
KR20020049944A (en) 2000-12-20 2002-06-26 박종섭 semiconductor package and method for fabricating the same
US6414385B1 (en) 1999-11-08 2002-07-02 Siliconware Precisionindustries Co., Ltd. Quad flat non-lead package of semiconductor
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6418615B1 (en) 1999-03-11 2002-07-16 Shinko Electronics Industries, Co., Ltd. Method of making multilayered substrate for semiconductor device
US6429508B1 (en) 2000-08-09 2002-08-06 Kostat Semiconductor Co., Ltd. Semiconductor package having implantable conductive lands and method for manufacturing the same
US6437429B1 (en) 2001-05-11 2002-08-20 Walsin Advanced Electronics Ltd Semiconductor package with metal pads
US6444499B1 (en) 2000-03-30 2002-09-03 Amkor Technology, Inc. Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components
US6448633B1 (en) 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6459148B1 (en) 2000-11-13 2002-10-01 Walsin Advanced Electronics Ltd QFN semiconductor package
US20020140061A1 (en) 2001-03-27 2002-10-03 Lee Hyung Ju Lead frame for semiconductor package
US20020140068A1 (en) 2001-03-28 2002-10-03 Ming-Hsun Lee Leadframe-based semiconductor package for multi-media card
US6464121B2 (en) 2000-12-21 2002-10-15 Xerox Corporation Specialized tool adapted for a process for manufacture and interconnection between adjoining printed wiring boards
US6476469B2 (en) 2000-11-23 2002-11-05 Siliconware Precision Industries Co., Ltd. Quad flat non-leaded package structure for housing CMOS sensor
US6476474B1 (en) 2000-10-10 2002-11-05 Siliconware Precision Industries Co., Ltd. Dual-die package structure and method for fabricating the same
US20020163015A1 (en) 2001-02-27 2002-11-07 Chippac, Inc. Plastic semiconductor package
US6482680B1 (en) 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
US6486005B1 (en) 2000-04-03 2002-11-26 Hynix Semiconductor Inc. Semiconductor package and method for fabricating the same
US6498392B2 (en) 2000-01-24 2002-12-24 Nec Corporation Semiconductor devices having different package sizes made by using common parts
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6507096B2 (en) 2000-08-09 2003-01-14 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6507120B2 (en) 2000-12-22 2003-01-14 Siliconware Precision Industries Co., Ltd. Flip chip type quad flat non-leaded package
US20030013232A1 (en) 2001-07-11 2003-01-16 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US20030030131A1 (en) 2000-09-15 2003-02-13 Samsung Techwin Co., Ltd., Semiconductor package apparatus and method
US6521530B2 (en) 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6524885B2 (en) 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
US20030064548A1 (en) 2000-06-21 2003-04-03 Isaak Harlan R. Panel stacking of BGA devices to form three-dimensional modules
US6545332B2 (en) 2001-01-17 2003-04-08 Siliconware Precision Industries Co., Ltd. Image sensor of a quad flat package
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
US6549891B1 (en) 1996-03-26 2003-04-15 Recovery Management Corporation Method for managing inventory
US6548898B2 (en) 2000-12-28 2003-04-15 Fujitsu Limited External connection terminal and semiconductor device
US20030073265A1 (en) 2001-10-12 2003-04-17 Tom Hu Semiconductor package with singulation crease
US6559525B2 (en) 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
EP0936671B1 (en) 1998-02-12 2003-05-07 Hitachi, Ltd. Resin-moulded semiconductor hybrid module and manufacturing method thereof
US6583503B2 (en) 1997-03-10 2003-06-24 Micron Technology, Inc. Semiconductor package with stacked substrates and multiple semiconductor dice
US6593645B2 (en) 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
US20030134455A1 (en) 2002-01-15 2003-07-17 Jao-Chin Cheng Method of forming IC package having upward-facing chip cavity
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6667546B2 (en) 2001-11-15 2003-12-23 Siliconware Precision Industries Co., Ltd. Ball grid array semiconductor package and substrate without power ring or ground ring
US6671398B2 (en) 1998-09-09 2003-12-30 Applied Materials, Inc. Method and apparatus for inspection of patterned semiconductor wafers
US20040004293A1 (en) 2001-04-27 2004-01-08 Shinko Electric Industries Co., Ltd Semiconductor package
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
KR20040012028A (en) 2002-07-31 2004-02-11 앰코 테크놀로지 코리아 주식회사 chip size package
US20040026781A1 (en) 2001-09-28 2004-02-12 Toru Nakai Printed wiring board and production method for printed wiring board
US20040046244A1 (en) 2001-10-31 2004-03-11 Shinko Electric Industries Co., Ltd. Multilayered substrate for semiconductor device
US20040056277A1 (en) 2002-09-17 2004-03-25 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US20040061213A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040061212A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040063242A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20040063246A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
US6730857B2 (en) 2001-03-13 2004-05-04 International Business Machines Corporation Structure having laser ablated features and method of fabricating
US6740964B2 (en) 2000-11-17 2004-05-25 Oki Electric Industry Co., Ltd. Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US20040113260A1 (en) 2002-11-26 2004-06-17 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
DE19734794B4 (en) 1997-01-09 2004-09-23 Mitsubishi Denki K.K. A lead frame with a plurality of wiring parts for use in a semiconductor device
EP0720225B1 (en) 1994-12-30 2004-10-27 SILICONIX Incorporated Lateral power MOSFET having metal strap layer to reduce distributed resistance and method of fabricating the same
US6831371B1 (en) 2002-03-16 2004-12-14 Amkor Technology, Inc. Integrated circuit substrate having embedded wire conductors and method therefor
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US20050001309A1 (en) 2003-06-20 2005-01-06 Akinori Tanaka Printed wiring board for mounting semiconductor
US6845554B2 (en) 2001-11-22 2005-01-25 Infineon Technologies Ag Method for connection of circuit units
US6853060B1 (en) 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
US20050124093A1 (en) 2003-12-03 2005-06-09 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US6921975B2 (en) 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US20050242425A1 (en) 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
US20050266608A1 (en) 2004-05-28 2005-12-01 Via Technologies, Inc. Packaging substrate without plating bar and a method of forming the same
US20050282314A1 (en) 2004-06-17 2005-12-22 Advanced Semiconductor Engineering Inc. Printed circuit boards and methods for fabricating the same
US7015075B2 (en) 2004-02-09 2006-03-21 Freescale Semiconuctor, Inc. Die encapsulation using a porous carrier
US7041534B2 (en) 2003-08-28 2006-05-09 Advanced Semiconductor Engineering, Inc. Semiconductor chip package and method for making the same
US20060145343A1 (en) 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. BGA package having half-etched bonding pad and cut plating line and method of fabricating same
US20060209497A1 (en) 2003-10-03 2006-09-21 Kazuhiko Ooi Pad structure of wiring board and wiring board
US20060225918A1 (en) 2005-03-17 2006-10-12 Hitachi Cable, Ltd. Electronic device substrate and its fabrication method, and electronic device and its fabrication method
US20060231958A1 (en) 2003-12-03 2006-10-19 Advanced Chip Engineering Technology, Inc. Fan out type wafer level package structure and method of the same
US20060243478A1 (en) 2004-02-04 2006-11-02 Ibiden Co., Ltd Multilayer printed wiring board
US20060284309A1 (en) 2005-06-16 2006-12-21 Samsung Electronics Co., Ltd. Integrated circuit package and integrated circuit module
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US7202107B2 (en) 2003-07-28 2007-04-10 Infineon Technologies Ag Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
US7238602B2 (en) 2004-10-26 2007-07-03 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7272444B2 (en) 2003-05-07 2007-09-18 Cardiac Pacemakers, Inc. Medical device interface system with automatic rate threshold adjustment
US20070273049A1 (en) 2006-05-12 2007-11-29 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US20070290376A1 (en) 2006-06-20 2007-12-20 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7405484B2 (en) 2003-09-30 2008-07-29 Sanyo Electric Co., Ltd. Semiconductor device containing stacked semiconductor chips and manufacturing method thereof
US7405102B2 (en) 2006-06-09 2008-07-29 Freescale Semiconductor, Inc. Methods and apparatus for thermal management in a multi-layer embedded chip structure
US20080182363A1 (en) 2007-01-31 2008-07-31 Freescale Semiconductor, Inc. Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer
US7408261B2 (en) 2004-07-26 2008-08-05 Samsung Electro-Mechanics Co., Ltd. BGA package board and method for manufacturing the same
US20080230887A1 (en) 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof

Family Cites Families (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55163868U (en) 1979-05-11 1980-11-25
JPS55163868A (en) 1979-06-08 1980-12-20 Fujitsu Ltd Lead frame and semiconductor device using the same
JPS6010756Y2 (en) 1979-06-13 1985-04-11 アイダエンジニアリング株式会社 Roll feed device
JPS629639Y2 (en) 1979-12-21 1987-03-06
JPS6333854Y2 (en) 1979-12-26 1988-09-08
JPS56105199A (en) 1980-01-21 1981-08-21 Kawasaki Heavy Ind Ltd Antifreezing structure for low temperature underground tank bottom
JPS5745959Y2 (en) 1980-04-25 1982-10-09
JPS5717629A (en) 1980-07-08 1982-01-29 Tokyo Electric Co Ltd Electric cleaner
JPS5745959A (en) 1980-09-02 1982-03-16 Nec Corp Resin-sealed semiconductor device
JPS6139555Y2 (en) 1980-10-30 1986-11-13
JPS6010756B2 (en) 1981-05-15 1985-03-19 アイシン精機株式会社 sewing machine
JPS5817705A (en) 1981-07-23 1983-02-02 Mazda Motor Corp Antenna in common use for conductor for heating window glass of car
JPS5819384A (en) 1981-07-27 1983-02-04 Osaka Gas Co Ltd Heating of coke oven
JPS5868570A (en) 1981-10-19 1983-04-23 Matsushita Electric Ind Co Ltd Proportional control valve
JPS59208756A (en) 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
JPS59227143A (en) 1983-06-07 1984-12-20 Dainippon Printing Co Ltd Package of integrated circuit
JPS6010756A (en) 1983-06-30 1985-01-19 Nec Corp Manufacture of beam-lead type semiconductor device
JPS60116239A (en) 1983-11-28 1985-06-22 Nec Corp Radio communication equipment
JPS60116239U (en) 1984-01-12 1985-08-06 日産自動車株式会社 Power MOSFET mounting structure
JPS60195957A (en) 1984-03-19 1985-10-04 Hitachi Ltd Lead frame
JPS60231349A (en) 1984-05-01 1985-11-16 Toshiba Corp Lead frame
JPS60195957U (en) 1984-06-06 1985-12-27 スズキ株式会社 Engine intake air temperature automatic adjustment device
JPS6139555A (en) 1984-07-31 1986-02-25 Toshiba Corp Resin sealed type semiconductor device with heat sink
JPS62208213A (en) 1986-03-07 1987-09-12 株式会社新宮商行 Cord delivery apparatus of reaper
JPS629639A (en) 1985-07-05 1987-01-17 Nec Yamagata Ltd Manufacture of semiconductor device
JPS6333854A (en) 1986-07-28 1988-02-13 Dainippon Printing Co Ltd Integrated circuit package
JPS6367762A (en) 1986-09-09 1988-03-26 Fujitsu Ltd Lead frame for resin sealed semiconductor device
JPS6367762U (en) 1986-10-23 1988-05-07
JPS63188964A (en) 1987-01-31 1988-08-04 Dainippon Printing Co Ltd Integrated circuit package
JPS63205935A (en) 1987-02-23 1988-08-25 Toshiba Corp Resin-sealed type semiconductor device equipped with heat sink
JP2509607B2 (en) 1987-03-23 1996-06-26 株式会社東芝 Resin-sealed semiconductor device
JPS63249345A (en) 1987-04-06 1988-10-17 Olympus Optical Co Ltd Flexible mounting substrate
JP2548939B2 (en) 1987-05-22 1996-10-30 大日本印刷株式会社 Lead frame for IC card
JPS63188964U (en) 1987-05-28 1988-12-05
JP2656495B2 (en) 1987-06-19 1997-09-24 株式会社フロンテック Method for manufacturing thin film transistor
JPS6454749A (en) 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPS6454749U (en) 1987-09-30 1989-04-04
JPH01106456A (en) 1987-10-19 1989-04-24 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JPH01175250A (en) 1987-12-28 1989-07-11 Sony Corp Lead frame and semiconductor device using it
JPH01106456U (en) 1988-01-08 1989-07-18
JPH01205544A (en) 1988-02-12 1989-08-17 Seiko Epson Corp Assembly tape of integrated circuit device
JPH01251747A (en) 1988-03-31 1989-10-06 Toshiba Corp Semiconductor device and manufacture thereof
JPH02129948A (en) 1988-11-09 1990-05-18 Dainippon Printing Co Ltd Pre-molded type semiconductor device
JPH0369248A (en) 1989-08-08 1991-03-25 Nec Off Syst Ltd Telephone set
JPH0732208B2 (en) 1989-10-31 1995-04-10 三菱電機株式会社 Semiconductor device
JPH0369248U (en) 1989-11-10 1991-07-09
JPH0692076B2 (en) 1989-11-22 1994-11-16 工業技術院長 Walking leg motion control device
JPH03177060A (en) 1989-12-05 1991-08-01 Mitsubishi Electric Corp Lead frame for semiconductor device
JPH0498864A (en) 1990-08-16 1992-03-31 Nec Kyushu Ltd Resin sealed type semiconductor device
JPH0498864U (en) 1991-01-31 1992-08-26
JPH05129473A (en) 1991-11-06 1993-05-25 Sony Corp Resin-sealed surface-mounting semiconductor device
JPH05166992A (en) 1991-12-13 1993-07-02 Fujitsu Ltd Semiconductor device
JP3480950B2 (en) 1992-04-02 2003-12-22 新光電気工業株式会社 Semiconductor device and film carrier for semiconductor device
GB9216079D0 (en) 1992-07-28 1992-09-09 Foseco Int Lining of molten metal handling vessel
JPH0692076A (en) 1992-09-16 1994-04-05 Oki Electric Ind Co Ltd Lead frame form for ic card module
JPH06140563A (en) 1992-10-23 1994-05-20 Rohm Co Ltd Semiconductor device
JP3259420B2 (en) 1993-03-05 2002-02-25 ソニー株式会社 Flip chip connection structure
JPH07297344A (en) 1994-04-25 1995-11-10 Toshiba Corp Lead frame
JP3243116B2 (en) 1994-05-17 2002-01-07 株式会社日立製作所 Semiconductor device
JPH0883877A (en) 1994-07-12 1996-03-26 Sony Corp Lead frame
JP3027512B2 (en) 1994-08-23 2000-04-04 株式会社日立製作所 Power MOSFET
JP3475306B2 (en) 1994-10-26 2003-12-08 大日本印刷株式会社 Method for manufacturing resin-encapsulated semiconductor device
JPH08222682A (en) 1995-02-14 1996-08-30 Dainippon Printing Co Ltd Lead frame and manufacturing method thereof
JPH098205A (en) 1995-06-14 1997-01-10 Dainippon Printing Co Ltd Resin sealed semiconductor device
JPH098206A (en) 1995-06-19 1997-01-10 Dainippon Printing Co Ltd Lead frame and bga resin sealed semiconductor device
JPH098207A (en) 1995-06-21 1997-01-10 Dainippon Printing Co Ltd Resin sealed semiconductor device
JP3163961B2 (en) 1995-09-22 2001-05-08 日立電線株式会社 Semiconductor device
JPH09293822A (en) 1996-04-25 1997-11-11 Seiko Epson Corp Semiconductor device with lead frame for power source only
JP2811170B2 (en) 1996-06-28 1998-10-15 株式会社後藤製作所 Resin-sealed semiconductor device and method of manufacturing the same
JPH10163401A (en) 1996-12-04 1998-06-19 Sony Corp Lead frame, semiconductor package, and manufacture of semiconductor package
JPH10256240A (en) 1997-01-10 1998-09-25 Sony Corp Manufacture of semiconductor device
JPH10199934A (en) 1997-01-13 1998-07-31 Hitachi Ltd Mounting structure of semiconductor element and mounting method thereof
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
JP3487774B2 (en) 1998-11-19 2004-01-19 沖電気工業株式会社 Transport method in semiconductor device manufacturing process
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6455355B1 (en) * 2001-04-10 2002-09-24 Siliconware Precision Industries, Co., Ltd. Method of mounting an exposed-pad type of semiconductor device over a printed circuit board
TW557521B (en) * 2002-01-16 2003-10-11 Via Tech Inc Integrated circuit package and its manufacturing process
JP5005603B2 (en) * 2008-04-03 2012-08-22 新光電気工業株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (437)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2596993A (en) 1949-01-13 1952-05-20 United Shoe Machinery Corp Method and mold for covering of eyelets by plastic injection
US3435815A (en) 1966-07-15 1969-04-01 Micro Tech Mfg Inc Wafer dicer
US3734660A (en) 1970-01-09 1973-05-22 Tuthill Pump Co Apparatus for fabricating a bearing device
US4189342A (en) 1971-10-07 1980-02-19 U.S. Philips Corporation Semiconductor device comprising projecting contact layers
US3781596A (en) 1972-07-07 1973-12-25 R Galli Semiconductor chip carriers and strips thereof
US3838984A (en) 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US4054238A (en) 1976-03-23 1977-10-18 Western Electric Company, Inc. Method, apparatus and lead frame for assembling leads with terminals on a substrate
US4258381A (en) 1977-12-07 1981-03-24 Steag, Kernergie Gmbh Lead frame for a semiconductor device suitable for mass production
US4332537A (en) 1978-07-17 1982-06-01 Dusan Slepcevic Encapsulation mold with removable cavity plates
US4301464A (en) 1978-08-02 1981-11-17 Hitachi, Ltd. Lead frame and semiconductor device employing the same with improved arrangement of supporting leads for securing the semiconductor supporting member
US4541003A (en) 1978-12-27 1985-09-10 Hitachi, Ltd. Semiconductor device including an alpha-particle shield
US4289922A (en) 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
US4417266A (en) 1981-08-14 1983-11-22 Amp Incorporated Power and ground plane structure for chip carrier
US4451224A (en) 1982-03-25 1984-05-29 General Electric Company Mold device for making plastic articles from resin
US4530152A (en) 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
US4646710A (en) 1982-09-22 1987-03-03 Crystal Systems, Inc. Multi-wafer slicing with a fixed abrasive
US4737839A (en) 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
US4707724A (en) 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
US4862246A (en) 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
US4862245A (en) 1985-04-18 1989-08-29 International Business Machines Corporation Package semiconductor chip
US4729061A (en) 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US4727633A (en) 1985-08-08 1988-03-01 Tektronix, Inc. Method of securing metallic members together
US4756080A (en) 1986-01-27 1988-07-12 American Microsystems, Inc. Metal foil semiconductor interconnection method
US4812896A (en) 1986-11-13 1989-03-14 Olin Corporation Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant
US5087961A (en) 1987-01-28 1992-02-11 Lsi Logic Corporation Semiconductor device package
US4920074A (en) 1987-02-25 1990-04-24 Hitachi, Ltd. Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US5059379A (en) 1987-07-20 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Method of resin sealing semiconductor devices
US4942454A (en) 1987-08-05 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
US5122860A (en) 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
US4987475A (en) 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US4907067A (en) 1988-05-11 1990-03-06 Texas Instruments Incorporated Thermally efficient power device package
US5096852A (en) 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
US5157475A (en) 1988-07-08 1992-10-20 Oki Electric Industry Co., Ltd. Semiconductor device having a particular conductive lead structure
US4935803A (en) 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5277972B1 (en) 1988-09-29 1996-11-05 Tomoegawa Paper Co Ltd Adhesive tapes
US5277972A (en) 1988-09-29 1994-01-11 Tomoegawa Paper Co., Ltd. Adhesive tapes
US5683806A (en) 1988-09-29 1997-11-04 Tomoegawa Paper Co., Ltd. Adhesive tapes
US5057900A (en) 1988-10-17 1991-10-15 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5018003A (en) 1988-10-20 1991-05-21 Mitsubishi Denki Kabushiki Kaisha Lead frame and semiconductor device
US5266834A (en) 1989-03-13 1993-11-30 Hitachi Ltd. Semiconductor device and an electronic device with the semiconductor devices mounted thereon
US5070039A (en) 1989-04-13 1991-12-03 Texas Instruments Incorporated Method of making an integrated circuit using a pre-served dam bar to reduce mold flash and to facilitate flash removal
EP0393997B1 (en) 1989-04-20 1995-02-01 Honeywell Inc. Method of providing a variable-pitch leadframe assembly
US5091341A (en) 1989-05-22 1992-02-25 Kabushiki Kaisha Toshiba Method of sealing semiconductor device with resin by pressing a lead frame to a heat sink using an upper mold pressure member
US5417905A (en) 1989-05-26 1995-05-23 Esec (Far East) Limited Method of making a card having decorations on both faces
US5134773A (en) 1989-05-26 1992-08-04 Gerard Lemaire Method for making a credit card containing a microprocessor chip
US5065223A (en) 1989-05-31 1991-11-12 Fujitsu Vlsi Limited Packaged semiconductor device
US5175060A (en) 1989-07-01 1992-12-29 Ibiden Co., Ltd. Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same
US5218231A (en) 1989-08-30 1993-06-08 Kabushiki Kaisha Toshiba Mold-type semiconductor device
US5273938A (en) 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5041902A (en) 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
US5151039A (en) 1990-04-06 1992-09-29 Advanced Interconnections Corporation Integrated circuit adapter having gullwing-shaped leads
EP0459493B1 (en) 1990-06-01 2001-08-16 Kabushiki Kaisha Toshiba A semiconductor device comprising a TAB tape and its manufacturing method
US5343076A (en) 1990-07-21 1994-08-30 Mitsui Petrochemical Industries, Ltd. Semiconductor device with an airtight space formed internally within a hollow package
US5279029A (en) 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5029386A (en) 1990-09-17 1991-07-09 Hewlett-Packard Company Hierarchical tape automated bonding method
US5335771A (en) 1990-09-25 1994-08-09 R. H. Murphy Company, Inc. Spacer trays for stacking storage trays with integrated circuits
US5391439A (en) 1990-09-27 1995-02-21 Dai Nippon Printing Co., Ltd. Leadframe adapted to support semiconductor elements
US5435057A (en) 1990-10-30 1995-07-25 International Business Machines Corporation Interconnection method and structure for organic circuit boards
US5216278A (en) 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5172214A (en) 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5118298A (en) 1991-04-04 1992-06-02 Advanced Interconnections Corporation Through hole mounting of integrated circuit adapter leads
US5281849A (en) 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
US5168368A (en) 1991-05-09 1992-12-01 International Business Machines Corporation Lead frame-chip package with improved configuration
US5172213A (en) 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
US5221642A (en) 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
US5258094A (en) 1991-09-18 1993-11-02 Nec Corporation Method for producing multilayer printed wiring boards
US5252853A (en) 1991-09-19 1993-10-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device having tab tape and particular power distribution lead structure
US5200809A (en) 1991-09-27 1993-04-06 Vlsi Technology, Inc. Exposed die-attach heatsink package
US5332864A (en) 1991-12-27 1994-07-26 Vlsi Technology, Inc. Integrated circuit package having an interposer
US5381042A (en) 1992-03-31 1995-01-10 Amkor Electronics, Inc. Packaged integrated circuit including heat slug having an exposed surface
US5250841A (en) 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads
US5214845A (en) 1992-05-11 1993-06-01 Micron Technology, Inc. Method for producing high speed integrated circuits
US5539251A (en) 1992-05-11 1996-07-23 Micron Technology, Inc. Tie bar over chip lead frame design
US5639990A (en) 1992-06-05 1997-06-17 Mitsui Toatsu Chemicals, Inc. Solid printed substrate and electronic circuit package using the same
US5278446A (en) 1992-07-06 1994-01-11 Motorola, Inc. Reduced stress plastic package
US5294897A (en) 1992-07-20 1994-03-15 Mitsubishi Denki Kabushiki Kaisha Microwave IC package
US5410180A (en) 1992-07-28 1995-04-25 Shinko Electric Industries Co., Ltd. Metal plane support for multi-layer lead frames and a process for manufacturing such frames
US5592025A (en) 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5428248A (en) 1992-08-21 1995-06-27 Goldstar Electron Co., Ltd. Resin molded semiconductor package
US5394303A (en) 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5608267A (en) 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
US5365106A (en) 1992-10-27 1994-11-15 Kabushiki Kaisha Toshiba Resin mold semiconductor device
US5859471A (en) 1992-11-17 1999-01-12 Shinko Electric Industries Co., Ltd. Semiconductor device having tab tape lead frame with reinforced outer leads
US5484274A (en) 1992-11-24 1996-01-16 Neu Dynamics Corp. Encapsulation molding equipment
US5268310A (en) 1992-11-25 1993-12-07 M/A-Com, Inc. Method for making a mesa type PIN diode
US5406124A (en) 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
USRE36907E (en) 1992-12-07 2000-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
US5643433A (en) 1992-12-23 1997-07-01 Shinko Electric Industries Co., Ltd. Lead frame and method for manufacturing same
US5909053A (en) 1992-12-23 1999-06-01 Shinko Electric Industries Co. Ltd. Lead frame and method for manufacturing same
US5454904A (en) 1993-01-04 1995-10-03 General Electric Company Micromachining methods for making micromechanical moving structures including multiple contact switching system
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5497033A (en) 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5432677A (en) 1993-02-09 1995-07-11 Texas Instruments Incorporated Multi-chip integrated circuit module
US5644169A (en) 1993-03-04 1997-07-01 Goldstar Electron Co., Ltd. Mold and method for manufacturing a package for a semiconductor chip and the package manufactured thereby
US5608265A (en) 1993-03-17 1997-03-04 Hitachi, Ltd. Encapsulated semiconductor device package having holes for electrically conductive material
US5534467A (en) 1993-03-18 1996-07-09 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
US5424576A (en) 1993-03-22 1995-06-13 Motorola, Inc. Semiconductor device having x-shaped die support member and method for making the same
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
US5358905A (en) 1993-04-02 1994-10-25 Texas Instruments Incorporated Semiconductor device having die pad locking to substantially reduce package cracking
USRE36613E (en) 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5444301A (en) 1993-06-23 1995-08-22 Goldstar Electron Co. Ltd. Semiconductor package and method for manufacturing the same
US5594274A (en) 1993-07-01 1997-01-14 Nec Corporation Lead frame for use in a semiconductor device and method of manufacturing the semiconductor device using the same
US5724233A (en) 1993-07-09 1998-03-03 Fujitsu Limited Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag
US5493151A (en) 1993-07-15 1996-02-20 Kabushiki Kaisha Toshiba Semiconductor device, lead frame and method for manufacturing semiconductor devices
US6326678B1 (en) 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5336931A (en) 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
US5641997A (en) 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5414299A (en) 1993-09-24 1995-05-09 Vlsi Technology, Inc. Semi-conductor device interconnect package assembly for improved package performance
US5517056A (en) 1993-09-30 1996-05-14 Motorola, Inc. Molded carrier ring leadframe having a particular resin injecting area design for gate removal and semiconductor device employing the same
US5545923A (en) 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5452511A (en) 1993-11-04 1995-09-26 Chang; Alexander H. C. Composite lead frame manufacturing method
US5625222A (en) 1993-11-18 1997-04-29 Fujitsu Limited Semiconductor device in a resin package housed in a frame having high thermal conductivity
US5521429A (en) 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
US5578525A (en) 1993-12-13 1996-11-26 Fujitsu Limited Semiconductor device and a fabrication process thereof
US5673479A (en) 1993-12-20 1997-10-07 Lsi Logic Corporation Method for mounting a microelectronic circuit peripherally-leaded package including integral support member with spacer
US5821457A (en) 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5783861A (en) 1994-03-29 1998-07-21 Lg Semicon Co., Ltd. Semiconductor package and lead frame
US5592019A (en) 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
US5701034A (en) 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
US5576517A (en) 1994-05-23 1996-11-19 General Electric Company Low Dielectric constant materials for high speed electronics
US5544412A (en) 1994-05-24 1996-08-13 Motorola, Inc. Method for coupling a power lead to a bond pad in an electronic module
US5633528A (en) 1994-05-25 1997-05-27 Texas Instruments Incorporated Lead frame structure for IC devices with strengthened encapsulation adhesion
US5766972A (en) 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
US5726493A (en) 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
US20010022396A1 (en) 1994-07-07 2001-09-20 Distefano Thomas H. Fan-out semiconductor chip assembly
US5818105A (en) 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
US5454905A (en) 1994-08-09 1995-10-03 National Semiconductor Corporation Method for manufacturing fine pitch lead frame
US5710064A (en) 1994-08-16 1998-01-20 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor package
US5723899A (en) 1994-08-30 1998-03-03 Amkor Electronics, Inc. Semiconductor lead frame having connection bar and guide rings
US5508556A (en) 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
US5814877A (en) 1994-10-07 1998-09-29 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5543657A (en) 1994-10-07 1996-08-06 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5581122A (en) 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
US5969426A (en) 1994-12-14 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Substrateless resin encapsulated semiconductor device
EP0720225B1 (en) 1994-12-30 2004-10-27 SILICONIX Incorporated Lateral power MOSFET having metal strap layer to reduce distributed resistance and method of fabricating the same
EP0720234B1 (en) 1994-12-30 2006-03-08 SILICONIX Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same
US5665996A (en) 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
US5982632A (en) 1995-01-24 1999-11-09 Intel Corporation Short power signal path integrated circuit package
US5528076A (en) 1995-02-01 1996-06-18 Motorola, Inc. Leadframe having metal impregnated silicon carbide mounting area
US5703407A (en) 1995-02-14 1997-12-30 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device
US5619068A (en) 1995-04-28 1997-04-08 Lucent Technologies Inc. Externally bondable overmolded package arrangements
US6127633A (en) 1995-04-28 2000-10-03 Victor Company Of Japan, Ltd. Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production
US6060768A (en) 1995-05-09 2000-05-09 Fujitsu Limited Semiconductor device, method of manufacturing the semiconductor device, and method of manufacturing lead frame
US5595934A (en) 1995-05-17 1997-01-21 Samsung Electronics Co., Ltd. Method for forming oxide protective film on bonding pads of semiconductor chips by UV/O3 treatment
US6323550B1 (en) 1995-06-06 2001-11-27 Analog Devices, Inc. Package for sealing an integrated circuit die
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
US5745984A (en) 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US6326243B1 (en) 1995-08-15 2001-12-04 Kabushiki Kaisha Toshiba Resin sealed semiconductor device including a die pad uniformly having heat conducting paths and circulating holes for fluid resin
US5753532A (en) 1995-08-30 1998-05-19 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor chip package
US6239384B1 (en) 1995-09-18 2001-05-29 Tessera, Inc. Microelectric lead structures with plural conductors
US5769989A (en) 1995-09-19 1998-06-23 International Business Machines Corporation Method and system for reworkable direct chip attach (DCA) structure with thermal enhancement
US5640047A (en) 1995-09-25 1997-06-17 Mitsui High-Tec, Inc. Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding function
US5844306A (en) 1995-09-28 1998-12-01 Mitsubishi Denki Kabushiki Kaisha Die pad structure for solder bonding
US5814883A (en) 1995-10-04 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor chip
US5801440A (en) 1995-10-10 1998-09-01 Acc Microelectronics Corporation Chip package board having utility rings
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5874784A (en) 1995-10-25 1999-02-23 Sharp Kabushiki Kaisha Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
US5959356A (en) 1995-11-25 1999-09-28 Samsung Electronics Co., Ltd. Solder ball grid array carrier package with heat sink
US5736448A (en) 1995-12-04 1998-04-07 General Electric Company Fabrication method for thin film capacitors
US5821615A (en) 1995-12-06 1998-10-13 Lg Semicon Co., Ltd. Semiconductor chip package having clip-type outlead and fabrication method of same
US5834830A (en) 1995-12-18 1998-11-10 Lg Semicon Co., Ltd. LOC (lead on chip) package and fabricating method thereof
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US5770888A (en) 1995-12-29 1998-06-23 Lg Semicon Co., Ltd. Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US5871782A (en) 1995-12-30 1999-02-16 Lg Semicon Co. Ltd. Transfer molding apparatus having laminated chase block
US5661088A (en) 1996-01-11 1997-08-26 Motorola, Inc. Electronic component and method of packaging
US5866939A (en) 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5877043A (en) 1996-02-01 1999-03-02 International Business Machines Corporation Electronic package with strain relief means and method of making
EP0794572A2 (en) 1996-03-07 1997-09-10 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
US5977613A (en) 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
US5753977A (en) 1996-03-22 1998-05-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and lead frame therefor
US6549891B1 (en) 1996-03-26 2003-04-15 Recovery Management Corporation Method for managing inventory
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US6208021B1 (en) 1996-03-27 2001-03-27 Oki Electric Industry Co., Ltd. Semiconductor device, manufacturing method thereof and aggregate type semiconductor device
KR100220154B1 (en) 1996-04-01 1999-09-01 김규현 Method manufacture of semiconductor package
US6169329B1 (en) 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6294830B1 (en) 1996-04-18 2001-09-25 Tessera, Inc. Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
US5859475A (en) 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5939779A (en) 1996-05-17 1999-08-17 Lg Semicon Co., Ltd. Bottom lead semiconductor chip stack package
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6159767A (en) 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5917242A (en) 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5915998A (en) 1996-06-19 1999-06-29 Erico International Corporation Electrical connector and method of making
US6133623A (en) 1996-07-03 2000-10-17 Seiko Epson Corporation Resin sealing type semiconductor device that includes a plurality of leads and method of making the same
US5900676A (en) 1996-08-19 1999-05-04 Samsung Electronics Co., Ltd. Semiconductor device package structure having column leads and a method for production thereof
US5937324A (en) 1996-08-26 1999-08-10 Motorola, Inc. Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits
US6031279A (en) 1996-09-02 2000-02-29 Siemens Aktiengesellschaft Power semiconductor component
US5776798A (en) 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US6204554B1 (en) 1996-09-05 2001-03-20 International Rectifier Corporation Surface mount semiconductor package
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US6214525B1 (en) 1996-09-06 2001-04-10 International Business Machines Corp. Printed circuit board with circuitized cavity and methods of producing same
US5897339A (en) 1996-09-11 1999-04-27 Samsung Electronics Co., Ltd. Lead-on-chip semiconductor device package having an adhesive layer formed from liquid adhesive and method for manufacturing the same
US5736432A (en) 1996-09-20 1998-04-07 National Semiconductor Corporation Lead frame with lead finger locking feature and method for making same
US6060769A (en) 1996-09-20 2000-05-09 Micron Technology, Inc. Flip-chip on leads devices
US5817540A (en) 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
US6281566B1 (en) 1996-09-30 2001-08-28 Sgs-Thomson Microelectronics S.R.L. Plastic package for electronic devices
US5874770A (en) 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
US5942794A (en) 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US6130115A (en) 1996-10-22 2000-10-10 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US5814884C1 (en) 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
US5814884A (en) 1996-10-24 1998-09-29 International Rectifier Corporation Commonly housed diverse semiconductor die
US6140154A (en) 1996-10-25 2000-10-31 Micron Technology, Inc. Multi-part lead frame with dissimilar materials and method of manufacturing
US6072228A (en) 1996-10-25 2000-06-06 Micron Technology, Inc. Multi-part lead frame with dissimilar materials and method of manufacturing
US5981314A (en) 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6222258B1 (en) 1996-11-11 2001-04-24 Fujitsu Limited Semiconductor device and method for producing a semiconductor device
US5856911A (en) 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US6217987B1 (en) 1996-11-20 2001-04-17 Ibiden Co. Ltd. Solder resist composition and printed circuit boards
EP0844665A3 (en) 1996-11-21 1999-10-27 Texas Instruments Incorporated Wafer level packaging
US5814881A (en) 1996-12-20 1998-09-29 Lsi Logic Corporation Stacked integrated chip package and method of making same
US5977615A (en) 1996-12-24 1999-11-02 Matsushita Electronics Corporation Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device
US6225146B1 (en) 1996-12-24 2001-05-01 Matsushita Electronics Corporation Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device
US6291273B1 (en) 1996-12-26 2001-09-18 Hitachi, Ltd. Plastic molded type semiconductor device and fabrication process thereof
US6118174A (en) 1996-12-28 2000-09-12 Lg Semicon Co., Ltd. Bottom lead frame and bottom lead semiconductor package using the same
DE19734794B4 (en) 1997-01-09 2004-09-23 Mitsubishi Denki K.K. A lead frame with a plurality of wiring parts for use in a semiconductor device
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5786238A (en) 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates
US5986333A (en) 1997-02-27 1999-11-16 Oki Electric Industry Co., Ltd. Semiconductor apparatus and method for fabricating the same
US6583503B2 (en) 1997-03-10 2003-06-24 Micron Technology, Inc. Semiconductor package with stacked substrates and multiple semiconductor dice
US6043430A (en) 1997-03-14 2000-03-28 Lg Semicon Co., Ltd. Bottom lead semiconductor chip package
US6018189A (en) 1997-03-31 2000-01-25 Nec Corporation Lead frame for face-down bonding
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6197615B1 (en) 1997-04-04 2001-03-06 Samsung Electronics Co., Ltd. Method of producing lead frame having uneven surfaces
US5986885A (en) 1997-04-08 1999-11-16 Integrated Device Technology, Inc. Semiconductor package with internal heatsink and assembly method
US6084310A (en) 1997-04-21 2000-07-04 Nec Corporation Semiconductor device, lead frame, and lead bonding
US6087715A (en) 1997-04-22 2000-07-11 Kabushiki Kaisha Toshiba Semiconductor device, and manufacturing method of the same
US6013947A (en) 1997-06-27 2000-01-11 Trimecs Co., Ltd. Substrate having gate recesses or slots and molding device and molding method thereof
US6229205B1 (en) 1997-06-30 2001-05-08 Samsung Electronics Co., Ltd. Semiconductor device package having twice-bent tie bar and small die pad
US6025640A (en) 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US6118184A (en) 1997-07-18 2000-09-12 Sharp Kabushiki Kaisha Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
US6303984B1 (en) 1997-08-12 2001-10-16 Micron Technology, Inc. Lead frame including angle iron tie bar
US5977630A (en) 1997-08-15 1999-11-02 International Rectifier Corp. Plural semiconductor die housed in common package with split heat sink
US5886398A (en) 1997-09-26 1999-03-23 Lsi Logic Corporation Molded laminate package with integral mold gate
US6113474A (en) 1997-10-01 2000-09-05 Cummins Engine Company, Inc. Constant force truing and dressing apparatus and method
US5903049A (en) 1997-10-29 1999-05-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor module comprising semiconductor packages
US6100594A (en) 1998-01-14 2000-08-08 Sharp Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5973388A (en) 1998-01-26 1999-10-26 Motorola, Inc. Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe
US6097089A (en) 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
EP0936671B1 (en) 1998-02-12 2003-05-07 Hitachi, Ltd. Resin-moulded semiconductor hybrid module and manufacturing method thereof
US6081029A (en) 1998-03-12 2000-06-27 Matsushita Electronics Corporation Resin encapsulated semiconductor device having a reduced thickness and improved reliability
US6020625A (en) 1998-03-27 2000-02-01 Mitsubishi Denki Kabushiki Kaisha Lead frame including hanging leads and hanging lead reinforcement in a semiconductor device including the lead frame
US6130473A (en) 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
US6034423A (en) 1998-04-02 2000-03-07 National Semiconductor Corporation Lead frame design for increased chip pinout
US6303997B1 (en) 1998-04-08 2001-10-16 Anam Semiconductor, Inc. Thin, stackable semiconductor packages
US6369447B2 (en) 1998-04-20 2002-04-09 Mitsubishi Denki Kabushiki Kaisha Plastic-packaged semiconductor device including a plurality of chips
US6177718B1 (en) 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US5903050A (en) 1998-04-30 1999-05-11 Lsi Logic Corporation Semiconductor package having capacitive extension spokes and method for making the same
US6335564B1 (en) 1998-05-06 2002-01-01 Conexant Systems, Inc. Single Paddle having a semiconductor device and a passive electronic component
US6307272B1 (en) 1998-05-27 2001-10-23 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
US6087722A (en) 1998-05-28 2000-07-11 Samsung Electronics Co., Ltd. Multi-chip package
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US20010008305A1 (en) 1998-06-10 2001-07-19 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6242281B1 (en) 1998-06-10 2001-06-05 Asat, Limited Saw-singulated leadless plastic chip carrier
US20010014538A1 (en) 1998-06-10 2001-08-16 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6194777B1 (en) 1998-06-27 2001-02-27 Texas Instruments Incorporated Leadframes with selective palladium plating
US6201186B1 (en) 1998-06-29 2001-03-13 Motorola, Inc. Electronic component assembly and method of making the same
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US6075284A (en) 1998-06-30 2000-06-13 Hyundai Electronics Industries Co., Ltd. Stack package
US6309909B1 (en) 1998-07-02 2001-10-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5951305A (en) 1998-07-09 1999-09-14 Tessera, Inc. Lidless socket and method of making same
US20010012704A1 (en) 1998-07-13 2001-08-09 Benjamin N. Eldridge Interconnect assemblies and methods
US20010011654A1 (en) 1998-07-16 2001-08-09 The University Of Texas System Method for rapid drying of coated materials with close capture of vapors
US6221754B1 (en) 1998-08-21 2001-04-24 United Microelectronics Corp. Method of fabricating a plug
US6326244B1 (en) 1998-09-03 2001-12-04 Micron Technology, Inc. Method of making a cavity ball grid array apparatus
US6671398B2 (en) 1998-09-09 2003-12-30 Applied Materials, Inc. Method and apparatus for inspection of patterned semiconductor wafers
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6222259B1 (en) 1998-09-15 2001-04-24 Hyundai Electronics Industries Co., Ltd. Stack package and method of fabricating the same
US6316822B1 (en) 1998-09-16 2001-11-13 Texas Instruments Incorporated Multichip assembly semiconductor
EP0989608A3 (en) 1998-09-21 2001-01-10 Amkor Technology Inc. Plastic integrated circuit device package and method of making the same
US6040626A (en) 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US6373127B1 (en) 1998-09-29 2002-04-16 Texas Instruments Incorporated Integrated capacitor on the back of a chip
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
JP2000150765A (en) 1998-10-21 2000-05-30 Amkor Technology Inc Semiconductor integrated circuit plastic package, ultra- compact lead frame for manufacture thereof, and its manufacture
US6339255B1 (en) 1998-10-24 2002-01-15 Hyundai Electronics Industries Co., Ltd. Stacked semiconductor chips in a single semiconductor package
US6285075B1 (en) 1998-11-02 2001-09-04 Asat, Limited Integrated circuit package with bonding planes on a ceramic ring using an adhesive assembly
US6211462B1 (en) 1998-11-05 2001-04-03 Texas Instruments Incorporated Low inductance power package for integrated circuits
US6295977B1 (en) 1998-11-05 2001-10-02 Wacker Chemie Gmbh Method and device for simultaneously cutting off a multiplicity of wafers from a workpiece
US6114752A (en) 1998-11-10 2000-09-05 Siliconware Precision Industries Co., Ltd. Semiconductor package having lead frame with an exposed base pad
US6184465B1 (en) 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6521530B2 (en) 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6448633B1 (en) 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6410979B2 (en) 1998-12-21 2002-06-25 Nec Corporation Ball-grid-array semiconductor device with protruding terminals
US6181002B1 (en) 1998-12-22 2001-01-30 Sharp Kabushiki Kaisha Semiconductor device having a plurality of semiconductor chips
US6369454B1 (en) 1998-12-31 2002-04-09 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6239367B1 (en) 1999-01-29 2001-05-29 United Microelectronics Corp. Multi-chip chip scale package
US6282095B1 (en) 1999-02-02 2001-08-28 Compaq Computer Corporation Method and system for controlling radio frequency radiation in microelectronic packages using heat dissipation structures
US6258192B1 (en) 1999-02-10 2001-07-10 International Business Machines Corporation Multi-thickness, multi-layer green sheet processing
EP1032037B1 (en) 1999-02-24 2004-06-09 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
US6208020B1 (en) 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
US6418615B1 (en) 1999-03-11 2002-07-16 Shinko Electronics Industries, Co., Ltd. Method of making multilayered substrate for semiconductor device
US6365974B1 (en) 1999-03-23 2002-04-02 Texas Instruments Incorporated Flex circuit substrate for an integrated circuit package
US6184573B1 (en) 1999-05-13 2001-02-06 Siliconware Precision Industries Co., Ltd. Chip packaging
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6218731B1 (en) 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6256200B1 (en) 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US20010032738A1 (en) 1999-07-15 2001-10-25 Dibene Joseph Ted Method and apparatus for providing power to a microprocessor with integrated thermal and EMI management
US6258629B1 (en) 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
JP2001060648A (en) 1999-08-23 2001-03-06 Dainippon Printing Co Ltd Lead frame, manufacture thereof and semiconductor device
US20020061642A1 (en) 1999-09-02 2002-05-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6291271B1 (en) 1999-09-14 2001-09-18 Advanced Semiconductor Engineering, Inc. Method of making semiconductor chip package
US6388336B1 (en) 1999-09-15 2002-05-14 Texas Instruments Incorporated Multichip semiconductor assembly
US6593645B2 (en) 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
US6396153B2 (en) 1999-10-04 2002-05-28 General Electric Company Circuit chip package and fabrication method
US6261918B1 (en) 1999-10-04 2001-07-17 Conexant Systems, Inc. Method for creating and preserving alignment marks for aligning mask layers in integrated circuit manufacture
JP2001118947A (en) 1999-10-19 2001-04-27 Nec Corp Semiconductor device and method of manufacturing package therefor
US6316838B1 (en) 1999-10-29 2001-11-13 Fujitsu Limited Semiconductor device
US6414385B1 (en) 1999-11-08 2002-07-02 Siliconware Precisionindustries Co., Ltd. Quad flat non-lead package of semiconductor
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6198171B1 (en) 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
US6559525B2 (en) 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
US6498392B2 (en) 2000-01-24 2002-12-24 Nec Corporation Semiconductor devices having different package sizes made by using common parts
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6384472B1 (en) 2000-03-24 2002-05-07 Siliconware Precision Industries Co., Ltd Leadless image sensor package structure and method for making the same
US6444499B1 (en) 2000-03-30 2002-09-03 Amkor Technology, Inc. Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components
US6486005B1 (en) 2000-04-03 2002-11-26 Hynix Semiconductor Inc. Semiconductor package and method for fabricating the same
US6355502B1 (en) 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
US20030064548A1 (en) 2000-06-21 2003-04-03 Isaak Harlan R. Panel stacking of BGA devices to form three-dimensional modules
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2002043497A (en) 2000-07-27 2002-02-08 Mitsubishi Electric Corp Semiconductor device
US6429508B1 (en) 2000-08-09 2002-08-06 Kostat Semiconductor Co., Ltd. Semiconductor package having implantable conductive lands and method for manufacturing the same
US6507096B2 (en) 2000-08-09 2003-01-14 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6566168B2 (en) 2000-08-09 2003-05-20 Kostat Semiconductor Co., Inc. Semiconductor package having implantable conductive lands and method for manufacturing the same
US6534849B1 (en) 2000-08-09 2003-03-18 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6400004B1 (en) 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
US20020024122A1 (en) 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US20020027297A1 (en) 2000-09-04 2002-03-07 Chikao Ikenaga Semiconductor package
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US20030030131A1 (en) 2000-09-15 2003-02-13 Samsung Techwin Co., Ltd., Semiconductor package apparatus and method
US6476474B1 (en) 2000-10-10 2002-11-05 Siliconware Precision Industries Co., Ltd. Dual-die package structure and method for fabricating the same
US6459148B1 (en) 2000-11-13 2002-10-01 Walsin Advanced Electronics Ltd QFN semiconductor package
US6337510B1 (en) 2000-11-17 2002-01-08 Walsin Advanced Electronics Ltd Stackable QFN semiconductor package
US6740964B2 (en) 2000-11-17 2004-05-25 Oki Electric Industry Co., Ltd. Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US6476469B2 (en) 2000-11-23 2002-11-05 Siliconware Precision Industries Co., Ltd. Quad flat non-leaded package structure for housing CMOS sensor
US6524885B2 (en) 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
KR20020049944A (en) 2000-12-20 2002-06-26 박종섭 semiconductor package and method for fabricating the same
US6464121B2 (en) 2000-12-21 2002-10-15 Xerox Corporation Specialized tool adapted for a process for manufacture and interconnection between adjoining printed wiring boards
US6507120B2 (en) 2000-12-22 2003-01-14 Siliconware Precision Industries Co., Ltd. Flip chip type quad flat non-leaded package
US6548898B2 (en) 2000-12-28 2003-04-15 Fujitsu Limited External connection terminal and semiconductor device
US6545332B2 (en) 2001-01-17 2003-04-08 Siliconware Precision Industries Co., Ltd. Image sensor of a quad flat package
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US20020163015A1 (en) 2001-02-27 2002-11-07 Chippac, Inc. Plastic semiconductor package
US6919514B2 (en) 2001-03-13 2005-07-19 International Business Machines Corporation Structure having laser ablated features and method of fabricating
US6730857B2 (en) 2001-03-13 2004-05-04 International Business Machines Corporation Structure having laser ablated features and method of fabricating
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
US20020140061A1 (en) 2001-03-27 2002-10-03 Lee Hyung Ju Lead frame for semiconductor package
US6603196B2 (en) 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US20020140068A1 (en) 2001-03-28 2002-10-03 Ming-Hsun Lee Leadframe-based semiconductor package for multi-media card
US20040004293A1 (en) 2001-04-27 2004-01-08 Shinko Electric Industries Co., Ltd Semiconductor package
US6437429B1 (en) 2001-05-11 2002-08-20 Walsin Advanced Electronics Ltd Semiconductor package with metal pads
US20030013232A1 (en) 2001-07-11 2003-01-16 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6482680B1 (en) 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
US6380048B1 (en) 2001-08-02 2002-04-30 St Assembly Test Services Pte Ltd Die paddle enhancement for exposed pad in semiconductor packaging
US20040026781A1 (en) 2001-09-28 2004-02-12 Toru Nakai Printed wiring board and production method for printed wiring board
US7129158B2 (en) 2001-09-28 2006-10-31 Ibiden Co., Ltd. Printed wiring board and production method for printed wiring board
US20030073265A1 (en) 2001-10-12 2003-04-17 Tom Hu Semiconductor package with singulation crease
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
US20040046244A1 (en) 2001-10-31 2004-03-11 Shinko Electric Industries Co., Ltd. Multilayered substrate for semiconductor device
US6667546B2 (en) 2001-11-15 2003-12-23 Siliconware Precision Industries Co., Ltd. Ball grid array semiconductor package and substrate without power ring or ground ring
US6845554B2 (en) 2001-11-22 2005-01-25 Infineon Technologies Ag Method for connection of circuit units
US20030134455A1 (en) 2002-01-15 2003-07-17 Jao-Chin Cheng Method of forming IC package having upward-facing chip cavity
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6831371B1 (en) 2002-03-16 2004-12-14 Amkor Technology, Inc. Integrated circuit substrate having embedded wire conductors and method therefor
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
KR20040012028A (en) 2002-07-31 2004-02-11 앰코 테크놀로지 코리아 주식회사 chip size package
US20040061212A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040063246A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040056277A1 (en) 2002-09-17 2004-03-25 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US20040061213A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040063242A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7247523B1 (en) 2002-11-08 2007-07-24 Amkor Technology, Inc. Two-sided wafer escape package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7192807B1 (en) 2002-11-08 2007-03-20 Amkor Technology, Inc. Wafer level package and fabrication method
US7692286B1 (en) 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7714431B1 (en) 2002-11-08 2010-05-11 Amkor Technology, Inc. Electronic component package comprising fan-out and fan-in traces
US7932595B1 (en) 2002-11-08 2011-04-26 Amkor Technology, Inc. Electronic component package comprising fan-out traces
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US7420272B1 (en) 2002-11-08 2008-09-02 Amkor Technology, Inc. Two-sided wafer escape package
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US20040113260A1 (en) 2002-11-26 2004-06-17 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US7361987B2 (en) 2003-04-18 2008-04-22 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US20080142960A1 (en) 2003-04-18 2008-06-19 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US6921975B2 (en) 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
US6853060B1 (en) 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
US7272444B2 (en) 2003-05-07 2007-09-18 Cardiac Pacemakers, Inc. Medical device interface system with automatic rate threshold adjustment
US20050001309A1 (en) 2003-06-20 2005-01-06 Akinori Tanaka Printed wiring board for mounting semiconductor
US7202107B2 (en) 2003-07-28 2007-04-10 Infineon Technologies Ag Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
US7041534B2 (en) 2003-08-28 2006-05-09 Advanced Semiconductor Engineering, Inc. Semiconductor chip package and method for making the same
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7405484B2 (en) 2003-09-30 2008-07-29 Sanyo Electric Co., Ltd. Semiconductor device containing stacked semiconductor chips and manufacturing method thereof
US20060209497A1 (en) 2003-10-03 2006-09-21 Kazuhiko Ooi Pad structure of wiring board and wiring board
US20090051025A1 (en) 2003-12-03 2009-02-26 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7459781B2 (en) 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US7196408B2 (en) 2003-12-03 2007-03-27 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US7262081B2 (en) 2003-12-03 2007-08-28 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US20050124093A1 (en) 2003-12-03 2005-06-09 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US20070059866A1 (en) 2003-12-03 2007-03-15 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US20060231958A1 (en) 2003-12-03 2006-10-19 Advanced Chip Engineering Technology, Inc. Fan out type wafer level package structure and method of the same
US20080105967A1 (en) 2003-12-03 2008-05-08 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US20060243478A1 (en) 2004-02-04 2006-11-02 Ibiden Co., Ltd Multilayer printed wiring board
US7015075B2 (en) 2004-02-09 2006-03-21 Freescale Semiconuctor, Inc. Die encapsulation using a porous carrier
US20060192301A1 (en) 2004-04-30 2006-08-31 Leal George R Semiconductor device with a protected active die region and method therefor
US20050242425A1 (en) 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
US20050266608A1 (en) 2004-05-28 2005-12-01 Via Technologies, Inc. Packaging substrate without plating bar and a method of forming the same
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US20050282314A1 (en) 2004-06-17 2005-12-22 Advanced Semiconductor Engineering Inc. Printed circuit boards and methods for fabricating the same
US7408261B2 (en) 2004-07-26 2008-08-05 Samsung Electro-Mechanics Co., Ltd. BGA package board and method for manufacturing the same
US7339279B2 (en) 2004-10-26 2008-03-04 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
US7238602B2 (en) 2004-10-26 2007-07-03 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
US20060145343A1 (en) 2004-12-30 2006-07-06 Samsung Electro-Mechanics Co., Ltd. BGA package having half-etched bonding pad and cut plating line and method of fabricating same
US20060225918A1 (en) 2005-03-17 2006-10-12 Hitachi Cable, Ltd. Electronic device substrate and its fabrication method, and electronic device and its fabrication method
US20080128884A1 (en) 2005-04-04 2008-06-05 Torsten Meyer Stacked Die Package
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US20060284309A1 (en) 2005-06-16 2006-12-21 Samsung Electronics Co., Ltd. Integrated circuit package and integrated circuit module
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US20070273049A1 (en) 2006-05-12 2007-11-29 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7405102B2 (en) 2006-06-09 2008-07-29 Freescale Semiconductor, Inc. Methods and apparatus for thermal management in a multi-layer embedded chip structure
US20070290376A1 (en) 2006-06-20 2007-12-20 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US20080182363A1 (en) 2007-01-31 2008-07-31 Freescale Semiconductor, Inc. Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer
US20080230887A1 (en) 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Berry et al., "Direct-write Wafer Level Chip Scale Package", U.S. Appl. No. 11/289,826, filed Nov. 29, 2005.
Berry et al., "Direct-Write Wafer Level Chip Scale Package", U.S. Appl. No. 12/661,597, filed Mar. 19, 2010.
Huemoeller et al., "Integrated Circuit Film Substrate Having Embedded Conductive Patterns and Vias", U.S. Appl. No. 10/261,868, filed Oct. 1, 2002.
Huemoeller et al., "Wafer Level Package and Fabrication Method," U.S. Appl. No. 13/358,947, filed Jan. 26, 2012.
Huemoeller et al., "Wafer Level Package and Fabrication Method," U.S. Appl. No. 13/627,815, filed Sep. 26, 2012.
Kim et al., "Application of Through Mold Via (TMV) as PoP base package", 58th ECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE.
Scanlan, "Package-on-package (PoP) with Through-mold Vias", Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation.

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US10886232B2 (en) 2019-05-10 2021-01-05 Applied Materials, Inc. Package structure and fabrication methods
US11063169B2 (en) 2019-05-10 2021-07-13 Applied Materials, Inc. Substrate structuring methods
US11264331B2 (en) 2019-05-10 2022-03-01 Applied Materials, Inc. Package structure and fabrication methods
US11064615B2 (en) 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package

Also Published As

Publication number Publication date
US7192807B1 (en) 2007-03-20
US8710649B1 (en) 2014-04-29
US8486764B1 (en) 2013-07-16
US7932595B1 (en) 2011-04-26
US8691632B1 (en) 2014-04-08
US7692286B1 (en) 2010-04-06
US7714431B1 (en) 2010-05-11
US7247523B1 (en) 2007-07-24
US10665567B1 (en) 2020-05-26
US9054117B1 (en) 2015-06-09
US7420272B1 (en) 2008-09-02
US8119455B1 (en) 2012-02-21
US9406645B1 (en) 2016-08-02
US8952522B1 (en) 2015-02-10
US9871015B1 (en) 2018-01-16
US6905914B1 (en) 2005-06-14
US8298866B1 (en) 2012-10-30

Similar Documents

Publication Publication Date Title
US8501543B1 (en) Direct-write wafer level chip scale package
US8188584B1 (en) Direct-write wafer level chip scale package
US6025995A (en) Integrated circuit module and method
US6251705B1 (en) Low profile integrated circuit packages
US6022758A (en) Process for manufacturing solder leads on a semiconductor device package
US6852607B2 (en) Wafer level package having a side package
KR100555241B1 (en) An electronic component package with posts on the active surface
US7115483B2 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
US7241679B2 (en) Method of manufacturing semiconductor device
US6605525B2 (en) Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed
US6384478B1 (en) Leadframe having a paddle with an isolated area
US7241643B1 (en) Wafer level chip scale package
US9345143B2 (en) Method of fabricating a wiring board
WO1999057763A1 (en) Leadframe having a paddle with an isolated area and a single paddle having a semiconductor device and a passive electronic component
JP2005538572A (en) Cutting method for wafer coating and die separation
DE102020112941A1 (en) SENSOR PACKAGE AND PROCEDURE
US6461894B2 (en) Methods of forming a circuit and methods of preparing an integrated circuit
EP1193750A3 (en) Micro soldering method and apparatus
US20100075462A1 (en) Method of forming semiconductor package
JP2001118953A (en) Manufacturing method of semiconductor electronic part
EP1291906A4 (en) Semiconductor device and fabrication method therefor
US6653168B2 (en) LSI package and internal connecting method used therefor
US20040248342A1 (en) Method for packaging integrated circuit chips
US6777648B2 (en) Method and system to manufacture stacked chip devices
JP2002515651A (en) Semiconductor device and method of manufacturing semiconductor device

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: BANK OF AMERICA, N.A., TEXAS

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:035613/0592

Effective date: 20150409

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:046683/0139

Effective date: 20180713

AS Assignment

Owner name: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMKOR TECHNOLOGY, INC.;REEL/FRAME:054067/0135

Effective date: 20191119

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8