US8482973B2 - Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material - Google Patents

Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material Download PDF

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US8482973B2
US8482973B2 US13/568,834 US201213568834A US8482973B2 US 8482973 B2 US8482973 B2 US 8482973B2 US 201213568834 A US201213568834 A US 201213568834A US 8482973 B2 US8482973 B2 US 8482973B2
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semiconductor junction
junction diode
diode
memory cell
silicon
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US20120300533A1 (en
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S. Brad Herner
Abhijit Bandyopadhyay
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SanDisk Technologies LLC
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SanDisk 3D LLC
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Priority claimed from US10/855,784 external-priority patent/US6952030B2/en
Priority claimed from US10/955,549 external-priority patent/US8637366B2/en
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/36Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/39Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors

Definitions

  • the invention relates to a nonvolatile one-time-programmable memory cell.
  • the dielectric antifuse layer (typically a layer of silicon dioxide) acts as an insulator, and when a read voltage is applied between the conductors, very little current flows between the conductors. When a sufficiently large voltage is applied between the conductors, however, the dielectric antifuse layer suffers dielectric breakdown and ruptures, and a permanent conductive path is formed through the dielectric antifuse layer.
  • a programmed cell when a read voltage is applied between conductors, a significantly higher current flows than in the unprogrammed cell, allowing the unprogrammed and programmed cells to be distinguished.
  • the memory state is stored in the state of the dielectric antifuse layer, which may be intact or ruptured.
  • Memory cells based on rupture of a dielectric antifuse layer suffer some disadvantages. If the dielectric antifuse layer is too thin, leakage current can be a severe problem. Disturb can also be a problem: every time the memory cell is read, the dielectric antifuse layer is exposed to some stress, and may eventually break down and be inadvertently programmed. This is avoided by making the dielectric antifuse layer thicker, but a thicker dielectric antifuse layer requires higher programming voltage to rupture.
  • dielectric antifuse layer is an oxide layer formed by oxidation
  • a thicker antifuse layer calls for either higher temperatures or slower fabrication time, both disadvantageous in forming a commercial device.
  • the present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
  • the invention is directed to a nonvolatile memory cell comprising a diode, the memory state stored in the state of the diode.
  • a first aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first maximum barrier height, and after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.
  • a nonvolatile memory cell including: a first conductor; a second conductor; and a polycrystalline semiconductor junction diode disposed between the first and second conductors, wherein a data state of the memory cell is determined by a state of an antifuse, and wherein the polycrystalline semiconductor junction diode is the antifuse.
  • Yet another aspect of the invention provides for a method for forming and programming a nonvolatile memory cell, the method including: forming a first conductor; forming a second conductor; depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors; crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline, wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and programming the memory cell by applying a programming voltage between the first and second conductors, wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
  • a preferred embodiment of the invention provides for a monolithic three dimensional memory array including: a) a first memory level above a substrate, the first memory level comprising: i) a first plurality of substantially parallel conductors; ii) a second plurality of substantially parallel conductors above the first conductors; iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and b) a second memory level mono
  • a monolithic three dimensional memory array including: a) a first memory level comprising: i) a plurality of bottom conductors; ii) a plurality of top conductors; and iii) a plurality of first polycrystalline semiconductor junction diodes, each diode disposed between one of the bottom and one of the top conductors; and iv) a first memory cell comprising one of the first diodes, wherein the data state of the first memory cells is determined by the state of an antifuse, and wherein the diode of the first memory cell is the antifuse; and b) a second memory level monolithically formed above the first memory level.
  • a final aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first rectification ratio at a read voltage between about 0.5 and about 2.5 volts, and after application of the programming voltage the diode has a second rectification ratio at the read voltage, the second rectification ratio at least 10 times the first rectification ratio.
  • FIG. 1 is a perspective view of a memory cell formed according to the present invention.
  • FIG. 2 is a graph showing I-V curves for an unprogrammed cell and a programmed cell formed like the cell of FIG. 1 .
  • FIG. 3 is a graph showing barrier height between 0 and 2.5 bias volts for a programmed and an unprogrammed memory cell formed according to the present invention.
  • FIG. 4 is a graph showing unprogrammed and programmed current for a cell according to the present invention at an applied read voltage.
  • FIG. 5 is a perspective view of a memory level according to the present invention.
  • FIGS. 6 a - 6 c are cross-sectional views showing stages in formation of a memory level according to the present invention.
  • FIG. 7 is a dark field TEM image showing crystal defects in silicon in a memory cell according to the present invention, shown in cross-section.
  • FIGS. 8 a - 8 b are cross-sectional views showing stages in formation of a memory level with a silicide contact described in U.S. patent application Ser. No. 10/955,387.
  • FIG. 9 is a dark field TEM image showing relatively defect-free silicon in the memory cell described in U.S. patent application Ser. No. 10/955,387, shown in cross-section.
  • FIG. 10 is a graph showing barrier height between 0 and 2.5 bias volts for a memory cell described in U.S. patent application Ser. No. 10/955,387.
  • FIG. 11 is a SEM image showing preferential etching of unprogrammed diodes in a memory level of the present invention.
  • FIG. 1 A preferred embodiment of a memory cell described in the '549 application is shown in FIG. 1 .
  • a diode 30 is disposed between a bottom conductor 20 and a top conductor 40 .
  • Diode 30 is in electrical contact with bottom conductor 20 and top conductor 40 , with no dielectric layer interposed between them.
  • Titanium nitride layer 8 is a conductive barrier layer to prevent reaction between tungsten layer 6 and the silicon of diode 30 .
  • Titanium nitride layer 18 serves as an adhesion layer and as a barrier layer between diode 30 and tungsten layer 22 .
  • the diode was formed by depositing and doping a silicon layer stack and patterning and etching the layer stack to form a pillar. Regions of the layer stack were doped (by in situ doping or by ion implantation) to form a p-i-n diode; in a preferred embodiment bottom region 10 was heavily doped n-type silicon, middle region 12 was intrinsic, undoped silicon, and top region 14 was heavily doped p-type silicon.
  • This diode is a form of semiconductor junction diode; this term refers to a semiconductor device with the property of conducting current more easily in one direction than the other, having two terminal electrodes, and made of semiconducting material which is p-type at one electrode and n-type at the other.
  • the silicon of diode 30 was annealed (either in a separate anneal step or during subsequent thermal processing) to fully crystallize it.
  • diode 30 is polycrystalline.
  • diode 30 has an I-V curve like the curve labeled “before programming) in the graph of FIG. 2 , allowing little current to flow when a typical read voltage, for example 2 volts, is applied between bottom conductor 20 and top conductor 40 . It was found that applying a programming voltage of, for example, about 8 volts between bottom conductor 20 and top conductor 40 permanently changes diode 30 .
  • the I-V curve labeled “after programming” in FIG. 2 shows current for the diode after programming. After programming, current increases sharply as the turn-on voltage is reached, and the programmed diode allows significantly more current to flow when a read voltage of 2 volts is applied between bottom conductor 20 and top conductor 40 . The difference in current flow at an applied read voltage allows a programmed cell to be distinguished from an unprogrammed cell, and thus for the cell to store a memory state (data “0” or data “1”, for example.) This cell does not include a dielectric antifuse layer.
  • a material exhibiting ohmic behavior conducts with equal ease in both directions, and current increases linearly with voltage.
  • a diode exhibits non-ohmic behavior: It conducts current more easily in one direction than the other, and has a non-linear relationship between voltage and current, as shown in FIG. 2 .
  • One measure of the effectiveness of a diode is its barrier height over a range of applied voltages.
  • the barrier height (roughly speaking, the barrier to current flow) is high at very low voltage, between about 0 and 0.2 volts, drops abruptly as the turn-on voltage is approached, and is very low above the turn-on voltage.
  • FIG. 3 shows the barrier height of the diode of FIG. 1 before and after programming at an applied bias ranging from 0 to 2.5 volts.
  • the maximum barrier height of a programmed diode (curve A in FIG. 3 ) is 0.218 electron-volts, nearly twice the maximum barrier height of an unprogrammed diode (curve B), which is 0.144 electron-volts.
  • the memory cell of the present invention is a nonvolatile memory cell comprising: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first maximum barrier height, and after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height, in some embodiments 1.7 times the first maximum barrier height.
  • Read voltages are selected to be well above the turn-on voltage, which for silicon is theoretically at a bias voltage of 1.1 volts.
  • the barrier height of a programmed diode is significantly less than that of an unprogrammed diode.
  • FIG. 4 which is a probability plot showing current for a distribution of programmed and unprogrammed diodes, the median current for unprogrammed cells (curve C) at 2 volts is 1.2 ⁇ 10 ⁇ 8 amps, while the median current for programmed cells (curve D) at 2 volts is 4.8 ⁇ 10 ⁇ 5 amps, a difference of more than three orders of magnitude.
  • a diode allows current to flow more easily in one direction than in the opposite direction; the diode is said to be rectifying. More current will flow through a diode when the diode is positively biased at a given voltage, for example 2 volts, than when the diode is negatively biased at the same voltage.
  • the ratio of these currents is the rectification ratio and is another measure of diode quality.
  • the diodes of the present invention show a large increase in rectification ratio after programming.
  • current through an unprogrammed diode at ⁇ 2 volts was about 8.1 ⁇ 10 ⁇ 13 amps, as compared to a current under positive bias of 2 volts of about 1.3 ⁇ 10 ⁇ 8 amps, yielding a rectification ratio at 2 volts of about 1.6 ⁇ 10 4 .
  • a programmed diode of the present invention will have a rectification ratio at 2 volts at least 100 times the rectification ratio at 2 volts of the unprogrammed diode. In less preferred embodiments, the rectification ratio at 2 volts will be at least 10 times higher after programming than before programming. For silicon, rectification ratio at 2 volts has been discussed. Two volts was selected because it is an advantageous read voltage.
  • an I-V curve for a diode has a characteristic shape: It is initially very low, rises abruptly as the turn-on voltage is reached, then stabilizes above the turn-on voltage. Two volts is an advantageous read voltage in the present invention because it is in the stable part of the curve, above the turn-on voltage. More generally, the diode of the present invention shows a large increase in rectification ratio, at least 10 times, in preferred embodiments 100 times, at a read voltage.
  • a read voltage is a voltage in the stable part of the curve, above the diode's turn-on voltage. Read voltages for silicon may range between about 1.5 volts and about 2.5 volts.
  • an appropriate read voltage will be lower, between about 0.5 volts and about 2.0 volts, preferably about 1.2 volts.
  • Semiconductor diodes formed of alloys comprising silicon and germanium will have intermediate read voltages, depending on the relative compositions of silicon and germanium, and will be between about 1.2 and about 2.0 volts.
  • Memory cells formed according to the present invention having diodes formed of germanium or semiconductor alloys comprising silicon and germanium will have a first rectification ratio before programming and a second rectification ratio after programming, the second rectification ratio at least 10 times the first rectification ratio, and in preferred embodiments at least 100 times the first rectification ratio.
  • FIG. 5 shows a memory level of exemplary memory cells formed according to the present invention, including bottom conductors 200 , pillars 300 (each pillar 300 comprising a diode), and top conductors 400 . Fabrication of this memory level will be described. More detailed information regarding fabrication of such a memory level is provided in the '470 and '549 applications, previously incorporated.
  • fabrication of a memory level comprising memory cells formed according to the present invention begins over a suitable substrate 100 , for example a monocrystalline semiconductor wafer substrate.
  • Circuitry such as sense amplifiers and drivers, can be formed in substrate 100 before fabrication of the memory level begins.
  • An insulating layer 102 is formed above substrate 100 .
  • Conductive layers 104 and 106 are deposited.
  • Layer 104 is an adhesion layer, preferably of titanium nitride.
  • Layer 106 is a conductive material, for example tungsten. Other conductive materials may be preferred.
  • Layers 104 and 106 are patterned and etched to form substantially parallel, substantially coplanar rail-shaped bottom conductors 200 , shown here in cross-section extending out of the page.
  • a dielectric material 108 is deposited over and between conductors 200 , filling gaps between them.
  • a planarizing step for example by chemical mechanical polishing (CMP), exposes tops of conductors 200 and creates a substantially planar surface.
  • CMP chemical mechanical polishing
  • barrier layer 110 is deposited.
  • This layer is preferably about 200 angstroms thick, and provides a chemical barrier between the conductive layer 106 and the semiconductor material to be deposited next.
  • Barrier layer 110 is preferably titanium nitride, though other appropriate barrier materials, for example tantalum nitride, tantalum, titanium tungsten, tungsten nitride, or tungsten, could be used instead.
  • the diode to be formed will be a vertically oriented p-i-n diode, having a heavily doped p-type region at one end, an intrinsic middle region (not intentionally doped), and a heavily doped n-type region at the other end.
  • the bottom region will be heavily doped n-type
  • the middle region will be intrinsic
  • the top region will be heavily doped p-type.
  • the conductivity types could be reversed if desired.
  • intrinsic silicon deposited with no dopants
  • this region could be lightly doped.
  • a semiconductor layer stack is deposited on barrier layer 110 .
  • the semiconductor material can be silicon, germanium, a silicon-germanium alloy, or any semiconductor alloy including silicon and/or germanium.
  • different parts of the layer stack comprise different semiconductor materials or alloys, as in the '577 application.
  • the semiconductor material is silicon, and bottom region 112 is heavily doped with an n-type dopant, for example phosphorus or arsenic, preferably by in situ doping.
  • an n-type dopant for example phosphorus or arsenic, preferably by in situ doping.
  • the silicon that will make up the rest of the diode, regions 114 and 116 is deposited next.
  • the thickness of silicon that will form regions 114 and 116 is preferably deposited undoped.
  • the top heavily doped p-type region 116 could be formed during deposition by in situ doping, but in preferred embodiments will be doped in a later implant step.
  • Silicon regions 116 (not yet doped), 114 and 112 and barrier layer 110 are patterned and etched to form pillars 300 .
  • U.S. patent application Ser. No. 11/061,952, “Method for Patterning Submicron Pillars,” filed Feb. 17, 2005, all three owned by the assignee of the present invention and hereby incorporated by reference, can advantageously be used to perform any photolithography step used in formation of a memory array according to the present invention.
  • Dielectric material 108 is deposited over and between pillars 300 , filling gaps between them.
  • a planarizing step for example by CMP, exposes tops of pillars 300 and forms a substantially planar surface.
  • heavily doped p-type region 116 is preferably formed at the tops of pillars 300 by ion implantation of a p-type dopant, for example boron or BF 2 .
  • Diodes 118 which are p-i-n diodes, have been formed.
  • the height (silicon thickness) of completed diodes 118 can range from about 800 to about 4000 angstroms. (Some silicon thickness may be lost during the planarizing step; an extra thickness should be deposited to compensate.) Intrinsic region 114 can be from about 600 to about 3500 angstroms thick. The structure at this point is shown in FIG. 6 b.
  • Adhesion layer 120 is preferably any of the materials used for barrier layer 110 , for example titanium nitride.
  • Conductive layer 122 can be any appropriate conductive material, for example tungsten.
  • Layers 120 and 122 are patterned and etched to form substantially parallel, substantially coplanar top conductors 400 .
  • Bottom conductors 200 extended in a first direction; top conductors 400 extend in a second direction different from the first direction, preferably perpendicular to it.
  • Each diode 118 is vertically disposed between one of bottom conductors 200 and one of top conductors 400 .
  • FIG. 6 c What has been formed, shown in FIG. 6 c , is a first memory level.
  • An interlevel dielectric can be formed above this first memory level, planarized, and a second memory level can be fabricated on this planarized dielectric surface as described.
  • Multiple memory levels of the same type can be monolithically formed above the same substrate, each fabricated on a prior memory level, to form a monolithic three dimensional memory array like those described in the '549 and '470 applications.
  • Each memory cell will be programmed by applying a programming voltage between about 3 and about 15 volts, preferably between about 6 and about 10 volts, preferably between about 7 and about 9 volts, for example about 8 volts.
  • the programming voltage selected will depend on a variety of factors, including the volume of each diode, initial defect density, dopant profile, and the semiconductor material used to form the diodes.
  • the read voltage will also vary, from about 0.5 to about 3 volts, for example between about 1 and about 2.5 volts, for example about 2 volts.
  • FIG. 7 is a dark field transmission electron microscope (TEM) image of an unprogrammed cell formed according to the present invention, with titanium nitride layer 110 , diode 118 , titanium nitride layer 120 , and conductive layer 122 labeled.
  • the view of FIG. 7 is at ninety degrees to the view of FIG. 6 a.
  • FIG. 7 shows that the resulting diode is polycrystalline, and typically has defects, including grain boundaries, dislocations, and twins, which are clearly visible. It is known that such defects can impede flow of charge carriers and decrease dopant activation, degrading device performance.
  • Conventional semiconductor devices are generally formed in a monocrystalline silicon wafer surface rather than in polycrystalline silicon for this reason, and result in higher quality devices. In this discussion, polycrystalline silicon will be called polysilicon.
  • a memory level of these cell is formed as described in FIGS. 6 a - 6 c , except, as shown in FIG. 8 a , a thin layer 119 of titanium is deposited before titanium nitride layer 120 .
  • a thin layer 119 of titanium is deposited before titanium nitride layer 120 .
  • titanium silicide contacts 121 are depicted as a continuous layer spanning each diode, but they may not actually take this form, and may form one or more discontinuous islands instead.
  • a resulting diode formed as in FIG. 8 b is shown in a dark field TEM image in FIG. 9 .
  • the view of FIG. 9 is at ninety degrees to the view of FIG. 8 b .
  • Titanium silicide contact 121 does not form a continuous layer across the diode 118 .
  • the cell shown in FIG. 9 has far fewer defects and grain boundaries than the cell shown in FIG. 7 .
  • This diode has a more highly ordered degree of crystallinity.
  • the barrier height of a cell having a titanium silicide contact is shown at bias voltages from 0 to 2.5 volts in FIG. 10 .
  • the barrier height curve shown by FIG. 10 is for the titanium-silicide-contact diode as formed, before the cell is subjected to a programming voltage.
  • the diode of FIG. 7 (of the present invention), with its barrier height before and after programming shown in FIG. 3 , is formed with the semiconductor material contacting titanium nitride layer 110 and 120 (or another of the named barrier materials) at its top and bottom ends, while the diode of FIG. 9 (of the '387 application), its barrier height shown in FIG. 10 , contacts titanium nitride layer 110 at its bottom end and titanium silicide contact 121 at its top end.
  • the barrier height of the silicide-contact diode as formed strongly resembles that of the titanium-nitride-contact diode of the present invention after programming (curve A).
  • the maximum barrier height of the silicide-contact diode of FIG. 9 is 0.235, close to 0.218, the maximum barrier height of the programmed titanium-nitride contact diode.
  • the silicide-contact diode of FIG. 9 when the silicide-contact diode of FIG. 9 is exposed to a programming voltage, for example of about 8 volts, the barrier height and current flow with applied read voltage are not appreciably changed.
  • the silicide-contact diode is essentially a programmed diode as formed.
  • the difference between the titanium-nitride-contact diode, which has high defect density, and the silicide-contact diode, which is nearly defect-free, is believed to be due to the presence of titanium silicide during crystallization of the silicon that makes up the diode.
  • the silicon that forms the diodes of both FIG. 7 and FIG. 9 is generally amorphous as deposited, and crystallizes after the top and bottom conductors have been formed.
  • the silicon of FIG. 7 crystallizes, it is in contact with titanium nitride layers 110 and 120 and with surrounding dielectric fill, generally silicon dioxide.
  • the silicon of FIG. 9 crystallizes, it is in contact with titanium nitride layer 110 , surrounding silicon dioxide, and top titanium silicide contact 121 .
  • Titanium nitride and titanium silicide each has a characteristic lattice structure.
  • the lattice spacing of the most likely orientation of titanium nitride at the surface which will contact the silicon of the diode is 2.510 angstroms.
  • a lattice spacing of titanium silicide in contact with silicon is 3.319 angstroms.
  • the lattice spacing of silicon at its predominant orientation is 3.316 angstroms.
  • titanium nitride and silicon have a large lattice mismatch, 22.8 percent, while the lattices of titanium silicide and silicon are much more closely matched, with a lattice mismatch of only 1.7 percent.
  • This mismatch is for a lattice spacing of C49-phase titanium silicide rather than C54-phase titanium silicide.
  • the C49-to-C54 phase transition has been shown to be difficult to achieve in features having line widths less than 250 nm.
  • the diodes are isolated structures formed at even smaller dimension, so it is expected that titanium silicide in the diodes is C49 phase rather than C54 phase.
  • Titanium silicide contacts 121 in FIG. 8 b were formed by reacting titanium layer 119 with silicon layer 116 . This silicide reaction happens at a temperature lower than the temperature at which amorphous silicon begins to crystallize, so titanium silicide contacts 121 are present before significant crystallization of the silicon begins.
  • C49 titanium silicide contact 121 provides a good crystallization template for the silicon of the diode 118 as it crystallizes, leading to low defect density in the diode of FIG. 8 b , as is evident in the TEM image of FIG. 9 .
  • the diode of the present invention in FIG. 6 c and FIG. 7 , no titanium silicide lattice is present, only titanium nitride.
  • the high lattice mismatch between titanium nitride (for the expected orientation) and silicon puts severe strains on the silicon lattice as it forms. For a very thin layer of silicon, high strain can be tolerated.
  • the combined thickness of silicon layers 112 , 114 , and 116 is between about 800 and over 4000 angstroms, too thick to sustain such strain, and defects such as those apparent in the TEM image of FIG. 7 are generated.
  • a diode is formed having a certain defect density, which in its initial, unprogrammed state, causes the diode to have poor conductivity and low rectification ratio, and to permit a small current flow when a read voltage is applied.
  • Application of a programming pulse improves conductivity, permanently improving the rectification ratio of the diode, so that when the same read voltage is applied, a much larger current flows.
  • the diode remains a diode after programming, exhibiting non-ohmic conduction.
  • the programmed current is preferably at least an order of magnitude greater than the unprogrammed current, most preferably at least two or three orders of magnitude greater.
  • the diode can store a memory state, and can behave as a nonvolatile, one-time-programmable memory cell.
  • Diodes according to the present invention can also be formed of silicon-germanium alloys, germanium and other semiconductor alloys comprising germanium and/or silicon.
  • the diode is preferably formed with a certain advantageous defect density.
  • the defect density was achieved by crystallizing silicon in contact with a crystallization template apparently provided by adjacent titanium nitride contacts, and, more specifically, not in contact with a template material having a very small lattice mismatch, such as C49 phase titanium silicide.
  • a memory cell which has a diode with the preferred defect density
  • it should be formed of a semiconductor material which, during crystallization, is not in contact with a template material having a lattice mismatch of less than about 3 or 4 percent with the semiconductor material.
  • the semiconductor material when crystallized, is not in contact with a template material having a lattice mismatch of less than about 12 percent with the semiconductor material.
  • the semiconductor material is silicon, then, it should be crystallized not in contact with materials like titanium silicide, cobalt silicide, or nickel monosilicide (NiSi) which can have very small lattice mismatches with silicon.
  • materials like titanium silicide, cobalt silicide, or nickel monosilicide (NiSi) which can have very small lattice mismatches with silicon.
  • NiSi nickel monosilicide
  • Many materials having an advantageous mismatch with silicon are known; among preferred materials for top and bottom contacts are titanium nitride, tantalum nitride, tantalum, titanium tungsten, tungsten nitride, or tungsten.
  • These materials not only provide the necessary large lattice mismatch, but also are compatible with the device, as they are thermally compatible with silicon and can serve as relatively effective barrier materials. These materials also provide sufficient lattice mismatch for use with germanium, a silicon-germanium alloy, or most semiconductor alloys including silicon and/or germanium.
  • the diameter of a diode in a memory cell like those of FIGS. 7 and 9 is very small, between about 45 nm and about 150 nm.
  • the low-resistivity filaments observed by Malhotra et al. were substantially larger in diameter than the diodes of the present invention. It is expected that, due to the small diameter of the diodes of the present invention, no filament is formed, and that instead the entire volume of the diode experiences a high-resistivity-to-low-resistivity change.
  • diodes rather than resistors, be formed between conductors.
  • a large memory array with many cells on a bit line or a word line, when voltage is applied across a specific cell, neighboring cells may also be exposed to some voltage, possibly resulting in inadvertent programming of those cells. Leakage current across unselected cells is also a problem, increasing power consumption.
  • the non-ohmic conduction characteristics of diodes allow for better electrical isolation of a cell from cells sharing one of its conductors, and thus a more robust memory array with lower power consumption.
  • the conversion of the semiconductor material making up the diode of the present invention is likely a thermal phenomenon.
  • resistance is initially relatively high, then drops very quickly, in a matter of nanoseconds, and then remains low. It is likely that during this brief programming time, some portion of the semiconductor material melts.
  • the molten semiconductor material is highly conductive and presents very little resistance. The temperature of the semiconductor material decreases and the semiconductor material is quickly quenched.
  • different regions of the diode must be doped with dopants of opposite conductivity types, like the n-type region 112 and the p-type region 116 of the diodes of FIG. 6 c . It might be expected that when the silicon of the diode 118 is melted, the dopants in these doped regions will diffuse, and the dopant profile necessary to maintain the diode will be lost.
  • the initial defect density, dopant profile, semiconductor volume, programming voltage, programming time, and other factors combine to form an advantageous and novel memory cell, in which the diode retains good non-ohmic behavior after programming, and remains a high-quality diode.
  • titanium-nitride-contact diodes which have been formed with high defect density, behave very differently before and after programming. A clear structural change after programming is not apparent in TEM images, however. Programmed titanium-nitride-contact diodes remain polycrystalline (not single-crystal) and do not appear nearly defect-free, as silicide-contact diodes do, as in FIG. 9 .
  • an array of cells was formed like the memory level of titanium-nitride contact cells shown in FIG. 6 c .
  • the cells in the memory were programmed in a checkerboard pattern.
  • the top conductors were removed by CMP, and the diodes and intervening dielectric exposed.
  • the programmed titanium-nitride-contact diode has a barrier height profile strongly resembling that of the silicide-contact diode as formed, which has low defect density and a more highly ordered crystalline structure.
  • the diode becomes more resistant to Secco solution, an etchant that prefers defective silicon. It is thus believed that the crystalline structure of the polycrystalline semiconductor material of the diode becomes more highly ordered after programming.
  • An antifuse is an element in a circuit that initially impedes current flow until, when subjected to high voltage, it permanently changes its nature, allowing current flow; this is opposite the operation of a fuse.
  • the device of Johnson et al. included a diode and a dielectric antifuse layer in series.
  • the diode of Johnson et al. was generally crystallized in contact with titanium silicide, and thus was low-resistance as formed, so the device depended on dielectric rupture of the dielectric antifuse layer.
  • the data state of the memory cell is determined by a state of an antifuse.
  • the antifuse was a dielectric antifuse layer, generally a silicon dioxide layer in series with a diode.
  • the polycrystalline semiconductor junction diode itself is the antifuse.
  • a thin dielectric layer such as silicon dioxide or some other appropriate dielectric material disposed between the diode and the top or the bottom conductor. Nonetheless, in such a cell the memory state of the cell is determined by the state of the polycrystalline semiconductor material, which is either programmed or unprogrammed.
  • a memory cell is formed by forming a first conductor; forming a second conductor; depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors; crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline, wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and programming the memory cell by applying a programming voltage between the first and second conductors, wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
  • the memory cell of the present invention does not comprise an additional resistance changing element, such as a dielectric antifuse layer or a chalcogenide material.
  • a monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates.
  • the layers forming one memory level are deposited or grown directly over the layers of an existing level or levels.
  • stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy U.S. Pat. No. 5,915,167, “Three dimensional structure memory.”
  • the substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
  • a monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array.
  • a monolithic three dimensional memory array of the present invention include: a) a first memory level above a substrate, the first memory level comprising: i) a first plurality of substantially parallel conductors; ii) a second plurality of substantially parallel conductors above the first conductors; iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and b) a second memory level mono

Abstract

A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

Description

RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 13/074,509, filed Mar. 29, 2011, now U.S. Pat. No. 8,243,509, which is a divisional of U.S. patent application Ser. No. 11/148,530, filed Jun. 8, 2005, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 10/955,549, filed Sep. 29, 2004 and hereinafter the '549 application, which is a continuation-in-part of U.S. patent application Ser. No. 10/855,784, filed May 26, 2004, now U.S. Pat. No. 6,952,030, which is a continuation of U.S. patent application Ser. No. 10/326,470, filed Dec. 19, 2002 (now abandoned) and hereinafter the '470 application, all assigned to the assignee of the present invention and hereby incorporated by reference in their entirety.
BACKGROUND
The invention relates to a nonvolatile one-time-programmable memory cell.
Prior art nonvolatile memories, such as Johnson et al. U.S. Pat. No. 6,034,882, “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” have been based on a memory cell pairing a semiconductor junction diode with a dielectric antifuse layer, the diode and the dielectric antifuse layer disposed between conductors.
When the memory cell is formed, the dielectric antifuse layer (typically a layer of silicon dioxide) acts as an insulator, and when a read voltage is applied between the conductors, very little current flows between the conductors. When a sufficiently large voltage is applied between the conductors, however, the dielectric antifuse layer suffers dielectric breakdown and ruptures, and a permanent conductive path is formed through the dielectric antifuse layer.
In a programmed cell, when a read voltage is applied between conductors, a significantly higher current flows than in the unprogrammed cell, allowing the unprogrammed and programmed cells to be distinguished. The memory state is stored in the state of the dielectric antifuse layer, which may be intact or ruptured.
Memory cells based on rupture of a dielectric antifuse layer, however, suffer some disadvantages. If the dielectric antifuse layer is too thin, leakage current can be a severe problem. Disturb can also be a problem: every time the memory cell is read, the dielectric antifuse layer is exposed to some stress, and may eventually break down and be inadvertently programmed. This is avoided by making the dielectric antifuse layer thicker, but a thicker dielectric antifuse layer requires higher programming voltage to rupture.
Higher voltages in electronic devices, for example in portable devices, are generally disadvantageous. If the dielectric antifuse layer is an oxide layer formed by oxidation, a thicker antifuse layer calls for either higher temperatures or slower fabrication time, both disadvantageous in forming a commercial device.
There is a need, therefore, for a one-time programmable memory cell which does not rely on rupture of a dielectric antifuse layer.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a nonvolatile memory cell comprising a diode, the memory state stored in the state of the diode.
A first aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first maximum barrier height, and after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.
Another aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a second conductor; and a polycrystalline semiconductor junction diode disposed between the first and second conductors, wherein a data state of the memory cell is determined by a state of an antifuse, and wherein the polycrystalline semiconductor junction diode is the antifuse.
Yet another aspect of the invention provides for a method for forming and programming a nonvolatile memory cell, the method including: forming a first conductor; forming a second conductor; depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors; crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline, wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and programming the memory cell by applying a programming voltage between the first and second conductors, wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
A preferred embodiment of the invention provides for a monolithic three dimensional memory array including: a) a first memory level above a substrate, the first memory level comprising: i) a first plurality of substantially parallel conductors; ii) a second plurality of substantially parallel conductors above the first conductors; iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and b) a second memory level monolithically formed above the first memory level.
Another preferred embodiment of the invention provides for a monolithic three dimensional memory array including: a) a first memory level comprising: i) a plurality of bottom conductors; ii) a plurality of top conductors; and iii) a plurality of first polycrystalline semiconductor junction diodes, each diode disposed between one of the bottom and one of the top conductors; and iv) a first memory cell comprising one of the first diodes, wherein the data state of the first memory cells is determined by the state of an antifuse, and wherein the diode of the first memory cell is the antifuse; and b) a second memory level monolithically formed above the first memory level.
A final aspect of the invention provides for a nonvolatile memory cell including: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first rectification ratio at a read voltage between about 0.5 and about 2.5 volts, and after application of the programming voltage the diode has a second rectification ratio at the read voltage, the second rectification ratio at least 10 times the first rectification ratio.
Each of the aspects and embodiments of the invention described herein can be used alone or in combination with one another.
The preferred aspects and embodiments will now be described with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view of a memory cell formed according to the present invention.
FIG. 2 is a graph showing I-V curves for an unprogrammed cell and a programmed cell formed like the cell of FIG. 1.
FIG. 3 is a graph showing barrier height between 0 and 2.5 bias volts for a programmed and an unprogrammed memory cell formed according to the present invention.
FIG. 4 is a graph showing unprogrammed and programmed current for a cell according to the present invention at an applied read voltage.
FIG. 5 is a perspective view of a memory level according to the present invention.
FIGS. 6 a-6 c are cross-sectional views showing stages in formation of a memory level according to the present invention.
FIG. 7 is a dark field TEM image showing crystal defects in silicon in a memory cell according to the present invention, shown in cross-section.
FIGS. 8 a-8 b are cross-sectional views showing stages in formation of a memory level with a silicide contact described in U.S. patent application Ser. No. 10/955,387.
FIG. 9 is a dark field TEM image showing relatively defect-free silicon in the memory cell described in U.S. patent application Ser. No. 10/955,387, shown in cross-section.
FIG. 10 is a graph showing barrier height between 0 and 2.5 bias volts for a memory cell described in U.S. patent application Ser. No. 10/955,387.
FIG. 11 is a SEM image showing preferential etching of unprogrammed diodes in a memory level of the present invention.
DETAILED DESCRIPTION
A preferred embodiment of a memory cell described in the '549 application is shown in FIG. 1. A diode 30 is disposed between a bottom conductor 20 and a top conductor 40. Diode 30 is in electrical contact with bottom conductor 20 and top conductor 40, with no dielectric layer interposed between them. Titanium nitride layer 8 is a conductive barrier layer to prevent reaction between tungsten layer 6 and the silicon of diode 30. Titanium nitride layer 18 serves as an adhesion layer and as a barrier layer between diode 30 and tungsten layer 22.
In preferred embodiments of the '549 application, the diode was formed by depositing and doping a silicon layer stack and patterning and etching the layer stack to form a pillar. Regions of the layer stack were doped (by in situ doping or by ion implantation) to form a p-i-n diode; in a preferred embodiment bottom region 10 was heavily doped n-type silicon, middle region 12 was intrinsic, undoped silicon, and top region 14 was heavily doped p-type silicon.
This diode is a form of semiconductor junction diode; this term refers to a semiconductor device with the property of conducting current more easily in one direction than the other, having two terminal electrodes, and made of semiconducting material which is p-type at one electrode and n-type at the other. After formation of top conductor 40, the silicon of diode 30 was annealed (either in a separate anneal step or during subsequent thermal processing) to fully crystallize it. In preferred embodiments of the completed device of the '549 application, diode 30 is polycrystalline.
As formed, diode 30 has an I-V curve like the curve labeled “before programming) in the graph of FIG. 2, allowing little current to flow when a typical read voltage, for example 2 volts, is applied between bottom conductor 20 and top conductor 40. It was found that applying a programming voltage of, for example, about 8 volts between bottom conductor 20 and top conductor 40 permanently changes diode 30.
The I-V curve labeled “after programming” in FIG. 2 shows current for the diode after programming. After programming, current increases sharply as the turn-on voltage is reached, and the programmed diode allows significantly more current to flow when a read voltage of 2 volts is applied between bottom conductor 20 and top conductor 40. The difference in current flow at an applied read voltage allows a programmed cell to be distinguished from an unprogrammed cell, and thus for the cell to store a memory state (data “0” or data “1”, for example.) This cell does not include a dielectric antifuse layer.
A material exhibiting ohmic behavior conducts with equal ease in both directions, and current increases linearly with voltage. A diode exhibits non-ohmic behavior: It conducts current more easily in one direction than the other, and has a non-linear relationship between voltage and current, as shown in FIG. 2. One measure of the effectiveness of a diode is its barrier height over a range of applied voltages.
In an ideal diode, the barrier height (roughly speaking, the barrier to current flow) is high at very low voltage, between about 0 and 0.2 volts, drops abruptly as the turn-on voltage is approached, and is very low above the turn-on voltage. FIG. 3 shows the barrier height of the diode of FIG. 1 before and after programming at an applied bias ranging from 0 to 2.5 volts. The maximum barrier height of a programmed diode (curve A in FIG. 3) is 0.218 electron-volts, nearly twice the maximum barrier height of an unprogrammed diode (curve B), which is 0.144 electron-volts.
The memory cell of the present invention is a nonvolatile memory cell comprising: a first conductor; a diode comprising amorphous or polycrystalline semiconductor material; and a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein before application of a programming voltage the diode has a first maximum barrier height, and after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height, in some embodiments 1.7 times the first maximum barrier height.
Read voltages are selected to be well above the turn-on voltage, which for silicon is theoretically at a bias voltage of 1.1 volts. As shown in FIG. 3, at voltages used for read, for example at 2.0 volts, the barrier height of a programmed diode is significantly less than that of an unprogrammed diode. Turning to FIG. 4, which is a probability plot showing current for a distribution of programmed and unprogrammed diodes, the median current for unprogrammed cells (curve C) at 2 volts is 1.2×10−8 amps, while the median current for programmed cells (curve D) at 2 volts is 4.8×10−5 amps, a difference of more than three orders of magnitude.
As described, a diode allows current to flow more easily in one direction than in the opposite direction; the diode is said to be rectifying. More current will flow through a diode when the diode is positively biased at a given voltage, for example 2 volts, than when the diode is negatively biased at the same voltage. The ratio of these currents is the rectification ratio and is another measure of diode quality.
The diodes of the present invention show a large increase in rectification ratio after programming. When silicon diodes formed according to the present invention were measured using a voltage sweep, current through an unprogrammed diode at −2 volts was about 8.1×10−13 amps, as compared to a current under positive bias of 2 volts of about 1.3×10−8 amps, yielding a rectification ratio at 2 volts of about 1.6×104.
In the same population of diodes, current through the programmed diode at −2 volts was about 2.0×10−12 amps, while the current for programmed cells at 2 volts was about 1.8×10−5 amps, for a rectification ratio at two volts of about 9.2×106. In this example, the rectification ratio of a diode of the present invention after programming was about 575 times greater than its rectification ratio before programming.
When the diode is silicon, a programmed diode of the present invention will have a rectification ratio at 2 volts at least 100 times the rectification ratio at 2 volts of the unprogrammed diode. In less preferred embodiments, the rectification ratio at 2 volts will be at least 10 times higher after programming than before programming. For silicon, rectification ratio at 2 volts has been discussed. Two volts was selected because it is an advantageous read voltage.
At positive voltage, an I-V curve for a diode has a characteristic shape: It is initially very low, rises abruptly as the turn-on voltage is reached, then stabilizes above the turn-on voltage. Two volts is an advantageous read voltage in the present invention because it is in the stable part of the curve, above the turn-on voltage. More generally, the diode of the present invention shows a large increase in rectification ratio, at least 10 times, in preferred embodiments 100 times, at a read voltage. A read voltage is a voltage in the stable part of the curve, above the diode's turn-on voltage. Read voltages for silicon may range between about 1.5 volts and about 2.5 volts.
For germanium diodes, an appropriate read voltage will be lower, between about 0.5 volts and about 2.0 volts, preferably about 1.2 volts. Semiconductor diodes formed of alloys comprising silicon and germanium will have intermediate read voltages, depending on the relative compositions of silicon and germanium, and will be between about 1.2 and about 2.0 volts.
Memory cells formed according to the present invention having diodes formed of germanium or semiconductor alloys comprising silicon and germanium will have a first rectification ratio before programming and a second rectification ratio after programming, the second rectification ratio at least 10 times the first rectification ratio, and in preferred embodiments at least 100 times the first rectification ratio.
Many factors can affect the quality of a diode, including dopant concentration, doping profiles, dopant activation, and degree of crystallinity and of crystalline defects. It is believed that in the present invention, programming changes the diode by increasing the degree of order of crystallinity of the semiconductor material of the diode.
FIG. 5 shows a memory level of exemplary memory cells formed according to the present invention, including bottom conductors 200, pillars 300 (each pillar 300 comprising a diode), and top conductors 400. Fabrication of this memory level will be described. More detailed information regarding fabrication of such a memory level is provided in the '470 and '549 applications, previously incorporated.
Additional information is found in Herner et al. U.S. patent application Ser. No. 11/015,824, “Nonvolatile Memory Cell Comprising a Reduced Height Vertical Diode,” filed Dec. 17, 2004; Herner et al. U.S. patent application Ser. No. 11/125,606, “High-Density Nonvolatile Memory Array Fabricated at Low Temperature Comprising Semiconductor Diodes,” filed May 9, 2005; and Herner et al. U.S. patent application Ser. No. 10/954,577, “Junction Diode Comprising Varying Semiconductor Compositions,” filed Sep. 29, 2004 and hereinafter the '577 application, all owned by the assignee of the present invention and hereby incorporated by reference. To avoid obscuring the invention, not all of this detail will be included in this description, but no teaching of these or other incorporated patents and applications is intended to be excluded.
Turning to FIG. 6 a, fabrication of a memory level comprising memory cells formed according to the present invention begins over a suitable substrate 100, for example a monocrystalline semiconductor wafer substrate. Circuitry, such as sense amplifiers and drivers, can be formed in substrate 100 before fabrication of the memory level begins. An insulating layer 102 is formed above substrate 100.
Conductive layers 104 and 106 are deposited. Layer 104 is an adhesion layer, preferably of titanium nitride. Layer 106 is a conductive material, for example tungsten. Other conductive materials may be preferred. Layers 104 and 106 are patterned and etched to form substantially parallel, substantially coplanar rail-shaped bottom conductors 200, shown here in cross-section extending out of the page.
A dielectric material 108 is deposited over and between conductors 200, filling gaps between them. A planarizing step, for example by chemical mechanical polishing (CMP), exposes tops of conductors 200 and creates a substantially planar surface.
Turning to FIG. 6 b, next a barrier layer 110 is deposited. (To save space, substrate 100 is omitted from FIG. 6 b; its presence should be assumed in this and subsequent figures.) This layer is preferably about 200 angstroms thick, and provides a chemical barrier between the conductive layer 106 and the semiconductor material to be deposited next. Barrier layer 110 is preferably titanium nitride, though other appropriate barrier materials, for example tantalum nitride, tantalum, titanium tungsten, tungsten nitride, or tungsten, could be used instead.
The diode to be formed will be a vertically oriented p-i-n diode, having a heavily doped p-type region at one end, an intrinsic middle region (not intentionally doped), and a heavily doped n-type region at the other end. In this example, the bottom region will be heavily doped n-type, the middle region will be intrinsic, and the top region will be heavily doped p-type. The conductivity types could be reversed if desired. Using conventional deposition techniques, intrinsic silicon (deposited with no dopants) has defects which tend to make it behave as if it were lightly doped with n-type dopants. If desired, this region could be lightly doped.
A semiconductor layer stack is deposited on barrier layer 110. The semiconductor material can be silicon, germanium, a silicon-germanium alloy, or any semiconductor alloy including silicon and/or germanium. In some embodiments, different parts of the layer stack comprise different semiconductor materials or alloys, as in the '577 application.
In this example the semiconductor material is silicon, and bottom region 112 is heavily doped with an n-type dopant, for example phosphorus or arsenic, preferably by in situ doping. The silicon that will make up the rest of the diode, regions 114 and 116, is deposited next. The thickness of silicon that will form regions 114 and 116 is preferably deposited undoped. The top heavily doped p-type region 116 could be formed during deposition by in situ doping, but in preferred embodiments will be doped in a later implant step.
Silicon regions 116 (not yet doped), 114 and 112 and barrier layer 110 are patterned and etched to form pillars 300. The photolithography techniques described in Chen U.S. patent application Ser. No. 10/728,436, “Photomask Features with Interior Nonprinting Window Using Alternating Phase Shifting,” filed Dec. 5, 2003; or Chen U.S. patent application Ser. No. 10/815,312, Photomask Features with Chromeless Nonprinting Phase Shifting Window,” filed Apr. 1, 2004; and in Raghuram et al. U.S. patent application Ser. No. 11/061,952, “Method for Patterning Submicron Pillars,” filed Feb. 17, 2005, all three owned by the assignee of the present invention and hereby incorporated by reference, can advantageously be used to perform any photolithography step used in formation of a memory array according to the present invention.
Dielectric material 108 is deposited over and between pillars 300, filling gaps between them. A planarizing step, for example by CMP, exposes tops of pillars 300 and forms a substantially planar surface. After this CMP step, heavily doped p-type region 116 is preferably formed at the tops of pillars 300 by ion implantation of a p-type dopant, for example boron or BF2. Diodes 118, which are p-i-n diodes, have been formed.
The height (silicon thickness) of completed diodes 118 can range from about 800 to about 4000 angstroms. (Some silicon thickness may be lost during the planarizing step; an extra thickness should be deposited to compensate.) Intrinsic region 114 can be from about 600 to about 3500 angstroms thick. The structure at this point is shown in FIG. 6 b.
Turning to FIG. 6 c, adhesion layer 120 and conductive layer 122 are deposited next. Adhesion layer 120 is preferably any of the materials used for barrier layer 110, for example titanium nitride. Conductive layer 122 can be any appropriate conductive material, for example tungsten. Layers 120 and 122 are patterned and etched to form substantially parallel, substantially coplanar top conductors 400. Bottom conductors 200 extended in a first direction; top conductors 400 extend in a second direction different from the first direction, preferably perpendicular to it. Each diode 118 is vertically disposed between one of bottom conductors 200 and one of top conductors 400.
What has been formed, shown in FIG. 6 c, is a first memory level. An interlevel dielectric can be formed above this first memory level, planarized, and a second memory level can be fabricated on this planarized dielectric surface as described. Multiple memory levels of the same type can be monolithically formed above the same substrate, each fabricated on a prior memory level, to form a monolithic three dimensional memory array like those described in the '549 and '470 applications.
Each memory cell will be programmed by applying a programming voltage between about 3 and about 15 volts, preferably between about 6 and about 10 volts, preferably between about 7 and about 9 volts, for example about 8 volts. The programming voltage selected will depend on a variety of factors, including the volume of each diode, initial defect density, dopant profile, and the semiconductor material used to form the diodes. The read voltage will also vary, from about 0.5 to about 3 volts, for example between about 1 and about 2.5 volts, for example about 2 volts.
When the silicon that makes up diode 118 is deposited, it is generally amorphous, and crystallizes during a later crystallization step. FIG. 7 is a dark field transmission electron microscope (TEM) image of an unprogrammed cell formed according to the present invention, with titanium nitride layer 110, diode 118, titanium nitride layer 120, and conductive layer 122 labeled. The view of FIG. 7 is at ninety degrees to the view of FIG. 6 a.
FIG. 7 shows that the resulting diode is polycrystalline, and typically has defects, including grain boundaries, dislocations, and twins, which are clearly visible. It is known that such defects can impede flow of charge carriers and decrease dopant activation, degrading device performance. Conventional semiconductor devices are generally formed in a monocrystalline silicon wafer surface rather than in polycrystalline silicon for this reason, and result in higher quality devices. In this discussion, polycrystalline silicon will be called polysilicon.
An alternative method of forming a memory cell having a vertical p-i-n diode formed of deposited and crystallized silicon is disclosed in Petti, U.S. application Ser. No. 10/955,387, “Fuse Memory Cell Comprising a Diode, the Diode Serving as the Fuse Element,” filed Sep. 29, 2004, hereinafter the '387 application, owned by the assignee of the present invention and hereby incorporated by reference.
In one embodiment, a memory level of these cell is formed as described in FIGS. 6 a-6 c, except, as shown in FIG. 8 a, a thin layer 119 of titanium is deposited before titanium nitride layer 120. During an anneal step, where titanium layer 119 is in contact with pillars 300, it reacts with the silicon of heavily doped regions 116 to form titanium silicide contacts 121 in FIG. 8 b. For simplicity, in FIG. 8 b, titanium silicide contacts 121 are depicted as a continuous layer spanning each diode, but they may not actually take this form, and may form one or more discontinuous islands instead.
A resulting diode formed as in FIG. 8 b is shown in a dark field TEM image in FIG. 9. The view of FIG. 9 is at ninety degrees to the view of FIG. 8 b. Titanium silicide contact 121 does not form a continuous layer across the diode 118. The cell shown in FIG. 9 has far fewer defects and grain boundaries than the cell shown in FIG. 7. This diode has a more highly ordered degree of crystallinity. The barrier height of a cell having a titanium silicide contact is shown at bias voltages from 0 to 2.5 volts in FIG. 10. The barrier height curve shown by FIG. 10 is for the titanium-silicide-contact diode as formed, before the cell is subjected to a programming voltage.
Recall that the diode of FIG. 7 (of the present invention), with its barrier height before and after programming shown in FIG. 3, is formed with the semiconductor material contacting titanium nitride layer 110 and 120 (or another of the named barrier materials) at its top and bottom ends, while the diode of FIG. 9 (of the '387 application), its barrier height shown in FIG. 10, contacts titanium nitride layer 110 at its bottom end and titanium silicide contact 121 at its top end.
In comparing FIG. 3 and FIG. 10, it is evident that the barrier height of the silicide-contact diode as formed strongly resembles that of the titanium-nitride-contact diode of the present invention after programming (curve A). The maximum barrier height of the silicide-contact diode of FIG. 9 is 0.235, close to 0.218, the maximum barrier height of the programmed titanium-nitride contact diode.
Unlike the titanium-nitride-contact diode, when the silicide-contact diode of FIG. 9 is exposed to a programming voltage, for example of about 8 volts, the barrier height and current flow with applied read voltage are not appreciably changed. The silicide-contact diode is essentially a programmed diode as formed.
The difference between the titanium-nitride-contact diode, which has high defect density, and the silicide-contact diode, which is nearly defect-free, is believed to be due to the presence of titanium silicide during crystallization of the silicon that makes up the diode.
As described earlier, the silicon that forms the diodes of both FIG. 7 and FIG. 9 is generally amorphous as deposited, and crystallizes after the top and bottom conductors have been formed. Thus when the silicon of FIG. 7 crystallizes, it is in contact with titanium nitride layers 110 and 120 and with surrounding dielectric fill, generally silicon dioxide. When the silicon of FIG. 9 crystallizes, it is in contact with titanium nitride layer 110, surrounding silicon dioxide, and top titanium silicide contact 121.
Titanium nitride and titanium silicide each has a characteristic lattice structure. The lattice spacing of the most likely orientation of titanium nitride at the surface which will contact the silicon of the diode is 2.510 angstroms. A lattice spacing of titanium silicide in contact with silicon is 3.319 angstroms. The lattice spacing of silicon at its predominant orientation is 3.316 angstroms.
At the interface, titanium nitride and silicon have a large lattice mismatch, 22.8 percent, while the lattices of titanium silicide and silicon are much more closely matched, with a lattice mismatch of only 1.7 percent. (This mismatch is for a lattice spacing of C49-phase titanium silicide rather than C54-phase titanium silicide. The C49-to-C54 phase transition has been shown to be difficult to achieve in features having line widths less than 250 nm.
The diodes are isolated structures formed at even smaller dimension, so it is expected that titanium silicide in the diodes is C49 phase rather than C54 phase. Titanium silicide contacts 121 in FIG. 8 b were formed by reacting titanium layer 119 with silicon layer 116. This silicide reaction happens at a temperature lower than the temperature at which amorphous silicon begins to crystallize, so titanium silicide contacts 121 are present before significant crystallization of the silicon begins.
It is believed that C49 titanium silicide contact 121 provides a good crystallization template for the silicon of the diode 118 as it crystallizes, leading to low defect density in the diode of FIG. 8 b, as is evident in the TEM image of FIG. 9. In contrast, in the diode of the present invention (in FIG. 6 c and FIG. 7), no titanium silicide lattice is present, only titanium nitride.
The high lattice mismatch between titanium nitride (for the expected orientation) and silicon puts severe strains on the silicon lattice as it forms. For a very thin layer of silicon, high strain can be tolerated. The combined thickness of silicon layers 112, 114, and 116, however, is between about 800 and over 4000 angstroms, too thick to sustain such strain, and defects such as those apparent in the TEM image of FIG. 7 are generated.
In the present invention, then, a diode is formed having a certain defect density, which in its initial, unprogrammed state, causes the diode to have poor conductivity and low rectification ratio, and to permit a small current flow when a read voltage is applied. Application of a programming pulse improves conductivity, permanently improving the rectification ratio of the diode, so that when the same read voltage is applied, a much larger current flows. The diode remains a diode after programming, exhibiting non-ohmic conduction.
When a read voltage is applied, the programmed current is preferably at least an order of magnitude greater than the unprogrammed current, most preferably at least two or three orders of magnitude greater. In this way the diode can store a memory state, and can behave as a nonvolatile, one-time-programmable memory cell. Diodes according to the present invention can also be formed of silicon-germanium alloys, germanium and other semiconductor alloys comprising germanium and/or silicon.
To store a memory state and function effectively as a memory cell, then, the diode is preferably formed with a certain advantageous defect density. In the example given, the defect density was achieved by crystallizing silicon in contact with a crystallization template apparently provided by adjacent titanium nitride contacts, and, more specifically, not in contact with a template material having a very small lattice mismatch, such as C49 phase titanium silicide.
More generally, to form a memory cell which has a diode with the preferred defect density, it should be formed of a semiconductor material which, during crystallization, is not in contact with a template material having a lattice mismatch of less than about 3 or 4 percent with the semiconductor material. Preferably the semiconductor material, when crystallized, is not in contact with a template material having a lattice mismatch of less than about 12 percent with the semiconductor material.
If the semiconductor material is silicon, then, it should be crystallized not in contact with materials like titanium silicide, cobalt silicide, or nickel monosilicide (NiSi) which can have very small lattice mismatches with silicon. Many materials having an advantageous mismatch with silicon are known; among preferred materials for top and bottom contacts are titanium nitride, tantalum nitride, tantalum, titanium tungsten, tungsten nitride, or tungsten.
These materials not only provide the necessary large lattice mismatch, but also are compatible with the device, as they are thermally compatible with silicon and can serve as relatively effective barrier materials. These materials also provide sufficient lattice mismatch for use with germanium, a silicon-germanium alloy, or most semiconductor alloys including silicon and/or germanium.
The phenomenon of changing the resistivity of polysilicon by subjecting it to a programming voltage has been described, for example in Malhotra et al., “Fundamentals of Memory Switching in Vertical Polycrystalline Silicon Structures,” IEEE Transactions on Electron Devices, ED-32 (11), 2441 (1985). In one study, large features, for example 1 micron in width, were formed of polysilicon having a relatively high resistivity, which were then exposed to a high-voltage pulse. After the voltage pulse was applied, a low-resistivity filament was formed through the polysilicon.
In the present invention, in preferred embodiments, the diameter of a diode in a memory cell like those of FIGS. 7 and 9 is very small, between about 45 nm and about 150 nm. The low-resistivity filaments observed by Malhotra et al. were substantially larger in diameter than the diodes of the present invention. It is expected that, due to the small diameter of the diodes of the present invention, no filament is formed, and that instead the entire volume of the diode experiences a high-resistivity-to-low-resistivity change.
Changing resistivity in polysilicon has been observed in polysilicon resistors. In a memory like that of the present invention, however, it is highly advantageous that diodes, rather than resistors, be formed between conductors. In a large memory array, with many cells on a bit line or a word line, when voltage is applied across a specific cell, neighboring cells may also be exposed to some voltage, possibly resulting in inadvertent programming of those cells. Leakage current across unselected cells is also a problem, increasing power consumption. The non-ohmic conduction characteristics of diodes allow for better electrical isolation of a cell from cells sharing one of its conductors, and thus a more robust memory array with lower power consumption.
The conversion of the semiconductor material making up the diode of the present invention is likely a thermal phenomenon. When a programming voltage is applied to a typical unprogrammed diode, resistance is initially relatively high, then drops very quickly, in a matter of nanoseconds, and then remains low. It is likely that during this brief programming time, some portion of the semiconductor material melts. The molten semiconductor material is highly conductive and presents very little resistance. The temperature of the semiconductor material decreases and the semiconductor material is quickly quenched.
To operate as a semiconductor junction diode, different regions of the diode must be doped with dopants of opposite conductivity types, like the n-type region 112 and the p-type region 116 of the diodes of FIG. 6 c. It might be expected that when the silicon of the diode 118 is melted, the dopants in these doped regions will diffuse, and the dopant profile necessary to maintain the diode will be lost.
In the present invention, however, the initial defect density, dopant profile, semiconductor volume, programming voltage, programming time, and other factors combine to form an advantageous and novel memory cell, in which the diode retains good non-ohmic behavior after programming, and remains a high-quality diode.
As described, titanium-nitride-contact diodes, which have been formed with high defect density, behave very differently before and after programming. A clear structural change after programming is not apparent in TEM images, however. Programmed titanium-nitride-contact diodes remain polycrystalline (not single-crystal) and do not appear nearly defect-free, as silicide-contact diodes do, as in FIG. 9.
To explore the degree of physical change in the programmable diode of the present invention, an array of cells was formed like the memory level of titanium-nitride contact cells shown in FIG. 6 c. The cells in the memory were programmed in a checkerboard pattern. The top conductors were removed by CMP, and the diodes and intervening dielectric exposed.
It is known that a Secco solution etches silicon with defects faster than silicon without defects. The exposed diodes were exposed to a Secco solution for two seconds. Referring to the scanning electron microscope (SEM) image of FIG. 11, the unprogrammed cells were entirely etched away, while the programmed cells remain. It is apparent, then, that the physical structure of polysilicon of the diodes was changed by programming.
As noted earlier, the programmed titanium-nitride-contact diode has a barrier height profile strongly resembling that of the silicide-contact diode as formed, which has low defect density and a more highly ordered crystalline structure. After programming, the diode becomes more resistant to Secco solution, an etchant that prefers defective silicon. It is thus believed that the crystalline structure of the polycrystalline semiconductor material of the diode becomes more highly ordered after programming. These changes in crystallinity, while apparently too subtle or too localized to be evident in TEM images, make a large difference in diode performance.
An antifuse is an element in a circuit that initially impedes current flow until, when subjected to high voltage, it permanently changes its nature, allowing current flow; this is opposite the operation of a fuse. The device of Johnson et al. included a diode and a dielectric antifuse layer in series. The diode of Johnson et al. was generally crystallized in contact with titanium silicide, and thus was low-resistance as formed, so the device depended on dielectric rupture of the dielectric antifuse layer.
In both the cell of Johnson et al. and in the cell of the present invention, the data state of the memory cell is determined by a state of an antifuse. In Johnson et al., the antifuse was a dielectric antifuse layer, generally a silicon dioxide layer in series with a diode. In the present invention, in contrast, the polycrystalline semiconductor junction diode itself is the antifuse.
To improve uniformity, it may be preferred in some embodiments of the present invention to include a thin dielectric layer such as silicon dioxide or some other appropriate dielectric material disposed between the diode and the top or the bottom conductor. Nonetheless, in such a cell the memory state of the cell is determined by the state of the polycrystalline semiconductor material, which is either programmed or unprogrammed.
It is possible that other elements, such as barrier layers, etc., disposed between the diode of the present invention and the top or bottom conductor may experience some incidental change in resistivity when a programming voltage is applied between the top and bottom conductors. In preferred aspects of the invention, it is nonetheless the change in resistivity of the material of the diode that predominates.
In these preferred aspects, a memory cell is formed by forming a first conductor; forming a second conductor; depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors; crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline, wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and programming the memory cell by applying a programming voltage between the first and second conductors, wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
In preferred embodiments, the memory cell of the present invention does not comprise an additional resistance changing element, such as a dielectric antifuse layer or a chalcogenide material.
A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy U.S. Pat. No. 5,915,167, “Three dimensional structure memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
A monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array.
In preferred embodiments, a monolithic three dimensional memory array of the present invention include: a) a first memory level above a substrate, the first memory level comprising: i) a first plurality of substantially parallel conductors; ii) a second plurality of substantially parallel conductors above the first conductors; iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and b) a second memory level monolithically formed above the first memory level.
Detailed methods of fabrication have been described herein, but any other methods that form the same structures can be used while the results fall within the scope of the invention.
The foregoing detailed description has described only a few of the many forms that this invention can take. For this reason, this detailed description is intended by way of illustration, and not by way of limitation. It is only the following claims, including all equivalents, which are intended to define the scope of this invention.

Claims (20)

The invention claimed is:
1. A memory cell comprising:
a first conductor;
a second conductor;
a semiconductor junction diode between the first and second conductors,
wherein:
the semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode, and
no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
2. The memory cell of claim 1, wherein the semiconductor junction diode comprises silicon, germanium, or a silicon-germanium alloy.
3. The memory cell of claim 1, wherein the memory cell does not comprise a dielectric antifuse layer.
4. The memory cell of claim 1, wherein the memory cell does not comprise a chalcogenide material.
5. The memory cell of claim 1, wherein the semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 4 percent with the semiconductor junction diode.
6. The memory cell of claim 1, further comprising a layer of titanium nitride, tungsten nitride, tantalum nitride, tantalum, tungsten, or titanium tungsten in contact with the semiconductor junction diode.
7. The memory cell of claim 1, wherein the semiconductor junction diode is not in contact with titanium silicide, cobalt silicide, or nickel monosilicide.
8. The memory cell of claim 1, wherein, before programming, the semiconductor junction diode has a first maximum barrier height, and after programming, the semiconductor junction diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.
9. A method comprising:
forming a semiconductor junction diode between first and second conductors;
crystallizing the semiconductor junction diode, wherein during the crystallizing step, the semiconductor junction diode is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor junction diode; and
programming the memory cell by applying a programming voltage between the first and second conductors,
wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.
10. The method of claim 9, wherein the semiconductor junction diode comprises silicon, germanium, or a silicon-germanium alloy.
11. The method of claim 9, wherein the memory cell does not comprise a dielectric antifuse layer.
12. The method of claim 9, wherein the memory cell does not comprise a chalcogenide material.
13. The method of claim 9, wherein, during the crystallization step, the semiconductor junction diode is not in contact with a template material having a lattice mismatch of less than 4 percent with the semiconductor junction diode.
14. The method of claim 9, wherein, during the crystallizing step, the semiconductor junction diode is in contact with titanium nitride, tungsten nitride, tantalum nitride, tantalum, tungsten, or titanium tungsten.
15. The method of claim 9, wherein, during the crystallizing step, the semiconductor junction diode is not in contact with titanium silicide, cobalt silicide, or nickel monosilicide.
16. The method of claim 9, wherein, before the programming step, the semiconductor junction diode has a first maximum barrier height, and after the programming step, the semiconductor junction diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.
17. A monolithic three dimensional memory array comprising:
(a) a first memory level above a substrate, the first memory level comprising:
i) a first plurality of substantially parallel conductors;
ii) a second plurality of substantially parallel conductors above the first plurality of substantially parallel conductors; and
iii) a first plurality of pillars comprising semiconductor junction diodes, each pillar disposed between one of the first plurality of substantially parallel conductors and the second plurality of substantially parallel conductors,
wherein:
each semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode, and
no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between any of the semiconductor junction diodes and the first plurality of substantially parallel conductors or the second plurality of substantially parallel conductors; and
(b) a second memory level monolithically formed above the first memory level.
18. The monolithic three dimensional memory array of claim 17, wherein the semiconductor junction diodes comprise silicon, germanium, or a silicon-germanium alloy.
19. The monolithic three dimensional memory array of claim 17, wherein the semiconductor junction diodes comprise vertically oriented p-i-n diodes.
20. The monolithic three dimensional memory array of claim 17, wherein the second memory level comprises a second plurality of pillars comprising semiconductor junction diodes.
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Families Citing this family (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5792918B2 (en) 2000-08-14 2015-10-14 サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニーSandisk 3D Llc Highly integrated memory device
US7176064B2 (en) * 2003-12-03 2007-02-13 Sandisk 3D Llc Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US20050226067A1 (en) 2002-12-19 2005-10-13 Matrix Semiconductor, Inc. Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
US8637366B2 (en) 2002-12-19 2014-01-28 Sandisk 3D Llc Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US7285464B2 (en) 2002-12-19 2007-10-23 Sandisk 3D Llc Nonvolatile memory cell comprising a reduced height vertical diode
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7767499B2 (en) * 2002-12-19 2010-08-03 Sandisk 3D Llc Method to form upward pointing p-i-n diodes having large and uniform current
WO2004061851A2 (en) 2002-12-19 2004-07-22 Matrix Semiconductor, Inc An improved method for making high-density nonvolatile memory
US8018024B2 (en) * 2003-12-03 2011-09-13 Sandisk 3D Llc P-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
US7682920B2 (en) * 2003-12-03 2010-03-23 Sandisk 3D Llc Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse
US7405465B2 (en) * 2004-09-29 2008-07-29 Sandisk 3D Llc Deposited semiconductor structure to minimize n-type dopant diffusion and method of making
US7307268B2 (en) 2005-01-19 2007-12-11 Sandisk Corporation Structure and method for biasing phase change memory array for reliable writing
US7812404B2 (en) * 2005-05-09 2010-10-12 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
WO2007016419A2 (en) * 2005-07-29 2007-02-08 The General Hospital Corporation Methods and compositions for reducing skin damage
US20070102724A1 (en) * 2005-11-10 2007-05-10 Matrix Semiconductor, Inc. Vertical diode doped with antimony to avoid or limit dopant diffusion
US7816659B2 (en) * 2005-11-23 2010-10-19 Sandisk 3D Llc Devices having reversible resistivity-switching metal oxide or nitride layer with added metal
US7834338B2 (en) * 2005-11-23 2010-11-16 Sandisk 3D Llc Memory cell comprising nickel-cobalt oxide switching element
US7615502B2 (en) * 2005-12-16 2009-11-10 Sandisk 3D Llc Laser anneal of vertically oriented semiconductor structures while maintaining a dopant profile
US7808810B2 (en) * 2006-03-31 2010-10-05 Sandisk 3D Llc Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7875871B2 (en) 2006-03-31 2011-01-25 Sandisk 3D Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
US7575984B2 (en) * 2006-05-31 2009-08-18 Sandisk 3D Llc Conductive hard mask to protect patterned features during trench etch
US7754605B2 (en) * 2006-06-30 2010-07-13 Sandisk 3D Llc Ultrashallow semiconductor contact by outdiffusion from a solid source
US7492630B2 (en) * 2006-07-31 2009-02-17 Sandisk 3D Llc Systems for reverse bias trim operations in non-volatile memory
US20080023790A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array
US7499355B2 (en) * 2006-07-31 2009-03-03 Sandisk 3D Llc High bandwidth one time field-programmable memory
US7522448B2 (en) * 2006-07-31 2009-04-21 Sandisk 3D Llc Controlled pulse operations in non-volatile memory
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US7499304B2 (en) * 2006-07-31 2009-03-03 Sandisk 3D Llc Systems for high bandwidth one time field-programmable memory
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US7719874B2 (en) * 2006-07-31 2010-05-18 Sandisk 3D Llc Systems for controlled pulse operations in non-volatile memory
US7495947B2 (en) * 2006-07-31 2009-02-24 Sandisk 3D Llc Reverse bias trim operations in non-volatile memory
TWI356415B (en) * 2006-07-31 2012-01-11 Sandisk 3D Llc Method of operating non-volatile storage and non-v
US7420851B2 (en) * 2006-10-24 2008-09-02 San Disk 3D Llc Memory device for controlling current during programming of memory cells
US7420850B2 (en) * 2006-10-24 2008-09-02 Sandisk 3D Llc Method for controlling current during programming of memory cells
WO2008051840A1 (en) * 2006-10-24 2008-05-02 Sandisk Corporation Memory device and method for controlling current during programming of memory cells
EP2092562A2 (en) * 2006-11-15 2009-08-26 Sandisk 3D LLC P-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse and methods of forming the same
US7728318B2 (en) * 2006-11-16 2010-06-01 Sandisk Corporation Nonvolatile phase change memory cell having a reduced contact area
US8163593B2 (en) * 2006-11-16 2012-04-24 Sandisk Corporation Method of making a nonvolatile phase change memory cell having a reduced contact area
US7811916B2 (en) * 2006-12-13 2010-10-12 Sandisk 3D Llc Method for isotropic doping of a non-planar surface exposed in a void
US7868388B2 (en) * 2007-01-31 2011-01-11 Sandisk 3D Llc Embedded memory in a CMOS circuit and methods of forming the same
US7888200B2 (en) * 2007-01-31 2011-02-15 Sandisk 3D Llc Embedded memory in a CMOS circuit and methods of forming the same
US7982209B2 (en) 2007-03-27 2011-07-19 Sandisk 3D Llc Memory cell comprising a carbon nanotube fabric element and a steering element
US7667999B2 (en) * 2007-03-27 2010-02-23 Sandisk 3D Llc Method to program a memory cell comprising a carbon nanotube fabric and a steering element
US7586773B2 (en) 2007-03-27 2009-09-08 Sandisk 3D Llc Large array of upward pointing p-i-n diodes having large and uniform current
US7855119B2 (en) * 2007-06-15 2010-12-21 Sandisk 3D Llc Method for forming polycrystalline thin film bipolar transistors
US8004013B2 (en) * 2007-06-15 2011-08-23 Sandisk 3D Llc Polycrystalline thin film bipolar transistors
US7790534B2 (en) * 2007-06-15 2010-09-07 Sandisk 3D Llc Method to form low-defect polycrystalline semiconductor material for use in a transistor
US7684226B2 (en) * 2007-06-25 2010-03-23 Sandisk 3D Llc Method of making high forward current diodes for reverse write 3D cell
US7830697B2 (en) * 2007-06-25 2010-11-09 Sandisk 3D Llc High forward current diodes for reverse write 3D cell
WO2009002477A1 (en) 2007-06-25 2008-12-31 Sandisk 3D Llc High forward current diodes for reverse write 3d cell and method of making thereof
WO2009005614A2 (en) 2007-06-29 2009-01-08 Sandisk 3D Llc 3d r/w cell with diode and resistive semiconductor element and method of making thereof
US20090104756A1 (en) * 2007-06-29 2009-04-23 Tanmay Kumar Method to form a rewriteable memory cell comprising a diode and a resistivity-switching grown oxide
US8349663B2 (en) * 2007-09-28 2013-01-08 Sandisk 3D Llc Vertical diode based memory cells having a lowered programming voltage and methods of forming the same
US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
US7759201B2 (en) * 2007-12-17 2010-07-20 Sandisk 3D Llc Method for fabricating pitch-doubling pillar structures
US7706169B2 (en) * 2007-12-27 2010-04-27 Sandisk 3D Llc Large capacity one-time programmable memory cell using metal oxides
US7764534B2 (en) * 2007-12-28 2010-07-27 Sandisk 3D Llc Two terminal nonvolatile memory using gate controlled diode elements
US7706177B2 (en) 2007-12-28 2010-04-27 Sandisk 3D Llc Method of programming cross-point diode memory array
US20090166610A1 (en) * 2007-12-31 2009-07-02 April Schricker Memory cell with planarized carbon nanotube layer and methods of forming the same
US7859887B2 (en) * 2008-04-11 2010-12-28 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US7713818B2 (en) * 2008-04-11 2010-05-11 Sandisk 3D, Llc Double patterning method
US7812335B2 (en) * 2008-04-11 2010-10-12 Sandisk 3D Llc Sidewall structured switchable resistor cell
US7723180B2 (en) * 2008-04-11 2010-05-25 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US8084366B2 (en) * 2008-04-11 2011-12-27 Sandisk 3D Llc Modified DARC stack for resist patterning
US7830698B2 (en) * 2008-04-11 2010-11-09 Sandisk 3D Llc Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same
US7981592B2 (en) * 2008-04-11 2011-07-19 Sandisk 3D Llc Double patterning method
US8445385B2 (en) * 2008-04-11 2013-05-21 Sandisk 3D Llc Methods for etching carbon nano-tube films for use in non-volatile memories
US8048474B2 (en) * 2008-04-11 2011-11-01 Sandisk 3D Llc Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing
US7786015B2 (en) * 2008-04-28 2010-08-31 Sandisk 3D Llc Method for fabricating self-aligned complementary pillar structures and wiring
US8133793B2 (en) 2008-05-16 2012-03-13 Sandisk 3D Llc Carbon nano-film reversible resistance-switchable elements and methods of forming the same
US7944728B2 (en) * 2008-12-19 2011-05-17 Sandisk 3D Llc Programming a memory cell with a diode in series by applying reverse bias
US7978507B2 (en) * 2008-06-27 2011-07-12 Sandisk 3D, Llc Pulse reset for non-volatile storage
US7781269B2 (en) * 2008-06-30 2010-08-24 Sandisk 3D Llc Triangle two dimensional complementary patterning of pillars
US7732235B2 (en) 2008-06-30 2010-06-08 Sandisk 3D Llc Method for fabricating high density pillar structures by double patterning using positive photoresist
US8569730B2 (en) * 2008-07-08 2013-10-29 Sandisk 3D Llc Carbon-based interface layer for a memory device and methods of forming the same
US8309407B2 (en) * 2008-07-15 2012-11-13 Sandisk 3D Llc Electronic devices including carbon-based films having sidewall liners, and methods of forming such devices
WO2010009364A1 (en) * 2008-07-18 2010-01-21 Sandisk 3D, Llc Carbon-based resistivity-switching materials and methods of forming the same
US8557685B2 (en) * 2008-08-07 2013-10-15 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
JP5454945B2 (en) * 2008-09-05 2014-03-26 株式会社東芝 Storage device
US8076056B2 (en) * 2008-10-06 2011-12-13 Sandisk 3D Llc Method of making sub-resolution pillar structures using undercutting technique
US8080443B2 (en) * 2008-10-27 2011-12-20 Sandisk 3D Llc Method of making pillars using photoresist spacer mask
US8835892B2 (en) * 2008-10-30 2014-09-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having boron nitride-based liners, and methods of forming the same
US20100108976A1 (en) * 2008-10-30 2010-05-06 Sandisk 3D Llc Electronic devices including carbon-based films, and methods of forming such devices
US8421050B2 (en) * 2008-10-30 2013-04-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same
US8193074B2 (en) * 2008-11-21 2012-06-05 Sandisk 3D Llc Integration of damascene type diodes and conductive wires for memory device
US7978496B2 (en) 2008-12-18 2011-07-12 Sandisk 3D Llc Method of programming a nonvolatile memory device containing a carbon storage material
US8120068B2 (en) * 2008-12-24 2012-02-21 Sandisk 3D Llc Three-dimensional memory structures having shared pillar memory cells
US8114765B2 (en) * 2008-12-31 2012-02-14 Sandisk 3D Llc Methods for increased array feature density
US8084347B2 (en) * 2008-12-31 2011-12-27 Sandisk 3D Llc Resist feature and removable spacer pitch doubling patterning method for pillar structures
US7846756B2 (en) * 2008-12-31 2010-12-07 Sandisk 3D Llc Nanoimprint enhanced resist spacer patterning method
US8023310B2 (en) * 2009-01-14 2011-09-20 Sandisk 3D Llc Nonvolatile memory cell including carbon storage element formed on a silicide layer
JP4829320B2 (en) * 2009-03-17 2011-12-07 株式会社東芝 Method for manufacturing nonvolatile semiconductor memory device
WO2010114770A1 (en) * 2009-03-30 2010-10-07 Cerulean Pharma Inc. Polymer-agent conjugates, particles, compositions, and related methods of use
US8183121B2 (en) * 2009-03-31 2012-05-22 Sandisk 3D Llc Carbon-based films, and methods of forming the same, having dielectric filler material and exhibiting reduced thermal resistance
US8270199B2 (en) 2009-04-03 2012-09-18 Sandisk 3D Llc Cross point non-volatile memory cell
US8207064B2 (en) 2009-09-17 2012-06-26 Sandisk 3D Llc 3D polysilicon diode with low contact resistance and method for forming same
US8481396B2 (en) * 2009-10-23 2013-07-09 Sandisk 3D Llc Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same
US8551855B2 (en) * 2009-10-23 2013-10-08 Sandisk 3D Llc Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same
US8551850B2 (en) * 2009-12-07 2013-10-08 Sandisk 3D Llc Methods of forming a reversible resistance-switching metal-insulator-metal structure
US8026178B2 (en) 2010-01-12 2011-09-27 Sandisk 3D Llc Patterning method for high density pillar structures
US7923305B1 (en) 2010-01-12 2011-04-12 Sandisk 3D Llc Patterning method for high density pillar structures
US8389375B2 (en) * 2010-02-11 2013-03-05 Sandisk 3D Llc Memory cell formed using a recess and methods for forming the same
US8237146B2 (en) * 2010-02-24 2012-08-07 Sandisk 3D Llc Memory cell with silicon-containing carbon switching layer and methods for forming the same
US20110210306A1 (en) * 2010-02-26 2011-09-01 Yubao Li Memory cell that includes a carbon-based memory element and methods of forming the same
JP2011222929A (en) * 2010-03-23 2011-11-04 Toshiba Corp Nonvolatile memory and manufacturing method of the same
US8471360B2 (en) 2010-04-14 2013-06-25 Sandisk 3D Llc Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same
US8395140B2 (en) 2010-07-09 2013-03-12 Micron Technology, Inc. Cross-point memory utilizing Ru/Si diode
JP5566217B2 (en) * 2010-07-30 2014-08-06 株式会社東芝 Nonvolatile memory device
JP5269010B2 (en) * 2010-08-17 2013-08-21 株式会社東芝 Nonvolatile semiconductor memory device
US8866121B2 (en) 2011-07-29 2014-10-21 Sandisk 3D Llc Current-limiting layer and a current-reducing layer in a memory device
US8659001B2 (en) 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
JP5564023B2 (en) * 2011-09-08 2014-07-30 株式会社東芝 Method for manufacturing nonvolatile memory device
US8637413B2 (en) 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
US8698119B2 (en) 2012-01-19 2014-04-15 Sandisk 3D Llc Nonvolatile memory device using a tunnel oxide as a current limiter element
US8686386B2 (en) 2012-02-17 2014-04-01 Sandisk 3D Llc Nonvolatile memory device using a varistor as a current limiter element
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
KR101956795B1 (en) * 2013-11-15 2019-03-13 에스케이하이닉스 주식회사 Electronic device and method for fabricating the same
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof
US9397111B1 (en) 2015-10-30 2016-07-19 Sandisk Technologies Llc Select gate transistor with single crystal silicon for three-dimensional memory
WO2017222592A1 (en) * 2016-06-20 2017-12-28 Massachusetts Institute Of Technology Apparatus and methods for electrical switching
US9806256B1 (en) 2016-10-21 2017-10-31 Sandisk Technologies Llc Resistive memory device having sidewall spacer electrode and method of making thereof
CN110520977A (en) * 2017-02-14 2019-11-29 成都皮兆永存科技有限公司 Multilayer One Time Programmable persistent memory unit and preparation method thereof
DE102019113401A1 (en) * 2018-06-01 2019-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM CIRCUIT AND METHOD
US11552246B2 (en) 2020-01-21 2023-01-10 Massachusetts Institute Of Technology Memristors and related systems and methods

Citations (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499557A (en) 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4646266A (en) 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US4665428A (en) 1984-01-13 1987-05-12 The British Petroleum Company P.L.C. Semiconductor device
US5432729A (en) 1993-04-23 1995-07-11 Irvine Sensors Corporation Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack
US5441907A (en) 1994-06-27 1995-08-15 Taiwan Semiconductor Manufacturing Company Process for manufacturing a plug-diode mask ROM
US5559732A (en) 1994-12-27 1996-09-24 Syracuse University Branched photocycle optical memory device
US5700737A (en) 1996-02-26 1997-12-23 Taiwan Semiconductor Manufactured Company Ltd. PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination
US5745407A (en) 1994-05-05 1998-04-28 California Institute Of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
US5751012A (en) 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US5792569A (en) 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
US5877538A (en) 1995-06-02 1999-03-02 Silixonix Incorporated Bidirectional trench gated power MOSFET with submerged body bus extending underneath gate trench
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US5991193A (en) 1997-12-02 1999-11-23 International Business Machines Corporation Voltage biasing for magnetic ram with magnetic tunnel memory cells
US6034882A (en) 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6111784A (en) 1997-09-18 2000-08-29 Canon Kabushiki Kaisha Magnetic thin film memory element utilizing GMR effect, and recording/reproduction method using such memory element
US6141241A (en) 1998-06-23 2000-10-31 Energy Conversion Devices, Inc. Universal memory element with systems employing same and apparatus and method for reading, writing and programming same
US6236587B1 (en) 1997-09-01 2001-05-22 Thin Film Electronics Asa Read-only memory and read-only memory devices
US6420215B1 (en) 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US20030025176A1 (en) 2000-08-14 2003-02-06 Vivek Subramanian Thermal processing for three dimensional circuits
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6534841B1 (en) 2001-12-14 2003-03-18 Hewlett-Packard Company Continuous antifuse material in memory structure
US6567301B2 (en) 2001-08-09 2003-05-20 Hewlett-Packard Development Company, L.P. One-time programmable unit memory cell based on vertically oriented fuse and diode and one-time programmable memory using the same
US6584029B2 (en) 2001-08-09 2003-06-24 Hewlett-Packard Development Company, L.P. One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells
US6611453B2 (en) 2001-01-24 2003-08-26 Infineon Technologies Ag Self-aligned cross-point MRAM device with aluminum metallization layers
US20030164491A1 (en) 2002-02-15 2003-09-04 Lee Thomas H. Diverse band gap energy level semiconductor device
US6627530B2 (en) 2000-12-22 2003-09-30 Matrix Semiconductor, Inc. Patterning three dimensional structures
US6635556B1 (en) 2001-05-17 2003-10-21 Matrix Semiconductor, Inc. Method of preventing autodoping
US6664639B2 (en) 2000-12-22 2003-12-16 Matrix Semiconductor, Inc. Contact and via structure and method of fabrication
US6677220B2 (en) 2002-01-16 2004-01-13 Hewlett-Packard Development Company, L.P. Antifuse structure and method of making
US6693823B2 (en) 2002-01-02 2004-02-17 Intel Corporation Minimization of metal migration in magnetic random access memory
WO2004061851A2 (en) 2002-12-19 2004-07-22 Matrix Semiconductor, Inc An improved method for making high-density nonvolatile memory
US6784517B2 (en) 2000-04-28 2004-08-31 Matrix Semiconductor, Inc. Three-dimensional memory array incorporating serial chain diode stack
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US20050052915A1 (en) 2002-12-19 2005-03-10 Matrix Semiconductor, Inc. Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US20050098800A1 (en) 2002-12-19 2005-05-12 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising a reduced height vertical diode
US6946719B2 (en) 2003-12-03 2005-09-20 Matrix Semiconductor, Inc Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
US6952043B2 (en) 2002-06-27 2005-10-04 Matrix Semiconductor, Inc. Electrically isolated pillars in active devices
US6951780B1 (en) 2003-12-18 2005-10-04 Matrix Semiconductor, Inc. Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays
US20050221200A1 (en) 2004-04-01 2005-10-06 Matrix Semiconductor, Inc. Photomask features with chromeless nonprinting phase shifting window
US20050226067A1 (en) 2002-12-19 2005-10-13 Matrix Semiconductor, Inc. Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
US20060067117A1 (en) 2004-09-29 2006-03-30 Matrix Semiconductor, Inc. Fuse memory cell comprising a diode, the diode serving as the fuse element
US7115967B2 (en) 2002-06-27 2006-10-03 Sandisk 3D Llc Three-dimensional memory
US20060249753A1 (en) 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes
US7172840B2 (en) 2003-12-05 2007-02-06 Sandisk Corporation Photomask features with interior nonprinting window using alternating phase shifting
US7176064B2 (en) 2003-12-03 2007-02-13 Sandisk 3D Llc Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US7224013B2 (en) 2004-09-29 2007-05-29 Sandisk 3D Llc Junction diode comprising varying semiconductor compositions
US7238607B2 (en) 2002-12-19 2007-07-03 Sandisk 3D Llc Method to minimize formation of recess at surface planarized by chemical mechanical planarization
US7265049B2 (en) 2002-12-19 2007-09-04 Sandisk 3D Llc Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices
US7307013B2 (en) 2004-06-30 2007-12-11 Sandisk 3D Llc Nonselective unpatterned etchback to expose buried patterned features
US7423304B2 (en) 2003-12-05 2008-09-09 Sandisck 3D Llc Optimization of critical dimensions and pitch of patterned features in and above a substrate
US7474000B2 (en) 2003-12-05 2009-01-06 Sandisk 3D Llc High density contact to relaxed geometry layers
US7511352B2 (en) 2003-05-19 2009-03-31 Sandisk 3D Llc Rail Schottky device and method of making
US7517796B2 (en) 2005-02-17 2009-04-14 Sandisk 3D Llc Method for patterning submicron pillars
US7767499B2 (en) 2002-12-19 2010-08-03 Sandisk 3D Llc Method to form upward pointing p-i-n diodes having large and uniform current

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US432729A (en) * 1890-07-22 Screw-driver
US4545111A (en) 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
US5774378A (en) * 1993-04-21 1998-06-30 The Foxboro Company Self-validating sensors
FR2714764B1 (en) * 1993-12-30 1996-03-29 Pixel Int Sa Method for positioning and fitting spacer balls for flat screens such as microtip fluorescent screens, and equipment associated with this method.
US5844297A (en) 1995-09-26 1998-12-01 Symbios, Inc. Antifuse device for use on a field programmable interconnect chip
US5926096A (en) * 1996-03-11 1999-07-20 The Foxboro Company Method and apparatus for correcting for performance degrading factors in a coriolis-type mass flowmeter
US5877954A (en) * 1996-05-03 1999-03-02 Aspen Technology, Inc. Hybrid linear-neural network process control
DE19621132A1 (en) * 1996-05-24 1997-11-27 Bailey Fischer & Porter Gmbh Method and device for magnetic-inductive flow measurement
US5804741A (en) * 1996-11-08 1998-09-08 Schlumberger Industries, Inc. Digital phase locked loop signal processing for coriolis mass flow meter
US6073495A (en) * 1997-03-21 2000-06-13 Endress + Hauser Flowtec Ag Measuring and operating circuit of a coriolis-type mass flow meter
US6185470B1 (en) * 1997-11-07 2001-02-06 Mcdonnell Douglas Corporation Neural network predictive control method and system
US6102846A (en) * 1998-02-26 2000-08-15 Eastman Kodak Company System and method of managing a psychological state of an individual using images
US6613823B1 (en) * 1998-10-21 2003-09-02 Phillips Petroleum Company Phosphite additives in polyolefins
US5969264A (en) * 1998-11-06 1999-10-19 Technology Commercialization Corp. Method and apparatus for total and individual flow measurement of a single-or multi-phase medium
US6303972B1 (en) 1998-11-25 2001-10-16 Micron Technology, Inc. Device including a conductive layer protected against oxidation
US6301973B1 (en) * 1999-04-30 2001-10-16 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Non-intrusive pressure/multipurpose sensor and method
US6879014B2 (en) 2000-03-20 2005-04-12 Aegis Semiconductor, Inc. Semitransparent optical detector including a polycrystalline layer and method of making
US6549447B1 (en) 2001-10-31 2003-04-15 Peter Fricke Memory cell structure
GB2382220A (en) 2001-11-20 2003-05-21 Zarlink Semiconductor Ltd Polysilicon diode antifuse
US6911233B2 (en) 2002-08-08 2005-06-28 Toppoly Optoelectronics Corp. Method for depositing thin film using plasma chemical vapor deposition
US7397101B1 (en) 2004-07-08 2008-07-08 Luxtera, Inc. Germanium silicon heterostructure photodetectors
JP5439147B2 (en) 2009-12-04 2014-03-12 株式会社東芝 Resistance change memory

Patent Citations (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499557A (en) 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4665428A (en) 1984-01-13 1987-05-12 The British Petroleum Company P.L.C. Semiconductor device
US4646266A (en) 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US5432729A (en) 1993-04-23 1995-07-11 Irvine Sensors Corporation Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack
US5745407A (en) 1994-05-05 1998-04-28 California Institute Of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
US5441907A (en) 1994-06-27 1995-08-15 Taiwan Semiconductor Manufacturing Company Process for manufacturing a plug-diode mask ROM
US5559732A (en) 1994-12-27 1996-09-24 Syracuse University Branched photocycle optical memory device
US5877538A (en) 1995-06-02 1999-03-02 Silixonix Incorporated Bidirectional trench gated power MOSFET with submerged body bus extending underneath gate trench
US5751012A (en) 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US5700737A (en) 1996-02-26 1997-12-23 Taiwan Semiconductor Manufactured Company Ltd. PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination
US5792569A (en) 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6236587B1 (en) 1997-09-01 2001-05-22 Thin Film Electronics Asa Read-only memory and read-only memory devices
US6111784A (en) 1997-09-18 2000-08-29 Canon Kabushiki Kaisha Magnetic thin film memory element utilizing GMR effect, and recording/reproduction method using such memory element
US5991193A (en) 1997-12-02 1999-11-23 International Business Machines Corporation Voltage biasing for magnetic ram with magnetic tunnel memory cells
US6141241A (en) 1998-06-23 2000-10-31 Energy Conversion Devices, Inc. Universal memory element with systems employing same and apparatus and method for reading, writing and programming same
US6034882A (en) 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6185122B1 (en) 1998-11-16 2001-02-06 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6420215B1 (en) 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6784517B2 (en) 2000-04-28 2004-08-31 Matrix Semiconductor, Inc. Three-dimensional memory array incorporating serial chain diode stack
US20030025176A1 (en) 2000-08-14 2003-02-06 Vivek Subramanian Thermal processing for three dimensional circuits
US6664639B2 (en) 2000-12-22 2003-12-16 Matrix Semiconductor, Inc. Contact and via structure and method of fabrication
US6627530B2 (en) 2000-12-22 2003-09-30 Matrix Semiconductor, Inc. Patterning three dimensional structures
US6611453B2 (en) 2001-01-24 2003-08-26 Infineon Technologies Ag Self-aligned cross-point MRAM device with aluminum metallization layers
US6635556B1 (en) 2001-05-17 2003-10-21 Matrix Semiconductor, Inc. Method of preventing autodoping
US6567301B2 (en) 2001-08-09 2003-05-20 Hewlett-Packard Development Company, L.P. One-time programmable unit memory cell based on vertically oriented fuse and diode and one-time programmable memory using the same
US6584029B2 (en) 2001-08-09 2003-06-24 Hewlett-Packard Development Company, L.P. One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells
US20050026334A1 (en) 2001-08-13 2005-02-03 Matrix Semiconductor, Inc. Vertically stacked, field programmable, nonvolatile memory and method of fabrication
US6689644B2 (en) 2001-08-13 2004-02-10 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6534841B1 (en) 2001-12-14 2003-03-18 Hewlett-Packard Company Continuous antifuse material in memory structure
US6693823B2 (en) 2002-01-02 2004-02-17 Intel Corporation Minimization of metal migration in magnetic random access memory
US6677220B2 (en) 2002-01-16 2004-01-13 Hewlett-Packard Development Company, L.P. Antifuse structure and method of making
US20030164491A1 (en) 2002-02-15 2003-09-04 Lee Thomas H. Diverse band gap energy level semiconductor device
US7038248B2 (en) 2002-02-15 2006-05-02 Sandisk Corporation Diverse band gap energy level semiconductor device
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US7115967B2 (en) 2002-06-27 2006-10-03 Sandisk 3D Llc Three-dimensional memory
US6952043B2 (en) 2002-06-27 2005-10-04 Matrix Semiconductor, Inc. Electrically isolated pillars in active devices
US20050098800A1 (en) 2002-12-19 2005-05-12 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising a reduced height vertical diode
US7557405B2 (en) 2002-12-19 2009-07-07 Sandisk 3D Llc High-density nonvolatile memory
US8243509B2 (en) * 2002-12-19 2012-08-14 Sandisk 3D Llc Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
US20050052915A1 (en) 2002-12-19 2005-03-10 Matrix Semiconductor, Inc. Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US6952030B2 (en) 2002-12-19 2005-10-04 Matrix Semiconductor, Inc. High-density three-dimensional memory cell
US20110318911A1 (en) 2002-12-19 2011-12-29 Herner S Brad Nonvolatile memory cell comprising a reduced height vertical diode
US20110287615A1 (en) 2002-12-19 2011-11-24 Herner S Brad High-density nonvolatile memory and methods of making the same
US20050226067A1 (en) 2002-12-19 2005-10-13 Matrix Semiconductor, Inc. Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
US6984561B2 (en) 2002-12-19 2006-01-10 Matrix Semiconductor, Inc. Method for making high density nonvolatile memory
US20110176352A1 (en) 2002-12-19 2011-07-21 Herner S Brad Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
US7026212B2 (en) 2002-12-19 2006-04-11 Matrix Semiconductors, Inc. Method for making high density nonvolatile memory
US20050012119A1 (en) 2002-12-19 2005-01-20 Matrix Semiconductor Method for making high density nonvolatile memory
WO2004061851A2 (en) 2002-12-19 2004-07-22 Matrix Semiconductor, Inc An improved method for making high-density nonvolatile memory
US7767499B2 (en) 2002-12-19 2010-08-03 Sandisk 3D Llc Method to form upward pointing p-i-n diodes having large and uniform current
US20100181657A1 (en) 2002-12-19 2010-07-22 Sandisk 3D Llc Nonvolatile memory cell comprising a reduced height vertical diode
US20090261343A1 (en) 2002-12-19 2009-10-22 Sandisk 3D Llc High-density nonvolatile memory and methods of making the same
US7560339B2 (en) 2002-12-19 2009-07-14 Sandisk 3D Llc Nonvolatile memory cell comprising a reduced height vertical diode
US7238607B2 (en) 2002-12-19 2007-07-03 Sandisk 3D Llc Method to minimize formation of recess at surface planarized by chemical mechanical planarization
US7265049B2 (en) 2002-12-19 2007-09-04 Sandisk 3D Llc Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices
US7285464B2 (en) 2002-12-19 2007-10-23 Sandisk 3D Llc Nonvolatile memory cell comprising a reduced height vertical diode
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7511352B2 (en) 2003-05-19 2009-03-31 Sandisk 3D Llc Rail Schottky device and method of making
US6946719B2 (en) 2003-12-03 2005-09-20 Matrix Semiconductor, Inc Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
US7176064B2 (en) 2003-12-03 2007-02-13 Sandisk 3D Llc Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US7423304B2 (en) 2003-12-05 2008-09-09 Sandisck 3D Llc Optimization of critical dimensions and pitch of patterned features in and above a substrate
US7474000B2 (en) 2003-12-05 2009-01-06 Sandisk 3D Llc High density contact to relaxed geometry layers
US7172840B2 (en) 2003-12-05 2007-02-06 Sandisk Corporation Photomask features with interior nonprinting window using alternating phase shifting
US6951780B1 (en) 2003-12-18 2005-10-04 Matrix Semiconductor, Inc. Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays
US20050221200A1 (en) 2004-04-01 2005-10-06 Matrix Semiconductor, Inc. Photomask features with chromeless nonprinting phase shifting window
US7307013B2 (en) 2004-06-30 2007-12-11 Sandisk 3D Llc Nonselective unpatterned etchback to expose buried patterned features
US7224013B2 (en) 2004-09-29 2007-05-29 Sandisk 3D Llc Junction diode comprising varying semiconductor compositions
US20060067117A1 (en) 2004-09-29 2006-03-30 Matrix Semiconductor, Inc. Fuse memory cell comprising a diode, the diode serving as the fuse element
US7517796B2 (en) 2005-02-17 2009-04-14 Sandisk 3D Llc Method for patterning submicron pillars
US20060249753A1 (en) 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes

Non-Patent Citations (101)

* Cited by examiner, † Cited by third party
Title
Akerman, "Toward a Universal Memory", Apr. 22, 2005, vol. 308, Science, 508-510.
Apr. 12, 2007 Reply to Dec. 14, 2006 Office Action of U.S. Appl. No. 11/015,824.
Apr. 17, 2007 Appeal Brief of U.S. Appl. No. 10/955,549.
Apr. 23, 2008 Pre-Appeal Brief Request for Review of U.S. Appl. No. 11/148,530.
Apr. 7, 2006 Reply to Restriction Requirement of U.S. Appl. No. 10/955,549 mailed Mar. 17, 2006.
Asuha, T. et al. "Ultrathin silicon dioxide layers with a low leakage current density formed by chemical oxidation of Si", Applied Physics Letters, vol. 81, No. 18 (Oct. 28, 2002), 3410-3412.
Aug. 12, 2008 Reply to Jun. 12, 2008 Ex Parte Quayle Office Action of U.S. Appl. No. 11/401,073.
Aug. 20, 2007 Reply to Apr. 19, 2007 Office Action of U.S. Appl. No. 11/148,530.
Aug. 31, 2010 Reply Jun. 4, 2010 Final Office Action and Interview Summary with Examiner of related U.S. Appl. No. 11/148,530.
Aug. 4, 2006, Reply to Jun. 27, 2006 Office Action of U.S. Appl. No. 10/955,549.
Babcock, J.A., et al., "Polysilicon Resistor Trimming for Packaged Integrated Circuits", IEDM 93, (1993),247-250.
Dec. 1, 2008 Reply Brief of U.S. Appl. No. 10/955,549.
Dec. 19, 2012 Reply to Sep. 19, 2012 Office Action of related U.S. Appl. No. 10/955,549.
Dec. 5, 2011 Response to Nov. 7, 2011 Restriction Requirement of related U.S. Appl. No. 13/195,518.
Decision on Appeal of related U.S. Appl. No. 10/955,549 mailed Apr. 27, 2012.
Ellis, K. A. et al. "Phosphorus Diffusion in Silicon Oxide and Oxynitride Gate Dielectrics", Electrochem, Sol. St. Lett. 2, (1999), 516-518.
Ex Parte Quayle Office Action of U.S. Appl. No. 11/401,073 mailed Jun. 12, 2008.
Examiner's Answer of U.S. Appl. No. 10/955,549 mailed Sep. 30, 2008.
Examiner's Interview Summary of related U.S. Appl. No. 11/148,530 mailed Aug. 2, 2010.
Feb. 7, 2011 Reply and Terminal Disclaimer to Nov. 5, 2010 Office Action of related U.S. Appl. No. 12/477,216.
Feb. 9, 2010 Reply to Nov. 9, 2009 Office Action of related U.S. Appl. No. 11/148,530.
Feldbaumer, D.W. et al. "Theory and Application of Polysilicon Resistor Trimming", Solid-State Electronics, Vol. 38 11, (1995), 1861-1869.
Final Office Action of related U.S. Appl. No. 11/148,530 mailed Jun. 4, 2010.
Final Office Action of U.S. Appl. No. 10/955,549 mailed Oct. 19, 2006.
Final Office Action of U.S. Appl. No. 10/955,549 mailed Sep. 24, 2007.
Final Office Action of U.S. Appl. No. 11/148,530 mailed Apr. 30, 2009.
Final Office Action of U.S. Appl. No. 11/148,530 mailed Nov. 23, 2007.
Hamada, T. et al., "Thin Inter-Polyoxide Films for Flash Memories Grown at Low Temperature (400°) by Oxygen Radicals", IEEE Elect. Dev. Lett. vol. 22, No. 9, (Sep. 2001), 423-425.
Herner et al., U.S. Appl. No. 10/326,470, filed Dec. 19, 2002.
International Preliminary Report on Patentability of International Application No. PCT/US2006/022023 issued Dec. 11, 2007.
International Search Report of International Application No. PCT/US2006/022023 mailed Sep. 21, 2006.
Interview Summary of related U.S. Appl. No. 11/148,530 mailed Mar. 22, 2011.
Interview Summary of U.S. Appl. No. 10/955,549 filed Oct. 16, 2007.
Jan. 29, 2009 Reply to Sep. 29, 2008 Office Action of U.S. Appl. No. 11/148,530.
Jan. 31, 2007 Reply to Nov. 3, 2006 Office Action of U.S. Appl. No. 11/237,169.
Jul. 3, 2008 Amended Appeal Brief of U.S. Appl. No. 10/955,549.
Jul. 30, 2009 Reply to Apr. 30, 2009 Final Office Action of U.S. Appl. No. 11/148,530.
Jun. 13, 2008 Reply to Feb. 13, 2008 Office Action of U.S. Appl. No. 11/866,403.
Jun. 22, 2012 RCE and Response to Sep. 24, 2007 Final Office Action of related U.S. Appl. No. 10/955,549.
Jun. 4, 2008 Notification of Non-Compliant Appeal Brief of U.S. Appl. No. 10/955,549.
Jun. 6, 2008 Pre-Brief Appeal Conference decision of U.S. Appl. No. 11/148,530.
Mahan, J. E. , "Threshold and Memory Switching in Polycrystalline Silicon", Applied Physics Letter, 41, 5. (Sep. 1982) 479-481.
Malhotra et al., "Fundamentals of Memory Switching in Vertical Polycrystalline Silicon Structures", IEEE Transactions on Electron Devices, ED-32 (11), 2441, (1985) (fr 086-A-4, 086-A-1 SPEC).
Malhotra, Vinod.,et al., "An Electrothermal Model of Memory Switching in Vertical Polycrystalline Silicon Structures", IEEE Transactions on Electron Devices, vol. 35, 9, (Sep. 1988), 1514-1523.
Mar. 1, 2007 Reply to Restriction Requirement of related U.S. Appl. No. 11/148,530 mailed Feb. 1, 2007.
Mar. 26, 2008 Reply to Oct. 26, 2007 Office Action of U.S. Appl. No. 11/401,073.
Mar. 8, 2011 Reply to Dec. 8, 2010 Office Action of related U.S. Appl. No. 12/481,684.
May 1, 2013 Reply to Feb. 1, 2013 Final Office Action of related U.S. Appl. No. 10/955,549.
May 14, 2012 Terminal Disclaimer and Response to Feb. 15, 2012 Office Action of related U.S. Appl. No. 13/195,518.
May 22, 2006 Reply to Restriction Requirement of U.S. Appl. No. 10/955,549 mailed Apr. 27, 2006.
May 27, 2008 Appeal Brief of U.S. Appl. No. 10/955,549.
Notice of Abandonment of related U.S. Appl. No. 11/148,530 mailed Jun. 23, 2011.
Notice of Allowance of related U.S. Appl. No. 12/477,216 mailed Mar. 16, 2011.
Notice of Allowance of related U.S. Appl. No. 12/481,684 mailed May 11, 2011.
Notice of Allowance of related U.S. Appl. No. 13/074,509 mailed Apr. 12, 2012.
Notice of Allowance of related U.S. Appl. No. 13/074,509 mailed Nov. 25, 2011.
Notice of Allowance of related U.S. Appl. No. 13/195,518 mailed Jul. 10, 2012.
Notice of Allowance of related U.S. Appl. No. 13/195,518 mailed Oct. 23, 2012.
Notice of Allowance of related U.S. Appl. No. 13/228,109 mailed Apr. 3, 2012.
Notice of Allowance of related U.S. Appl. No. 13/228,109 mailed Feb. 15, 2012.
Notice of Allowance of U.S. Appl. No. 11/015,824 mailed Jun. 14, 2007.
Notice of Allowance of U.S. Appl. No. 11/215,951 mailed Apr. 25, 2007.
Notice of Allowance of U.S. Appl. No. 11/237,169 mailed Mar. 26, 2007.
Notice of Allowance of U.S. Appl. No. 11/401,073 mailed Mar. 3, 2009.
Notice of Allowance of U.S. Appl. No. 11/401,073 mailed Sep. 23, 2008.
Notice of Allowance of U.S. Appl. No. 11/866,403 mailed Apr. 22, 2009.
Notice of Allowance of U.S. Appl. No. 11/866,403 mailed Aug. 14, 2008.
Notice of Allowance of U.S. Appl. No. 11/866,403 mailed Jan. 21, 2009.
Nov. 2, 2010 Reply to Restriction Requirement of related U.S. Appl. No. 12/481,684 mailed Oct. 18, 2010.
Nutzel, J.F., et al., "Comparison of P and Sb as n-dopants for Si molecular beam epitaxy", J. Appl. Phys. 78 (2), (Jul. 15, 1995), 937-940.
Oct. 11, 2006 Reply to Restriction Requirement of U.S. Appl. No. 11/015,824 mailed Sep. 14, 2006.
Oct. 12, 2007 Reply to Restriction Requirement of related U.S. Appl. No. 11/401,073 mailed Sep. 12, 2007.
Oct. 9, 2009 Office Action of related Chinese Application No. 200680027149.2.
Office Action and Search Report of Taiwan Application No. 095120206 issued Jun. 30, 2008.
Office Action of Europe Application No. 06 760 714.3 mailed Apr. 30, 2008.
Office Action of related U.S. Appl. No. 10/955,549 mailed Sep. 19, 2012.
Office Action of related U.S. Appl. No. 11/148,530 mailed Dec. 14, 2010.
Office Action of related U.S. Appl. No. 11/148,530 mailed Nov. 9, 2009.
Office Action of related U.S. Appl. No. 12/477,216 mailed Nov. 5, 2010.
Office Action of related U.S. Appl. No. 13/195,518 mailed Feb. 15, 2012.
Office Action of related U.S. Patent Appl. No. 12/481,684 mailed Dec. 8, 2010.
Office Action of U.S. Appl. No. 10/955,549 mailed Jun. 27, 2006.
Office Action of U.S. Appl. No. 11/015,824 mailed Dec. 14, 2006.
Office Action of U.S. Appl. No. 11/148,530 mailed Apr. 19, 2007.
Office Action of U.S. Appl. No. 11/148,530 mailed Sep. 29, 2009.
Office Action of U.S. Appl. No. 11/237,169 mailed Nov. 3, 2006.
Office Action of U.S. Appl. No. 11/401,073 mailed Oct. 26, 2007.
Office Action of U.S. Appl. No. 11/866,403 mailed Feb. 13, 2008.
Park, B., et al., "Study of contact resistance in in-situ phosphorus layer doped Si deposition process", Electrochemical Society Proceedings 99-31, (1999), 34-45.
Raider, S. I. et al., "Abstract: Stoichiometry of SiO2/Si interfacial regions: I. Ultrathin oxide films", J. Vac. Sci. Tech. vol. 13, No. 1, (Jan./Feb. 1976), 58.
Restriction Requirement of related U.S. Appl. No. 11/148,530 mailed Feb. 2, 2007.
Restriction Requirement of related U.S. Appl. No. 11/401,073 mailed Sep. 12, 2007.
Restriction Requirement of related U.S. Appl. No. 13/195,518 mailed Nov. 7, 2011.
Restriction Requirement of U.S. Appl. No. 10/955,549 mailed Apr. 27, 2006.
Restriction Requirement of U.S. Appl. No. 10/955,549 mailed Mar. 17, 2006.
Restriction Requirement of U.S. Appl. No. 11/015,824 mailed Sep. 14, 2006.
Restriction Requirement of U.S. Appl. No. 12/477,216 mailed Sep. 8, 2010.
Restriction Requirement of U.S. Appl. No. 12/481,684 mailed Oct. 18, 2010.
Sep. 24, 2010 Reply to Restriction Requirement of related U.S. Appl. No. 12/477,216 mailed Sep. 8, 2010.
Singh, D.V., et al., "Abrupt phosphorus profiles in Si: Effects of temperature and substitutional carbon on phosphorus autodoping", Journal of the Electrochemical Society, 150, (2003) G553-G556.
Written Opinion of International Application No. PCT/US2006/022023 mailed Sep. 21, 2006.

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