US8368170B2 - Reducing device performance drift caused by large spacings between active regions - Google Patents

Reducing device performance drift caused by large spacings between active regions Download PDF

Info

Publication number
US8368170B2
US8368170B2 US13/367,103 US201213367103A US8368170B2 US 8368170 B2 US8368170 B2 US 8368170B2 US 201213367103 A US201213367103 A US 201213367103A US 8368170 B2 US8368170 B2 US 8368170B2
Authority
US
United States
Prior art keywords
region
sti
active region
surface portion
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/367,103
Other versions
US20120132987A1 (en
Inventor
Harry-Hak-Lay Chuang
Kong-Beng Thei
Mong-Song Liang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US13/367,103 priority Critical patent/US8368170B2/en
Publication of US20120132987A1 publication Critical patent/US20120132987A1/en
Application granted granted Critical
Publication of US8368170B2 publication Critical patent/US8368170B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation

Definitions

  • This invention relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to reducing the performance drift caused by the difference in stresses applied on the MOS devices.
  • MOS metal-oxide-semiconductor
  • MOS metal-oxide-semiconductor
  • the stresses in the channel regions may improve the carrier mobility.
  • NMOS n-type MOS
  • PMOS p-type MOS
  • the magnitudes of the drive current improvement is related to the magnitudes of the stresses.
  • the MOS devices may be applied with stresses having different magnitudes. Accordingly, the drive current improvements for different MOS devices may be different, resulting in non-uniform drive currents, hence drive current drift.
  • MOS devices are predictable, so that at circuit design time, simulations that accurately reflect the circuit behavior may be performed. Accordingly, it is preferred that in a semiconductor chip, MOS devices of a same type and in a same type of circuits have a uniform performance.
  • the drive current drift has to be compensated for. What makes the compensation of the drive current drift complicated is that the stresses of MOS device are affected by various factors and those factors behave differently for different layouts. Accordingly, new methods for reducing the drive current drift of MOS devices are needed.
  • a method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device.
  • the first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region.
  • the second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region.
  • the method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
  • a method of forming an integrated circuit structure includes providing a semiconductor chip including a semiconductor substrate; forming a hard mask over the semiconductor substrate; forming an opening in the mask to expose a portion of the semiconductor substrate; forming a field region in the opening, wherein the field region adjoins an active region of the semiconductor substrate; implanting a top portion of the field region to form a stress-released region in the dielectric region; and after the step of implanting, forming a gate electrode over the active region.
  • a method of forming an integrated circuit structure includes providing a semiconductor chip including a semiconductor substrate; forming a field region in the semiconductor chip, wherein the field region is between and adjoining a first and a second active region in the semiconductor substrate; forming a first MOS device comprising forming a first gate over the first active region; forming a second MOS device including forming a second gate over the second active region; forming a dielectric stressed layer including a first portion over the first gate and the first active region, and a second portion over the second gate and the second active region; and implanting an upper portion of the dielectric stressed layer to form a stress-released region in the dielectric stressed layer.
  • the upper portion of the dielectric stressed layer is horizontally between the first and the second active regions. A lower portion of the dielectric stressed layer directly underlying the upper portion is not implanted during the step of implanting.
  • an integrated circuit structure includes a semiconductor substrate; a first and a second active region in the semiconductor substrate, wherein the first and the second active regions have a first spacing; and a field region between and adjoining the first and the second active regions.
  • a top central portion of the field region is a stress-released region doped with an element.
  • a lower portion and top edge portions of the field region are substantially free from the element.
  • an integrated circuit structure includes a semiconductor substrate including a first active region and a second active region, wherein the first and the second active regions have a first spacing; a field region between, and adjoining, the first and the second active regions; a first MOS device including a first gate over the first active region; a second MOS device including a second gate over the second active region; and a dielectric stressed layer including a first portion over the first gate and the first active region, and a second portion over the second gate and the second active region.
  • the dielectric stress layer includes a top central portion directly over the field region, wherein the top central portion is doped with an element; a lower central portion directly underlying the top central portion, wherein the lower central portion is substantially free from the element; and portions directly over the first and the second active regions substantially free from the element.
  • the advantageous features of the present invention include reduced device performance drift, and hence there is no longer the need for compensate for the performance drift during circuit simulations.
  • FIGS. 1A and 1B illustrate neighboring metal-oxide-semiconductor (MOS) devices spaced apart by spacings;
  • FIGS. 1C and 1D show the drive current drift of MOS devices as a function of the spacings between neighboring MOS devices
  • FIGS. 2A through 3 are embodiments of the present invention, wherein stress-released regions are formed in field regions between MOS devices;
  • FIGS. 4 through 7 are cross-sectional views of intermediate stages in the manufacturing of the stress-released regions.
  • FIGS. 8A through 8D illustrate different views of an embodiment of the present invention, wherein stress-released regions are formed in stressed layers formed over MOS devices.
  • MOS metal-oxide-semiconductor
  • FIG. 1A illustrates two neighboring MOS devices.
  • the first MOS device includes active region 10 and gate electrode strip 12 over active region 10 .
  • the second MOS device includes active region 14 and gate electrode strip 12 over active region 14 .
  • Active regions 10 and 14 are spaced apart by spacing SP 1 .
  • FIG. 1C Experiments were performed to study the effect of spacing SP 1 to the performance of the neighboring MOS devices. The results are shown in FIG. 1C , wherein the X-axis represents the spacing SP 1 , and the Y-axis represents the drive current drift ( ⁇ Idsat, normalized to the drive current of MOS devices having spacing SP 1 equal to 0). Lines 17 , 19 , and 21 were obtained, each corresponding to one of the active region dimensions D 1 (refer to FIG. 1 ).
  • the drive current drift ( ⁇ Idsat) has a direct correlation to the spacing SP 1 .
  • the drive current drift ⁇ Idsat also increases.
  • the drive current drift ⁇ Idsat becomes significant when the spacing SP 1 is greater than about 0.4 ⁇ m.
  • the spacing SP 1 shown in FIGS. 1A and 1C are in the gate width direction.
  • FIGS. 1B and 1D illustrate that the spacing SP 2 in the gate length direction also affects the drive current of MOS device.
  • the first MOS device includes active region 16 and gate electrode strip 20 over active region 16 .
  • the second MOS device includes active region 18 and gate electrode strip 22 over active region 18 .
  • Experiments were also performed to study the effect of spacing SP 2 to the performance of the neighboring MOS devices. The results are shown in FIG.
  • the drive current drifts of the MOS devices may vary significantly. It is very hard to compensate for such drive current drifts in circuit simulations. Particularly, the variations in the spacings affect the stresses generated by STI regions, dielectric etch stop layers (DESL, also commonly known as contact etch stop layers, or CESL), stress memorization layers, and the like. It is even harder to predict and compensate for the drive current drifts in circuit simulations. Embodiments of the present invention are thus used to reduce such variation in the stresses.
  • DSL dielectric etch stop layers
  • CESL contact etch stop layers
  • FIG. 2A illustrates an embodiment of the present invention.
  • active regions 36 and 38 which belong to a semiconductor chip, are spaced apart by spacing S 1 , wherein the spacing S 1 is filled with isolation region 34 .
  • isolation region 34 (alternatively referred to as field regions) comprises field oxide, for example, thermal silicon oxide formed of local oxidation of silicon (LOCOS).
  • LOC local oxidation of silicon
  • isolation region 34 is a shallow trench isolation (STI) region, which may include silicon oxide, silicon nitride, and/or the like. Isolation region 34 may also be extended to encircle one or both of the active regions 36 and 38 .
  • Gate electrode strip 40 extends over active regions 36 and 38 and isolation region 34 to form MOS devices 30 and 32 , respectively.
  • a first portion of STI region 34 within the region 44 is implanted, while the second portion of STI region 34 outside region 44 is not implanted.
  • the implantation is preferably performed before the formation of gate electrode strip 40 and the formation of source and drain regions in active regions 36 and 38 .
  • the spacing S 2 between the edges of region 44 and the respective edges of active regions 36 and 38 is preferably small enough, so that the variations in the drive currents of the MOS devices are not significant (refer to FIG. 1D ). In an exemplary embodiment, spacing S 2 is less than about 100 ⁇ .
  • length L 1 is preferably greater than about 80 percent of length L 2 of active regions 36 and/or 38 , and more preferably greater than length L 2 .
  • the implantation has the effect of relaxing (releasing) the stress in the implanted portion 45 (refer to FIG. 7 , referred to as stress-released region 45 hereinafter) of STI region 34 , wherein the boundaries of stress-released region 45 is defined by region 44 .
  • the relaxing effect is partially caused by the break of the bonds of the STI materials, for example, oxides, in STI region 34 .
  • the stress-released region 45 applies much smaller stress (in the channel-width-direction, or X direction), if at all, to the MOS devices 30 and 32 than the unimplanted regions (referred to as stressed STI portions/regions hereinafter) of STI region 34 .
  • stressed portions of STI region 34 continue to have inherent stresses, and apply stresses to MOS devices 30 and 32 .
  • a semiconductor chip includes multiple MOS devices, wherein the spacings S 1 between neighboring MOS devices may be different from each other.
  • the widths W 1 of the stress-released region 45 are preferably such determined that spacings S 2 are uniform throughout the semiconductor substrate. In other words, if spacings S 1 are greater, the width W 1 of the stress-released regions 45 (also refer to FIG. 7 ) will also be greater.
  • the values (S 1 -W 1 ) are preferably uniform throughout the semiconductor chip (or at least throughout a stress-sensitive integrated circuit, such as analog circuit, standard cell circuit, and the like).
  • all STI regions 34 throughout the semiconductor chip/wafer are implanted. In these embodiments, the stresses applied by the STI regions are substantially eliminated, and hence the drive current drift between the MOS devices is substantially eliminated.
  • FIG. 2B illustrates an alternative embodiment of the present invention, wherein MOS devices 130 and 132 , instead of sharing a common gate electrode strip, have two parallel gate electrode strips 140 , and two parallel active regions 136 and 138 having spacing S 3 .
  • stress-released region 45 is formed in STI region 34 to reduce the drive current drifts of MOS devices 130 and 132 .
  • spacings S 4 between MOS devices are preferably uniform.
  • the formation of stress-released region 45 reduces the channel-length-direction stresses in the channel regions (underlying gate strips 140 ) of MOS devices 130 and 132 .
  • the dimensions of region 45 are determined based on essentially the same principle for the embodiment shown in FIG. 2A .
  • FIG. 3 illustrates a top view of a semiconductor chip 500 , which includes four device regions 100 , 200 , 300 , and 400 .
  • the first device region 100 includes essentially the same semiconductor structure as shown in FIG. 2A , in which the active regions 36 and 38 have a first spacing S 1 .
  • active regions 36 ′ and 38 ′ have a second spacing S 1 ′.
  • the third device region 300 includes essentially the same semiconductor structure as shown in FIG. 2B , in which the active regions 136 and 138 have spacing S 3 .
  • active regions 136 ′ and 138 ′ have spacing S 3 ′.
  • Spacing S 1 ′ is smaller than spacing S 1 , and hence no stress-released regions are formed between the neighboring MOS devices 30 ′ and 32 ′.
  • spacing S 3 ′ is smaller than spacing S 3 , and hence no stress-released regions are formed between MOS devices 130 ′ and 132 ′.
  • a pre-determined threshold value for example, about 0.3 ⁇ m
  • stress-released STI regions are formed.
  • FIGS. 4 and 5 illustrate the method for forming stress-released regions 45 , wherein the cross-sectional views shown in FIGS. 4 and 5 are taken along the plane crossing line A-A′ in 2 A.
  • substrate 50 which is in semiconductor chip 500 , is provided.
  • Substrate 50 is preferably a semiconductor substrate comprising, for example, silicon, and may be a bulk substrate, or has a silicon-on-insulator (SOI) structure.
  • Pad layer 52 and hard mask 54 are then formed on substrate 50 .
  • Pad layer 52 may be formed of thermal oxide, while hard mask 54 may be formed of silicon nitride.
  • opening 56 is formed in pad layer 52 and hard mask 54 , and extending into substrate 50 .
  • an oxide liner (not shown) is then formed, followed by filling a dielectric material(s) into opening 56 , for example, using high-density plasma chemical vapor deposition (HDP), sub atmospheric chemical vapor deposition (SACVD), or spin on.
  • the materials of the filling dielectric materials may include silicon oxide or spin-on glass.
  • a chemical mechanical polish (CMP) is then performed to remove excess dielectric material over hard mask 54 , forming STI region 34 , as shown in FIG. 5 .
  • stress-released region 45 is formed in STI region 34 .
  • the implanted elements are heavy, so that the bonds of the materials in STI region 34 can be broken to release stresses.
  • the implanted elements may include argon, indium, arsenic, or other elements that are heavy enough to break the bonds.
  • the depth T 1 of stress-released region 45 is preferably deeper than the channel region of MOS devices 32 and 34 (refer to FIG. 2A ). More preferably, depth T 1 is between 100 ⁇ and about 1000 ⁇ . Even more preferably, depth T 1 is greater than about 30 percent of the thickness T 2 of STI region 34 .
  • the dosage of the implanted elements may be between about 1 ⁇ 10 14 /cm 2 and about 1 ⁇ 10 16 /cm 3 .
  • the concentration of the implanted elements in stress-released region 45 is preferably greater than about 1 ⁇ 10 17 /cm 3 .
  • the implantation energy may be about 2 keV to about 100 keV.
  • the formation of stress-released region 45 as shown in FIG. 5 is referred to as a self-aligned formation, since the patterned pad layer 52 and hard mask 54 are used as masks. In this embodiment, all STI regions 34 in semiconductor chip 500 (refer to FIG. 3 ) may be stress-released. After the implantation, pad layer 52 and hard mask 54 are removed.
  • FIGS. 6 and 7 illustrate an alternative embodiment for forming stress-released region 45 in STI region 34 .
  • FIGS. 6 and 7 are cross-sectional views taken along the plane crossing line A-A′ in FIG. 2A .
  • STI region 34 is formed.
  • photo resist 60 is formed and patterned. Opening 62 is formed in photo resist 60 , exposing STI region 34 .
  • the edges of photo resist 60 and the respective edges of active regions 36 and 38 have the spacing S 2 .
  • Photo resist 60 may be formed before, or after, the removal of pad layer 52 and hard mask 54 .
  • an implantation is performed. The implantation process is essentially the same as shown in FIG. 5 .
  • the resulting stress-released region 45 only occupies a top center region of STI region 34 , while the remaining portions, including a lower center region directly underlying the top center region, and edge regions, of STI region 34 are still stressed.
  • FIGS. 8A through 8C illustrate an alternative embodiment of the present invention.
  • stressed layers 70 , 72 , 70 ′, and 72 ′ are formed, for example, using plasma-enhanced chemical vapor deposition (PECVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • the exemplary materials include silicon nitride, silicon oxide, silicon oxynitride, and/or the like.
  • the thickness of stressed layers 70 , 72 , 70 ′, and 72 ′ may be between about 10 nm and about 100 nm.
  • stressed layers 70 and 72 may be portions of a same stressed layer. Depending on the type of the underlying MOS devices, stressed layers 70 , 72 , 70 ′, and 72 ′ may have different combinations of tensile or compressive stresses. Again, the spacing S 3 is greater than spacing S 3 ′. Stressed layers 70 , 72 , 70 ′, and 72 ′ may be DESLs or stress memorization layers. Photo resist 76 is formed over stressed layers 70 , 72 , 70 ′, and 72 ′, wherein opening 78 is formed in photo resist 76 to expose underlying stressed layers 70 and 72 . No opening is formed to expose stressed layers 70 ′ and 72 ′.
  • the thickness T 3 of stress-released region 45 ′ is less than the thickness T 4 of each of the stressed layers 70 and 72 , and more preferably less than 50 percent of thickness T 4 of the stressed layers 70 and/or 72 .
  • the dosage of the implanted elements may be between about 1 ⁇ 10 14 /cm 2 and about 1 ⁇ 10 16 /cm 3 .
  • the concentration of the implanted elements in stress-released region 45 ′ is preferably greater than about 1 ⁇ 10 17 /cm 3 .
  • the implantation energy may be about 2 keV to about 50 keV.
  • FIG. 8B The top view of the structure shown in FIG. 8A is shown in FIG. 8B , wherein the cross-section view in FIG. 8A is taken along a plane crossing line B-B′ in FIG. 8B .
  • the structure shown in FIG. 8B may be the resulting structure after more process steps are performed on the structure shown in FIG. 3 .
  • the stressed layers 70 and 72 in spacings S 1 /S 3 greater than about a pre-determined threshold spacing are implanted, and hence the stresses in the stressed layers are relaxed, while the stressed layers 70 ′ and 72 ′ in spacings S 1 ′/S 3 ′ smaller than about the pre-determined threshold spacing are not implanted. Since the stressed layers apply stresses to the channel regions of the underlying MOS devices, the implantation results in more uniform stresses in the channel regions of the MOS devices, and hence more uniform drive currents.
  • the stressed layers 70 , 72 , 70 ′, and 72 ′ are stress memorization layers
  • an anneal for example, at between about 800° C. and about 1100° C. is performed.
  • the stresses in the stressed layers 70 , 72 , 70 ′, and 72 ′ are thus transferred to the underlying source/drain regions 74 and 74 ′, gate electrodes 140 and 140 ′.
  • FIG. 8D the stressed layers 70 , 72 , 70 ′, and 72 ′ are removed.
  • gate silicides and source/drain silicides may be (not shown) formed, followed by the formation of DESL layers 80 , 80 ′, 82 , and 82 ′.
  • DESL layers 80 , 80 ′, 82 , and 82 ′ may have different combinations of tensile or compressive stresses.
  • stress-released region 45 ′′ may be formed by implantation in DESL layers 80 , 80 ′, 82 , and 82 ′, as shown in FIG. 8D .
  • an inter-layer dielectric (ILD) 84 , and contact plugs 86 are formed.
  • ILD 84 may be formed on stressed layers 70 , 72 , 70 ′, and 72 ′, followed by the formation of the contact plugs.
  • FIG. 8B also illustrates the stress-released regions formed between active regions 36 and 38 , but not between active regions 36 ′ and 38 ′, which is similar to the case shown in FIG. 3 .
  • FIG. 8C illustrates an additional cross-sectional view of the structure as shown in FIG. 8B , wherein the cross-sectional view is taken along a plane crossing line C-C′ in FIG. 8B .
  • the stress-released region 45 ′ is preferably limited in the region directly over STI region 34 .
  • an additional stress-released region 45 may also be formed in the STI region 34 and directly under the stress-released region 45 ′.
  • stress-released regions 45 / 45 ′ may be formed in STI regions, in stress memorization layers, and DESL layers, with different combinations. Further, the stress-released regions 45 / 45 ′ may be formed for different combinations of devices and/or circuits. For example, in an embodiment of the present invention, the stress-released regions are formed between only PMOS devices, but not NMOS, or vise versa. In other embodiments, the stress-released regions are formed between the MOS devices in core circuits, but not between the MOS devices in memory circuits, or vise versa. In yet other embodiments of the present invention, the stress-released regions are formed between the MOS devices in the core circuits, but not between the MOS devices in input/output (IO) circuits, or vise versa.
  • IO input/output
  • the embodiments of the present invention have several advantageous features.
  • the stressed regions may apply uniform stresses to the adjacent (or adjoining) MOS devices; the performance drift (for example, drive current drift) is thus minimized. Accordingly, there is not need to compensate for the performance drift in simulations of the integrated circuits.

Abstract

A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

Description

This application is a continuation of U.S. patent application Ser. No. 13/155,251, filed on Jun. 7, 2011, and entitled “Reducing Device Performance Drift Caused by Large Spacings Between Active Regions;” which application further claims the benefit of U.S. patent application Ser. No. 12/175,976, filed on Jul. 18, 2008, and entitled “Reducing Device Performance Drift Caused by Large Spacings Between Active Regions;” which application further claims the benefit of U.S. Provisional Patent Application Ser. No. 61/050,064, filed on May 2, 2008, and entitled “Reducing Device Performance Drift Caused by Large Spacings Between Active Regions,” which applications are hereby incorporated herein by reference.
TECHNICAL FIELD
This invention relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to reducing the performance drift caused by the difference in stresses applied on the MOS devices.
BACKGROUND
It is well known that the drive currents of metal-oxide-semiconductor (MOS) devices are affected by the stresses applied on the channel regions of the MOS devices. The stresses in the channel regions may improve the carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction (channel length direction) and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in the channel length direction.
Although the beneficial stresses in the channel regions are generally desirable, it is also realized that the magnitudes of the drive current improvement is related to the magnitudes of the stresses. On a same semiconductor chip, the MOS devices may be applied with stresses having different magnitudes. Accordingly, the drive current improvements for different MOS devices may be different, resulting in non-uniform drive currents, hence drive current drift.
It is preferred that the performances of MOS devices are predictable, so that at circuit design time, simulations that accurately reflect the circuit behavior may be performed. Accordingly, it is preferred that in a semiconductor chip, MOS devices of a same type and in a same type of circuits have a uniform performance. However, with the drive current drift, during the simulations of the circuit design, the drive current drift has to be compensated for. What makes the compensation of the drive current drift complicated is that the stresses of MOS device are affected by various factors and those factors behave differently for different layouts. Accordingly, new methods for reducing the drive current drift of MOS devices are needed.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
In accordance with another aspect of the present invention, a method of forming an integrated circuit structure includes providing a semiconductor chip including a semiconductor substrate; forming a hard mask over the semiconductor substrate; forming an opening in the mask to expose a portion of the semiconductor substrate; forming a field region in the opening, wherein the field region adjoins an active region of the semiconductor substrate; implanting a top portion of the field region to form a stress-released region in the dielectric region; and after the step of implanting, forming a gate electrode over the active region.
In accordance with yet another aspect of the present invention, a method of forming an integrated circuit structure includes providing a semiconductor chip including a semiconductor substrate; forming a field region in the semiconductor chip, wherein the field region is between and adjoining a first and a second active region in the semiconductor substrate; forming a first MOS device comprising forming a first gate over the first active region; forming a second MOS device including forming a second gate over the second active region; forming a dielectric stressed layer including a first portion over the first gate and the first active region, and a second portion over the second gate and the second active region; and implanting an upper portion of the dielectric stressed layer to form a stress-released region in the dielectric stressed layer. The upper portion of the dielectric stressed layer is horizontally between the first and the second active regions. A lower portion of the dielectric stressed layer directly underlying the upper portion is not implanted during the step of implanting.
In accordance with yet another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate; a first and a second active region in the semiconductor substrate, wherein the first and the second active regions have a first spacing; and a field region between and adjoining the first and the second active regions. A top central portion of the field region is a stress-released region doped with an element. A lower portion and top edge portions of the field region are substantially free from the element.
In accordance with yet another aspect of the present invention, an integrated circuit structure includes a semiconductor substrate including a first active region and a second active region, wherein the first and the second active regions have a first spacing; a field region between, and adjoining, the first and the second active regions; a first MOS device including a first gate over the first active region; a second MOS device including a second gate over the second active region; and a dielectric stressed layer including a first portion over the first gate and the first active region, and a second portion over the second gate and the second active region. The dielectric stress layer includes a top central portion directly over the field region, wherein the top central portion is doped with an element; a lower central portion directly underlying the top central portion, wherein the lower central portion is substantially free from the element; and portions directly over the first and the second active regions substantially free from the element.
The advantageous features of the present invention include reduced device performance drift, and hence there is no longer the need for compensate for the performance drift during circuit simulations.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1A and 1B illustrate neighboring metal-oxide-semiconductor (MOS) devices spaced apart by spacings;
FIGS. 1C and 1D show the drive current drift of MOS devices as a function of the spacings between neighboring MOS devices;
FIGS. 2A through 3 are embodiments of the present invention, wherein stress-released regions are formed in field regions between MOS devices;
FIGS. 4 through 7 are cross-sectional views of intermediate stages in the manufacturing of the stress-released regions; and
FIGS. 8A through 8D illustrate different views of an embodiment of the present invention, wherein stress-released regions are formed in stressed layers formed over MOS devices.
 DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
A novel method for reducing the drive current drift of metal-oxide-semiconductor (MOS) devices, and the resulting MOS device structures, are provided. The intermediate stages of manufacturing exemplary embodiments of the present invention are illustrated. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.
FIG. 1A illustrates two neighboring MOS devices. The first MOS device includes active region 10 and gate electrode strip 12 over active region 10. The second MOS device includes active region 14 and gate electrode strip 12 over active region 14. Active regions 10 and 14 are spaced apart by spacing SP1. Experiments were performed to study the effect of spacing SP1 to the performance of the neighboring MOS devices. The results are shown in FIG. 1C, wherein the X-axis represents the spacing SP1, and the Y-axis represents the drive current drift (ΔIdsat, normalized to the drive current of MOS devices having spacing SP1 equal to 0). Lines 17, 19, and 21 were obtained, each corresponding to one of the active region dimensions D1 (refer to FIG. 1). It is noted that the drive current drift (ΔIdsat) has a direct correlation to the spacing SP1. When spacing SP1 increases, the drive current drift ΔIdsat also increases. It is also noted that the drive current drift ΔIdsat becomes significant when the spacing SP1 is greater than about 0.4 μm.
The spacing SP1 shown in FIGS. 1A and 1C are in the gate width direction. FIGS. 1B and 1D illustrate that the spacing SP2 in the gate length direction also affects the drive current of MOS device. Referring to FIG. 1B, two MOS devices are laid out side by side. The first MOS device includes active region 16 and gate electrode strip 20 over active region 16. The second MOS device includes active region 18 and gate electrode strip 22 over active region 18. Experiments were also performed to study the effect of spacing SP2 to the performance of the neighboring MOS devices. The results are shown in FIG. 1D, wherein the X-axis represents the spacing SP2, while the Y-axis represents the drive current drift (ΔIdsat, normalized to the drive current of MOS devices having spacing SP2 equal to 0). A plurality of lines was obtained, each corresponding to one of the active region dimension D2. It is noted that the drive current drift (ΔIdsat) is related to the spacing SP2. When spacing SP2 increases, the current drift ΔIdsat also increases. It is also noted that the drive current drift ΔIdsat becomes significant when the spacing SP2 is greater than about 0.25 μm.
It is realized that in a semiconductor chip, there will be a plurality of MOS devices, with different spacings SP1 and SP2 (which may vary in a big range) in different combinations. For each of the MOS devices, the respective spacings SP1 and SP2 affect its performance. Accordingly, in a semiconductor chip, the drive current drifts of the MOS devices may vary significantly. It is very hard to compensate for such drive current drifts in circuit simulations. Particularly, the variations in the spacings affect the stresses generated by STI regions, dielectric etch stop layers (DESL, also commonly known as contact etch stop layers, or CESL), stress memorization layers, and the like. It is even harder to predict and compensate for the drive current drifts in circuit simulations. Embodiments of the present invention are thus used to reduce such variation in the stresses.
FIG. 2A illustrates an embodiment of the present invention. In this embodiment, active regions 36 and 38, which belong to a semiconductor chip, are spaced apart by spacing S1, wherein the spacing S1 is filled with isolation region 34. In an embodiment, isolation region 34 (alternatively referred to as field regions) comprises field oxide, for example, thermal silicon oxide formed of local oxidation of silicon (LOCOS). In other embodiments, isolation region 34 is a shallow trench isolation (STI) region, which may include silicon oxide, silicon nitride, and/or the like. Isolation region 34 may also be extended to encircle one or both of the active regions 36 and 38. Gate electrode strip 40 extends over active regions 36 and 38 and isolation region 34 to form MOS devices 30 and 32, respectively.
In an embodiment, a first portion of STI region 34 within the region 44 (marked with dashed lines) is implanted, while the second portion of STI region 34 outside region 44 is not implanted. The implantation is preferably performed before the formation of gate electrode strip 40 and the formation of source and drain regions in active regions 36 and 38. The spacing S2 between the edges of region 44 and the respective edges of active regions 36 and 38 is preferably small enough, so that the variations in the drive currents of the MOS devices are not significant (refer to FIG. 1D). In an exemplary embodiment, spacing S2 is less than about 100 Å. One skilled in the art will realize, however, that the dimensions recited throughout the description are merely examples, and will change if different formation technologies are used. In the gate length direction (Y direction), length L1 is preferably greater than about 80 percent of length L2 of active regions 36 and/or 38, and more preferably greater than length L2.
The implantation has the effect of relaxing (releasing) the stress in the implanted portion 45 (refer to FIG. 7, referred to as stress-released region 45 hereinafter) of STI region 34, wherein the boundaries of stress-released region 45 is defined by region 44. The relaxing effect is partially caused by the break of the bonds of the STI materials, for example, oxides, in STI region 34. Accordingly, the stress-released region 45 applies much smaller stress (in the channel-width-direction, or X direction), if at all, to the MOS devices 30 and 32 than the unimplanted regions (referred to as stressed STI portions/regions hereinafter) of STI region 34. On the other hand, the stressed portions of STI region 34 continue to have inherent stresses, and apply stresses to MOS devices 30 and 32.
It is realized that a semiconductor chip includes multiple MOS devices, wherein the spacings S1 between neighboring MOS devices may be different from each other. To achieve uniform drive currents throughout the semiconductor chip, the widths W1 of the stress-released region 45 are preferably such determined that spacings S2 are uniform throughout the semiconductor substrate. In other words, if spacings S1 are greater, the width W1 of the stress-released regions 45 (also refer to FIG. 7) will also be greater. However, the values (S1-W1) are preferably uniform throughout the semiconductor chip (or at least throughout a stress-sensitive integrated circuit, such as analog circuit, standard cell circuit, and the like). With substantially uniform spacings S2 throughout the chip, the stresses applied by the STI regions to the MOS devices are substantially uniform. Accordingly, the drive current changes caused by the STI regions are uniform, and hence the drive current drift between MOS devices is reduced.
In alternative embodiments, all STI regions 34 throughout the semiconductor chip/wafer are implanted. In these embodiments, the stresses applied by the STI regions are substantially eliminated, and hence the drive current drift between the MOS devices is substantially eliminated.
FIG. 2B illustrates an alternative embodiment of the present invention, wherein MOS devices 130 and 132, instead of sharing a common gate electrode strip, have two parallel gate electrode strips 140, and two parallel active regions 136 and 138 having spacing S3. Similarly, stress-released region 45 is formed in STI region 34 to reduce the drive current drifts of MOS devices 130 and 132. Also, throughout a stress-sensitive integrated circuit or a semiconductor chip, spacings S4 between MOS devices are preferably uniform. The formation of stress-released region 45 reduces the channel-length-direction stresses in the channel regions (underlying gate strips 140) of MOS devices 130 and 132. The dimensions of region 45 are determined based on essentially the same principle for the embodiment shown in FIG. 2A.
FIG. 3 illustrates a top view of a semiconductor chip 500, which includes four device regions 100, 200, 300, and 400. The first device region 100 includes essentially the same semiconductor structure as shown in FIG. 2A, in which the active regions 36 and 38 have a first spacing S1. In the second device region 200, active regions 36′ and 38′ have a second spacing S1′. The third device region 300 includes essentially the same semiconductor structure as shown in FIG. 2B, in which the active regions 136 and 138 have spacing S3. In the fourth region 400, active regions 136′ and 138′ have spacing S3′. Spacing S1′ is smaller than spacing S1, and hence no stress-released regions are formed between the neighboring MOS devices 30′ and 32′. Similarly, spacing S3′ is smaller than spacing S3, and hence no stress-released regions are formed between MOS devices 130′ and 132′. Preferably, throughout a stress-sensitive circuit or throughout semiconductor chip 500, for substantially all spacings between neighboring active regions smaller than a pre-determined threshold value, for example, about 0.3 μm, no stress-released STI regions are formed. Conversely, for substantially all spacings between neighboring active regions greater than the pre-determined threshold value, stress-released STI regions are formed.
FIGS. 4 and 5 illustrate the method for forming stress-released regions 45, wherein the cross-sectional views shown in FIGS. 4 and 5 are taken along the plane crossing line A-A′ in 2A. Referring to FIG. 4, substrate 50, which is in semiconductor chip 500, is provided. Substrate 50 is preferably a semiconductor substrate comprising, for example, silicon, and may be a bulk substrate, or has a silicon-on-insulator (SOI) structure. Pad layer 52 and hard mask 54 are then formed on substrate 50. Pad layer 52 may be formed of thermal oxide, while hard mask 54 may be formed of silicon nitride. Next, with the formation and patterning of a photo resist (not shown), opening 56 is formed in pad layer 52 and hard mask 54, and extending into substrate 50. Referring to FIG. 5, an oxide liner (not shown) is then formed, followed by filling a dielectric material(s) into opening 56, for example, using high-density plasma chemical vapor deposition (HDP), sub atmospheric chemical vapor deposition (SACVD), or spin on. The materials of the filling dielectric materials may include silicon oxide or spin-on glass. A chemical mechanical polish (CMP) is then performed to remove excess dielectric material over hard mask 54, forming STI region 34, as shown in FIG. 5.
Next, as also shown in FIG. 5, an implantation is performed, forming stress-released region 45 in STI region 34. Preferably, the implanted elements are heavy, so that the bonds of the materials in STI region 34 can be broken to release stresses. The implanted elements may include argon, indium, arsenic, or other elements that are heavy enough to break the bonds. The depth T1 of stress-released region 45 is preferably deeper than the channel region of MOS devices 32 and 34 (refer to FIG. 2A). More preferably, depth T1 is between 100 Å and about 1000 Å. Even more preferably, depth T1 is greater than about 30 percent of the thickness T2 of STI region 34. The dosage of the implanted elements may be between about 1×1014/cm2 and about 1×1016/cm3. The concentration of the implanted elements in stress-released region 45 is preferably greater than about 1×1017/cm3. The implantation energy may be about 2 keV to about 100 keV. The formation of stress-released region 45 as shown in FIG. 5 is referred to as a self-aligned formation, since the patterned pad layer 52 and hard mask 54 are used as masks. In this embodiment, all STI regions 34 in semiconductor chip 500 (refer to FIG. 3) may be stress-released. After the implantation, pad layer 52 and hard mask 54 are removed.
FIGS. 6 and 7 illustrate an alternative embodiment for forming stress-released region 45 in STI region 34. FIGS. 6 and 7 are cross-sectional views taken along the plane crossing line A-A′ in FIG. 2A. Referring to FIG. 6, STI region 34 is formed. Next, as shown in FIG. 7, photo resist 60 is formed and patterned. Opening 62 is formed in photo resist 60, exposing STI region 34. The edges of photo resist 60 and the respective edges of active regions 36 and 38 have the spacing S2. Photo resist 60 may be formed before, or after, the removal of pad layer 52 and hard mask 54. Next, an implantation is performed. The implantation process is essentially the same as shown in FIG. 5. The resulting stress-released region 45 only occupies a top center region of STI region 34, while the remaining portions, including a lower center region directly underlying the top center region, and edge regions, of STI region 34 are still stressed.
FIGS. 8A through 8C illustrate an alternative embodiment of the present invention. Referring to FIG. 8A, after the formation of MOS devices 130, 132, 130′, and 132′ (please also refer to FIG. 8B), stressed layers 70, 72, 70′, and 72′ are formed, for example, using plasma-enhanced chemical vapor deposition (PECVD). The exemplary materials include silicon nitride, silicon oxide, silicon oxynitride, and/or the like. The thickness of stressed layers 70, 72, 70′, and 72′ may be between about 10 nm and about 100 nm.
In the case MOS devices 130 and 132 are of a same conductivity type, stressed layers 70 and 72 may be portions of a same stressed layer. Depending on the type of the underlying MOS devices, stressed layers 70, 72, 70′, and 72′ may have different combinations of tensile or compressive stresses. Again, the spacing S3 is greater than spacing S3′. Stressed layers 70, 72, 70′, and 72′ may be DESLs or stress memorization layers. Photo resist 76 is formed over stressed layers 70, 72, 70′, and 72′, wherein opening 78 is formed in photo resist 76 to expose underlying stressed layers 70 and 72. No opening is formed to expose stressed layers 70′ and 72′.
Next, an implantation is performed to implant the exposed stressed layers 70 and 72, forming stress-released region 45′. Preferably, the thickness T3 of stress-released region 45′ is less than the thickness T4 of each of the stressed layers 70 and 72, and more preferably less than 50 percent of thickness T4 of the stressed layers 70 and/or 72. The dosage of the implanted elements may be between about 1×1014/cm2 and about 1×1016/cm3. The concentration of the implanted elements in stress-released region 45′ is preferably greater than about 1×1017/cm3. The implantation energy may be about 2 keV to about 50 keV.
The top view of the structure shown in FIG. 8A is shown in FIG. 8B, wherein the cross-section view in FIG. 8A is taken along a plane crossing line B-B′ in FIG. 8B. The structure shown in FIG. 8B may be the resulting structure after more process steps are performed on the structure shown in FIG. 3. Similar to the embodiment as shown in FIG. 3, preferably, throughout a stress-sensitive integrated circuit or throughout semiconductor chip 500, the stressed layers 70 and 72 in spacings S1/S3 greater than about a pre-determined threshold spacing are implanted, and hence the stresses in the stressed layers are relaxed, while the stressed layers 70′ and 72′ in spacings S1′/S3′ smaller than about the pre-determined threshold spacing are not implanted. Since the stressed layers apply stresses to the channel regions of the underlying MOS devices, the implantation results in more uniform stresses in the channel regions of the MOS devices, and hence more uniform drive currents.
Referring back to FIG. 8A, in the case the stressed layers 70, 72, 70′, and 72′ are stress memorization layers, after the implantation, an anneal, for example, at between about 800° C. and about 1100° C. is performed. The stresses in the stressed layers 70, 72, 70′, and 72′ are thus transferred to the underlying source/ drain regions 74 and 74′, gate electrodes 140 and 140′. In FIG. 8D, the stressed layers 70, 72, 70′, and 72′ are removed. Then, gate silicides and source/drain silicides may be (not shown) formed, followed by the formation of DESL layers 80, 80′, 82, and 82′. Like the stressed layers 70, 72, 70′, and 72′, DESL layers 80, 80′, 82, and 82′ may have different combinations of tensile or compressive stresses. Similar to the formation of stress-released region 45′ in FIG. 8A, stress-released region 45″ may be formed by implantation in DESL layers 80, 80′, 82, and 82′, as shown in FIG. 8D. Next, an inter-layer dielectric (ILD) 84, and contact plugs 86 are formed. In the case stressed layers 70, 72, 70′, and 72′ are DESLs, ILD 84 may be formed on stressed layers 70, 72, 70′, and 72′, followed by the formation of the contact plugs.
FIG. 8B also illustrates the stress-released regions formed between active regions 36 and 38, but not between active regions 36′ and 38′, which is similar to the case shown in FIG. 3.
FIG. 8C illustrates an additional cross-sectional view of the structure as shown in FIG. 8B, wherein the cross-sectional view is taken along a plane crossing line C-C′ in FIG. 8B. It shows that the stress-released region 45′ is preferably limited in the region directly over STI region 34. Further, an additional stress-released region 45 may also be formed in the STI region 34 and directly under the stress-released region 45′.
Please note that in the embodiments of the present invention, stress-released regions 45/45′ may be formed in STI regions, in stress memorization layers, and DESL layers, with different combinations. Further, the stress-released regions 45/45′ may be formed for different combinations of devices and/or circuits. For example, in an embodiment of the present invention, the stress-released regions are formed between only PMOS devices, but not NMOS, or vise versa. In other embodiments, the stress-released regions are formed between the MOS devices in core circuits, but not between the MOS devices in memory circuits, or vise versa. In yet other embodiments of the present invention, the stress-released regions are formed between the MOS devices in the core circuits, but not between the MOS devices in input/output (IO) circuits, or vise versa.
The embodiments of the present invention have several advantageous features. By forming stress-released regions in stressed regions, the stressed regions may apply uniform stresses to the adjacent (or adjoining) MOS devices; the performance drift (for example, drive current drift) is thus minimized. Accordingly, there is not need to compensate for the performance drift in simulations of the integrated circuits.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (17)

1. A device comprising:
a semiconductor substrate;
a first active region in the semiconductor substrate; and
a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the STI region comprises:
a first surface portion doped with a doping element and having a first inherent stress; and
a second surface portion substantially free from the doping element, having a second inherent stress greater than the first inherent stress, wherein the first active region and the first surface portion are on opposite sides of, and are in contact with, the second surface portion.
2. The device of claim 1 further comprising a second active region in the semiconductor substrate, wherein the first active region and the second active region are on opposite sides of the STI region.
3. The device of claim 2, wherein the STI region further comprises a third surface portion having a third inherent stress greater than the first inherent stress, wherein the second active region and the first surface portion are on opposite sides of, and are in contact with, the third surface portion.
4. The device of claim 1 further comprising a gate electrode strip over and crossing the first active region in a top view of the device, wherein the gate electrode strip is directly over the first surface portion and the second surface portion of the STI region.
5. The device of claim 1, wherein a distance between the first active region and the first surface portion is smaller than about 100 Å.
6. The device of claim 1, wherein the STI region further comprises a bottom portion having an inherent stress greater than the first inherent stress, wherein the bottom portion is underlying and aligned to the first surface portion.
7. The device of claim 1, wherein the element is selected from the group consisting essentially of argon, indium, arsenic, and combinations thereof.
8. The device of claim 1, wherein the STI region further comprises bottom portion having underlying and aligned to the first surface portion, wherein the bottom portion is substantially free from the element.
9. The device of claim 1, wherein the element in the first portion of the STI region has a concentration greater than about 1×1017/cm3.
10. A semiconductor device, comprising:
a semiconductor substrate;
a first active region in the semiconductor substrate; and
a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the STI region comprises:
a first surface portion having a first inherent stress; and
a second surface portion having a second inherent stress greater than the first inherent stress, and separating the first active region and the first surface portion;
wherein a distance between the first active region and the first surface portion is smaller than about 100 Å.
11. The device of claim 10, wherein the first surface portion is doped with an element, and wherein the second surface portion is substantially free from the element.
12. The device of claim 10 further comprising a second active region in the semiconductor substrate, wherein the first active region and the second active region are on opposite sides of the STI region.
13. The device of claim 12, wherein the STI region further comprises a third surface portion having a third inherent stress greater than the first inherent stress, wherein the second active region and the first surface portion are on opposite sides of, and are in contact with, the third surface portion.
14. A semiconductor device, comprising:
a semiconductor substrate; and
a plurality of device regions, each device region comprising:
a first active region;
a second active region separated from the first active region by a first spacing (S1);
a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate, disposed between and adjacent to the first active region and the second active region;
a first STI surface region doped with a doping element, and having a first inherent stress, and disposed in the STI region between the first active region and the second active region and having a first width (W1); and
a second STI surface region substantially free of the doping element, and having a second inherent stress greater than the first inherent stress, and disposed in the STI region, a portion of the second STI surface region disposed between and separating the first active region and the first STI surface portion by a second spacing (S2), and a portion of the second STI surface region disposed between and separating the second active region and the first STI surface portion by the second spacing (S2);
wherein the second spacing (S2) of a first device region and the second spacing (S2) of a second device region are substantially constant.
15. The device of claim 14, wherein the first spacing (S1) of the first device region and the first spacing (S1) of the second device region are different.
16. The device of claim 14, wherein the first spacing (S1) is equal to the second spacing (S2) multiplied by two and added to the first width (W1).
17. The device of claim 14, wherein the second spacing (S2) is less than about 100 Å.
US13/367,103 2008-05-02 2012-02-06 Reducing device performance drift caused by large spacings between active regions Active US8368170B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/367,103 US8368170B2 (en) 2008-05-02 2012-02-06 Reducing device performance drift caused by large spacings between active regions

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US5006408P 2008-05-02 2008-05-02
US12/175,976 US7977202B2 (en) 2008-05-02 2008-07-18 Reducing device performance drift caused by large spacings between active regions
US13/155,251 US8115271B2 (en) 2008-05-02 2011-06-07 Reducing device performance drift caused by large spacings between active regions
US13/367,103 US8368170B2 (en) 2008-05-02 2012-02-06 Reducing device performance drift caused by large spacings between active regions

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/155,251 Continuation US8115271B2 (en) 2008-05-02 2011-06-07 Reducing device performance drift caused by large spacings between active regions

Publications (2)

Publication Number Publication Date
US20120132987A1 US20120132987A1 (en) 2012-05-31
US8368170B2 true US8368170B2 (en) 2013-02-05

Family

ID=41256554

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/175,976 Expired - Fee Related US7977202B2 (en) 2008-05-02 2008-07-18 Reducing device performance drift caused by large spacings between active regions
US13/155,251 Active US8115271B2 (en) 2008-05-02 2011-06-07 Reducing device performance drift caused by large spacings between active regions
US13/367,103 Active US8368170B2 (en) 2008-05-02 2012-02-06 Reducing device performance drift caused by large spacings between active regions

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US12/175,976 Expired - Fee Related US7977202B2 (en) 2008-05-02 2008-07-18 Reducing device performance drift caused by large spacings between active regions
US13/155,251 Active US8115271B2 (en) 2008-05-02 2011-06-07 Reducing device performance drift caused by large spacings between active regions

Country Status (1)

Country Link
US (3) US7977202B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170337320A1 (en) * 2016-05-18 2017-11-23 Matthew Berzins Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977202B2 (en) 2008-05-02 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing device performance drift caused by large spacings between active regions
US8877602B2 (en) * 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
KR101831936B1 (en) * 2011-12-22 2018-02-26 삼성전자주식회사 Method for forming a thin film and method for manufacturing a semiconductor device by using the same
US20130248978A1 (en) * 2012-03-22 2013-09-26 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9728637B2 (en) * 2013-11-14 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for forming semiconductor device with gate
CN103646954A (en) * 2013-11-28 2014-03-19 上海华力微电子有限公司 A method for manufacturing a dual stress liner and a semiconductor device containing a dual stress liner
US9508844B2 (en) * 2014-01-06 2016-11-29 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and formation thereof
CN104795412B (en) * 2014-01-20 2018-03-30 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation
US10192985B2 (en) * 2015-07-21 2019-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET with doped isolation insulating layer
KR102414957B1 (en) 2018-06-15 2022-06-29 삼성전자주식회사 Method for fabricating semiconductor device
KR20200105197A (en) 2019-02-28 2020-09-07 삼성전자주식회사 Image sensor

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6284626B1 (en) 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6875053B2 (en) 2002-12-10 2005-04-05 Sumitomo Wiring Systems, Ltd. Ground connector and method of mounting it
US20050127474A1 (en) * 2003-12-12 2005-06-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US6984564B1 (en) 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
US7109443B2 (en) 2004-03-26 2006-09-19 Intel Corporation Multi-zone reflecting device for use in flash lamp processes
US7119404B2 (en) 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
US20060226490A1 (en) 2005-04-06 2006-10-12 Burnett James D Interlayer dielectric under stress for an integrated circuit
US7164163B2 (en) 2005-02-22 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with hybrid-strain inducing layer
US20070105336A1 (en) 2005-11-10 2007-05-10 Shinji Takeoka Semiconductor device and method for fabricating the same
US7232730B2 (en) 2005-04-29 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a locally strained transistor
US20080150037A1 (en) 2006-12-24 2008-06-26 Chartered Semiconductor Manufacturing, Ltd Selective STI Stress Relaxation Through Ion Implantation
US20090057809A1 (en) 2007-08-31 2009-03-05 Ralf Richter Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device
US20090140345A1 (en) * 2007-11-29 2009-06-04 International Business Machines Corporation Semiconductor structure including self-aligned deposited gate dielectric
US20110233682A1 (en) 2008-05-02 2011-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing Device Performance Drift Caused by Large Spacings Between Active Regions

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4168995B2 (en) * 2004-09-30 2008-10-22 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6284626B1 (en) 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6875053B2 (en) 2002-12-10 2005-04-05 Sumitomo Wiring Systems, Ltd. Ground connector and method of mounting it
US20050127474A1 (en) * 2003-12-12 2005-06-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US7109443B2 (en) 2004-03-26 2006-09-19 Intel Corporation Multi-zone reflecting device for use in flash lamp processes
US7119404B2 (en) 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
US6984564B1 (en) 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
US7164163B2 (en) 2005-02-22 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with hybrid-strain inducing layer
US20060226490A1 (en) 2005-04-06 2006-10-12 Burnett James D Interlayer dielectric under stress for an integrated circuit
US7232730B2 (en) 2005-04-29 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a locally strained transistor
US20070105336A1 (en) 2005-11-10 2007-05-10 Shinji Takeoka Semiconductor device and method for fabricating the same
US20080150037A1 (en) 2006-12-24 2008-06-26 Chartered Semiconductor Manufacturing, Ltd Selective STI Stress Relaxation Through Ion Implantation
US20090057809A1 (en) 2007-08-31 2009-03-05 Ralf Richter Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device
US20090140345A1 (en) * 2007-11-29 2009-06-04 International Business Machines Corporation Semiconductor structure including self-aligned deposited gate dielectric
US20110233682A1 (en) 2008-05-02 2011-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing Device Performance Drift Caused by Large Spacings Between Active Regions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170337320A1 (en) * 2016-05-18 2017-11-23 Matthew Berzins Using deep sub-micron stress effects and proximity effects to create a high performance standard cell
US9904758B2 (en) * 2016-05-18 2018-02-27 Samsung Electronics Co., Ltd. Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

Also Published As

Publication number Publication date
US8115271B2 (en) 2012-02-14
US20090273052A1 (en) 2009-11-05
US20110233682A1 (en) 2011-09-29
US7977202B2 (en) 2011-07-12
US20120132987A1 (en) 2012-05-31

Similar Documents

Publication Publication Date Title
US8368170B2 (en) Reducing device performance drift caused by large spacings between active regions
US7449753B2 (en) Write margin improvement for SRAM cells with SiGe stressors
US7704855B2 (en) Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby
US8497168B2 (en) Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers
US7678636B2 (en) Selective formation of stress memorization layer
US8338909B2 (en) Two-Step STI formation process
US7649233B2 (en) High performance transistor with a highly stressed channel
US7423319B2 (en) LDPMOS structure with enhanced breakdown voltage
US7932141B2 (en) Semiconductor device and method for fabricating the same
US8502326B2 (en) Gate dielectric formation for high-voltage MOS devices
US8546241B2 (en) Semiconductor device with stress trench isolation and method for forming the same
JP2006278754A (en) Semiconductor device and its manufacturing method
US20090315115A1 (en) Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement
US7781844B2 (en) Semiconductor device having a stressor film
JP5268385B2 (en) Semiconductor device
US7737466B1 (en) Semiconductor device and manufacturing method thereof
US8502325B2 (en) Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance
US9281246B2 (en) Strain adjustment in the formation of MOS devices
US7588987B2 (en) Semiconductor device and method for fabricating the same
JP2008539592A (en) Semiconductor devices with gate insulating films with different blocking characteristics
US20070281432A1 (en) Transistor and method of providing interlocking strained silicon on a silicon substrate
CN114497217A (en) Semiconductor structure and forming method thereof
KR20080022473A (en) Fabricating method for semiconductor integrated circuit device and semiconductor integrated circuit device fabricated by the same
KR20090042586A (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8