US8338230B2 - System and method for multi-chip module die extraction and replacement - Google Patents
System and method for multi-chip module die extraction and replacement Download PDFInfo
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- US8338230B2 US8338230B2 US13/245,909 US201113245909A US8338230B2 US 8338230 B2 US8338230 B2 US 8338230B2 US 201113245909 A US201113245909 A US 201113245909A US 8338230 B2 US8338230 B2 US 8338230B2
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Abstract
A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
Description
This Application is a divisional of U.S. application Ser. No. 12/432,672 filed Apr. 29, 2009, the contents of which are incorporated herein by reference.
The invention was made with United States Government support under Contract No. 03-C-0216. The United States Government has certain rights in this invention.
Embodiments of the present invention relate generally to integrated circuit device packaging, and more specifically to multichip module packages that may have stacked chip arrangements.
When it comes to chip or integrated circuit device packaging, it is often desirable and sometimes imperative to have a relatively high device packaging density. Device packaging density can be defined as the number of devices per unit package volume. To such end, multichip module (MCM) packages are increasingly attractive for a variety of reasons. For example, MCM packages, which contain more than one chip per package, provide increased functionality of a given package, and decrease the interconnection length among chips in the package, thereby reducing signal delays and access times among chips.
One common MCM package is the three-dimensional “stacked” MCM package, in which one chip is disposed on a substrate and one or more other chips are stacked successively on top of one another and the first chip. Interconnections among chips and conductive traces on the common substrate are electrically made via bond wires.
The active circuit area of first chip 112 is covered by a passivation layer 125. An adhesive layer 126 is interposed between and connects passivation layer 125 and an interposer 127. Interposer 127 is often made of a material similar in properties to first chip 112 and second chip 113 in order to avoid thermal expansion mismatch over temperature variations. For example, if first chip 112 and second chip 113 are made of bulk silicon, interposer 127 should also be made of silicon. Interposer 127 has a thickness sufficient to allow clearance and access to the bond pads 112 a along the edges of first chip 112. Interposer 127 also serves as a pedestal for supporting second chip 113. An adhesive layer 128 is disposed between and connects interposer 127 and bondable surface 123 of second chip 113.
One application in which stacked MCM packages are commonly used is space applications, or applications in other environments wherein physical space is limited and tolerance to high levels of radiation required. Packages with such tolerance to high levels of radiation are referred to as “hardened” packages. The chips in such hardened packages are also typically “hardened” through the addition of redundant circuitry and/or error detection and correction circuitry so that the chips function properly in high radiation environments like space. Due to the hardened nature, of the chips used in such environments, manufacturing costs for these chips can be inordinately expensive—often tens or even hundreds of times more expensive than counterparts of equivalent complexity used in consumer applications. For example, a hardened microprocessor could cost $10,000.
Unfortunately, due to current methods for manufacturing an MCM package in a stacked configuration, each chip or die in an MCM is so securely affixed to those above and below it that separation of that chip from the body of the MCM requires processes that are expensive, require high amounts of heat, or both. Thus, reworking or replacing a chip or die that has failed within a stacked MCM package often results in the destruction of one or more chips immediately above or below it. This naturally multiplies the cost of the original chip failure.
Consequently, it is desirable to provide an improved system and method for both manufacturing stacked MCM packages, and for reworking specific failed chips or dies within such packages.
A need still exists, therefore, for providing an MCM package that allows the removal and/or replacement of one or more failed chips or dies without inflicting concomitant damage or destruction to nearby chips that would otherwise still be functional. In particular, there is a need to provide such functionality that is low in cost and allows for the removal or replacement to occur at room temperature.
According to certain embodiments of the present invention, a system and method are provided in which a first chip in a stacked MCM configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder balls or “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
The drawings are semi-diagrammatic not necessarily to scale and, particularly, some of the dimensions may be for clarity of presentation and shown greatly exaggerated. Similarly, although the views in the drawings, for ease of description, generally show similar orientations, this depiction is arbitrary for the most part. Generally, embodiments of the invention can be operated in any orientation. In addition, where multiple embodiments are disclosed and, described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
In the following description, certain details are set forth in conjunction with the described embodiments of the present invention to provide a sufficient understanding of the invention. One skilled in the art will appreciate, however, that the invention may be practiced without these particular details. Furthermore, one skilled in the art will appreciate that the example embodiments described below do not limit the scope of the present invention, and will also understand that various modifications, equivalents, and combinations of the disclosed embodiments and components of such embodiments are within the scope of the present invention. Embodiments including fewer than all the components of any of the respective described embodiments may also be within the scope of the present invention although not expressly described in detail below. Finally, the operation of well-known components and/or processes has not been shown or described in detail below to avoid unnecessarily obscuring the present invention.
The upper interposer partition 250 is connected to second chip 113 via adhesive layer 128 and also soldered to lower interposer partition 255 via solder bumps 260. Solder bumps 260, as discussed above with respect to FIG. 2 , provide a high tensile strength for vertically bonding the upper and lower interposer partitions 250 and 255, but are easily broken via horizontal shear force 254 or rotational torque 257. Lower interposer partition 255 is, in turn, adhered to passivation layer 125 via adhesive layer 126.
To examine the MCM package 400 of FIG. 4 in operation of the interposer 449, assume that second chip 413 has been shown to be nonoperational. This type of failure can occur at the time of the chip manufacture or through the course of operation over time. In either case, it is advantageous to be able to remove (and possibly replace) the non-operational chip.
Force line AA shows a line substantially bisecting the solder bumps 460. The vertical placement of line AA is arbitrary with respect to the vertical extension of the bumps. To separate upper and lower interposer partitions 350 and 355, a technician or end-user collectively creates torsion in solder bumps 460 by applying equal but opposing shear forces to upper and lower interposer partitions 350, 355 respectively, parallel to line AA and the plane of substrate 411. The shear force thus provided to each solder bump 460 causes the bonds formed by those solder bumps to break and allows the separation of MCM package 400 along line AA. Because the force required to effectuate the removal of second chip 413 is so low, it can be accomplished without damaging first chip 412. Furthermore, because the chip removal can be done at room temperature, it may be performed in the same area where modules are tested, allowing immediate confirmation that the first chip has not been damaged.
In certain embodiments, the surface of the dies or of the interposer partitions are constructed with such shape or footprint as may easily integrate with a rotational tool, such as a wrench, to enable faster and more precise breaking of the bonds between the upper and lower interposer partitions. In other embodiments, a technician or other user may simply separate the interposer partitions by applying the needed horizontal shear force or torque by hand.
It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, variations on certain embodiments described above or depicted in the drawings may include three or more chips in a single MCM package, many or all of which may be separated by interposer units in accord with the present invention. As another example, certain embodiments may include additional structures affixed within the MCM package between one or more chips and a respective interposer unit. Therefore, the present invention is to be limited only by the appended claims.
Claims (7)
1. A method, comprising:
providing a substrate;
providing first and second integrated circuit dies, wherein each of said dies comprises a top surface and a bottom surface;
coupling said bottom surface of the first die to the substrate;
providing an interposer having a lower portion and an upper portion coupled by a plurality of solder units;
coupling said lower portion of the interposer directly to said top surface of the first die; and
coupling said bottom surface of the second die directly to said upper portion of the interposer.
2. The method of claim 1 , further comprising:
Uncoupling said lower and upper portions of the interposer by applying opposing rotational forces to said lower and upper portions substantially parallel to the plane of said portions.
3. The method of claim 2 , wherein applying opposing rotational forces comprises using a tool to apply a torque to one of said portions.
4. The method of claim 1 , further comprising:
Uncoupling said lower and upper portions of the interposer by applying opposing lateral forces to said lower and upper portions substantially parallel to the plane of the portions.
5. A method comprising,
providing a substrate;
providing first and second integrated circuit dies, wherein each of said dies
comprises a top surface and a lower surface;
coupling said lower surface of the first die to the substrate;
providing an interposer having a lower portion and an upper portion coupled by a plurality of solder units;
coupling said lower portion of the interposer directly to said top surface of the first die;
coupling said lower surface of the second die directly to said upper portion of the interposer; and
uncoupling said upper and lower portions of the interposer by applying opposing rotational forces to said lower and upper portions substantially parallel to the plane of the portions.
6. The method of claim 5 , wherein applying opposing rotational forces comprises using a tool to apply a torque to one of said portions.
7. A method comprising,
providing a substrate;
providing first and second integrated circuit dies, wherein each of said dies
comprises a top surface and a lower surface;
coupling said lower surface of the first die to the substrate;
providing an interposer having a lower portion and an upper portion coupled by a plurality of solder units;
coupling said lower portion of the interposer directly to said top surface of the first die;
coupling said lower surface of the second die directly to said upper portion of the interposer; and
uncoupling said lower and upper portions of the interposer by applying opposing lateral forces to said lower and upper portions substantially parallel to the plane of the portions.
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US13/245,909 US8338230B2 (en) | 2009-04-29 | 2011-09-27 | System and method for multi-chip module die extraction and replacement |
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US12/432,672 US8067829B2 (en) | 2009-04-29 | 2009-04-29 | System and method for multi-chip module die extraction and replacement |
US13/245,909 US8338230B2 (en) | 2009-04-29 | 2011-09-27 | System and method for multi-chip module die extraction and replacement |
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US13/245,909 Active US8338230B2 (en) | 2009-04-29 | 2011-09-27 | System and method for multi-chip module die extraction and replacement |
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US9294092B2 (en) * | 2013-07-26 | 2016-03-22 | Altera Corporation | Error resilient packaged components |
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CN111799182A (en) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | Package stack structure and method for fabricating the same |
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WO2008092003A2 (en) * | 2007-01-25 | 2008-07-31 | Honda Motor Co., Ltd. | Vehicle systems control for improving stability |
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US6661088B1 (en) | 1999-09-27 | 2003-12-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having interposer and method of manufacturing the same |
US6335491B1 (en) | 2000-02-08 | 2002-01-01 | Lsi Logic Corporation | Interposer for semiconductor package assembly |
US6589180B2 (en) | 2001-06-20 | 2003-07-08 | Bae Systems Information And Electronic Systems Integration, Inc | Acoustical array with multilayer substrate integrated circuits |
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US20100276794A1 (en) | 2010-11-04 |
US8067829B2 (en) | 2011-11-29 |
US20120015480A1 (en) | 2012-01-19 |
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