US7915742B2 - Determining the placement of semiconductor components on an integrated circuit - Google Patents
Determining the placement of semiconductor components on an integrated circuit Download PDFInfo
- Publication number
- US7915742B2 US7915742B2 US12/111,536 US11153608A US7915742B2 US 7915742 B2 US7915742 B2 US 7915742B2 US 11153608 A US11153608 A US 11153608A US 7915742 B2 US7915742 B2 US 7915742B2
- Authority
- US
- United States
- Prior art keywords
- radiation
- region
- standard cell
- regions
- placement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/111,536 US7915742B2 (en) | 2005-07-26 | 2008-04-29 | Determining the placement of semiconductor components on an integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/189,227 US7386824B2 (en) | 2005-07-26 | 2005-07-26 | Determining the placement of semiconductor components on an integrated circuit |
US12/111,536 US7915742B2 (en) | 2005-07-26 | 2008-04-29 | Determining the placement of semiconductor components on an integrated circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/189,227 Division US7386824B2 (en) | 2005-07-26 | 2005-07-26 | Determining the placement of semiconductor components on an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080230900A1 US20080230900A1 (en) | 2008-09-25 |
US7915742B2 true US7915742B2 (en) | 2011-03-29 |
Family
ID=37718169
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/189,227 Expired - Fee Related US7386824B2 (en) | 2005-07-26 | 2005-07-26 | Determining the placement of semiconductor components on an integrated circuit |
US12/111,536 Expired - Fee Related US7915742B2 (en) | 2005-07-26 | 2008-04-29 | Determining the placement of semiconductor components on an integrated circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/189,227 Expired - Fee Related US7386824B2 (en) | 2005-07-26 | 2005-07-26 | Determining the placement of semiconductor components on an integrated circuit |
Country Status (1)
Country | Link |
---|---|
US (2) | US7386824B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7550858B1 (en) * | 2005-07-19 | 2009-06-23 | Xilinx, Inc. | Random sequence generation using alpha particle emission |
US7386824B2 (en) * | 2005-07-26 | 2008-06-10 | Avago Technologies General Ip Pte Ltd | Determining the placement of semiconductor components on an integrated circuit |
US8199580B2 (en) * | 2008-02-25 | 2012-06-12 | The Board Of Trustees Of The University Of Illinois | Memory device that selectively stores holes |
US7958477B2 (en) * | 2008-03-12 | 2011-06-07 | International Business Machines Corporation | Structure, failure analysis tool and method of determining white bump location using failure analysis tool |
US8198133B2 (en) * | 2009-07-13 | 2012-06-12 | International Business Machines Corporation | Structures and methods to improve lead-free C4 interconnect reliability |
US9058454B1 (en) * | 2009-09-30 | 2015-06-16 | Xilinx, Inc. | Method and apparatus to reduce power segmentation overhead within an integrated circuit |
US8288177B2 (en) * | 2010-08-17 | 2012-10-16 | International Business Machines Corporation | SER testing for an IC chip using hot underfill |
US8914764B2 (en) * | 2012-06-18 | 2014-12-16 | International Business Machines Corporation | Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits |
CN111400988B (en) * | 2018-12-27 | 2023-08-22 | 北京忆芯科技有限公司 | Bump (Bump) pad layout method for integrated circuit chip |
Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4679171A (en) | 1985-02-07 | 1987-07-07 | Visic, Inc. | MOS/CMOS memory cell |
US4887236A (en) | 1987-05-29 | 1989-12-12 | Raytheon Company | Non-volatile, radiation-hard, random-access memory |
US5594262A (en) | 1994-06-06 | 1997-01-14 | The United States Of America As Represented By The Secretary Of The Air Force | Elevated temperature gallium arsenide field effect transistor with aluminum arsenide to aluminum gallium arsenide mole fractioned buffer layer |
US5886375A (en) | 1996-06-17 | 1999-03-23 | United Microelectronics Corporation | SRAM having improved soft-error immunity |
US5898223A (en) * | 1997-10-08 | 1999-04-27 | Lucent Technologies Inc. | Chip-on-chip IC packages |
US5999440A (en) | 1998-03-30 | 1999-12-07 | Lsi Logic Corporation | Embedded DRAM with noise-protecting substrate isolation well |
US6043429A (en) | 1997-05-08 | 2000-03-28 | Advanced Micro Devices, Inc. | Method of making flip chip packages |
US6329712B1 (en) | 1998-03-25 | 2001-12-11 | Micron Technology, Inc. | High density flip chip memory arrays |
US6436737B1 (en) | 2000-06-29 | 2002-08-20 | Sun Microsystems, Inc. | Method for reducing soft error rates in semiconductor devices |
US6483134B1 (en) | 1996-05-31 | 2002-11-19 | The United States Of America As Represented By The Secretary Of The Navy | Integrated circuits with immunity to single event effects |
US6504256B2 (en) * | 2001-01-30 | 2003-01-07 | Bae Systems Information And Electronic Systems Integration, Inc. | Insitu radiation protection of integrated circuits |
US6507511B1 (en) | 2001-10-02 | 2003-01-14 | International Business Machines Corporation | Secure and dense SRAM cells in EDRAM technology |
US6531759B2 (en) | 2001-02-06 | 2003-03-11 | International Business Machines Corporation | Alpha particle shield for integrated circuit |
US6693820B2 (en) | 2001-05-31 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Soft error resistant semiconductor memory device |
US20040063288A1 (en) | 2002-09-18 | 2004-04-01 | Danny Kenney | System and method for reducing soft error rate utilizing customized epitaxial layers |
US6724676B1 (en) | 2002-11-18 | 2004-04-20 | Infineon Technologies Ag | Soft error improvement for latches |
US6744661B1 (en) | 2002-05-15 | 2004-06-01 | Virage Logic Corp. | Radiation-hardened static memory cell using isolation technology |
US6762506B2 (en) * | 2002-01-07 | 2004-07-13 | Texas Instruments Incorporated | Assembly of semiconductor device and wiring substrate |
US6785847B1 (en) | 2000-08-03 | 2004-08-31 | International Business Machines Corporation | Soft error detection in high speed microprocessors |
US6891743B2 (en) | 2002-01-17 | 2005-05-10 | Renesas Technology Corp. | Semiconductor memory device having a capacitive plate to reduce soft errors |
US7081635B2 (en) * | 2003-04-23 | 2006-07-25 | Texas Instruments Incorporated | High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments |
US7221053B2 (en) * | 2005-03-21 | 2007-05-22 | Infineon Technologies Ag | Integrated device and electronic system |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US7386824B2 (en) * | 2005-07-26 | 2008-06-10 | Avago Technologies General Ip Pte Ltd | Determining the placement of semiconductor components on an integrated circuit |
US7451418B2 (en) * | 2005-07-26 | 2008-11-11 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size |
US7550856B2 (en) * | 2004-09-03 | 2009-06-23 | Texas Instruments Incorporated | Grooved substrates for uniform underfilling solder ball assembled electronic devices |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6873743B2 (en) | 2001-03-29 | 2005-03-29 | Fotonation Holdings, Llc | Method and apparatus for the automatic real-time detection and correction of red-eye defects in batches of digital images or in handheld appliances |
-
2005
- 2005-07-26 US US11/189,227 patent/US7386824B2/en not_active Expired - Fee Related
-
2008
- 2008-04-29 US US12/111,536 patent/US7915742B2/en not_active Expired - Fee Related
Patent Citations (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4679171A (en) | 1985-02-07 | 1987-07-07 | Visic, Inc. | MOS/CMOS memory cell |
US4887236A (en) | 1987-05-29 | 1989-12-12 | Raytheon Company | Non-volatile, radiation-hard, random-access memory |
US5594262A (en) | 1994-06-06 | 1997-01-14 | The United States Of America As Represented By The Secretary Of The Air Force | Elevated temperature gallium arsenide field effect transistor with aluminum arsenide to aluminum gallium arsenide mole fractioned buffer layer |
US6483134B1 (en) | 1996-05-31 | 2002-11-19 | The United States Of America As Represented By The Secretary Of The Navy | Integrated circuits with immunity to single event effects |
US5886375A (en) | 1996-06-17 | 1999-03-23 | United Microelectronics Corporation | SRAM having improved soft-error immunity |
US6043429A (en) | 1997-05-08 | 2000-03-28 | Advanced Micro Devices, Inc. | Method of making flip chip packages |
US5898223A (en) * | 1997-10-08 | 1999-04-27 | Lucent Technologies Inc. | Chip-on-chip IC packages |
US6548392B2 (en) * | 1998-03-25 | 2003-04-15 | Micron Technology, Inc. | Methods of a high density flip chip memory arrays |
US6329712B1 (en) | 1998-03-25 | 2001-12-11 | Micron Technology, Inc. | High density flip chip memory arrays |
US6538334B2 (en) | 1998-03-25 | 2003-03-25 | Micron Technology, Inc. | High density flip chip memory arrays |
US5999440A (en) | 1998-03-30 | 1999-12-07 | Lsi Logic Corporation | Embedded DRAM with noise-protecting substrate isolation well |
US6436737B1 (en) | 2000-06-29 | 2002-08-20 | Sun Microsystems, Inc. | Method for reducing soft error rates in semiconductor devices |
US6785847B1 (en) | 2000-08-03 | 2004-08-31 | International Business Machines Corporation | Soft error detection in high speed microprocessors |
US6504256B2 (en) * | 2001-01-30 | 2003-01-07 | Bae Systems Information And Electronic Systems Integration, Inc. | Insitu radiation protection of integrated circuits |
US6531759B2 (en) | 2001-02-06 | 2003-03-11 | International Business Machines Corporation | Alpha particle shield for integrated circuit |
US6693820B2 (en) | 2001-05-31 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Soft error resistant semiconductor memory device |
US6507511B1 (en) | 2001-10-02 | 2003-01-14 | International Business Machines Corporation | Secure and dense SRAM cells in EDRAM technology |
US6762506B2 (en) * | 2002-01-07 | 2004-07-13 | Texas Instruments Incorporated | Assembly of semiconductor device and wiring substrate |
US6891743B2 (en) | 2002-01-17 | 2005-05-10 | Renesas Technology Corp. | Semiconductor memory device having a capacitive plate to reduce soft errors |
US6744661B1 (en) | 2002-05-15 | 2004-06-01 | Virage Logic Corp. | Radiation-hardened static memory cell using isolation technology |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US20040063288A1 (en) | 2002-09-18 | 2004-04-01 | Danny Kenney | System and method for reducing soft error rate utilizing customized epitaxial layers |
US6724676B1 (en) | 2002-11-18 | 2004-04-20 | Infineon Technologies Ag | Soft error improvement for latches |
US7081635B2 (en) * | 2003-04-23 | 2006-07-25 | Texas Instruments Incorporated | High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments |
US7550856B2 (en) * | 2004-09-03 | 2009-06-23 | Texas Instruments Incorporated | Grooved substrates for uniform underfilling solder ball assembled electronic devices |
US7221053B2 (en) * | 2005-03-21 | 2007-05-22 | Infineon Technologies Ag | Integrated device and electronic system |
US7386824B2 (en) * | 2005-07-26 | 2008-06-10 | Avago Technologies General Ip Pte Ltd | Determining the placement of semiconductor components on an integrated circuit |
US7451418B2 (en) * | 2005-07-26 | 2008-11-11 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size |
Non-Patent Citations (1)
Title |
---|
Frye, Robert C., "Design Issues for Flip-Chip IC's in Multilayer Packages", IEEE 1997. |
Also Published As
Publication number | Publication date |
---|---|
US20080230900A1 (en) | 2008-09-25 |
US20070050599A1 (en) | 2007-03-01 |
US7386824B2 (en) | 2008-06-10 |
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