|Publication number||US7827131 B2|
|Application number||US 12/100,552|
|Publication date||2 Nov 2010|
|Priority date||22 Aug 2002|
|Also published as||US20090228416|
|Publication number||100552, 12100552, US 7827131 B2, US 7827131B2, US-B2-7827131, US7827131 B2, US7827131B2|
|Original Assignee||Knowm Tech, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (87), Non-Patent Citations (71), Referenced by (12), Classifications (12), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. patent application Ser. No. 10/748,546 filed Dec. 30, 2003, which was issued on Jun. 24, 2008 (U.S. Pat. No. 7,392,230) and claims priority as a Continuation-In-Part of U.S. patent application Ser. No. 10/226,191 filed Aug. 22, 2002 which was abandoned on Jun. 28, 2007.
The present invention generally relates to nanotechnology. The present invention also relates to neural networks and neural computing systems and methods thereof. The present invention also relates to physical neural networks, which may be constructed based on nanotechnology. The present invention also related to VLSI (Very Large Scale Integrated) analog neural network chips. The present invention also relates to nanoconductors, such as nanotubes and nanowires. The present invention also relates to methods and systems for forming a neural network.
Neural networks are computational systems that permit computers to essentially function in a manner analogous to that of the human brain. Neural networks do not utilize the traditional digital model of manipulating 0's and 1's. Instead, neural networks create connections between processing elements, which are equivalent to neurons of a human brain. Neural networks are thus based on various electronic circuits that are modeled on human nerve cells (i.e., neurons). Generally, a neural network is an information-processing network, which is inspired by the manner in which a human brain performs a particular task or function of interest. Computational or artificial neural networks are thus inspired by biological neural systems. The elementary building block of biological neural systems is of course the neuron, the modifiable connections between the neurons, and the topology of the network.
Biologically inspired artificial neural networks have opened up new possibilities to apply computation to areas that were previously thought to be the exclusive domain of human intelligence. Neural networks learn and remember in ways that resemble human processes. Areas that show the greatest promise for neural networks, such as pattern classification tasks such as speech and image recognition, are areas where conventional computers and data-processing systems have had the greatest difficulty.
In general, artificial neural networks are systems composed of many nonlinear computational elements operating in parallel and arranged in patterns reminiscent of biological neural nets. The computational elements, or nodes, are connected via variable weights that are typically adapted during use to improve performance. Thus, in solving a problem, neural net models can explore many competing hypothesis simultaneously using massively parallel nets composed of many computational elements connected by links with variable weights. In contrast, with conventional von Neumann computers, an algorithm must first be developed manually, and a program of instructions written and executed sequentially. In some applications, this has proved extremely difficult. This makes conventional computers unsuitable for many real-time problems. A description and examples of artificial neural networks are disclosed in the publication entitled “Artificial Neural Networks Technology,” by Dave Anderson and George McNeill, Aug. 10, 1992, a DACS (Data & Analysis Center for Software) State-of-the-Art Report under Contract Number F30602-89-C-0082, Rome Laboratory RL/C3C, Griffiss Air Force Base, New York, which is herein incorporated by reference.
In a neural network, “neuron-like” nodes can output a signal based on the sum of their inputs, the output being the result of an activation function. In a neural network, there exists a plurality of connections, which are electrically coupled among a plurality of neurons. The connections serve as communication bridges among of a plurality of neurons coupled thereto. A network of such neuron-like nodes has the ability to process information in a variety of useful ways. By adjusting the connection values between neurons in a network, one can match certain inputs with desired outputs.
One does not program a neural network. Instead, one “teaches” a neural network by examples. Of course, there are many variations. For instance, some networks do not require examples and extract information directly from the input data. The two variations are thus called supervised and unsupervised learning. Neural networks are currently used in applications such as noise filtering, face and voice recognition and pattern recognition. Neural networks can thus be utilized as an advanced mathematical technique for processing information.
Neural networks that have been developed to date are largely software-based. A true neural network (e.g., the human brain) is massively parallel (and therefore very fast computationally) and very adaptable. For example, half of a human brain can suffer a lesion early in its development and not seriously affect its performance. Software simulations are slow because during the learning phase a standard computer must serially calculate connection strengths. When the networks get larger (and therefore more powerful and useful), the computational time becomes enormous. For example, networks with 10,000 connections can easily overwhelm a computer. In comparison, the human brain has about 100 billion neurons, each of which can be connected to about 5,000 other neurons. On the other hand, if a network is trained to perform a specific task, perhaps taking many days or months to train, the final useful result can be etched onto a piece of silicon and also mass-produced.
A number of software simulations of neural networks have been developed. Because software simulations are performed on conventional sequential computers, however, they do not take advantage of the inherent parallelism of neural network architectures. Consequently, they are relatively slow. One frequently used measurement of the speed of a neural network processor is the number of interconnections it can perform per second. For example, the fastest software simulations available can perform up to about 18 million interconnects per second. Such speeds, however, currently require expensive super computers to achieve. Even so, 18 million interconnects per second is still too slow to perform many classes of pattern classification tasks in real time. These include radar target classifications, sonar target classification, automatic speaker identification, automatic speech recognition and electrocardiogram analysis, etc.
The implementation of neural network systems has lagged somewhat behind their theoretical potential due to the difficulties in building neural network hardware. This is primarily because of the large numbers of neurons and weighted connections required. The emulation of even of the simplest biological nervous systems would require neurons and connections numbering in the millions. Due to the difficulties in building such highly interconnected processors, the currently available neural network hardware systems have not approached this level of complexity. Another disadvantage of hardware systems is that they typically are often custom designed and built to implement one particular neural network architecture and are not easily, if at all, reconfigurable to implement different architectures. A true physical neural network chip, for example, has not yet been designed and successfully implemented.
The problem with pure hardware implementation of a neural network with technology as it exists today, is the inability to physically form a great number of connections and neurons. On-chip learning can exist, but the size of the network would be limited by digital processing methods and associated electronic circuitry. One of the difficulties in creating true physical neural networks lies in the highly complex manner in which a physical neural network must be designed and built. The present inventor believes that solutions to creating a true physical and artificial neural network lies in the use of nanotechnology and the implementation of a novel form of variable connections. The term “Nanotechnology” generally refers to nanometer-scale manufacturing processes, materials and devices, as associated with, for example, nanometer-scale lithography and nanometer-scale information storage. Nanometer-scale components find utility in a wide variety of fields, particularly in the fabrication of microelectrical and microelectromechanical systems (commonly referred to as “MEMS”). Microelectrical nano-sized components include transistors, resistors, capacitors and other nano-integrated circuit components. MEMS devices include, for example, micro-sensors, micro-actuators, micro-instruments, micro-optics, and the like.
In general, nanotechnology presents a solution to the problems faced in the rapid pace of computer chip design in recent years. According to Moore's law, the number of switches that can be produced on a computer chip has doubled every 18 months. Chips now can hold millions of transistors. However, it is becoming increasingly difficult to increase the number of elements on a chip using present technologies. At the present rate, in the next few years the theoretical limit of silicon based chips will be reached. Because the number of elements, which can be manufactured on a chip, determines the data storage and processing capabilities of microchips, new technologies are required which will allow for the development of higher performance chips.
Present chip technology is also limited in cases where wires must be crossed on a chip. For the most part, the design of a computer chip is limited to two dimensions. Each time a circuit is forced to cross another circuit, another layer must be added to the chip. This increases the cost and decreases the speed of the resulting chip. A number of alternatives to standard silicon based complementary metal oxide semiconductor (“CMOS”) devices have been proposed. The common goal is to produce logic devices on a nanometer scale. Such dimensions are more commonly associated with molecules than integrated circuits.
Integrated circuits and electrical components thereof, which can be produced at a molecular and nanometer scale, include devices such as carbon nanotubes and nanowires, which essentially are nanoscale conductors (“nanoconductors”). Nanoconductors are tiny conductive tubes (i.e., hollow) or wires (i.e., solid) with a very small size scale (e.g., 0.7 to 300 nanometers in diameter and up to 1 mm in length). Their structure and fabrication have been widely reported and are well known in the art. Carbon nanotubes, for example, exhibit a unique atomic arrangement, and possess useful physical properties such as one-dimensional electrical behavior, quantum conductance, and ballistic electron transport.
Carbon nanotubes are among the smallest dimensioned nanotube materials with a generally high aspect ratio and small diameter. High-quality single-walled carbon nanotubes can be grown as randomly oriented, needle-like or spaghetti-like tangled tubules. They can be grown by a number of fabrication methods, including chemical vapor deposition (CVD), laser ablation or electric arc growth. Carbon nanotubes can be grown on a substrate by catalytic decomposition of hydrocarbon containing precursors such as ethylene, methane, or benzene. Nucleation layers, such as thin coatings of Ni, Co, or Fe are often intentionally added onto the substrate surface in order to nucleate a multiplicity of isolated nanotubes. Carbon nanotubes can also be nucleated and grown on a substrate without a metal nucleating layer by using a precursor including one or more of these metal atoms. Semiconductor nanowires can be grown on substrates by similar processes.
Attempts have been made to construct electronic devices utilizing nano-sized electrical devices and components. For example, a molecular wire crossbar memory is disclosed in U.S. Pat. No. 6,128,214 entitled “Molecular Wire Crossbar Memory” dated Oct. 3, 2000 to Kuekes et al. Kuekes et al disclose a memory device that is constructed from crossbar arrays of nanowires sandwiching molecules that act as on/off switches. The device is formed from a plurality of nanometer-scale devices, each device comprising a junction formed by a pair of crossed wires where one wire crosses another and at least one connector species connects the pair of crossed wires in the junction. The connector species comprises a bi-stable molecular switch. The junction forms either a resistor or a diode or an asymmetric non-linear resistor. The junction has a state that is capable of being altered by application of a first voltage and sensed by the application of a second, non-destructive voltage. A series of related patents attempts to cover everything from molecular logic to how to chemically assemble these devices.
Such a molecular crossbar device has two general applications. The notion of transistors built from nanotubes and relying on nanotube properties is being pursued. Second, two wires can be selectively brought to a certain voltage and the resulting electrostatic force attracts them. When they touch, the Van der Walls force keeps them in contact with each other and a “bit” is stored. The connections in this apparatus can therefore be utilized for a standard (i.e., binary and serial) computer. The inventors of such a device thus desire to coax a nanoconductor into a binary storage media or a transistor. As it turns out, such a device is easier to utilize as a storage device.
The molecular wire crossbar memory device disclosed in Kuekes et al and related patents thereof simply comprise a digital storage medium that functions at a nano-sized level. Such a device, however, is not well-suited for non-linear and analog functions. Neural networks are non-linear in nature and naturally analog. A neural network is a very non-linear system, in that small changes to its input can create large changes in its output. To date, nanotechnology has not been applied to the creation of truly physical neural networks.
Based on the foregoing, the present inventor believes that a physical neural network, which incorporates nanotechnology, is a solution to the problems encountered by prior art neural network solutions. The present inventor has proposed a true physical neural network, which can be designed and constructed without relying on computer calculations for training, or relying on standard digital or analog memory to store connections strengths. Such a true physical neural was disclosed in U.S. patent application Ser. No. 10/095,273 entitled “A Physical Neural Network Design Incorporating Nanotechnology,” which was filed by the present inventor with the United States Patent & Trademark Office on Mar. 12, 2002.
The present inventor has also proposed a technique, including methods and systems thereof, for training a physical neural network formed utilizing nanotechnology, particularly for physical neural networks having multiple layers therein. Such a training technique was disclosed in U.S. patent application Ser. No. 10/162,524 entitled “Multi-Layer Training in a Physical Neural Network Formed Utilizing Nanotechnology,” which was filed with the United States Patent & Trademark Office on Jun. 5, 2002.
The present inventor has concluded that a need exists for a physical neural network, which can be implemented in the context of a semiconductor integrated circuit (i.e., a computer chip). Such a device, which can be referred to as a “physical neural network chip” or a “synapse chip” is thus disclosed herein.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is, therefore, one aspect of the present invention to provide a physical neural network.
It is therefore another aspect of the present to provide a physical neural network, which can be formed and implemented utilizing nanotechnology.
It is still another aspect of the present invention to provide a physical neural network, which can be formed from a plurality of interconnected nanoconnections or nanoconnectors.
It is a further aspect of the present invention to provide neuron like nodes, which can be formed and implemented utilizing nanotechnology.
It is also an aspect of the present invention to provide a physical neural network that can be formed from one or more neuron-like nodes.
It is yet a further aspect of the present invention to provide a physical neural network, which can be formed from a plurality of nanoconductors, such as, for example, nanowires and/or nanotubes.
It is still an additional aspect of the present invention to provide a physical neural network, which can be implemented physically in the form of a chip structure.
It is a further aspect of the present invention to provide a synapse chip, which implements a physical neural network.
It is another aspect of the present invention to provide methods and systems for the training of multiple connection networks located between neuron layers within one or more multi-layer physical neural networks thereof.
The above and other aspects can be achieved as is now described. A physical neural network synapse chip and a method for forming such a synapse chip are described herein. The synapse chip disclosed herein generally can be configured to include an input layer comprising a plurality of input electrodes and an output layer comprising a plurality of output electrodes, such that the output electrodes are located above or below the input electrodes. A gap is generally formed between the input layer and the output layer. A solution can then be provided which is prepared from a plurality of nanoconductors and a dielectric solvent. The solution is located within the gap, such that an electric field is applied across the gap from the input layer to the output layer to form nanoconnections of a physical neural network implemented by the synapse chip. Such a gap can thus be configured as an electrode gap. The input electrodes can be configured as an array of input electrodes, while the output electrodes can be configured as an array of output electrodes.
The nanoconductors form nanoconnections at one or more intersections between the input electrodes and the output electrodes in accordance with an increase in a strength or frequency of the electric field applied across the gap from the input layer to the output layer. Additionally, an insulating layer can be associated with the input layer, and another insulating layer associated with the output layer. The input layer can be formed from a plurality of parallel N-type semiconductors and the output layer formed from a plurality of parallel P-type semiconductors. Similarly, the input layer can be formed from a plurality of parallel P-type semiconductors and the output layer formed from a plurality of parallel N-type semiconductors. Thus, the nanoconnections can be strengthened or weakened respectively according to an increase or a decrease in strength of the electric field from input electrodes to output electrodes. As an electric field is applied across the electrode gap, nanoconnections thus form between the electrodes, precipitating from the solution to form electrical conduits between electrodes.
The accompanying figures, in which like reference numerals refer to identical or functionally-similar elements throughout the separate views and which are incorporated in and form part of the specification, further illustrate the present invention and, together with the detailed description of the invention, serve to explain the principles of the present invention.
The particular values and configurations discussed in these non-limiting examples can be varied and are cited merely to illustrate an embodiment of the present invention and are not intended to limit the scope of the invention.
The physical neural network described and disclosed herein is different from prior art forms of neural networks in that the disclosed physical neural network does not require computer calculations for training, nor is its architecture based on any current neural network hardware device. The design of the physical neural network of the present invention is actually quite “organic”. The physical neural network described herein is generally fast and adaptable, no matter how large such a physical neural network becomes. The physical neural network described herein can be referred to generically as a Knowm™. The terms “physical neural network” and “Knowm” can thus be utilized interchangeably to refer to the same device, network, or structure. The term “Knowm” can also refer to a semiconductor implementation, such as a physical neural network chip and/or synapse chip. Note that the terms “physical neural network chip” and “synapse chip” can also be utilized herein to refer generally to the same or analogous type of Knowm™ device
Network orders of magnitude larger than current VSLI neural networks can be built and trained with a standard computer. One consideration for a Knowm™ is that it must be large enough for its inherent parallelism to shine through. Because the connection strengths of such a physical neural network are dependant on the physical movement of nanoconnections thereof, the rate at which a small network can learn is generally very small and a comparable network simulation on a standard computer can be very fast. On the other hand, as the size of the network increases, the time to train the device does not change. Thus, even if the network takes a full second to change a connection value a small amount, if it does the same to a billion connections simultaneously, then its parallel nature begins to express itself.
A physical neural network (i.e., a Knowm™) must have two components to function properly. First, the physical neural network must have one or more neuron-like nodes that sum a signal and output a signal based on the amount of input signal received. Such a neuron-like node is generally non-linear in output. In other words, there should be a certain threshold for input signals, below which nothing is output and above which a constant or nearly constant output is generated or allowed to pass. This is a very basic requirement of standard software-based neural networks, and can be accomplished by an activation function. The second requirement of a physical neural network is the inclusion of a connection network composed of a plurality of interconnected connections (i.e., nanoconnections). Such a connection network is described in greater detail herein.
As illustrated in
In a Knowm™, the neuron-like node can be configured as a standard diode-based circuit, the diode being the most basic semiconductor electrical component, and the signal it sums can be a voltage. An example of such an arrangement of circuitry is illustrated in
Although a diode may not necessarily be utilized, its current versus voltage characteristics are non-linear when used with associated resistors and similar to the relationship depicted in
Thus, neuron 200 comprises a neuron-like node that may include a diode 206, which is labeled D1, and a resistor 204, which is labeled R2. Resistor 204 is connected to a ground 210 and an input 205 of diode 206. Additionally, a resistor 202, which is represented as a block and labeled R1 can be connected to input 205 of diode 206. Block 202 includes an input 212, which comprises an input to neuron 200. A resistor 208, which is labeled R3, is also connected to an output 214 of diode 206. Additionally, resistor 208 is coupled to ground 210. Diode 206 in a physical neural network is analogous to a neuron of a human brain, while an associated connection formed thereof as explained in greater detail herein, is analogous to a synapse of a human brain.
As depicted in
An amplifier may also replace diode 206 so that the output voltage immediately saturates at a reference threshold voltage, thus resembling a step function. R3 (i.e., resistor 208) functions generally as a bias for diode 206 (i.e., D1) and should generally be about 10 times larger than resistor 204 (i.e., R2). In the circuit configuration illustrated in
For example, carbon particles (e.g., granules or bearings) can be used for developing nanoconnections. The nanoconductors utilized to form a connection network can be formed as a plurality of nanoparticles. For example, each nanoconnection within a connection network can be formed from a chain of carbon nanoparticles. In “Self-assembled chains of graphitized carbon nanoparticles” by Bezryadin et al., Applied Physics Letters, Vol. 74, No. 18, pp. 2699-2701, May 3, 1999, which is incorporated herein by reference, a technique is reported, which permits the self-assembly of conducting nanoparticles into long continuous chains. The authors suggest that new approaches be developed in order to organize such nanoparticles into usefully electronic devices. Thus, nanoconductors that are utilized to form a physical neural network (i.e., Knowm™) can be formed from such nanoparticles. Note that as utilized herein, the term “nanoparticle” can be utilized interchangeably with the term “nanoconductor.” The term “nanoparticle” can refer simply to a particular type of nanoconductors, such as, for example, a carbon nanoparticle, or another type of nanoconductors, such as, for example, a carbon nanotube or carbon nanowire. Devices that conduct electricity and have dimensions on the order of nanometers can be referred to as nanoconductors.
It should be appreciated by those skilled in the art that the Bezyadin et al reference does not, of course, comprise limiting features of the present invention, nor does it teach, suggest nor anticipate a physical neural network. Rather, such a reference merely demonstrate recent advances in the carbon nanotechnology arts and how such advances can be adapted for use in association with the Knowm™-based system described herein. It can be further appreciated that a connection network as disclosed herein can be composed from a variety of different types of nanoconductors. For example, a connection network can be formed from a plurality of nanoconductors, including nanowires, nanotubes and/or nanoparticles. Note that such nanowires, nanotubes and/or nanoparticles, along with other types of nanoconductors can be formed from materials such as carbon or silicon. For example, carbon nanotubes may comprise a type of nanotube that can be utilized in accordance with the present invention.
As illustrated in
The connection network also comprises a plurality of interconnected nanoconnections, wherein each nanoconnection thereof is strengthened or weakened according to an application of an electric field. A connection network is not possible if built in one layer because the presence of one connection can alter the electric field so that other connections between adjacent electrodes could not be formed. Instead, such a connection network can be built in layers, so that each connection thereof can be formed without being influenced by field disturbances resulting from other connections. This can be seen in
Nanoconnections 572, 574, 576, 578, and 580 may comprise nanoconductors such as, for example, nanotubes and/or nanowires. Nanoconnections 572, 574, 576, 578, and 580 thus comprise one or more nanoconductors. Additionally, input lines 522, 524, 526, 528, and 530 are respectively coupled to a plurality of input lines 542, 544, 546, 548 and 550, which are in turn each respectively coupled to nanoconnections 582, 584, 586, 588, and 590. Thus, for example, input line 542 is connected to nanoconnections 582, while input line 544 is connected to nanoconnections 584. Similarly, input line 546 is connected to nanoconnections 586 and input line 548 is connected to nanoconnections 588. Additionally, input line 550 is connected to nanoconnections 590. Box 556 and 554 generally represent simply the output and are thus illustrated connected to outputs 562 and 568. In other words, outputs 556 and 554 respectively comprise outputs 562 and 568. The aforementioned input lines and associated components thereof actually comprise physical electronic components, including conducting input and output lines and physical nanoconnections, such as nanotubes and/or nanowires.
Thus, the number of layers 558 and 560 equals the number of desired outputs 562 and 568 from physical neural network 500. In the previous two figures, every input was potentially connected to every output, but many other configurations are possible. The connection network can be made of any electrically conducting material, although the physics of it requires that they be very small so that they will align with a practical voltage. Carbon nanotubes or any conductive nanowire can be implemented in accordance with the physical neural network described herein.
Such components can thus form connections between electrodes by the presence of an electric field. For example, the orientation and purification of carbon nanotubes has been demonstrated using ac electrophoresis in isopropyl alcohol, as indicated in “Orientation and purification of carbon nanotubes using ac electrophoresis” by Yamamoto et al., J. Phys. D: Applied Physics, 31 (1998), L34-36, which is incorporated herein by reference. Additionally, an electric-field assisted assembly technique used to position individual nanowires suspended in an electric medium between two electrodes defined lithographically on an SiO2 substrate is indicated in “Electric-field assisted assembly and alignment of metallic nanowires,” by Smith et al., Applied Physics Letters, Vol. 77, Num. 9, Aug. 28, 2000, and is also herein incorporated by reference.
Additionally, it has been reported that it is possible to fabricate deterministic wiring networks from single-walled carbon nanotubes (SWNTs) as indicated in “Self-Assembled, Deterministic Carbon Nanotube Wiring Networks” by Diehl, et al. in Angew. Chem. Int. Ed. 2002, 41. No. 2, which is also herein incorporated by reference. In addition, the publication “Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices” by Duan, et al., Nature, Vol. 409, Jan. 4, 2001, which is incorporated herein by reference, reports that an electric-field-directed assembly can be used to create highly integrated device arrays from nanowire building blocks. It should be appreciated by those skilled in the art these references do not comprise limiting features of the present invention, nor do such references teach or anticipate a physical neural network. Rather, such references are incorporated herein by reference to demonstrate recent advances in the carbon nanotechnology arts and how such advances can be adapted for use in association with the physical neural network described herein.
The only general requirements for the conducting material utilized to configure the nanoconductors are that such conducting material must conduct electricity, and a dipole should preferably be induced in the material when in the presence of an electric field. Alternatively, the nanoconductors utilized in association with the physical neural network described herein can be configured to include a permanent dipole that is produced by a chemical means, rather than a dipole that is induced by an electric field. Therefore, it should be appreciated by those skilled in the art that a connection network could also be configured from other conductive particles that are developed or found useful in the nanotechnology arts. For example, carbon particles (e.g., carbon “dust”) may also be used as nanoconductors in place of nanowires or nanotubes. Such particles may include bearings or granule-like particles.
A connection network can be constructed as follows: A voltage is applied across a gap that is filled with a mixture of nanowires and a “solvent”. This mixture could be made of many things. The only requirements are that the conducting wires must be suspended in the solvent, either dissolved or in some sort of suspension, free to move around; the electrical conductance of the substance must be less than the electrical conductance of the suspended conducting wire or particle; and the viscosity of the substance should not be too much so that the conducting wire cannot move when an electric field is applied.
The goal for such a connection network is to develop a network of connections of just the right values so as to satisfy the particular signal-processing requirement—exactly what a neural network does. Such a connection network can be constructed by applying a voltage across a space occupied by the mixture mentioned. To create the connection network, the input terminals can be selectively raised to a positive voltage while the output terminals can be selectively grounded. Alternatively, an electric field, either AC or DC can be applied across the terminals. Such an electric field can be, for example, a sinusoidal, square or a saw-tooth waveform. Thus, connections can gradually form between the inputs and outputs. The important requirement that makes the physical neural network of the present invention functional as a neural network is that the longer this electric field is applied across a connection gap, or the greater the frequency or amplitude of the field, the more nanotubes and/or nanowires and/or particles align and the stronger the connection thereof becomes.
The connections can either be initially formed and have random resistances or no connections may be formed at all. By initially forming random connections, it might be possible to teach the desired relationships faster, because the base connections do not have to be built up from scratch. Depending on the rate of connection decay, having initial random connections could prove faster, although not necessarily. The connection network can adapt itself to the requirements of a given situation regardless of the initial state of the connections. Either initial condition will work, as connections that are not used will “dissolve” back into the solution.
The resistance of the connection can be maintained or lowered by selective activations of the connection. In other words, if the connection is not used, it will fade away, analogous to the connections between neurons in a biological brain. The temperature of the solution can also be controlled so that the rate that connections fade away can be controlled. Additionally an electric field can be applied perpendicular to the connections to weaken them, or even erase them out altogether (i.e., as in clear, zero, or reformatting of a “disk”).
The nanoconnections may or may not be arranged in an orderly array pattern. The nanoconnections (e.g., nanotubes, nanowires, etc) of a physical neural network do not have to order themselves into neatly formed arrays. They simply float in the solution, or lie at the bottom of the gap, and more or less line up in the presence an electric field. Precise patterns are thus not necessary. In fact, neat and precise patterns may not be desired. Rather, due to the non-linear nature of neural networks, precise patterns could be a drawback rather than an advantage. In fact, it may be desirable that the connections themselves function as poor conductors, so that variable connections are formed thereof, overcoming simply an “on” and “off” structure, which is commonly associated with binary and serial networks and structures thereof.
Diode 616 is further coupled to a resistor 608, which is labeled R3, and first output 626. Additionally, resistor 608 is coupled to ground 602 and an input to an amplifier 618. An output from amplifier 618, as indicated at node B and dashed lines thereof, can be tied back to node A. A desired output 622 from amplifier 618 is coupled to amplifier 618 at node H. Diode 614 is coupled to a resistor 612 at node F. Note that resistor 612 is labeled R3. Node F is in turn coupled to an input of amplifier 620 and to second output 628 (i.e., Output 2). Diode 614 is also connected to second output 628 and an input to amplifier 620 at second output 628. Note that second output 628 is connected to the input to amplifier 620 at node F. An output from amplifier 620 is further coupled to node D, which in turn is connected to node C. A desired output 624, which is indicated by a dashed line in
The op-amp outputs and grounds the pre-diode junction (i.e., see node A) and causes a greater electric field across inputs 1 and 4 and the layer 1 output. This increased electric field (larger voltage drop) can cause the nanoconductors in the solution between the electrode junctions to align themselves, aggregate, and form a stronger connection between the 1 and 4 electrodes. Feedback can continue to be applied until output of physical neural network 600 matches the desired output. The same procedure can be applied to every output.
In accordance with the aforementioned example, assume that Output 1 was higher than the desired output (i.e., desired output 622). If this were the case, the op-amp output can be +V and the connection between inputs 1 and 4 and layer one output can be raised to +V. Columbic repulsions between the nanoconductors can force the connection apart, thereby weakening the connection. The feedback will then continue until the desired output is obtained. This is just one training mechanism. One can see that the training mechanism does not require any computations, because it is a simple feedback mechanism.
Such a training mechanism, however, may be implemented in many different forms. Basically, the connections in a connection network must be able to change in accordance with the feedback provided. In other words, the very general notion of connections being strengthened or connections being weakened in a physical system is the essence of a physical neural network (i.e., Knowm™). Thus, it can be appreciated that the training of such a physical neural network may not require a “CPU” to calculate connection values thereof. The Knowm™ can adapt itself. Complicated neural network solutions could be implemented very rapidly “on the fly”, much like a human brain adapts as it performs.
The physical neural network disclosed herein thus has a number of broad applications. The core concept of a Knowm™ however, is basic. The very basic idea that the connection values between electrode junctions by nanoconductors can be used in a neural network devise is all that required to develop an enormous number of possible configurations and applications thereof.
Another important feature of a physical neural network is the ability to form negative connections. This is an important feature that makes possible inhibitory effects useful in data processing. The basic idea is that the presence of one input can inhibit the effect of another input. In artificial neural networks as they currently exist, this is accomplished by multiplying the input by a negative connection value. Unfortunately, with a physical device, the connection may only take on zero or positive values under such a scenario.
In other words, either there can be a connection or no connection. A connection can simulate a negative connection by dedicating a particular connection to be negative, but one connection cannot begin positive and through a learning process change to a negative connection. In general, if starts positive, it can only go to zero. In essence, it is the idea of possessing a negative connection initially that results in the simulation, because this does not occur in a brain. Only one type of signal travels through axons/dendrites in a human brain. That signal is transferred into the flow of a neurotransmitter whose effect on the postsynaptic neuron can be either excitatory or inhibitory, depending on the neuron, thereby dedicating certain connections inhibitory and excitatory.
One method for solving this problem is to utilize two sets of connections for the same output, having one set represent the positive connections and the other set represent the negative connections. The output of these two layers can be compared, and the layer with the greater output will output either a high signal or a low signal, depending on the type of connection set (inhibitory or excitatory). This can be seen in
The output of inverting amplifier 736 can then be input to a NOR device 740. Similarly, an output 716 of layer 706 may be connected to resistor 714, transistor 733 and a first input 733 of an amplifier 728. A threshold voltage 760 is connected to a second input 737 of amplifier 728. Resistor 714 is generally coupled between ground 701 and first input 733 of amplifier 728. Note that first input 733 of amplifier 728 is also generally connected to an output 715 of layer 706. The output of amplifier 728 can in turn be provided to NOR device 740. The output from NOR device 740 is generally connected to a first input 745 of an amplifier 744. An actual output 750 can be taken from first input 745 to amplifier 744. A desired output 748 can be taken from a second input 747 to amplifier 744. The output from amplifier 744 is generally provided at node A, which in turn is connected to the input to transistor 720 and the input to transistor 724. Note that transistor 724 is generally coupled between ground 701 and first input 733 of amplifier 728. The second input 731 of amplifier 728 can produce a threshold voltage 760.
Layer 708 provides an output 717 that can be connected to resistor 716, transistor 725 and a first input 737 to an amplifier 732. Resistor 716 is generally coupled between ground 701 and the output 717 of layer 708. The first input 737 of amplifier 732 is also electrically connected to the output 717 of layer 708. A second input 735 to amplifier 732 may be tied to a threshold voltage 758. The output from amplifier 732 can in turn be fed to an inverting amplifier 738. The output from inverting amplifier 738 may in turn be provided to a NOR device 742. Similarly, an output 718 from layer 710 can be connected to a resistor 719, a transistor 728 and a first input 739 of an amplifier 734. Note that resistor 719 is generally coupled between node 701 and the output 719 of layer 710. A second input 741 of amplifier 734 may be coupled to a threshold voltage 762. The output from of NOR device 742 is generally connected to a first input 749 of an amplifier 746. A desired output 752 can be taken from a second input 751 of amplifier 746. An actual output 754 can be taken from first input 749 of amplifier 746. The output of amplifier 746 may be provided at node B, which in turn can be tied back to the respective inputs to transistors 725 and 728. Note that transistor 725 is generally coupled between ground 701 and the first input 737 of amplifier 732. Similarly, transistor 728 is generally connected between ground 701 and the first input 739 of amplifier 734.
Note that transistors 720, 724, 725 and/or 728 each can essentially function as a switch to ground. A transistor such as, for example, transistor 720, 724, 725 and/or 728 may comprise a field-effect transistor (FET) or another type of transistor, such as, for example, a single-electron transistor (SET). Single-electron transistor (SET) circuits are essential for hybrid circuits combining quantum SET devices with conventional electronic devices. Thus, SET devices and circuits may be adapted for use with the physical neural network of the present invention. This is particularly important because as circuit design rules begin to move into regions of the sub-100 nanometer scale, where circuit paths are only 0.001 of the thickness of a human hair, prior art device technologies will begin to fail, and current leakage in traditional transistors will become a problem. SET offers a solution at the quantum level, through the precise control of a small number of individual electrons.
Transistors such as transistors 720, 724, 725 and/or 728 can also be implemented as carbon nanotube transistors. An example of a carbon nanotube transistor is disclosed in U.S. Patent Application No. 2001/0023986A1 to Macevski, which is dated Sep. 27, 2001 and is entitled, “System and Method for Fabricating Logic Devices Comprising Carbon Nanotube Transistors.” U.S. Patent Application No. 2001/0023986A1 to Macevski is herein incorporated by reference. U.S. Patent Application No. 2001/0023986A1 does not teach or claim a physical neural network, but instead teaches the formation of a discrete carbon nanotube transistor. Thus, U.S. Patent Application No. 2001/0023986A1 is not considered a limiting feature of the present invention but is instead referenced herein to illustrate the use of a particular type of discrete transistor in the nanodomain.
A truth table for the output of circuit 700 is illustrated at block 780 in
For every desired output, two sets of connections are used. The output of a “two-diode” neuron can be fed into an op-amp (comparator). If the output that the op-amp receives is low when it should be high, the op-amp outputs a low signal. This low signal can cause the transistors (e.g., transistors 720 and/or 725) to saturate and ground out the pre-diode junction for the excitatory diode. This causes, like before, an increase in the voltage drop across those connections that need to increase their strength. Note that only those connections going to the excitatory diode are strengthened. Likewise, if the desired output were low when the actual output was high, the op-amp can output a high signal. This can cause the inhibitory transistor (e.g., an NPN transistor) to saturate and ground out the neuron junction of the inhibitory connections. Those connections going to the inhibitory diode can thereafter strengthen.
At all times during the learning process, a weak alternating electric field can be applied perpendicular to the connections. This can cause the connections to weaken by rotating the nanotube perpendicular to the connection direction. This perpendicular field is important because it can allow for a much higher degree of adaptation. To understand this, one must realize that the connections cannot (practically) keep getting stronger and stronger. By weakening those connections not contributing much to the desired output, we decrease the necessary strength of the needed connections and allow for more flexibility in continuous training. This perpendicular alternating voltage can be realized by the addition of two electrodes on the outer extremity of the connection set, such as plates sandwiching the connections (i.e., above and below). Other mechanisms, such as increasing the temperature of the nanotube suspension could also be used for such a purpose, although this method is perhaps a little less controllable or practical.
The circuit depicted in
Similarly, such an input array can includes a plurality of inputs 831, 832, 833, 834 and 835 which are respectively input to a plurality of layers 816, 817, 818, 819, 820, 821, 822, 823, 824 and 825. Thus, inputs 831 are connected to layers 816 and 817, while inputs 832 are coupled to layers 818 and 819. Additionally, inputs 833 are connected to layers 820 and 821. Inputs 834 are connected to layers 822 and 823. Finally, inputs 835 are connected to layers 824 and 825. Arrows 828 and 830 represent a continuation of the aforementioned connection network pattern. Those skilled in the art can appreciate, of course, that chip layout 800 is not intended to represent an exhaustive chip layout or to limit the scope of the invention. Many modifications and variations to chip layout 800 are possible in light of the teachings herein without departing from the scope of the present invention. It is contemplated that the use of a chip layout, such as chip layout 800, can involve a variety of components having different characteristics.
Preliminary calculations based on a maximum etching capability of 200 nm resolution indicated that over 600 million synapses could fit on an area of approximately 1 cm2. The smallest width that an electrode can possess is generally based on current lithography, and the resolution one requires for the nano-connection synapse. Such a width may of course change as the lithographic arts advance. This value is actually about 70 nm for state-of-the-art techniques currently. These calculations are of course extremely conservative, and are not considered a limiting feature of the present invention. Such calculations are based on an electrode width, separation, and gap of approximately 200 nm. For such a calculation, 25,000 perpendicular input electrodes may cross 25,000 output electrodes in a manner similar to that illustrated in
If such chips are stacked vertically, an untold number of synapses could be attained. This is two to three orders of magnitude greater than some of the most capable neural network chips out there today, chips that rely on standard methods to calculate synapse weights. Of course, the geometry of the chip could take on many different forms, and it is quite possible (based on a conservative lithography and chip layout) that many more synapses could fit in the same space. The training of a chip this size would take a fraction of the time of a comparably sized traditional chip utilizing traditional technology.
The training of such a chip is primarily based on two assumptions. First, the inherent parallelism of a physical neural network (i.e., a Knowm™) can permit all training sessions to occur simultaneously, no matter how large the associated connection network. Second, recent research has indicated that near perfect aligning of nanotubes can be accomplished in no more than 15 minutes utilizing practical voltages of about 5V. If one considers that the input data, arranged as a vector of binary “high's” and “low's” is presented to the Knowm™ simultaneously, and that all training vectors are presented one after the other in rapid succession (e.g., perhaps 100 MHz or more), then each connection would “see” a different frequency in direct proportion to the amount of time that its connection is required for accurate data processing (i.e., provided by a feedback mechanism). Thus, if it only takes approximately 15 minutes to attain an almost perfect state of alignment, then this amount of time would comprise the longest amount of time required to train, assuming that all of the training vectors are presented during that particular time period.
The solvent utilized can comprise a volatile liquid that can be confined or sealed and not exposed to air. For example, the solvent and the nanoconductors present within the resulting solution can be sandwiched between wafers of silicon or other materials. If the fluid has a melting point that is approximately at operating temperature, then the viscosity of the fluid could be controlled easily. Thus, if it is desired to lock the connection values into a particular state, the associated physical neural network (i.e., Knowm™) can be cooled slightly until the fluid freezes. The term “solvent” as utilized herein thus can include fluids such as for example, toluene, hexadecane, mineral oil, liquid crystals, etc. Note that the solution in which the nanoconductors (i.e., nanoconnections) are present should generally comprise a substance that does not conduct electricity and allows for the suspension of nanoparticles.
Thus, when the resistance between the electrodes is measured, the conductivity of the nanoconductors can be measured, not that of the solvent. The nanoconductors can be suspended in the solution or can alternately lie on the bottom surface of the connection gap. Note that the solvent described herein may also comprise liquid crystal media. It has been found that carbon nanotube alignment is possible by dissolving nanotubes in liquid crystal media, such that liquid crystals thereof align with an electric field and take the nanotubes and/or other nanoconductors with them (i.e., see “Liquid Crystals Allow Large-Scale Alignment of Carbon Nanotubes,” by Abraham Harte, CURJ, November, 2001, Vol. 1, No. 2, pp. 44-49, which is incorporated herein by reference). Alternatively, the solvent may also be provided in the form of a gas.
As illustrated thereafter at block 906, the nanoconductors must be suspended in the solvent, either dissolved or in a suspension of sorts, but generally free to move around, either in the solution or on the bottom surface of the gap. As depicted next at block 908, the electrical conductance of the solution must be less than the electrical conductance of the suspended nanoconductor(s).
Next, as illustrated at block 910, the viscosity of the substance should not be too much so that the nanoconductors cannot move when an electric field (e.g., voltage) is applied across the electrodes. Finally, as depicted at block 912, the resulting solution of the “solvent” and the nanoconductors is thus located within the connection gap.
Note that although a logical series of steps is illustrated in
As indicated at block 1008, the connections can either be initially formed and have random resistances or no connections will be formed at all. By forming initial random connections, it might be possible to teach the desired relationships faster, because the base connections do not have to be built up as much. Depending on the rate of connection decay, having initial random connections could prove to be a faster method, although not necessarily. A connection network will adapt itself to whatever is required regardless of the initial state of the connections. Thus, as indicated at block 1010, as the electric field is applied across the connection gap, the more the nonconductor(s) will align and the stronger the connection becomes. Connections (i.e., synapses) that are not used are dissolved back into the solution, as illustrated at block 1012. As illustrated at block 1014, the resistance of the connection can be maintained or lowered by selective activations of the connections. In other words, “if you do not use the connection, it will fade away,” much like the connections between neurons in a human brain.
The neurons in a human brain, although seemingly simple when viewed individually, interact in a complicated network that computes with both space and time. The most basic picture of a neuron, which is usually implemented in technology, is a summing device that adds up a signal. Actually, this statement can be made even more general by stating that a neuron adds up a signal in discrete units of time. In other words, every group of signals incident upon the neuron can be viewed as occurring in one moment in time. Summation thus occurs in a spatial manner. The only difference between one signal and another signal depends on where such signals originate. Unfortunately, this type of data processing excludes a large range of dynamic, varying situations that cannot necessarily be broken up into discrete units of time.
The example of speech recognition is a case in point. Speech occurs in the time domain. A word is understood as the temporal pronunciation of various phonemes. A sentence is composed of the temporal separation of varying words. Thoughts are composed of the temporal separation of varying sentences. Thus, for an individual to understand a spoken language at all, a phoneme, word, sentence or thought must exert some type of influence on another phoneme, word, sentence or thought. The most natural way that one sentence can exert any influence on another sentence, in the light of neural networks, is by a form of temporal summation. That is, a neuron “remembers” the signals it received in the past.
The human brain accomplishes this feat in an almost trivial manner. When a signal reaches a neuron, the neuron has an influx of ions rush through its membrane. The influx of ions contributes to an overall increase in the electrical potential of the neuron. Activation is achieved when the potential inside the cell reaches a certain threshold. The one caveat is that it takes time for the cell to pump out the ions, something that it does at a more or less constant rate. So, if another signal arrives before the neuron has time to pump out all of the ions, the second signal will add with the remnants of the first signal and achieve a raised potential greater than that which could have occurred with only the second signal. The first signal influences the second signal, which results in temporal summation.
Implementing this in a technological manner has proved difficult in the past. Any simulation would have to include a “memory” for the neuron. In a digital representation, this requires data to be stored for every neuron, and this memory would have to be accessed continually. In a computer simulation, one must discritize the incoming data, since operations (such as summations and learning) occur serially. That is, a computer can only do one thing at a time. Transformations of a signal from the time domain into the spatial domain require that time be broken up into discrete lengths, something that is not necessarily possible with real-time analog signals in which no point exists within a time-varying signal that is uninfluenced by another point.
A physical neural network, however, is generally not digital. A physical neural network is a massively parallel analog device. The fact that actual molecules (e.g., nanoconductors) must move around (in time) makes temporal summation a natural occurrence. This temporal summation is built into the nanoconnections. The easiest way to understand this is to view the multiplicity of nanoconnections as one connection with one input into a neuron-like node (Op-amp, Comparator, etc.). This can be seen in
Input 1102 can be provided by another physical neural network (i.e., Knowm™) to cause increased connection strength of nanoconnections 1104 over time. This input would most likely arrive in pulses, but could also be continuous. A constant or pulsed electric field perpendicular to the connections would serve to constantly erode the connections, so that only signals of a desired length or amplitude connection to form. Once the connection is formed, the voltage divider formed by nanoconnection 1104 and resistor 1106 can cause a voltage at node A in direct proportion to the strength of nanoconnections 1104. When the voltage at node A reaches a desired threshold, the amplifier (i.e., an op-amp and/or comparator), will output a high voltage (i.e., output 1114). The key to the temporal summation is that, just like a real neuron, it takes time for the electric field to breakdown the nanoconnections 1104, so that signals arriving close in time will contribute to the firing of the neuron (i.e., op-amp, comparator, etc.). Temporal summation has thus been achieved. The parameters of the temporal summation could be adjusted by the amplitude and frequency of the input signals and the perpendicular electric field.
The CPU 1211 can perform various processing and controlling functions, such as pattern recognition, including but not limited to speech and/or visual recognition based on the output signals from the physical neural network device 1222. The CPU 1211 is connected to a read-only memory (ROM) 1213, a random-access memory (RAM) 1214, a communication control unit 1215, a printer 1216, a display unit 1217, a keyboard 1218, an FFT (fast Fourier transform) unit 1221, a physical neural network device 1222 and a graphic reading unit 1224 through a bus line 1220 such as a data bus line. The bus line 1220 may comprise, for example, an ISA, EISA, or PCI bus.
The ROM 1213 is a read-only memory storing various programs or data used by the CPU 1211 for performing processing or controlling the learning process, and speech recognition of the physical neural network device 1222. The ROM 1213 may store programs for carrying out the learning process according to error back-propagation for the physical neural network device or code rows concerning, for example, 80 kinds of phonemes for performing speech recognition. The code rows concerning the phonemes can be utilized as second instructor signals and for recognizing phonemes from output signals of the neuron device network. Also, the ROM 1213 can store programs of a transformation system for recognizing speech from recognized phonemes and transforming the recognized speech into a writing (i.e., written form) represented by characters.
A predetermined program stored in the ROM 1213 can be downloaded and stored in the RAM 1214. RAM 1214 generally functions as a random access memory used as a working memory of the CPU 1211. In the RAM 1214, a vector row storing area can be provided for temporarily storing a power obtained at each point in time for each frequency of the speech signal analyzed by the FFT unit 1221. A value of the power for each frequency serves as a vector row input to a first input portion of the physical neural network device 1222. Further, in the case where characters or graphics are recognized in the physical neural network device, the image data read by the graphic reading unit 1224 are stored in the RAM 1214.
The communication control unit 1215 transmits and/or receives various data such as recognized speech data to and/or from another communication control unit through a communication network 1202 such as a telephone line network, an ISDN line, a LAN, or a personal computer communication network. Network 1202 may also comprise, for example, a telecommunications network, such as a wireless communications network. Communication hardware methods and systems thereof are well known in the art.
The printer 1216 can be provided with a laser printer, a bubble-type printer, a dot matrix printer, or the like, and prints contents of input data or the recognized speech. The display unit 1217 includes an image display portion such as a CRT display or a liquid crystal display, and a display control portion. The display unit 1217 can display the contents of the input data or the recognized speech as well as a direction of an operation required for speech recognition utilizing a graphical user interface (GUI).
The keyboard 1218 generally functions as an input unit for varying operating parameters or inputting setting conditions of the FFT unit 1221, or for inputting sentences. The keyboard 1218 is generally provided with a ten-key numeric pad for inputting numerical figures, character keys for inputting characters, and function keys for performing various functions. A mouse 1219 can be connected to the keyboard 1218 and serves as a pointing device.
A speech input unit 1223, such as a microphone can be connected to the FFT unit 1221. The FFT unit 1221 transforms analog speech data input from the voice input unit 1223 into digital data and carries out spectral analysis of the digital data by discrete Fourier transformation. By performing a spectral analysis using the FFT unit 1221, the vector row based on the powers of the respective frequencies are output at predetermined intervals of time. The FFT unit 1221 performs an analysis of time-series vector rows, which represent characteristics of the inputted speech. The vector rows output by the FET 1221 are stored in the vector row storing area in the RAM 1214. The graphic reading unit 224, provided with devices such as a CCD (Charged Coupled Device), can be used for reading images such as characters or graphics recorded on paper or the like. The image data read by the image-reading unit 1224 are stored in the RAM 1214. Note that an example of a pattern recognition apparatus, which can be modified for use with the physical neural network of the present invention, is disclosed in U.S. Pat. No. 6,026,358 to Tomabechi, Feb. 16, 2000, “Neural Network, A Method of Learning of a Neural Network and Phoneme Recognition Apparatus Utilizing a Neural Network.” U.S. Pat. No. 6,026,358 is incorporated herein by reference.
The implications of a physical neural network are tremendous. With existing lithography technology, many electrodes in an array such as depicted in
For example, such a chip can be constructed utilizing a standard computer processor in parallel with a large physical neural network or group of physical neural networks. A program can then be written such that the standard computer teaches the neural network to read, or create an association between words, which is precisely the same sort of task in which neural networks can be implemented. Once the physical neural network is able to read, it can be taught for example to “surf” the Internet and find material of any particular nature. A search engine can then be developed that does not search the Internet by “keywords”, but instead by meaning. This idea of an intelligent search engine has already been proposed for standard neural networks, but until now has been impractical because the network required was too big for a standard computer to simulate. The use of a physical neural network as disclosed herein now makes a truly intelligent search engine possible.
A physical neural network can be utilized in other applications, such as, for example, speech recognition and synthesis, visual and image identification, management of distributed systems, self-driving cars and filtering. Such applications have to some extent already been accomplished with standard neural networks, but are generally limited in expense, practicality and not very adaptable once implemented. The use of a physical neural network can permit such applications to become more powerful and adaptable. Indeed, anything that requires a bit more “intelligence” could incorporate a physical neural network. One of the primary advantages of a physical neural network is that such a device and applications thereof can be very inexpensive to manufacture, even with present technology. The lithographic techniques required for fabricating the electrodes and channels therebetween has already been perfected and implemented in industry.
Most problems in which a neural network solution is implemented are complex adaptive problems, which change in time. An example is weather prediction. The usefulness of a physical neural network is that it could handle the enormous network needed for such computations and adapt itself in real-time. An example wherein a physical neural network (i.e., Knowm™) can be particularly useful is the Personal Digital Assistant (PDA). PDA's are well known in the art. A physical neural network applied to a PDA device can be advantageous because the physical neural network can ideally function with a large network that could constantly adapt itself to the individual user without devouring too much computational time from the PDA processor. A physical neural network could also be implemented in many industrial applications, such as developing a real-time systems control to the manufacture of various components. This systems control can be adaptable and totally tailored to the particular application, as necessarily it must.
The training of multiple connection networks between neuron layers within a multi-layer neural network is an important feature of any neural network. The addition of neuron layers to a neural network can increase the ability of the network to create increasingly complex associations between inputs and outputs. Unfortunately, the addition of extra neuron layers in a network raises an important question: How does one optimize the connections within the hidden layers to produce the desired output? The neural network field was stalled for some time trying to answer this question until several parties simultaneously stumbled onto a computationally efficient solution, now referred to generally as “back-propagation” or “back-prop” for short. As the name implies, the solution involves a propagation of error back from the output to the input. Essentially, back-propagation amounts to efficiently determining the minimum of an error surface composed of n variables, where the variable n represents the number of connections.
Because back propagation is a computational algorithm, it does not make much sense physically. Another related question to ask is do the neurons in a human brain take a derivative? Do they “know” the result of a connection on another neuron? In other words, how does a neuron know what the desired output is if each neuron is an independent summing machine, only concerned with its own activation level and firing only when that activation is above threshold? What exactly can a neuron “know” about its environment?
Although this question is certainly open for debate, it is plausible to state that a neuron can only “know” if it has fired and whether or not its own connections have caused the firing of other neurons. This is precisely the Hebb hypothesis for learning: “if neuron A repeatedly takes part in firing neuron B, then the connection between neuron A and B strengthens so that neuron A can more efficiently take part in firing neuron B”. With this hypothesis, a technique can be derived to train a multi-layer physical neural network device without utilizing back-propagation or any other training algorithm, although the technique mirrors back-propagation in form. In fact, the resulting Knowm™ (i.e., physical neural network) is self-adaptable and does not require any calculations, derivates, or multiplication. The structure of a Knowm™ thus creates a situation in which learning simply takes place when a desired output is given. The description that follows is thus based on the use of a physical neural network (i.e., a Knowm™) and constituent nanoconnections thereof.
Amplifier 1312 thus functions as a neuron A and amplifier 1314 functions as a neuron B. The two neurons, A and B, respectively sum the signals provided at nodes 1303 and 1305 to provide output signals thereof at nodes 1319 and 1321 (i.e., respectively H1 and H2). Additionally, a switch 1308, which is labeled S1, is connected between nodes 1303 and 1319. Likewise, a switch 1322, which is also labeled S1, is connected between nodes 1305 and 1321. A resistor 1318 is coupled between an output of amplifier 1312 and node 1319. Similarly, a resistor 1320 is coupled between an output of amplifier 1314 and node 1321. Node 1319, which carries signal H1, is connected to a connection network 1328. Also, node 1321, which carries signal H2, is connected to connection network 1328. Note that connection network 1328 is labeled C2 in
A voltage Vt can be measured at an input 1335 to amplifier 1336 and an input 1337 to amplifier 1338. Amplifiers 1335 and 1338 can be respectively referred to as neurons C and D. An output from amplifier 1336 is connected to a NOT gate 1340, which provides a signal that is input to a NOR gate 1342. Additionally, amplifier 1338 provides a signal, which can be input to NOR gate 1342. Such a signal, which is output from amplifier 1338 can form an inhibitory signal, which is input to NOR gate 1342. Similarly, the output from amplifier 1336 can comprise an excitatory signal, which is generally input to NOT gate 1340. The excitatory and inhibitory signals respectively output from amplifiers 1336 and 1338 form an excitatory/inhibitory signal pair. NOR gate 1342 generates an output, which is input to an amplifier 1344 at input node 1347. A voltage Vd can be measured at input node 1346, which is coupled to amplifier 1344.
Thus, the signals H1 and H2, which are respectively carried at nodes 1319 and 1321 are generally propagated through connection network 1328, which is labeled C2, where the signals are again summed by the two neurons, C and D (i.e., amplifiers 1336 and 1338). The output of these two neurons therefore form an excitatory/inhibitory signal pair, which through the NOT gate 1340 and the NOR gate 1342 are transformed into a signal output O1 as indicated at output 1348. Note that signal output node O1 can be measured at input node 1347 of amplifier 1344. Amplifier 1344 also includes an output node 1349, which is coupled to node 1331 through a switch 1350, which is labeled S2. Output 1349 is further coupled to a NOT gate 1354, which in turn provides an output which is coupled to node 133 through a switch 1352, which is also labeled S2.
For inhibitory effects to occur, it may be necessary to implement twice as many outputs from the final connection network as actual outputs. Thus, every actual output represents a competition between a dedicated excitatory signal and inhibitory signal. The resistors labeled Rb (i.e., resistors 1330 and 1334) are generally very large, about 10 or 20 times as large as a nanoconnection. On the other hand, the resistors labeled Rf (i.e., resistors 1318 and 1320) may possess resistance values that are generally less than that of a nanoconnection, although such resistances can be altered to affect the overall behavior of the associated physical neural network. Vt represents the threshold voltage of the neuron while Vd represents the desired output. S1 and S2 are switches involved in the training of layers 1 and 2 respectively (i.e., L1 and L2, which are indicated respectively by brackets 1326 and 1356 in
For reasons that will become clear later, a typical training cycle can be described as follows: First an input vector can be presented at I1 and I2. For this particular example, such an input vector generally corresponds to only 4 possible combinations, 11, 10, 01 or 00. Actual applications would obviously require many more inputs, perhaps several thousand or more. One should be aware that the input vector does not have to occur in discrete time intervals, but can occur in real time. The inputs also need not necessarily be digital, but for the sake of simplicity in explaining this example, digital representations are helpful. While an input pattern is being presented, a corresponding output can be presented at Vd. Again, in this particular case there is generally only one output with only two corresponding possible outcomes, 1 or 0. The desired output also does not have to be presented in discrete units of time.
For learning to occur, the switches 1350 and 1352 (i.e., S2) can be closed, followed by switches 1308 and 1322 (i.e., S1). Both groupings of switches (S1 and S2) can then be opened and the cycle thereof repeated. Although only two layers L1 and L2 are illustrated in
For example, it can be assumed that no connections have formed within connection networks C1 or C2 and that inputs are being matched by desired outputs while the training wave is present. Since no connections are present, the voltage at neurons A, B, C and D are all zero and consequently all neurons output zero. One can quickly realize that whether the training wave is present or not, a voltage drop will not ensue across any connections other than those associated with the input connection network. The inputs, however, are being activated. Thus, each input is seeing a different frequency. Connections then form in connection network C1, with the value of the connections essentially being random.
Before a connection has been made, the voltage incident on neurons A and B are zero, but after a connection has formed, the voltage jumps up to almost two diode drops short of the input voltage. This is because the connections are forming a voltage divider with Rb, such that Rb (i.e., resistors 1310 and/or 1316) possesses a resistance very much larger than that of the nanoconnections. The two reasons for utilizing a large Rb is to minimize power consumption of the physical neural network during a normal operation thereof, and to lower the voltage drop across the connections so that learning only takes place when feedback is present. Fortunately, nanotube contact resistances are on the order of about 100 kΩ, or more, which allows for an Rb of a few MΩ or greater. Vt must be somewhere between two diode drops of the input voltage and the voltage produce by one nanoconnection in a voltage divider with Rb, the later being lower than the former.
Once connections have formed across C1 and grown sufficiently strong enough to activate neurons A and B, the connections across C2 will form in the same manner. Before continuing, however, it is important to determine what will occur to the nanoconnections of connection network 1302 (i.e., C1) after they grow strong enough to activate the first layer neurons. For the sake of example, assume that neuron A has been activated. When S1 is closed in the training wave, neuron A “sees” a feedback that is positive (i.e., activated). This locks the neuron into a state of activation, while S1 is closed. Because of the presence of diodes in connection network 1302 (i.e., C1), current can only flow from left to right in C1. This results in the lack of a voltage drop across the nanoconnections.
If another electric field is applied at this time to weaken the nanoconnections (e.g., perhaps a perpendicular field), the nanoconnections causing activation to the neuron can be weakened (i.e., the connections running from positive inputs to the neuron are weakened) This feedback will continue as long as the connections are strong enough to activate the neuron (i.e., and no connections have formed in the second layer). Nanoconnections can thus form and be maintained at or near the values of neuron activation. This process will also occur for ensuing layers until an actual network output is achieved.
Although the following explanation for the training of the newly formed (and random) connections may appear unusual with respect to
It can be appreciated from
Because of the presence of diodes within connection network 1328 (i.e., C2), there will be no voltage drop across those connections going to the excitatory neuron. There will be a voltage drop, however, across the nanoconnections extending from positive inputs of C2 to the inhibitory neuron (i.e., amplifier 1338). This can result in increases in inhibitory nanoconnections and a decrease in excitatory nanoconnections thereof (i.e., if a perpendicular field is present). This is exactly what is desired if the desired output is low when the actual output is high. A correspondingly opposite mechanism strengthens excitatory connections and weakens inhibitory connections if the desired output is high when the actual output is low. When the desired output matches the actual output, the training neurons output is undetermined and random, sometimes strengthening and sometimes weakening connections. This is not necessarily an undesirable result. By randomly activating both excitatory and inhibitory connections when the output matches the desired output, one prevents the connection values from degrading in the perpendicular electric field utilized in the training.
Thus far an explanation has been presented describing how the last layer of a physical neural network can in essence train itself to match the desired output. An important concept to realize, however, is that the activations coming from the previous layer are basically random. Thus, the last connection network tries to match essentially random activations with desired outputs. For reasons previously explained, the activations emanating from the previous layer do not remain the same, but fluctuate. There must then be some way to “tell” the layers preceding the output layer which particular outputs are required so that their activations are no longer random.
One must realize that neurons simply cannot fire unless a neuron in a preceding layer has fired. The activation of output neurons can be seen as being aided by the activations of neurons in previous layers. An output neuron “doesn't care” what neuron in the previous layer is activating it, so long as it is able to produce the desired output. If an output neuron must produce a high output, then there must be at least one neuron in the previous layer that both has a connection to it and is also activated, with the nanoconnection(s) being strong enough to allow for activation, either by itself or in combination with other activated neurons.
With this in mind, one can appreciate that the nanoconnections associated with pre-output layers can be modified. Again, by referring to
By thereafter closing S1, the previous layer neurons in essence “know” how much of their activation signal is being utilized. If their signal is being utilized by many neurons in a preceding layer, or by only a few with very strong nanoconnections, then the voltage that the neuron receives as feedback when S1 is closed decreases to a point below the threshold of the neuron. Exactly what point this occurs at is dependent on the value of Rf (i.e., resistors 1318 and/or 1320) As Rf becomes larger, less resistance is generally required to lower H1 or H2 to a point below the threshold of the neuron. Thus, based on the foregoing, those skilled in the art can appreciate how nanoconnections in layers preceding the output layer can modify themselves.
Referring again to
Although a detailed description of the process has been provided above, it is helpful to view the process from a generalized perspective. Again, assuming that no connections are present in any of the connection networks, assume that a series of input vectors are presented to the inputs of the network, and a series of output vectors are presented to the desired output, while the training wave is present. The training wave should be at a frequency equal or greater than the frequency at which input patterns are presented or otherwise the first few layers will not be trained and the network will be unable to learn the associations. The first layer connection network, analogous to C1 in
The connections can, just like C1, build up and hover around the threshold voltage for the succeeding neurons. This pattern of forming connections can generally occur until a signal is achieved at the output. Once a signal has been outputted, the feedback process begins and the training wave guides the feedback so that connections are modified strategically, from the output connection network to the input connection network, to achieve the desired output. The training is continued until the user is satisfied with the networks ability to correctly generate the correct output for a given input.
In evaluating a standard feed-forward multi-layer neural network, it will become apparent that that connections form between every neuron in one layer and every neuron in the next layer. Thus, neurons in adjacent layers are generally completely interconnected. When implementing this in a physical structure where connection strengths are stored as a physical connection, an architecture must be configured that allows for both total connectedness between layers and which also provides for the efficient use of space. In a physical neural network device (i.e., a “Knowm™ device), connections form between two conducting electrodes. The space between the electrodes can be filled with a nano-conductor/dielectric solvent mixture, which has been described previously herein. As an electric field is applied across the electrode gap, connections form between the electrodes. A basic method and structure for generating a large number of synapses on a small area substrate is illustrated in
The basic structure of a physical neural network device, such as a physical neural network chip and/or synapse chip, is depicted in
The input electrodes are indicated in
Applying a perpendicular electric field to the connection direction can weaken the connections by aligning the nanoconductors in a direction opposite to the current flow. With the design of
A perpendicular field is preferred across all connections that need to be weakened (i.e., positive inputs to positive outputs) and a parallel field across all connections that need to be strengthened (positive inputs to negative outputs). This can be easily accomplished by removing plates P1 and P2 and replacing them with conductors running parallel to the outputs, separated by an insulator so that current cannot flow, but a field can be produced. If the top layer conductor is formed from a N-type semiconductor and the bottom layer from a P-type semiconductor, a diode can be formed at the output so that current cannot flow backwards through the network as discussed earlier. This arrangement can be seen in
It can be appreciated by those skilled in the art, of course, that although only four input electrodes and four output electrodes are illustrated in
Other attempts at creating a neural-like processor require components to be placed precisely, with resolutions of a nanometer. This design only requires two perpendicular electrode arrays. The nanoconductors, such as nanotubes, are simply mixed with a dielectric solvent and a micro-drop of the solution is placed between the electrode arrays. Regarding the efficient use of space, even with electrode widths of 1 micron and spacing between electrodes of 2 microns, 11 million synapses or more could fit on 1 square centimeter. If one instead uses electrode widths of 100 nm, with spacing of 200 nm, approximately 1 billion synapses could fit on 1 cm2. Although one could not lower the electrode dimensions indefinitely without a considerable loss in connection resistance variation, it is conceivable that a 1 cm2 chip could hold over 4 billion synapses (50 nm electrodes and 100 nm spacing=4.4 billion synapes/cm2).
Some considerations about the construction of a chip such as that depicted in
Note that as utilized herein, the term “chip” generally refers to a type of integrated circuit, which is known in the art as a device comprising a number of connected circuit elements such as transistors and resistors, fabricated on a single chip of silicon crystal or other semiconductor material. Such chips have traditionally been manufactured as flat rectangular or square shaped objects. It can be appreciated, however, that such chips can be fabricated in a variety of shapes, including circular and spherical shapes in addition to traditional square, box or rectangular shaped integrated circuit chips. Thus, a synapse chip or physical neural network chip (i.e., a Knowm™ chip) can also be fabricated as a spherical integrated circuit.
An example of a spherical chip is disclosed in U.S. Pat. No. 6,245,630, “Spherical Shaped Semiconductor Circuit,” which issued to Akira Ishikawa of Ball Semiconductor, Inc. on Jun. 12, 2001. The spherical chip disclosed in U.S. Pat. No. 6,245,630, which is incorporated herein by reference, generally comprises a spherical shaped semiconductor integrated circuit (“ball”) and a system and method for manufacturing the same. Thus, the ball replaces the function of the flat, conventional chip. The physical dimensions of the ball allow it to adapt to many different manufacturing processes which otherwise could not be used. Furthermore, the assembly and mounting of the ball may facilitate efficient use of the semiconductor as well as circuit board space. Thus, a physical neural network chip and/or synapse chip as disclosed herein can be configured as such a ball-type chip rather than simply a rectangular or square shaped integrated circuit chip.
Based on the foregoing it can be appreciated that the present invention generally discloses a physical neural network synapse chip and a method for forming such a synapse chip. The synapse chip disclosed herein can be configured to include an input layer comprising a plurality of input electrodes and an output layer comprising a plurality of output electrodes, such that the output electrodes are located above or below the input electrodes. A gap is generally formed between the input layer and the output layer. A solution can then be provided which is prepared from a plurality of nanoconductors and a dielectric solvent. The solution is located within the gap, such that an electric field is applied across the gap from the input layer to the output layer to form nanoconnections of a physical neural network implemented by the synapse chip. Such a gap can thus be configured as an electrode gap. The input electrodes can be configured as an array of input electrodes, while the output electrodes can be configured as an array of output electrodes.
The nanoconductors can form nanoconnections at one or more intersections between the input electrodes and the output electrodes in accordance with an increase in strength of the electric field applied across the gap from the input layer to the output layer. Additionally, an insulating layer can be associated with the input layer, and another insulating layer associated with the output layer. The input layer can be formed from a plurality of parallel N-type semiconductors and the output layer formed from a plurality of parallel P-type semiconductors. Similarly, the input layer can be formed from a plurality of parallel P-type semiconductors and the output layer formed from a plurality of parallel N-type semiconductors. Thus, the nanoconnections can be strengthened or weakened respectively according to an increase or a decrease in strength of the electric field. As an electric field is applied across the electrode gap, nanoconnections thus form between the electrodes.
The most important aspect of the electrode arrays described herein is their geometry. Generally, any pattern of electrodes in which almost every input electrode is connected to every output electrode, separated by a small gap, is a valid base for a connection network. What makes this particular arrangement better than other arrangements is that it is very space-efficient. By allowing the connection to form vertically, a third dimension can be being utilized, consequently gaining enormous benefits in synapse density.
To understand just how space-efficient a Knowm™ chip utilizing connection formation in a third dimension could be, consider the NET talk network created by Terry Sejnowski and Charles Rosenberg in the mid 1980's. NET talk took the text-representation of a word and could output the phonemic representation, thereby providing a text-to-speech translation. The network had 203 inputs, 120 hidden neurons and 26 outputs, for a total of about 28 thousand synapses. Using electrode widths of 200 nm and spacing between electrodes of 400 nm, one could contain 28 thousand synapses on about 10160 μm2. In comparison, a conventional synapse including all of the weight storage resistors and switches, I0-I4 current mirrors, multiplier and sign switching circuitry takes up approximately 106◊113 μm or 11978 μm2 (e.g., see Adaptive Analog VLSI Neural Systems, Jabri, M. A et al., Chapman & Hall, London SE1 8HN, UK, p. 93, which is incorporated herein by reference). In other words, one could fit 28 thousand synapses in less than the area previously needed to store just one
Based on the foregoing it can be appreciated that the benefits of creating a neural network processor are great. The ability to implements as many as 1 billion synapses on 1 cm2 of surface substrate is a tremendous leap forward over prior art neural network technologies. Another innovation is the ability to mass-produce pre-trained, large-scale neural network chips. A physical neural network as disclosed herein does not have to be taught at all, but can instead be manufactured with the desired connections already in place. This is an important feature for consumer devices. For example, in most cellular telephones produced today, the ability to recognize rudimentary speech is available. One might, after pre-recording a voice, speak the word “Dave” and the cellular telephone can automatically call Dave after matching the word just spoken to a list of other pre-recorded names and thereafter pick the best match.
This is a rather rudimentary form of pattern recognition and could therefore be replaced by an exceedingly small Knowm™ synapse chip. For example, a Knowm™ chip can be taught at the factory to translate speech into text, thereby eliminating the need to pre-record ones voice for recognition tasks and instead relying on a more general speech recognition. Once the factory Knowm™ chip is trained, the synapse resistance values can be determined. With knowledge of what each synapse value needs to be, one can then design a perpendicular array chip so that the electrode widths create a cross-sectional area inversely proportional to the resistance of each synapse. In other words, the resistance of each connection is generally a function of the cross-sectional area of the connection between electrodes. By pre-forming the electrodes to certain specified widths, and then allowing the maximum number of connections to form at each electrode intersection, a physical neural network can be mass-produced. Such a configuration can allow a very general network function (e.g., voice or facial recognition) to be produced and sold to consumers, without the necessity of forcing the consumer to train the network.
A synapse or physical neural network chip could therefore be produced with certain ready-made abilities, such as voice or facial recognition. After installation, it is up to the designer to create a product that can then modify itself further and continue to adapt to the consumer. This could undoubtedly be an advantageous ability. Utilizing the example of the cellular telephone, the cellular telephone could in essence adapt its speech-recognition to the accent or manner of speech of the individual user. And all of this is possible because the Knowm™ synapses are so space-efficient. Networks with very powerful pattern recognition abilities could fit into a tiny fraction of a hand-held device, such as, for example, a wireless personal digital assistant and/or a cellular telephone.
The embodiments and examples set forth herein are presented to best explain the present invention and its practical application and to thereby enable those skilled in the art to make and utilize the invention. Those skilled in the art, however, will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. Other variations and modifications of the present invention will be apparent to those of skill in the art, and it is the intent of the appended claims that such variations and modifications be covered. The description as set forth is not intended to be exhaustive or to limit the scope of the invention. Many modifications and variations are possible in light of the above teaching without departing from the scope of the following claims. It is contemplated that the use of the present invention can involve components having different characteristics. It is intended that the scope of the present invention be defined by the claims appended hereto, giving full cognizance to equivalents in all respects.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US2707223||15 Jun 1949||26 Apr 1955||Hans E Hollmann||Electric resistor|
|US3222654||8 Sep 1961||7 Dec 1965||Widrow Bernard||Logic circuit and electrolytic memory element therefor|
|US3833894||20 Jun 1973||3 Sep 1974||Ibm||Organic memory device|
|US4802951||23 Dec 1987||7 Feb 1989||Trustees Of Boston University||Method for parallel fabrication of nanometer scale multi-device structures|
|US4926064||26 Jul 1989||15 May 1990||Syntonic Systems Inc.||Sleep refreshed memory for neural network|
|US4974146||6 May 1988||27 Nov 1990||Science Applications International Corporation||Array processor|
|US4988891||13 Sep 1989||29 Jan 1991||Mitsubishi Denki Kabushiki Kaisha||Semiconductor neural network including photosensitive coupling elements|
|US5315162||4 Oct 1991||24 May 1994||Hughes Aircraft Company||Electrochemical synapses for artificial neural networks|
|US5422983||19 Jul 1993||6 Jun 1995||Hughes Aircraft Company||Neural engine for emulating a neural network|
|US5475794||17 Aug 1994||12 Dec 1995||Mitsubishi Denki Kabushiki Kaisha||Semiconductor neural network and operating method thereof|
|US5589692||11 Apr 1995||31 Dec 1996||Yale University||Sub-nanoscale electronic systems and devices|
|US5649063||16 Dec 1994||15 Jul 1997||Lucent Technologies Inc.||Feedback process control using a neural network parameter estimator|
|US5670818||16 Aug 1994||23 Sep 1997||Actel Corporation||Electrically programmable antifuse|
|US5706404||30 Jul 1996||6 Jan 1998||U.S. Philips Corporation||Neural network using inhomogeneities in a medium as neurons and transmitting input signals in an unchannelled wave pattern through the medium|
|US5717832||7 Jun 1995||10 Feb 1998||International Business Machines Corporation||Neural semiconductor chip and neural networks incorporated therein|
|US5761115||30 May 1996||2 Jun 1998||Axon Technologies Corporation||Programmable metallization cell structure and method of making same|
|US5783840||7 Jun 1995||21 Jul 1998||Texas Instruments Incorporated||Universal quantum dot logic cell|
|US5812993||27 Feb 1997||22 Sep 1998||Technion Research And Development Foundation Ltd.||Digital hardware architecture for realizing neural network|
|US5896312||7 Jan 1998||20 Apr 1999||Axon Technologies Corporation||Programmable metallization cell structure and method of making same|
|US5904545||7 Jun 1995||18 May 1999||The Regents Of The University Of California||Apparatus for fabricating self-assembling microstructures|
|US5914893||7 Jan 1998||22 Jun 1999||Axon Technologies Corporation||Programmable metallization cell structure and method of making same|
|US5951881||22 Jul 1996||14 Sep 1999||President And Fellows Of Harvard College||Fabrication of small-scale cylindrical articles|
|US5978782||5 Jul 1996||2 Nov 1999||National Semiconductor Corporation||Neural network signal processor for magnetic storage channels|
|US6026358||21 Dec 1995||15 Feb 2000||Justsystem Corporation||Neural network, a method of learning of a neural network and phoneme recognition apparatus utilizing a neural network|
|US6084796||12 Jan 1999||4 Jul 2000||Axon Technologies Corporation||Programmable metallization cell structure and method of making same|
|US6128214||29 Mar 1999||3 Oct 2000||Hewlett-Packard||Molecular wire crossbar memory|
|US6245630||29 May 1998||12 Jun 2001||Ball Semiconductor, Inc.||Spherical shaped semiconductor integrated circuit|
|US6248529||20 May 1999||19 Jun 2001||Integrated Nano-Technologies, Llc||Method of chemically assembling nano-scale devices|
|US6256767||29 Mar 1999||3 Jul 2001||Hewlett-Packard Company||Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)|
|US6282530||9 Jun 1999||28 Aug 2001||Helios Semiconductor Inc.||Digital neural node|
|US6294450||1 Mar 2000||25 Sep 2001||Hewlett-Packard Company||Nanoscale patterning for the formation of extensive wires|
|US6314019||29 Mar 1999||6 Nov 2001||Hewlett-Packard Company||Molecular-wire crossbar interconnect (MWCI) for signal routing and communications|
|US6330553||9 Apr 1998||11 Dec 2001||Yamaha Hatsudoki Kabushiki Kaisha||Autonomic system for updating fuzzy neural network and control system using the fuzzy neural network|
|US6335291||24 Nov 1999||1 Jan 2002||Ball Semiconductor, Inc.||System and method for plasma etch on a spherical shaped device|
|US6339227||1 Feb 1999||15 Jan 2002||The Mitre Corporation||Monomolecular electronic device|
|US6359288||22 Apr 1998||19 Mar 2002||Massachusetts Institute Of Technology||Nanowire arrays|
|US6363369||11 Jun 1998||26 Mar 2002||University Of Southern California||Dynamic synapse for signal processing in neural networks|
|US6383923||22 Aug 2000||7 May 2002||Agere Systems Guardian Corp.||Article comprising vertically nano-interconnected circuit devices and method for making the same|
|US6389404||30 Dec 1998||14 May 2002||Irvine Sensors Corporation||Neural processing module with input architectures that make maximal use of a weighted synapse array|
|US6407443||20 Jun 2001||18 Jun 2002||Hewlett-Packard Company||Nanoscale patterning for the formation of extensive wires|
|US6418423||29 Jan 1999||9 Jul 2002||International Business Machines Corporation||Method and apparatus for executing neural network applications on a network of embedded devices|
|US6420092||13 Oct 1999||16 Jul 2002||Cheng-Jer Yang||Low dielectric constant nanotube|
|US6422450||15 Sep 2000||23 Jul 2002||University Of North Carolina, The Chapel||Nanotube-based high energy material and method|
|US6423583||3 Jan 2001||23 Jul 2002||International Business Machines Corporation||Methodology for electrically induced selective breakdown of nanotubes|
|US6424961||6 Dec 1999||23 Jul 2002||AYALA FRANCISCO JOSť||Adaptive neural learning system|
|US6426134||29 Jun 1999||30 Jul 2002||E. I. Du Pont De Nemours And Company||Single-wall carbon nanotube-polymer composites|
|US6536106||30 Jun 2000||25 Mar 2003||The Penn State Research Foundation||Electric field assisted assembly process|
|US6620346||11 Aug 1998||16 Sep 2003||Hydro-Quebec||Varistors based on nanocrystalline powders produced by mechanical grinding|
|US6798692||21 May 2002||28 Sep 2004||Axon Technologies Corporation||Programmable sub-surface aggregating metallization structure and method of making same|
|US6855329||20 Jan 1999||15 Feb 2005||Massachusetts Institute Of Technology||Surface coating spatially controlled patterns|
|US6889216||12 Mar 2002||3 May 2005||Knowm Tech, Llc||Physical neural network design incorporating nanotechnology|
|US6995649||31 Jan 2005||7 Feb 2006||Knowmtech, Llc||Variable resistor apparatus formed utilizing nanotechnology|
|US7028017||31 Jan 2005||11 Apr 2006||Knowm Tech, Llc||Temporal summation device utilizing nanotechnology|
|US7039619||31 Jan 2005||2 May 2006||Knowm Tech, Llc||Utilized nanotechnology apparatus using a neutral network, a solution and a connection gap|
|US7107252||31 Jan 2005||12 Sep 2006||Knowm Tech, Llc||Pattern recognition utilizing a nanotechnology-based neural network|
|US20010004471||18 Dec 2000||21 Jun 2001||Nec Corporation||Method of processing a nanotube|
|US20010023986||7 Feb 2001||27 Sep 2001||Vladimir Mancevski||System and method for fabricating logic devices comprising carbon nanotube transistors|
|US20010024633||15 Mar 2001||27 Sep 2001||Young-Hee Lee||Method of vertically aligning carbon nanotubes on substrates at low pressure and low pressure using thermal chemical vapor deposition with DC bias|
|US20010031900||16 Mar 2001||18 Oct 2001||Margrave John L.||Chemical derivatization of single-wall carbon nanotubes to facilitate solvation thereof; and use of derivatized nanotubes to form catalyst-containing seed materials for use in making carbon fibers|
|US20010041160||16 Mar 2001||15 Nov 2001||Margrave John L.||Chemical derivatization of single-wall carbon nanotubes to facilitate solvation thereof; and use of derivatized nanotubes to form catalyst-containing seed materials for use in making carbon fibers|
|US20010044114||17 May 2001||22 Nov 2001||Integrated Nano-Technologies, Llc.||Chemically assembled nano-scale circuit elements|
|US20020001905||27 Jun 2001||3 Jan 2002||Choi Won-Bong||Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof|
|US20020004028||16 Mar 2001||10 Jan 2002||Margrave John L.||Chemical derivatization of single-wall carbon nanotubes to facilitate solvation thereof; and use of derivatized nanotubes to form catalyst-containing seed materials for use in making carbon fibers|
|US20020004136||14 Jun 1999||10 Jan 2002||Yufei Gao||Carbon nanotubes on a substrate|
|US20020030205||9 Aug 1999||14 Mar 2002||Victor I. Varshavsky||Artificial neuron on the base of beta-driven threshold element|
|US20020075126||3 Oct 2001||20 Jun 2002||Reitz Hariklia Dris||Multiple reactant nozzles for a flowing reactor|
|US20020086124||16 Mar 2001||4 Jul 2002||Margrave John L.|
|US20020090468||30 Oct 2001||11 Jul 2002||Honda Giken Kogyo Kabushiki Kaisha||Method of manufacturing carbon nanotube|
|US20020102353||20 Mar 2002||1 Aug 2002||Electrovac, Fabrikation Electrotechnischer Spezialartikel Gesellschaft M.B.H.||Method of producing a nanotube layer on a substrate|
|US20030031438||25 Feb 2002||13 Feb 2003||Nobuyuki Kambe||Structures incorporating polymer-inorganic particle blends|
|US20030177450||12 Mar 2002||18 Sep 2003||Alex Nugent||Physical neural network design incorporating nanotechnology|
|US20030236760||5 Jun 2002||25 Dec 2003||Alex Nugent||Multi-layer training in a physical neural network formed utilizing nanotechnology|
|US20040039717||22 Aug 2002||26 Feb 2004||Alex Nugent||High-density synapse chip using nanoparticles|
|US20040150010||31 Jan 2003||5 Aug 2004||Greg Snider||Molecular-junction-nanowire-crossbar-based neural network|
|US20040153426||30 Dec 2003||5 Aug 2004||Alex Nugent||Physical neural network liquid state machine utilizing nanotechnology|
|US20040162796||30 Dec 2003||19 Aug 2004||Alex Nugent||Application of Hebbian and anti-Hebbian learning to nanotechnology-based physical neural networks|
|US20040193558||8 Dec 2003||30 Sep 2004||Alex Nugent||Adaptive neural network utilizing nanotechnology-based components|
|EP0989579A2||14 Sep 1999||29 Mar 2000||Lucent Technologies Inc.||Device comprising a carbon nanotube field emitter structure and process for forming device|
|EP1022764A1||19 Jan 2000||26 Jul 2000||Lucent Technologies Inc.||Article comprising enhanced nanotube emitter structure and process for fabricating article|
|EP1046613A2||25 Apr 2000||25 Oct 2000||Iljin Nanotech Co., Ltd.||Method of forming carbon nanotubes|
|EP1069206A2||3 Jul 2000||17 Jan 2001||Lucent Technologies Inc.||Nanoscale conductive connectors and method for making same|
|EP1100106A2||9 Oct 2000||16 May 2001||Lucent Technologies Inc.||Article comprising aligned nanowires and process for fabricating article|
|EP1115135A1||5 Jan 2001||11 Jul 2001||Samsung SDI Co., Ltd.||Method for fabricating triode-structure carbon nanotube field emitter array|
|EP1134304A2||15 Mar 2001||19 Sep 2001||Lee, Young-hee||Method of vertically aligning carbon nanotubes on substrates using thermal chemical vapor deposition with dc bias|
|RU2071126C1||Title not available|
|WO2000044094A1||20 Jan 2000||27 Jul 2000||University Of South Carolina||Molecular computer|
|WO2003017282A1||13 Aug 2001||27 Feb 2003||Advanced Micro Devices, Inc.||Memory cell|
|1||"A Basic Introduction to Neural Networks"; http://blizzard.gis.uiuc.edu/htmldocs/Neural/neural.html.|
|2||"A New Class of Nanostructures: Semiconducting Nanobelts Offer Potential for Nanosensors and Nanoelectronics," Mar. 12, 2001, http://www.sciencedaily.com/releases/2001/03/010309080953.htm.|
|3||"Collective Transport in Arrays of Small Metallic Dots" A. Alan Middleton, N.S. Wingreen, 1993, The American Physical Society, 0031-9007/93/71(19)/3198(4), pp. 3198 through 3201.|
|4||"Computational nanotechnology with carbon nanotubes and fullernes", Srivastava, D. Menon M. Kyeongjae Cho, NASA Ames Res. Center, Moffett Field, CA, Computing in Science & Engineering, Jul./Aug. 2001, vol. 3, Issue 4, pp. 42-55.|
|5||"Elements of Artificial Neural Networks" K. Mehrotra, C. K. Mohan, S. Ranka, 1997, MIT Press, pp. 116-135.|
|6||"Nanoparticles Get Wire," Sciencenow, Aug. 28, 1997, Dimes Institute, Delft University of Technology.|
|7||"Neural Networks," StatSoft, Inc., http://www.statsoftinc.com/textbook/stevnet.html.|
|8||"Quantum-Dot Arrays for Computation," ORNL Review vol. 34, No. 2, 2001, pp. 1-5 http://www.ornlgov/ORNLReview/v34-2-01/arrays.htm.|
|9||"Solid-State thin-film memistor for electronic neural networks", S. Thakoor, A. Moopenn, T. Daud, and A.P. Thakoor, Journal of Applied Physics-Mar. 15, 1990-vol. 67, Issue 6, pp. 3132-3135.|
|10||"Quantum-Dot Arrays for Computation," ORNL Review vol. 34, No. 2, 2001, pp. 1-5 http://www.ornlgov/ORNLReview/v34—2—01/arrays.htm.|
|11||"Solid-State thin-film memistor for electronic neural networks", S. Thakoor, A. Moopenn, T. Daud, and A.P. Thakoor, Journal of Applied Physics—Mar. 15, 1990—vol. 67, Issue 6, pp. 3132-3135.|
|12||Abraham Harte, "Liquid Crystals Allow Large-Scale Alignment of Carbon Nanotubes," CURJ (Caltech Undergraduate Research Journal), Nov. 2001, vol. 1, No. 2, pp. 44-49.|
|13||Andriotis et al., "Various bonding configurations of transition-metal atoms on carbon nanotubes: Their effect on contact resistance," Applied Physics Letters, vol. 76, No. 26, Jun. 26, 2000, pp. 3890-3892.|
|14||Avouris et al., "Carbon nanotubes: nanomechanics, manipulation, and electronic devices," Applied Surface Science 141 (1999), pp. 201-209.|
|15||Bandow et al., "Purification of Single-Wall Carbon Nanotubes by Microfiltration," J. Phys. Chem. B 1997, 101, pp. 8839-8842.|
|16||Bezryadin et al., "Evolution of avalanche conducting states in electroheological liquids," Physical Review E, vol. 59, No. 6, Jun. 1999, pp. 6896-6901.|
|17||Bezryadin et al., "Self-assembled chains of graphitized carbon nanoparticles," Applied Physics Letters, vol. 74, No. 18, May 3, 1999, pp. 2699-2701.|
|18||Bezryadin, A. et al., "Trapping Single Particle with Nanoelectrodes," Physics News Graphics, Sep. 1997.|
|19||Chen et al., "Aligning single-wall carbon nanotubes with an alternating-current electric field," Applied Physics Letters, vol. 78, No. 23, Jun. 4, 2001, pp. 3714-3716.|
|20||CMP Cientifica, "Nanotech: the tiny revolution"; CMP Cientifica, Nov. 2001.|
|21||Collins et al., "Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown," Science, vol. 292, pp. 706-709, Apr. 27, 2001.|
|22||Collins et al., "Nanotubes for Electronics," Scientific American, Dec. 2000, pp. 62-69.|
|23||Dave Anderson & George McNeill, "Artificial Neural Networks Technology," A DACS (Data & Analysis Center for Software) State-of-the-Art Report, Contract No. F30602-89-C-0082, ELIN: A011, Rome Laboratory RL/C3C, Griffiss Air Force Base, New York, Aug. 20, 1992.|
|24||David Rotman, "Molecular Memory, Replacing silicon with organic molecules could mean tiny supercomputers," Technology Review, May 2001, p. 46.|
|25||David W. Clark, "An Introduction to Neural Networks"; http://members.home.net/neuralnet/introtonn/index.htm.|
|26||Dejan Rakovic, "Hierarchical Neural Networks and Brainwaves: Towards a Theory of Consciousness," Brain & Consciousness: Proc. ECPD Workshop (ECPD, Belgrade, 1997), pp. 189-204.|
|27||*||Derycke, et al., "Carbon Nontube Inter- and Intramodular Logic Gates", 2001.|
|28||Diehl, et al., "Self-Assembled, Deterministic Carbon Nanotube Wiring Networks," Angew. Chem. Int. Ed. 2002, 41, No. 2; Received Oct. 22, 2001.|
|29||Duan et al., "Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices," Nature, vol. 409, Jan. 4, 2001, pp. 66-69.|
|30||Espejo, et al., "A 16◊16 Cellular Neural Network Chip for Connected Component Detection," Jun. 30, 1999; http://www.imse.cnm.csic.es/Chipcat/espejo/chip-2.pdf.|
|31||G. Pirio, et al., "Fabrication and electrical characteristics of carbon nanotube field emission microcathodes with an integrated gate electrode," Institute of Physics Publishing, Nanotechnology 13 (2002), pp. 1-4, Oct. 2, 2001.|
|32||Greg Mitchell, "Sub-50 nm Device Fabrication Strategies," Project No. 890-00, Cornell Nanofabrication Facility, Electronics-p. 90-91, National Nanofabrication Users Network.|
|33||Greg Mitchell, "Sub-50 nm Device Fabrication Strategies," Project No. 890-00, Cornell Nanofabrication Facility, Electronics—p. 90-91, National Nanofabrication Users Network.|
|34||Hermanson et al., "Dielectrophoretic Assembly of Electrically Functional Microwires from Nanoparticle Suspensions," Materials Science, vol. 294, No. 5544, Issue of Nov. 2, 2001, pp. 1082-1086.|
|35||Hone et al., "Electrical and thermal transport properties of magnetically aligned single wall carbon nanotube films," Applied Physics Letters, vol. 77, No. 5, Jul. 31, 2000, pp. 666-668.|
|36||J. Appenzeller et al., "Optimized contact configuration for the study of transport phenomena in ropes of single-wall carbon nanotubes," Applied Physics Letters, vol. 78, No. 21, pp. 3313-3315, May 21, 2001.|
|37||Jeong-Mi Moon et al., "High-Yield Purification Process of Singlewalled Carbon Nanotubes," J. Phys. Chem. B 2001, 105, pp. 5677-5681.|
|38||John G. Spooner, "Tiny tubes mean big chip advances," Cnet News.com, Tech News First, Apr. 26, 2001.|
|39||John-William DeClaris, "An Introduction to Neural Networks," http://www.ee.umd.edu/medlab/neural/nn1.html.|
|40||Landman et al., "Metal-Semiconductor Nanocontacts: Silicon Nanowires," Physical Review Letters, vol. 85, No. 9, Aug. 28, 2000.|
|41||Leslie Smith, "An Introduction to Neural Networks," Center for Cognitive and Computational Neuroscience, Dept. of Computing & Mathematics, University of Stirling, Oct. 25, 1996; http//www.cs.stir.ac.uk/~Iss/NNIntro/InvSlides.html.|
|42||Leslie Smith, "An Introduction to Neural Networks," Center for Cognitive and Computational Neuroscience, Dept. of Computing & Mathematics, University of Stirling, Oct. 25, 1996; http//www.cs.stir.ac.uk/˜Iss/NNIntro/InvSlides.html.|
|43||*||Liu et al., "Electric-Field-Induced Accumulation and Alignment of Carbon Nanotubes", 2002.|
|44||Liu et al., "Fullerene Pipes," Science, vol. 280, May 22, 1998, pp. 1253-1255.|
|45||Mark K. Anderson, "Mega Steps Toward the Nanochip," Wired News, Apr. 27, 2001.|
|46||Meyer et al., "Computational neural networks: a general purpose tool for nanotechnology," Abstract, 5th Foresight Conference on Molecular Nanotechnology; http://www.foresight.org/Conferences/MNT05/Abstracts/Meyeabst.html.|
|47||Niyogi et al., "Chromatographic Purification of Soluble Single-Walled Carbon Nanotubes (s-SWNTs)," J. Am. Chem. Soc 2001, 123, pp. 733-734, Received Jul. 10, 2000.|
|48||O'Connor, P. et al., "CMOS Preamplifier with High Lincarity and Ultra Low Noise for X-Ray Spectroscopy," IEEE Transactions on Nuclear Science, Jun. 3, 1997, vol. 44, Issue 3, pp. 318-325|
|49||*||ORNL, Quantum-Dot Arrays for Computation, 2001.|
|50||Osamu Fujita, "Statistical estimation of the number of hidden units for feedforward neural networks," Neural Networks 11 (1998), pp. 851-859.|
|51||Pati et al., "Neural Networks for Tactile Perception," Systems Research Center and Dept. of Electrical Engineering, University of Maryland and U.S Naval Research Laboratory. 1987; http://www.isr.umd.edu/TechReports/ISR/1987/TR-87-123/TR-87-123.phtml.|
|52||Pati et al., "Neural Networks for Tactile Perception," Systems Research Center and Dept. of Electrical Engineering, University of Maryland and U.S Naval Research Laboratory. 1987; http://www.isr.umd.edu/TechReports/ISR/1987/TR—87-123/TR—87-123.phtml.|
|53||Paulson, et al., "Tunable Resistance of a Carbon Nanotube-Graphite Interface," Science, vol. 290, Dec. 1, 2000, pp. 1742-1744.|
|54||Peter Weiss, "Circuitry in a Nanowire: Novel Growth Method May Transform Chips," Science News Online, vol. 161, No. 6; Feb. 9, 2002.|
|55||Press Release, "Nanowire-based electronics and optics comes one step closer," Eureka Alert, American Chemical Society; Feb. 1, 2002.|
|56||Press Release, "Toshiba Demonstrates Operation of Single-Electron Transistor Circuit at Room Temperature," Toshiba, Jan. 10, 2001.|
|57||Saito et al., "A 1M Synapse Self-Learning Digital Neural Network Chip," ISSCC, pp. 6.5-1 to 6.5-10, IEEE 1998.|
|58||Smith et al., "Electric-field assisted assembly and alignment of metallic nanowires," Applied Physics Letters, vol. 77, No. 9, Aug. 28, 2000, pp. 1399-1401.|
|59||Smith et al., "Structural anisotropy of magnetically aligned single wall carbone nanotube films," Applied Physics Letters, vol. 77, No. 5, Jul. 31, 2000, pp. 663-665.|
|60||Snow, E. S., et al., "Nanofabrication with Proximal Probes," Proceedings of the IEEE, Apr. 1997, vol. 85, No. 4, pp. 601-611.|
|61||*||Srivastava et al., "Computational Nanotechnology with Carbon Nanotubes and Fullerenes", 2001.|
|62||Stephen Jones, "Neural Networks and the Computation Brain or Maters relating to Artificial Intelligence," The Brain Project, http://www.culture.com.au/brain-proj/neur-net.htm.|
|63||Stephen Jones, "Neural Networks and the Computation Brain or Maters relating to Artificial Intelligence," The Brain Project, http://www.culture.com.au/brain—proj/neur—net.htm.|
|64||Tohji et al., "Purifying single walled nanotubes," Nature, vol. 383, Oct. 24, 1996, p. 679.|
|65||V. Derycke et al., "Carbon Nanotube Inter- and Intramolecular Logic Gates," American Chemical Society, Nano Letters, XXXX, vol. 0, No. 0, A-D.|
|66||Weeks et al., "High-pressure nanolithography using low-energy electrons from a scanning tunneling microscope," Institute of Physics Publishing, Nanotechnology 13 (2002), pp. 38-42; Dec. 12, 2001.|
|67||Wei et al., "Reliability and current carrying capacity of carbon nanotubes," Applied Physics Letters, vol. 79, No. 8, Aug. 20, 2001, pp. 1172-1174.|
|68||Westervelt et al., "Molecular Electronics," NSF Functional Nanostructures Grant 9871810, NSF Partnership in Nanotechnology Conference, Jan. 29-30, 2001; http://www.unix.oit.umass.edu/~nano/NewFiles/FN19-Harvard.pdf.|
|69||Westervelt et al., "Molecular Electronics," NSF Functional Nanostructures Grant 9871810, NSF Partnership in Nanotechnology Conference, Jan. 29-30, 2001; http://www.unix.oit.umass.edu/˜nano/NewFiles/FN19—Harvard.pdf.|
|70||X. Liu, et al., "Electric-Field-Induced Accumulation and Alignment of Carbon Nanotubes," 2002 Annual Conference on Electrical Insulation and Dielectric Phenomena; 2002 IEEE, pp. 31-34.|
|71||Yamamoto et al., "Orientation and purification of carbon nanotubes using ac electrophoresis," J. Phys. D: Appl. Phys 31 (1998) L34-L36.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8781983||21 Dec 2010||15 Jul 2014||Knowmtech, Llc||Framework for the evolution of electronic neural assemblies toward directed goals|
|US8918353||27 Aug 2012||23 Dec 2014||Knowmtech, Llc||Methods and systems for feature extraction|
|US8972316||14 Sep 2012||3 Mar 2015||Knowmtech, Llc||Extensible adaptive classification framework|
|US8983886||4 Sep 2012||17 Mar 2015||Knowmtech, Llc||Self-evolvable logic fabric|
|US8990136||13 Sep 2012||24 Mar 2015||Knowmtech, Llc||Methods and systems for fractal flow fabric|
|US9104975||15 Mar 2012||11 Aug 2015||Knowmtech, Llc||Memristor apparatus|
|US9152917||13 May 2014||6 Oct 2015||Knowmtech, Llc||Framework for the evolution of electronic neural assemblies toward directed goals|
|US9269043||3 Jun 2013||23 Feb 2016||Knowm Tech, Llc||Memristive neural processor utilizing anti-hebbian and hebbian technology|
|US9280748||13 Sep 2012||8 Mar 2016||Knowm Tech, Llc||Methods and systems for Anti-Hebbian and Hebbian (AHaH) feature extraction of surface manifolds using|
|US9378455||7 Feb 2013||28 Jun 2016||Yan M. Yufik||Systems and methods for a computer understanding multi modal data streams|
|US20110145179 *||3 Nov 2010||16 Jun 2011||Knowmtech, Llc||Framework for the organization of neural assemblies|
|US20110161268 *||30 Jun 2011||Knowmtech, Llc.||Framework for the evolution of electronic neural assemblies toward directed goals|
|U.S. Classification||706/33, 706/14|
|International Classification||G06F15/18, G06N3/06, G06N99/00, G06N3/063|
|Cooperative Classification||G06N3/063, B82Y10/00, G06N99/007|
|European Classification||B82Y10/00, G06N3/063, G06N99/00M|
|10 Apr 2008||AS||Assignment|
Owner name: KNOWMTECH, LLC, NEW MEXICO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NUGENT, ALEX;REEL/FRAME:020782/0873
Effective date: 20080407
|29 Apr 2014||FPAY||Fee payment|
Year of fee payment: 4