US7824964B2 - Method for fabricating package structures for optoelectronic devices - Google Patents
Method for fabricating package structures for optoelectronic devices Download PDFInfo
- Publication number
- US7824964B2 US7824964B2 US12/412,479 US41247909A US7824964B2 US 7824964 B2 US7824964 B2 US 7824964B2 US 41247909 A US41247909 A US 41247909A US 7824964 B2 US7824964 B2 US 7824964B2
- Authority
- US
- United States
- Prior art keywords
- substrate
- dielectric layer
- layer
- metal layer
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 142
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 239000011521 glass Substances 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- PWMJHFGIYXGLDX-UHFFFAOYSA-N C(C)O[Si](OCC)(OCC)OCC.[F] Chemical compound C(C)O[Si](OCC)(OCC)OCC.[F] PWMJHFGIYXGLDX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Definitions
- the invention relates to semiconductor package technology and in particular to a wafer-level chip scale package (WLCSP) structure for an optoelectronic device.
- WLCSP wafer-level chip scale package
- a digital imaging sensor typically includes an optoelectronic device chip, such as a charge-coupled device (CCD) image sensor chip and CMOS image sensor chip.
- CCD charge-coupled device
- Such image sensor chips may be packaged by an advanced package technology called “WLCSP”.
- WLCSP advanced package technology
- a wafer having micro-devices such as electronic devices, electromechanical devices or optoelectronic devices formed thereon, is first diced into multiple chips, and thereafter the chips are packaged.
- micro-devices may be packaged prior to dicing a wafer into multiple chips.
- FIGS. 1 and 2 are cross-sections of a pair of package structures for front and back-illuminated optoelectronic devices, respectively.
- the optoelectronic devices such as image sensors
- WLCSP WLCSP
- each package structure comprises a device chip disposed between a pair of glass substrates 100 and 110 .
- the device chip includes a device substrate 106 having micro-devices (not shown) thereon and a dielectric layer 104 formed on the device substrate 106 .
- An extension pad 105 is formed in the dielectric layer 104 , comprising a pad portion 103 and an extending portion 101 .
- the device chip is bonded with the glass substrate 100 through a glue layer 102 formed therebetween.
- the device chip is bonded with the glass substrate 110 through a glue layer 108 formed therebetween.
- a buffer layer 112 is disposed on the glass substrate 110 .
- a metal layer 114 covers the glass substrates 100 and 110 and directly contacts the sidewall of the pad portion 103 of the extension pad 105 .
- a protective layer 116 is disposed on the metal layer 114 , having an opening above the buffer layer 112 .
- a solder ball 118 is disposed in the opening to electrically connect the metal layer 114 , serving as a connection between internal and external circuits.
- each package structure also comprises a device chip disposed between a pair of glass substrates 200 and 212 .
- the device chip is reversely placed on a carrier substrate 208 , including a device substrate 204 and a dielectric layer 206 between the device and carrier substrates 204 and 208 .
- An extension pad 205 is formed in the dielectric layer 206 , comprising a pad portion 203 and an extending portion 201 .
- Glue layers 202 and 210 are employed to bond the device chip to the glass substrates 200 and 212 , respectively.
- a buffer layer 214 , a metal layer 216 , a protective layer 218 and a solder ball 220 are successively disposed on the glass substrate 212 .
- the contact area between the package metal layer 114 or 216 and the extension pad 105 or 205 is limited to the thickness of the pad portion 103 or 203 of the extension pad 105 or 205 . Accordingly, as the device size is reduced to increase device density, resistance of the extension pad 105 or 205 is increased and device performance reduced. Although the extending portion 101 or 201 of the extension pad 105 or 205 can reduce resistance thereof, the device size may be increased. Thus, difficulty in device size reduction is increased. Moreover, the small contact area between the metal layer and the extension pad is detrimental for adhesion between the metal layer and the extension pad.
- An embodiment of a package structure for an optoelectronic device comprises a device chip reversely disposed on a first substrate, comprising a second substrate and a first dielectric layer between the first and second substrates.
- the first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed.
- a metal layer is formed directly on the exposed surface of the pad and covers the second substrate.
- a protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate.
- a solder ball is disposed in the opening, electrically connecting to the metal layer.
- a package structure for an optoelectronic device comprises a device chip disposed between first and second substrates, comprising a third substrate adjacent to the first substrate and a first dielectric layer between the second and third substrate.
- the first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed.
- a metal layer is formed directly on the exposed surface of the pad and covers the second substrate.
- a protective layer covers the metal layer, having an opening exposing a portion of the metal layer on the second substrate.
- a solder ball is disposed in the opening, electrically connecting to the metal layer.
- An embodiment of a method for fabricating package structures for optoelectronic devices comprises reversely placing a device wafer on a first substrate, in which the device wafer comprises a second substrate and a first dielectric layer between the first and second substrates.
- the first dielectric layer comprises at least one pair of pads formed in the first dielectric layer.
- a first opening is formed in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads.
- a metal layer is formed directly on the exposed surface of each pad and covers the second substrate.
- a protective layer is formed on the metal layer and fills the first opening in the first dielectric layer.
- At least one second opening is formed in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate.
- a solder ball is formed in the second opening, electrically connecting to the metal layer.
- the device wafer and the first substrate are diced along the first opening in the first dielectric layer.
- Another embodiment of a method for fabricating package structures for optoelectronic devices comprises placing a device wafer between first and second substrates, in which the device wafer comprises a third substrate adjacent to the first substrate and a first dielectric layer between the second and third substrates.
- the first dielectric layer comprises at least one pair of pads formed in the first dielectric layer.
- a first opening is formed in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads.
- a metal layer is formed directly on the exposed surface of each pad and covers the second substrate.
- a protective layer is formed on the metal layer and fills the first opening in the first dielectric layer. At least one second opening is formed in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate.
- a solder ball is formed in the second opening, electrically connecting to the metal layer.
- the device wafer and the first substrate are diced along the first opening in the first dielectric layer.
- FIG. 1 is a cross section of a pair of package structures for front-illuminated optoelectronic devices
- FIG. 2 is a cross section of a pair of package structures for back-illuminated optoelectronic devices
- FIGS. 3A to 3G are cross sections of an embodiment of a method for fabricating package structures for front-illuminated optoelectronic devices
- FIG. 4 is a cross section of an embodiment of a pair of package structures for front-illuminated optoelectronic devices
- FIGS. 5A to 5G are cross sections of an embodiment of a method for fabricating package structures for back-illuminated optoelectronic devices
- FIG. 6 is a cross section of another embodiment of a pair of package structures for back-illuminated optoelectronic devices.
- FIG. 3G illustrates an embodiment of a pair of package structures for front-illuminated optoelectronic devices, such as image sensors.
- Each package structure comprises a device chip bonded with a substrate 306 through a glue layer 304 , such that the device chip is reversely disposed on the substrate 306 .
- the device chip may comprise a device substrate 300 a and a dielectric layer 302 between the substrate 306 and the device substrate 300 a .
- the dielectric layer 302 comprises a pad 301 formed in a corner of the dielectric layer 302 non-overlapping the device substrate 300 a , such that the surface 301 a and sidewall 301 b of the pad 301 are exposed.
- the pad 301 may have an extending portion (not shown) similar to the extension pad 105 or 205 shown in FIG. 1 or 2 .
- a dielectric layer 308 covers the reverse device substrate 300 a , serving as an insulator for subsequent metal formation.
- a metal layer 310 is formed directly on the exposed surface 301 a of the pad 301 and covers the dielectric layer 308 above the device substrate 300 a .
- a protective layer 312 covers the metal layer 310 , having an opening 310 a to expose a portion of the metal layer 310 on the device substrate 300 a . Moreover, the protective layer 312 further extends to the exposed sidewall 301 b of the pad 301 to prevent exposure of metal layer 310 and pad 301 to the air.
- a solder ball 314 is disposed in the opening 310 a , electrically connecting to the metal layer 310 .
- a dam 315 may be disposed between the substrate 306 and the dielectric layer 302 of the device chip to form a cavity 317 therebetween, as shown in FIG. 4 .
- FIGS. 3A to 3G are cross sections of an embodiment of a method for fabricating package structures for front-illuminated optoelectronic devices.
- an optoelectronic device wafer and a substrate 306 such as a glass substrate or other transparent substrate, is provided.
- the optoelectronic device wafer is reversely mounted on the substrate 306 through a glue layer 304 .
- the optoelectronic device wafer comprises a device substrate 300 , such as a silicon substrate or other semiconductor substrate and a dielectric layer 302 formed thereon.
- the device substrate 300 may contain a variety of elements, including, for example, transistors, resistors, and other semiconductor elements as are known in the art.
- the device substrate 300 may also contain conductive layers, insulating layers or isolation structures.
- the conductive layer typically comprises metal, such as copper, commonly used in the semiconductor industry for wiring discrete optoelectronic devices, such as image sensors, in and on the substrate. In order to simplify the diagram, a flat substrate is depicted.
- the dielectric layer 302 disposed on the device substrate 300 may comprise silicon oxide or other low k materials, such as fluorinated silicate glass (FSG), carbon doped oxide, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), or fluorine tetra-ethyl-orthosilicate (FTEOS). Additionally, in some embodiments, the dielectric layer 302 may comprise multiple layers. A plurality of pads is embedded in the dielectric layer 302 . In order to simplify the diagram, only a pair of pads 301 is depicted. In this embodiment, the pad 301 comprises metal, such as copper or aluminum. As mentioned above, the pad 301 may further comprise an extending portion (not shown).
- FSG fluorinated silicate glass
- MSQ methyl silsesquioxane
- HSQ hydrogen silsesquioxane
- FTEOS fluorine tetra-ethyl-orthosilicate
- FTEOS fluorine
- the device substrate 300 After mounting the device wafer on the substrate 306 , the device substrate 300 is reduced to a predetermined thickness by polishing or etching, to leave a portion of device substrate 300 a , as shown in FIG. 3B . In some embodiments, the device substrate 300 can be thinned prior to mounting the device wafer and the substrate 306 .
- the device substrate 300 a and the dielectric layer 302 are successively patterned to form an opening 305 therein, where the surfaces 301 a and sidewalls 301 b of the pair of pads 301 are exposed.
- a dielectric layer 308 is conformally deposited on the device substrate 300 a and the inner surface of the opening 305 by conventional deposition, such as chemical vapor deposition (CVD). Thereafter, the dielectric layer 308 on the surfaces 301 a and sidewalls 301 b of the pair of pads 301 are removed by etching, as shown in FIG. 3D .
- CVD chemical vapor deposition
- a metal layer 310 is conformally deposited on the dielectric layer 308 and the inner surface of the opening 305 by conventional deposition, such as CVD or sputtering, such that the metal layer 310 is formed directly on the surface 301 a of the pair of pads 301 . Thereafter, the metal layer 310 on the inner surface of the opening 305 in the dielectric layer 302 is removed by etching, as shown in 3 E. The remaining metal layer 310 serves an electronic connection between the pad 301 and the subsequent solder ball.
- a protective layer 312 such as a silicon nitride layer, is formed by, for example, CVD, to cover the metal layer 310 and fill the opening 305 in the dielectric layer 302 .
- a plurality of openings corresponding to pads 301 is formed in the protective layer 312 to expose the metal layer 310 .
- Solder balls 314 are correspondingly formed in the openings 310 a , such that each solder ball 314 is electrically connected to the corresponding pad 301 through the metal layer 310 .
- the device wafer and the substrate 306 are successively diced along the opening 305 in the dielectric layer 302 to form multiple device chips which are packaged.
- a dam 315 can be formed between the dielectric layer 302 and the substrate 306 to form a cavity 317 therebetween.
- the dam 315 may be bonded with the dielectric layer 302 and the substrate 306 through glue layers 304 a and 304 b , respectively, as shown in FIG. 4 .
- FIG. 5G illustrates another embodiment of a pair of package structures for back-illuminated optoelectronic devices.
- Each package structure comprises a device chip disposed between substrates 408 and 404 a , comprising a device substrate 400 adjacent to the substrate 408 and a dielectric layer 402 between the substrate 404 a and the device substrate 400 .
- the dielectric layer 402 comprises a pad 401 formed in a corner of the dielectric layer 402 non-overlapping the substrate 404 a , such that the surface 401 a and sidewall 401 b of the pad 401 are exposed.
- the pad 401 may have an extending portion (not shown) similar to the extension pad 105 or 205 shown in FIG. 1 or 2 .
- a dielectric layer 410 covers the substrate 404 a , serving as an insulator for subsequent metal formation.
- a metal layer 412 is formed directly on the exposed surface 401 a of the pad 401 and covers the dielectric layer 410 on the substrate 404 a .
- a protective layer 414 covers the metal layer 412 , having an opening 410 a to expose a portion of the metal layer 412 on the substrate 404 a .
- a solder ball 416 is disposed in the opening 410 a , electrically connecting to the metal layer 412 .
- a dam 415 may be disposed between the substrate 408 and the device substrate 400 of the device chip to form a cavity 417 therebetween, as shown in FIG. 6 .
- FIGS. 5A to 5G are cross sections of an embodiment of a method for fabricating package structures for back-illuminated optoelectronic devices.
- an optoelectronic device wafer and a carrier substrate 404 such as a silicon substrate, are provided.
- the optoelectronic device wafer is reversely mounted on the carrier substrate 404 .
- the optoelectronic device wafer comprises a device substrate 400 and a dielectric layer 402 formed thereon.
- the device substrate 400 such as a silicon substrate or other semiconductor substrate, is similar to the device substrate 300 shown in FIG. 3A .
- the dielectric layer 402 disposed on the device substrate 400 may comprise silicon oxide or other low k materials. Additionally, in some embodiments, the dielectric layer 402 may comprise multiple layers. A plurality of pads is embedded in the dielectric layer 402 . In order to simplify the diagram, only a pair of pads 401 is depicted. As mentioned above, the pad 401 may further comprise an extending portion (not shown). After mounting the device wafer on the carrier substrate 404 , the device substrate 400 is etched to form an opening 400 a between the pair of pads 401 .
- a substrate 408 such as a glass substrate or other transparent substrate is mounted on the device substrate 400 by coating a glue layer 406 on the device substrate 400 and filing in the opening 400 a , as shown in FIG. 5B .
- the carrier substrate 404 is reduced to a predetermined thickness by polishing or etching, to leave a portion of carrier substrate 404 a.
- the carrier substrate 404 a and the dielectric layer 402 are successively patterned to form an opening 405 therein, where the surfaces 401 a and sidewalls 401 b of the pair of pads 401 are exposed.
- a dielectric layer 410 is conformally deposited on the carrier substrate 404 a and the inner surface of the opening 405 by conventional deposition, such as CVD. Thereafter, the dielectric layer 410 on the surface 401 a and sidewall 401 b of the pair of pads 401 is removed by etching.
- a metal layer 412 is conformally deposited on the dielectric layer 410 and the inner surface of the opening 405 by conventional deposition, such as CVD or sputtering, such that the metal layer 412 is formed directly on the surface 401 a of the pair of pads 401 . Thereafter, the metal layer 412 on the inner surface of the opening 405 in the dielectric layer 402 is removed by etching. The remaining metal layer 412 electronically connects the pad 401 and the subsequent solder ball.
- a protective layer 414 such as a silicon nitride layer, is formed by, for example, CVD, to cover the metal layer 412 and fills the opening 405 in the dielectric layer 402 .
- a plurality of openings corresponding to pads 401 is formed in the protective layer 414 to expose the metal layer 412 .
- Solder balls 416 are correspondingly formed in the openings 410 a , such that each solder ball 416 is electrically connected to the corresponding pad 401 through the metal layer 412 .
- the device wafer and the substrate 408 are successively diced along the opening 405 in the dielectric layer 402 to form multiple device chips which are packaged.
- a dam 415 can be formed between the substrate 408 and the device substrate 400 to form a cavity 417 therebetween.
- the dam 415 may be bonded with the substrate 408 and the device substrate 400 through glue layers 406 a and 406 b , respectively, as shown in FIG. 6 .
- the package structure only one glass substrate is utilized for the package structure.
- package size can be reduced. Since the surface of the pad, acting as a contact area between the metal layer and the pad, can be increased using the sidewall of the pad, thus adhesion therebetween can be enhanced to increase device reliability. Moreover, since using the surface of the pad as the contact area is not limited by the thickness of the pad, the pad without extending portion can be used in the chip of the package structure, thereby increasing device density of the chip. Additionally, since the protective layer is extended to the sidewall of the pad to entirely cover the metal layer on the pad, the metal layer can be prevented from humidity damage after dicing the wafer into multiple chips. Thus, device reliability can be further increased.
Abstract
A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.
Description
This application is a Divisional of U.S. patent application Ser. No. 11/652,084, filed Jan. 11, 2007 now U.S. Pat. No. 7,566,944 and entitled “PACKAGE STRUCTURE FOR OPTOELECTRONIC DEVICE AND FABRICATION METHOD THEREOF”.
1. Field of the Invention
The invention relates to semiconductor package technology and in particular to a wafer-level chip scale package (WLCSP) structure for an optoelectronic device.
2. Description of the Related Art
Digital image devices are widely used in, for example, digital cameras, digital video recorders, cellular phones with image capture function, and monitors. A digital imaging sensor typically includes an optoelectronic device chip, such as a charge-coupled device (CCD) image sensor chip and CMOS image sensor chip.
Such image sensor chips may be packaged by an advanced package technology called “WLCSP”. In the traditional package technology, a wafer having micro-devices, such as electronic devices, electromechanical devices or optoelectronic devices formed thereon, is first diced into multiple chips, and thereafter the chips are packaged. Unlike the traditional package technology, according to WLCSP, micro-devices may be packaged prior to dicing a wafer into multiple chips.
In FIG. 2 , each package structure also comprises a device chip disposed between a pair of glass substrates 200 and 212. The device chip is reversely placed on a carrier substrate 208, including a device substrate 204 and a dielectric layer 206 between the device and carrier substrates 204 and 208. An extension pad 205 is formed in the dielectric layer 206, comprising a pad portion 203 and an extending portion 201. Glue layers 202 and 210 are employed to bond the device chip to the glass substrates 200 and 212, respectively. Similar to the package structure shown in FIG. 1 , a buffer layer 214, a metal layer 216, a protective layer 218 and a solder ball 220 are successively disposed on the glass substrate 212.
In such package structures, the contact area between the package metal layer 114 or 216 and the extension pad 105 or 205 is limited to the thickness of the pad portion 103 or 203 of the extension pad 105 or 205. Accordingly, as the device size is reduced to increase device density, resistance of the extension pad 105 or 205 is increased and device performance reduced. Although the extending portion 101 or 201 of the extension pad 105 or 205 can reduce resistance thereof, the device size may be increased. Thus, difficulty in device size reduction is increased. Moreover, the small contact area between the metal layer and the extension pad is detrimental for adhesion between the metal layer and the extension pad.
Thus, there exists a need for a package structure for an optoelectronic device with increased contact area between the pad and package metal layer.
A detailed description is given in the following embodiments with reference to the accompanying drawings. Package structures for optoelectronic devices and methods for fabricating the same are provided. An embodiment of a package structure for an optoelectronic device comprises a device chip reversely disposed on a first substrate, comprising a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer.
Another embodiment of a package structure for an optoelectronic device comprises a device chip disposed between first and second substrates, comprising a third substrate adjacent to the first substrate and a first dielectric layer between the second and third substrate. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening exposing a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer.
An embodiment of a method for fabricating package structures for optoelectronic devices comprises reversely placing a device wafer on a first substrate, in which the device wafer comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises at least one pair of pads formed in the first dielectric layer. A first opening is formed in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads. A metal layer is formed directly on the exposed surface of each pad and covers the second substrate. A protective layer is formed on the metal layer and fills the first opening in the first dielectric layer. At least one second opening is formed in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate. A solder ball is formed in the second opening, electrically connecting to the metal layer. The device wafer and the first substrate are diced along the first opening in the first dielectric layer.
Another embodiment of a method for fabricating package structures for optoelectronic devices comprises placing a device wafer between first and second substrates, in which the device wafer comprises a third substrate adjacent to the first substrate and a first dielectric layer between the second and third substrates. The first dielectric layer comprises at least one pair of pads formed in the first dielectric layer. A first opening is formed in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads. A metal layer is formed directly on the exposed surface of each pad and covers the second substrate. A protective layer is formed on the metal layer and fills the first opening in the first dielectric layer. At least one second opening is formed in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate. A solder ball is formed in the second opening, electrically connecting to the metal layer. The device wafer and the first substrate are diced along the first opening in the first dielectric layer.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is provided for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The invention relates to a package structure for an optoelectronic device and a method for fabricating the same. FIG. 3G illustrates an embodiment of a pair of package structures for front-illuminated optoelectronic devices, such as image sensors. Each package structure comprises a device chip bonded with a substrate 306 through a glue layer 304, such that the device chip is reversely disposed on the substrate 306. The device chip may comprise a device substrate 300 a and a dielectric layer 302 between the substrate 306 and the device substrate 300 a. In this embodiment, the dielectric layer 302 comprises a pad 301 formed in a corner of the dielectric layer 302 non-overlapping the device substrate 300 a, such that the surface 301 a and sidewall 301 b of the pad 301 are exposed. In some embodiments, the pad 301 may have an extending portion (not shown) similar to the extension pad 105 or 205 shown in FIG. 1 or 2.
A dielectric layer 308 covers the reverse device substrate 300 a, serving as an insulator for subsequent metal formation. A metal layer 310 is formed directly on the exposed surface 301 a of the pad 301 and covers the dielectric layer 308 above the device substrate 300 a. A protective layer 312 covers the metal layer 310, having an opening 310 a to expose a portion of the metal layer 310 on the device substrate 300 a. Moreover, the protective layer 312 further extends to the exposed sidewall 301 b of the pad 301 to prevent exposure of metal layer 310 and pad 301 to the air. A solder ball 314 is disposed in the opening 310 a, electrically connecting to the metal layer 310.
In some embodiments, a dam 315 may be disposed between the substrate 306 and the dielectric layer 302 of the device chip to form a cavity 317 therebetween, as shown in FIG. 4 .
The dielectric layer 302 disposed on the device substrate 300 may comprise silicon oxide or other low k materials, such as fluorinated silicate glass (FSG), carbon doped oxide, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), or fluorine tetra-ethyl-orthosilicate (FTEOS). Additionally, in some embodiments, the dielectric layer 302 may comprise multiple layers. A plurality of pads is embedded in the dielectric layer 302. In order to simplify the diagram, only a pair of pads 301 is depicted. In this embodiment, the pad 301 comprises metal, such as copper or aluminum. As mentioned above, the pad 301 may further comprise an extending portion (not shown). After mounting the device wafer on the substrate 306, the device substrate 300 is reduced to a predetermined thickness by polishing or etching, to leave a portion of device substrate 300 a, as shown in FIG. 3B . In some embodiments, the device substrate 300 can be thinned prior to mounting the device wafer and the substrate 306.
As shown in FIG. 3C , the device substrate 300 a and the dielectric layer 302 are successively patterned to form an opening 305 therein, where the surfaces 301 a and sidewalls 301 b of the pair of pads 301 are exposed.
Next, a dielectric layer 308 is conformally deposited on the device substrate 300 a and the inner surface of the opening 305 by conventional deposition, such as chemical vapor deposition (CVD). Thereafter, the dielectric layer 308 on the surfaces 301 a and sidewalls 301 b of the pair of pads 301 are removed by etching, as shown in FIG. 3D .
A metal layer 310 is conformally deposited on the dielectric layer 308 and the inner surface of the opening 305 by conventional deposition, such as CVD or sputtering, such that the metal layer 310 is formed directly on the surface 301 a of the pair of pads 301. Thereafter, the metal layer 310 on the inner surface of the opening 305 in the dielectric layer 302 is removed by etching, as shown in 3E. The remaining metal layer 310 serves an electronic connection between the pad 301 and the subsequent solder ball.
As shown in FIG. 3F , a protective layer 312, such as a silicon nitride layer, is formed by, for example, CVD, to cover the metal layer 310 and fill the opening 305 in the dielectric layer 302.
Thereafter, a plurality of openings corresponding to pads 301 is formed in the protective layer 312 to expose the metal layer 310. In order to simplify the diagram, only two openings 310 a are depicted, as shown in FIG. 3G . Solder balls 314 are correspondingly formed in the openings 310 a, such that each solder ball 314 is electrically connected to the corresponding pad 301 through the metal layer 310. After formation of solder balls 314, the device wafer and the substrate 306 are successively diced along the opening 305 in the dielectric layer 302 to form multiple device chips which are packaged. In some embodiments, a dam 315 can be formed between the dielectric layer 302 and the substrate 306 to form a cavity 317 therebetween. The dam 315 may be bonded with the dielectric layer 302 and the substrate 306 through glue layers 304 a and 304 b, respectively, as shown in FIG. 4 .
A dielectric layer 410 covers the substrate 404 a, serving as an insulator for subsequent metal formation. A metal layer 412 is formed directly on the exposed surface 401 a of the pad 401 and covers the dielectric layer 410 on the substrate 404 a. A protective layer 414 covers the metal layer 412, having an opening 410 a to expose a portion of the metal layer 412 on the substrate 404 a. A solder ball 416 is disposed in the opening 410 a, electrically connecting to the metal layer 412.
In some embodiments, a dam 415 may be disposed between the substrate 408 and the device substrate 400 of the device chip to form a cavity 417 therebetween, as shown in FIG. 6 .
The dielectric layer 402 disposed on the device substrate 400 may comprise silicon oxide or other low k materials. Additionally, in some embodiments, the dielectric layer 402 may comprise multiple layers. A plurality of pads is embedded in the dielectric layer 402. In order to simplify the diagram, only a pair of pads 401 is depicted. As mentioned above, the pad 401 may further comprise an extending portion (not shown). After mounting the device wafer on the carrier substrate 404, the device substrate 400 is etched to form an opening 400 a between the pair of pads 401.
Next, a substrate 408, such as a glass substrate or other transparent substrate is mounted on the device substrate 400 by coating a glue layer 406 on the device substrate 400 and filing in the opening 400 a, as shown in FIG. 5B . Thereafter, the carrier substrate 404 is reduced to a predetermined thickness by polishing or etching, to leave a portion of carrier substrate 404 a.
As shown in FIG. 5C , the carrier substrate 404 a and the dielectric layer 402 are successively patterned to form an opening 405 therein, where the surfaces 401 a and sidewalls 401 b of the pair of pads 401 are exposed.
As shown in FIG. 5D , a dielectric layer 410 is conformally deposited on the carrier substrate 404 a and the inner surface of the opening 405 by conventional deposition, such as CVD. Thereafter, the dielectric layer 410 on the surface 401 a and sidewall 401 b of the pair of pads 401 is removed by etching.
As shown in 5E, a metal layer 412 is conformally deposited on the dielectric layer 410 and the inner surface of the opening 405 by conventional deposition, such as CVD or sputtering, such that the metal layer 412 is formed directly on the surface 401 a of the pair of pads 401. Thereafter, the metal layer 412 on the inner surface of the opening 405 in the dielectric layer 402 is removed by etching. The remaining metal layer 412 electronically connects the pad 401 and the subsequent solder ball.
As shown in FIG. 5F , a protective layer 414, such as a silicon nitride layer, is formed by, for example, CVD, to cover the metal layer 412 and fills the opening 405 in the dielectric layer 402.
Thereafter, a plurality of openings corresponding to pads 401 is formed in the protective layer 414 to expose the metal layer 412. In order to simplify the diagram, only two openings 410 a are depicted, as shown in FIG. 5G . Solder balls 416 are correspondingly formed in the openings 410 a, such that each solder ball 416 is electrically connected to the corresponding pad 401 through the metal layer 412. After formation of solder balls 416, the device wafer and the substrate 408 are successively diced along the opening 405 in the dielectric layer 402 to form multiple device chips which are packaged. In some embodiments, a dam 415 can be formed between the substrate 408 and the device substrate 400 to form a cavity 417 therebetween. The dam 415 may be bonded with the substrate 408 and the device substrate 400 through glue layers 406 a and 406 b, respectively, as shown in FIG. 6 .
According to the invention, only one glass substrate is utilized for the package structure. Compared to conventional package structures utilizing two glass substrates, package size can be reduced. Since the surface of the pad, acting as a contact area between the metal layer and the pad, can be increased using the sidewall of the pad, thus adhesion therebetween can be enhanced to increase device reliability. Moreover, since using the surface of the pad as the contact area is not limited by the thickness of the pad, the pad without extending portion can be used in the chip of the package structure, thereby increasing device density of the chip. Additionally, since the protective layer is extended to the sidewall of the pad to entirely cover the metal layer on the pad, the metal layer can be prevented from humidity damage after dicing the wafer into multiple chips. Thus, device reliability can be further increased.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (10)
1. A method for fabricating package structures for optoelectronic devices, comprising:
reversely placing a device wafer on a first substrate, wherein the device wafer comprises:
a second substrate; and
a first dielectric layer between the first and second substrates, comprising at least one pair of pads formed in the first dielectric layer;
forming a first opening in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads;
forming a metal layer directly on the exposed surface of each pad and covering the second substrate;
forming a protective layer on the metal layer and filling the first opening in the first dielectric layer;
forming at least one second opening in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate;
forming a solder ball in the second opening, electrically connecting to the metal layer; and
dicing the device wafer and the first substrate along the first opening in the first dielectric layer.
2. The method as claimed in claim 1 , further forming a second dielectric layer between the second substrate and the metal layer.
3. The method as claimed in claim 1 , further forming a dam between the first substrate and the first dielectric layer to form a cavity therebetween.
4. The method as claimed in claim 1 , further forming a glue layer between the first substrate and the first dielectric layer.
5. The method as claimed in claim 1 , wherein the first substrate comprises glass and the second substrate comprises silicon.
6. A method for fabricating package structures for optoelectronic devices, comprising:
placing a device wafer between first and second substrates, comprising:
a third substrate adjacent to the first substrate; and
a first dielectric layer between the second and third substrates, comprising at least one pair of pads formed in the first dielectric layer;
forming a first opening in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads;
forming a metal layer directly on the exposed surface of each pad and covering the second substrate;
forming a protective layer on the metal layer and filling the first opening in the first dielectric layer;
forming at least one second opening in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate;
forming a solder ball in the second opening, electrically connecting to the metal layer; and
dicing the device wafer and the first substrate along the first opening in the first dielectric layer.
7. The method as claimed in claim 6 , further forming a second dielectric layer between the second substrate and the metal layer.
8. The method as claimed in claim 6 , further forming a dam between the first and third substrates to form a cavity therebetween.
9. The method as claimed in claim 6 , further forming a glue layer between the first and third substrates.
10. The method as claimed in claim 6 , wherein the first substrate comprises glass and the second and third substrates comprises silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/412,479 US7824964B2 (en) | 2007-01-11 | 2009-03-27 | Method for fabricating package structures for optoelectronic devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/652,084 US7566944B2 (en) | 2007-01-11 | 2007-01-11 | Package structure for optoelectronic device and fabrication method thereof |
US12/412,479 US7824964B2 (en) | 2007-01-11 | 2009-03-27 | Method for fabricating package structures for optoelectronic devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/652,084 Division US7566944B2 (en) | 2007-01-11 | 2007-01-11 | Package structure for optoelectronic device and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090186449A1 US20090186449A1 (en) | 2009-07-23 |
US7824964B2 true US7824964B2 (en) | 2010-11-02 |
Family
ID=39617079
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/652,084 Active 2027-04-12 US7566944B2 (en) | 2007-01-11 | 2007-01-11 | Package structure for optoelectronic device and fabrication method thereof |
US12/412,479 Active 2027-04-02 US7824964B2 (en) | 2007-01-11 | 2009-03-27 | Method for fabricating package structures for optoelectronic devices |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/652,084 Active 2027-04-12 US7566944B2 (en) | 2007-01-11 | 2007-01-11 | Package structure for optoelectronic device and fabrication method thereof |
Country Status (3)
Country | Link |
---|---|
US (2) | US7566944B2 (en) |
CN (1) | CN101221939B (en) |
TW (1) | TWI348750B (en) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008207306A (en) * | 2007-02-28 | 2008-09-11 | Fujitsu Ltd | Method of manufacturing packaged micro movable element, and packaged micro movable element |
TWI353667B (en) * | 2007-07-13 | 2011-12-01 | Xintec Inc | Image sensor package and fabrication method thereo |
TWI418002B (en) * | 2009-12-01 | 2013-12-01 | Xintec Inc | Chip package and fabrication method thereof |
TWI546910B (en) * | 2010-02-26 | 2016-08-21 | 精材科技股份有限公司 | Chip package and fabrication method thereof |
US8692382B2 (en) | 2010-03-11 | 2014-04-08 | Yu-Lin Yen | Chip package |
US8698316B2 (en) | 2010-03-11 | 2014-04-15 | Yu-Lin Yen | Chip package |
JP2012059881A (en) * | 2010-09-08 | 2012-03-22 | Toshiba Corp | Imaging device, imaging module and method for manufacturing imaging device |
US9105588B2 (en) * | 2010-10-21 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer |
CN102034720B (en) * | 2010-11-05 | 2013-05-15 | 南通富士通微电子股份有限公司 | Chip packaging method |
CN102034721B (en) | 2010-11-05 | 2013-07-10 | 南通富士通微电子股份有限公司 | Method for encapsulating chip |
US8507316B2 (en) * | 2010-12-22 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting T-contacts of chip scale packages from moisture |
US8697473B2 (en) * | 2011-01-31 | 2014-04-15 | Aptina Imaging Corporation | Methods for forming backside illuminated image sensors with front side metal redistribution layers |
US9216898B2 (en) | 2011-05-09 | 2015-12-22 | Chien-Hung Liu | Chip package and method for forming the same |
CN102774805B (en) * | 2011-05-13 | 2015-10-28 | 精材科技股份有限公司 | Wafer encapsulation body and forming method thereof |
CN102891120B (en) * | 2011-07-22 | 2016-06-08 | 精材科技股份有限公司 | Wafer encapsulation body and forming method thereof |
US8810012B2 (en) * | 2011-11-15 | 2014-08-19 | Xintec Inc. | Chip package, method for forming the same, and package wafer |
US9196532B2 (en) | 2012-06-21 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages and methods for forming the same |
US20140061864A1 (en) * | 2012-09-04 | 2014-03-06 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor substrate having crack preventing structure and method of manufacturing the same |
US8975739B2 (en) * | 2013-01-11 | 2015-03-10 | Xintec Inc. | Package structure and method for manufacturing thereof |
CN104851852B (en) * | 2015-04-07 | 2017-10-24 | 华天科技(昆山)电子有限公司 | Encapsulating structure of fingerprint recognition chip and preparation method thereof |
CN105655311A (en) * | 2016-01-02 | 2016-06-08 | 北京工业大学 | Wafer-level chip package backside interconnection structure and manufacturing method thereof |
TWI699005B (en) * | 2016-11-02 | 2020-07-11 | 原相科技股份有限公司 | Optical component packaging structure |
CN109003973B (en) * | 2018-09-19 | 2023-11-28 | 华天科技(西安)有限公司 | Double-cushion block photoelectric sensor packaging structure and packaging method thereof |
TWI727870B (en) * | 2019-07-29 | 2021-05-11 | 精材科技股份有限公司 | Chip structure and manufacturing method thereof |
CN110718533B (en) * | 2019-10-08 | 2021-01-29 | 上海集成电路研发中心有限公司 | Sunken structure convenient for online monitoring and preparation method thereof |
CN111463233B (en) * | 2020-04-16 | 2022-09-13 | 錼创显示科技股份有限公司 | Micro light emitting device display device |
TWI726685B (en) | 2020-04-16 | 2021-05-01 | 錼創顯示科技股份有限公司 | Micro light-emitting device display apparatus |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060033198A1 (en) | 2002-04-23 | 2006-02-16 | Sanyo Electric Co., Ltd. | Semiconductor device with sidewall wiring |
US20060079019A1 (en) * | 2004-10-08 | 2006-04-13 | Easetech Korea Co., Ltd. | Method for manufacturing wafer level chip scale package using redistribution substrate |
US20070026639A1 (en) * | 2002-10-30 | 2007-02-01 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device |
US20080128914A1 (en) | 2006-10-23 | 2008-06-05 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20080283951A1 (en) | 2007-05-16 | 2008-11-20 | Sony Corporation | Semiconductor device and method for manufacturing the same |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100411124C (en) * | 2006-08-01 | 2008-08-13 | 上海凯虹电子有限公司 | CSP packaging technique |
-
2007
- 2007-01-11 US US11/652,084 patent/US7566944B2/en active Active
- 2007-04-25 CN CN2007101018411A patent/CN101221939B/en active Active
- 2007-11-12 TW TW096142678A patent/TWI348750B/en active
-
2009
- 2009-03-27 US US12/412,479 patent/US7824964B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060033198A1 (en) | 2002-04-23 | 2006-02-16 | Sanyo Electric Co., Ltd. | Semiconductor device with sidewall wiring |
US20070026639A1 (en) * | 2002-10-30 | 2007-02-01 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device |
US20060079019A1 (en) * | 2004-10-08 | 2006-04-13 | Easetech Korea Co., Ltd. | Method for manufacturing wafer level chip scale package using redistribution substrate |
US20080128914A1 (en) | 2006-10-23 | 2008-06-05 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20080283951A1 (en) | 2007-05-16 | 2008-11-20 | Sony Corporation | Semiconductor device and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
CN101221939B (en) | 2010-08-11 |
US7566944B2 (en) | 2009-07-28 |
US20090186449A1 (en) | 2009-07-23 |
TW200830487A (en) | 2008-07-16 |
TWI348750B (en) | 2011-09-11 |
CN101221939A (en) | 2008-07-16 |
US20080169477A1 (en) | 2008-07-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7824964B2 (en) | Method for fabricating package structures for optoelectronic devices | |
US7679187B2 (en) | Bonding pad structure for back illuminated optoelectronic device and fabricating method thereof | |
US7923798B2 (en) | Optical device and method for fabricating the same, camera module using optical device, and electronic equipment mounting camera module | |
US7663213B2 (en) | Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same | |
US8541820B2 (en) | Semiconductor device including through-electrode | |
US8228426B2 (en) | Semiconductor package and camera module | |
US10269863B2 (en) | Methods and apparatus for via last through-vias | |
US8274101B2 (en) | CMOS image sensor with heat management structures | |
JP4432502B2 (en) | Semiconductor device | |
US8558387B2 (en) | Semiconductor device including bottom surface wiring and manfacturing method of the semiconductor device | |
US8053353B2 (en) | Method of making connections in a back-lit circuit | |
US10867969B2 (en) | Multi-wafer stacking structure and fabrication method thereof | |
US8232202B2 (en) | Image sensor package and fabrication method thereof | |
US10930619B2 (en) | Multi-wafer bonding structure and bonding method | |
CN104733435A (en) | 3DIC Interconnect Apparatus and Method | |
JP2006237594A (en) | Semiconductor device and manufacturing method thereof | |
JP2005235860A (en) | Semiconductor device and manufacturing method thereof | |
US11488998B2 (en) | Semiconductor apparatus and equipment | |
US20110024864A1 (en) | Semiconductor device and method for manufacturing the same | |
CN109860031A (en) | Semiconductor device and equipment | |
JP2007194498A (en) | Solid-state image pick-up device and manufacturing method therefor | |
US20090026562A1 (en) | Package structure for optoelectronic device | |
WO2005076360A1 (en) | Opto-electronic semiconductor device, method of manufacturing same, and camera provided with such a device | |
KR20090022325A (en) | Bonding pad of semiconductor device and method for manufacturing the same | |
US20020061640A1 (en) | Method of manufacturing passivation layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |