US7721018B2 - Direct memory access controller with flow control - Google Patents
Direct memory access controller with flow control Download PDFInfo
- Publication number
- US7721018B2 US7721018B2 US11/466,915 US46691506A US7721018B2 US 7721018 B2 US7721018 B2 US 7721018B2 US 46691506 A US46691506 A US 46691506A US 7721018 B2 US7721018 B2 US 7721018B2
- Authority
- US
- United States
- Prior art keywords
- data
- pattern
- register
- coupled
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Definitions
- the technical field of the present application relates to a direct memory access controller.
- Direct memory access controller are typically used in microprocessor systems, integrated microcontrollers, etc. DMA controllers are used to perform a data transfer from and to memory to and from a peripheral independently from the central processing unit of the computer system. To this end, a DMA controller can be seen as a second programmable processing unit with limited capabilities. Generally, a DMA controller is instructed to transfer a specific amount of data from a source location to a destination location.
- the source can be within a memory, for example, a data memory of a microcontroller, memory of a peripheral, or data generated by or accessible within a peripheral, such as an analog to digital converter, a port, a capture compare unit, etc.
- the destination can also be within a memory, thus, allowing high speed transfers within a memory device of a computer system or microcontroller.
- the destination can also be a peripheral, such as a digital to analog converter, a port, etc.
- To transfer data from a source to a destination the DMA controller must receive the respective source and destination addresses.
- each transfer length needs to be specified.
- the DMA controller needs to receive either the length of the data transfer or the start and end address of the data to be transferred. There, thus, exists a need for a more flexible DMA controller.
- a direct memory access controller may comprise a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
- a microcontroller may comprise a central processing unit, a bus coupled with the central processing unit, a memory coupled with the bus, a peripheral unit coupled with the bus, and a direct memory access controller coupled with the bus comprising a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
- a microcontroller may comprise a central processing unit, a first bus coupled with the central processing unit, a peripheral unit coupled with the first bus, a second bus coupled with the central processing unit, a memory coupled with the second bus, a direct memory access controller coupled with the first and second bus comprising a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
- a method of performing a transmission of a plurality of data from a source to a destination by a direct memory access controller may comprise the steps of a) determining whether a pattern detection is used; b) storing start addresses for a source address and a destination address; c) if a pattern detection is used storing a pattern; otherwise storing a transmission length; d) reading data from the source address; e) storing data in the destination address; f) if a pattern detection is used, comparing the data with the pattern and terminating the transmission upon a match; g) incrementing the source and destination addresses; h) if no pattern detection is used, terminating the transmission if the transmission length has been reached; and i) repeating steps d)-h).
- FIG. 1 is a block diagram showing typical DMA controller within a computer system, such as for example, a microcontroller;
- FIG. 2 is a block diagram showing a details of a first embodiment of a DMA controller
- FIG. 3 is a block diagram showing a details of a second embodiment of a DMA controller
- FIG. 4 is a block diagram showing a details of a third embodiment of a DMA controller
- FIG. 5 is a flowchart of a initialization routine for a DMA controller.
- FIG. 6 is a flowchart of a transfer routine of a DMA controller.
- a direct memory access controller may comprise a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
- a direct memory access controller may further comprise an address comparator for comparing a source or destination address with a predefined end address.
- a direct memory access controller may further comprise logic means for generating an end of transmission signal from output signals of the data and address comparators.
- the pattern register may comprise a plurality of data segments and the data comparator can be controlled to compare a selected segment with the data register.
- a direct memory access controller may further comprise a plurality of comparators coupled with the data registers.
- a direct memory access controller may further comprise a multiplexer coupled with the pattern register and the data register.
- a direct memory access controller may further comprise a control unit for controlling the multiplexer.
- a microcontroller may comprise a central processing unit, a bus coupled with the central processing unit, a memory coupled with the bus, a peripheral unit coupled with the bus, and a direct memory access controller coupled with the bus comprising a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.
- the above mentioned direct memory access controller may further comprise an address comparator for comparing a source or destination address with a predefined end address.
- the direct memory access controller may further comprise logic means for generating an end of transmission signal from output signals of the data and address comparators.
- the pattern register may comprise a plurality of data segments and the data comparator can be controlled to compare a selected segment with the data register.
- the direct memory access controller may further comprise a plurality of comparators coupled with the data registers.
- the direct memory access controller may further comprise a multiplexer coupled with the pattern register and the data register.
- the direct memory access controller may further comprise a control unit for controlling the multiplexer.
- a method of performing a transmission of a plurality of data from a source to a destination by a direct memory access controller may comprise the steps of a) determining whether a pattern detection is used; b) storing start addresses for a source address and a destination address; c) if a pattern detection is used storing a pattern; otherwise storing a transmission length; d) reading data from the source address; e) storing data in the destination address; f) if a pattern detection is used, comparing the data with the pattern and terminating the transmission upon a match; g) incrementing the source and destination addresses; h) if no pattern detection is used, terminating the transmission if the transmission length has been reached; and i) repeating steps d)-h).
- Such a method may further comprise using step h) even if a pattern detection is used.
- a plurality of data can be compared with a plurality of data pattern and only if the plurality of data matches the plurality of data pattern the transmission is terminated.
- the plurality of data pattern can be a sequential data pattern.
- the sequential data pattern may comprise a sequence of continuous data.
- FIG. 1 depicts a typical embodiment of a DMA controller within a computer system, such as a microcontroller.
- a computer system 100 such as for example a microcontroller, generally comprises a central processing unit (CPU) 110 which is coupled to one or more bus systems.
- CPU central processing unit
- FIG. 1 an exemplary main bus 140 is shown.
- the CPU 110 can communicate with a plurality of peripheral devices 180 a . . . 180 n , such as I/O ports, memories; A/D and D/A converters, timers; pulse width modulators, etc.
- a dedicated memory bus 160 can be provided to couple the CPU 110 with a main memory 120 .
- a direct memory access controller is shown with numeral 130 .
- this DMA controller 130 is also coupled with the main bus 140 to allow for data transfer between the devices coupled with this bus 140 .
- the DMA unit may also be coupled through an additional bus 170 with main memory 120 .
- DMA controller 130 may receive a plurality of control signals 150 from CPU 110 .
- Such a system allows for data transfer by the DMA controller without CPU 110 between any devices 180 a . . . 180 n coupled with bus 140 as well as between those devices 180 a . . . 180 n and memory 120 or within memory 120 .
- CPU 110 is usually only needed to initialize DMA controller 130 . Once DMA controller 130 is programmed, the data transfer proper is conducted without the aid of CPU 110 . CPU 110 is then free to perform other tasks.
- FIG. 2 shows more details of a DMA controller.
- a DMA controller 130 comprises at least a data register or latch 210 a and an associated address register or latch 240 a both coupled a receiving bus 270 and a transmitting bus 280 .
- FIG. 2 indicates by the dotted line that receiving bus 270 and transmitting bus 280 can be one and the same, such as bus 140 shown in FIG. 1 .
- DMA controller 130 can also be configured to communicate between two different buses.
- a receiving bus 270 can be, for example, bus 140 as shown in FIG. 1 and a transmitting bus 280 can be bus 170 as shown in FIG. 1 .
- Both registers or latches for address and data 210 a and 240 a are coupled with these buses.
- separate registers for transmitting and receiving can be provided.
- Separate address registers 240 a and 240 b as shown in FIG. 2 are useful as source and destination address usually differ.
- the data register 210 a and the transmitting and/or receiving register 240 a, b may further be coupled with a comparator to determine a match 230 , 260 in the data or address.
- the DMA controller 130 can be programmed to transfer a specific amount of data beginning at a source start address and ending at a source end address to a destination which also begins at a destination start address and ends at a destination end address.
- register 240 a is loaded with the source start address
- register 240 b is loaded with the destination start address.
- DMA controller 130 further receives either the length of the data block to transferred or a source end address. If the source end address is used, then this address is loaded in a respective register 240 c coupled with a comparator 250 .
- the destination end address or as stated above, the length of the data block can be used to determine the end of the transfer.
- DMA controller 130 puts the first address, the source start address stored in register 240 a on bus 140 . This address can be within a memory or any device coupled with bus 140 . An associated data is then transferred into data register 210 a . In a following step, register 240 a is decoupled from bus 140 and register 240 b is coupled with bus 140 . Alternatively, if only one address register is used, this address register is loaded with the destination start address. Thus, the destination address is now put on bus 140 addressing the respective destination such as a memory or any device coupled with bus 140 . Then, the data stored in register 210 a is transferred to this destination address.
- Source address register 240 a and destination address register 240 b are then incremented and the process is repeated until the source address register 240 a contains the source end address.
- This end of transmission can, for example, be detected by comparator 250 which compares the contents of address register 240 a and register 240 c and generates a match signal 260 .
- DMA controller 130 allows for a conditional transfer that stops the transfer once a specific pattern such as a predefined data byte has been received.
- DMA controller 130 comprises a further pattern register 210 b .
- this register 210 b is loaded with a pattern such as a specific byte.
- comparator 220 detects a match between the loaded data in register 210 a and the pattern register 210 b a respective signal 230 is generated which indicates to DMA controller 130 that the end of transmission has been reached.
- the address comparator 250 can be used in addition defining a maximum transfer.
- the DMA controller generally allows two different types of transaction.
- a first transaction is defined as a fixed length transmission allowing for a defined block of data to be transferred by the DMA controller.
- the second transaction has an open length and its length is defined by a specific pattern.
- the end of transmission can be defined by a specific symbol.
- a sequence of symbols may define the end of transmission.
- a more flexible definition of an end of transmission is possible. For example, instead of a single byte a sequence of two bytes can be used such as a carriage return (CR) line feed (LF) sequence.
- CR carriage return
- LF line feed
- a plurality of registers can be provided which are programmed with the respective sequence.
- the second transaction type can be enhanced with a maximum transfer length to avoid an endless transfer loop and thus provide for additional security.
- FIG. 3 shows specific registers of another exemplary embodiment of a DMA controller.
- a source register 310 and a destination address register 320 are provided.
- a length/maximum length register 330 is coupled with a comparator 380 which can generate an end address detection EndAddr.
- Comparator 380 is furthermore coupled with a counter 370 .
- a pattern register 340 is coupled with another comparator 350 which is also coupled with a data register 360 receiving and transmitting the data proper Din and Dout.
- Comparator 350 generates a signal Match which can then produce an end of transmission signal EofTrans.
- Multiple pattern registers 340 and associated comparators can be provided as indicated by respective elements using dotted lines. Respective logic between the registers and the comparators can be provided to allow for the different types of transmission.
- FIG. 3 shows a first controllable driver 385 receiving the signal EndAddr from comparator 380 .
- the output of driver 385 is coupled with a first input of an OR gate 390 .
- a second controllable inverter 355 receives signal Match from comparator 350 .
- the output of driver 355 is coupled with the second input of OR gate 390 .
- the output of OR gate 390 provides for an end of transmission signal EofTrans.
- driver 355 is controlled to decouple comparator 350 from OR gate 390 generating a constant logic low signal at the second input of OR gate 390 and driver 385 is controlled to couple comparator 380 with OR gate 390 .
- Register 310 and 320 are loaded with the respective source start address and destination start address.
- Register 330 is loaded with the length of the data block to be transmitted and counter 370 is reset to zero. Then the data transfer can be started. To this end, the data addressed by register 310 is loaded into register 360 and written to the address contained in register 320 . Then, registers 310 and 320 are incremented by the size of the transmitted data. For example, if data register is a byte wide register, then registers 310 and 320 are incremented by 1.
- registers 310 and 320 are incremented by 2, and so on.
- Counter 370 is incremented accordingly.
- Comparator 380 is comparing the counter value of counter 370 with register 330 . The transfer of data is repeated until the counter value matches the content of register 330 . If such a match is reached, the EndAddr signal goes logic high and the output of Or gate 390 will go high indicating an end of transmission EofTrans. As a result, the DMA controller is stopped.
- driver 385 is controlled to decouple comparator 380 from OR gate 390 generating a constant logic low signal at the first input of OR gate 390 and driver 355 is controlled to couple comparator 350 with OR gate 390 .
- source and destination registers 310 and 320 are loaded with the respective start addresses.
- pattern register 340 is loaded with predefined pattern. Again, the DMA transfer is staffed and the first data associated with the source register is loaded into data register 360 and compared with pattern register 340 . If a match occurs, comparator 350 generates a high signal at its output which causes a high signal at the output of OR gate 390 and indicates the end of the transmission. Otherwise, registers 310 and 320 are incremented and the transfer continues until a match between the transmitted data and the pattern register 340 occurs.
- both drivers 355 and 385 are activated coupling both comparators 350 and 380 with OR gate 390 .
- registers 310 and 320 are again loaded with the respective start addresses.
- a maximum length value is loaded into register 330 and a pattern is loaded into register 340 .
- the data transfer takes place as described above.
- the end of transmission is either generated by comparator 350 or 380 .
- comparator 350 will detect the end of transmission by a match between the transmitted data and the pattern register 340 . If, however, due to an error or a malfunction this data never occurs, then comparator 380 will terminate the transmission once the maximum length of data transmission has been reached.
- FIG. 4 shows another embodiment of a pattern register.
- a pattern register 410 has a width of 32 bits and, thus, consists of four bytes 410 a . . . 410 d .
- Each byte 410 a . . . 410 d is coupled with a 4:1 multiplexer 420 having 32 inputs and 8 outputs.
- the output lines of multiplexer 420 are coupled with a comparator 430 which compares the 8 bits with the content of the data register (not shown).
- a control unit 440 is provided to control multiplexer 420 . This embodiment allows for the comparison of a data sequence.
- pattern register 410 is loaded with a predefined 32 bit pattern.
- the multiplexer is controlled to couple the first byte 410 a of register 410 with comparator 430 .
- the comparator signals such a match to control unit 440 .
- Control unit 440 then switches multiplexer 420 to couple the second byte 410 b with comparator 430 . If the next data byte transferred byte the DMA controller matches the second byte 410 b , then control unit switches the multiplexer again to allow for a comparison of the next byte with byte 410 c . Only if four sequential bytes match the content of register 410 d an end of transmission signal is generated.
- multiplexer 420 is reset to the first byte 410 a to start a new sequence comparison.
- the unit can be programmed to allow for any length of the pattern sequence. In this embodiment, for example, a one byte sequence, a two byte sequence, a three byte sequence or a four byte sequence can be used. Depending on the size of the pattern register any sequence length can be implemented.
- the sequence In a second mode, the sequence must not occur in a continuous order. For example, any number of intermediary bytes can be allowed. Thus, multiplexer 420 would not be reset to the first byte 410 a if a mismatch occurs in a following byte. Thus, if pattern register is programmed, for example, with “0x64A8” a sequence of “0x 6 88 4 0A A BC 8 ” (underlined bytes show match) would trigger the end of transmission signal. If yet another embodiment, a plurality of comparators and a multiple byte register can be used to even allow for a non sequential match. Thus, an end of transmission signal would be generated if all bytes within the pattern occurred even if they are out of order.
- the configuration shown in FIG. 4 can also be used to compare each byte 410 a . . . 410 d with each transmitted data by sequentially switching through all four data bytes 410 a . . . 410 d per data cycle.
- the control unit can set respective bits for each data segment 410 a . . . 410 d . Once all bits have been set, an end of transmission signal can be generated. Any other combination of possible comparisons can be implemented.
- FIG. 5 shows a flow chart of an embodiment of an initialization routine for a DMA controller.
- a decision is made whether a pattern mode is used or not. If no, the routine branches to step 520 in which the source and destination address are stored. in a following step 530 the length of the transmission is determined either by an end address or a block length. then the routine ends. If the pattern mode is used, the routine goes to step 540 in which the source and destination are set. Then in step 550 , optionally the maximum length of the transmission is set and in step 560 the data termination pattern value is stored. In step 570 the pattern mode is set and the initialization routine ends.
- FIG. 6 shows a flow chart of an embodiment of a DMA transfer routine following the initialization routine shown in FIG. 5 .
- the routine starts in step 610 in which the source data under the start address is read. In step 620 this data written to the destination address. In step 630 it is checked whether the pattern matching mode has been set. If not the source address and destination address are incremented in step 640 and in step 660 the data length value is decremented. In step 670 it is checked whether the data length value is 0. If yes, the transfer ends, if not the routine returns to step 610 . If the pattern mode has been set, the routine branches from step 630 to step 650 in which it is checked whether the data matches the pattern. If a match occurs, then the transfer ends. Otherwise, the routine continues with step 640 as stated above.
Abstract
Description
Claims (25)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/466,915 US7721018B2 (en) | 2006-08-24 | 2006-08-24 | Direct memory access controller with flow control |
EP07841006.5A EP2095245B1 (en) | 2006-08-24 | 2007-08-16 | Direct memory access controller |
CN2007800313803A CN101506785B (en) | 2006-08-24 | 2007-08-16 | Direct memory access controller |
KR1020097005408A KR101158780B1 (en) | 2006-08-24 | 2007-08-16 | Direct memory access controller and microcontroller |
PCT/US2007/076103 WO2008024670A2 (en) | 2006-08-24 | 2007-08-16 | Direct memory access controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/466,915 US7721018B2 (en) | 2006-08-24 | 2006-08-24 | Direct memory access controller with flow control |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080126662A1 US20080126662A1 (en) | 2008-05-29 |
US7721018B2 true US7721018B2 (en) | 2010-05-18 |
Family
ID=39107543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/466,915 Active 2027-07-04 US7721018B2 (en) | 2006-08-24 | 2006-08-24 | Direct memory access controller with flow control |
Country Status (5)
Country | Link |
---|---|
US (1) | US7721018B2 (en) |
EP (1) | EP2095245B1 (en) |
KR (1) | KR101158780B1 (en) |
CN (1) | CN101506785B (en) |
WO (1) | WO2008024670A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140281098A1 (en) * | 2013-03-14 | 2014-09-18 | Infineon Technologies Ag | Conditional links for direct memory access controllers |
US20150039803A1 (en) * | 2012-02-29 | 2015-02-05 | Mitsubishi Electric Corporation | Data transfer apparatus, data transfer method, and data transfer program |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7934025B2 (en) * | 2007-01-24 | 2011-04-26 | Qualcomm Incorporated | Content terminated DMA |
DE102007029833B4 (en) * | 2007-06-28 | 2019-03-28 | Texas Instruments Deutschland Gmbh | A microcontroller with data modification module and system comprising a data modification module |
US8184503B2 (en) * | 2009-05-18 | 2012-05-22 | Magnetrol International, Incorporated | Process measurement instrument with target rejection |
KR101579592B1 (en) * | 2009-12-03 | 2015-12-22 | 삼성전자 주식회사 | Direct memory access controller and method for operating thereof |
US8635412B1 (en) * | 2010-09-09 | 2014-01-21 | Western Digital Technologies, Inc. | Inter-processor communication |
CN103119573A (en) * | 2010-09-21 | 2013-05-22 | 三菱电机株式会社 | DMA controller and data readout device |
US9164886B1 (en) | 2010-09-21 | 2015-10-20 | Western Digital Technologies, Inc. | System and method for multistage processing in a memory storage subsystem |
WO2013081588A1 (en) * | 2011-11-30 | 2013-06-06 | Intel Corporation | Instruction and logic to provide vector horizontal compare functionality |
US10318291B2 (en) | 2011-11-30 | 2019-06-11 | Intel Corporation | Providing vector horizontal compare functionality within a vector register |
DE102013218305A1 (en) * | 2013-08-30 | 2015-03-05 | Dr. Johannes Heidenhain Gmbh | Method and device for synchronizing a control unit and at least one associated peripheral unit |
Citations (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4161719A (en) * | 1977-10-04 | 1979-07-17 | Ncr Corporation | System for controlling synchronization in a digital communication system |
JPS5999525A (en) * | 1982-11-30 | 1984-06-08 | Toshiba Corp | Dma transfer control system |
US4989135A (en) * | 1987-02-16 | 1991-01-29 | Hitachi, Ltd. | Communication control microcomputer |
EP0422776A2 (en) * | 1989-10-11 | 1991-04-17 | International Business Machines Corporation | Serial communication apparatus for receiving serial communication status data with a DMA controller |
EP0470030A2 (en) | 1990-08-02 | 1992-02-05 | International Business Machines Corporation | Fast memory power-on diagnostics using direct memory addressing |
EP0470624A2 (en) | 1990-08-08 | 1992-02-12 | Nec Corporation | DMA controller having jump function |
US5175818A (en) * | 1988-02-23 | 1992-12-29 | Hitachi, Ltd. | Communication interface for independently generating frame information that is subsequently stored in host memory and sent out to transmitting fifo by dma |
US5463762A (en) * | 1993-12-30 | 1995-10-31 | Unisys Corporation | I/O subsystem with header and error detection code generation and checking |
US5974480A (en) * | 1996-10-18 | 1999-10-26 | Samsung Electronics Co., Ltd. | DMA controller which receives size data for each DMA channel |
US5983289A (en) | 1996-09-11 | 1999-11-09 | Oki Data Corporation | Data transfer methods and controller for transferring data in blocks without crossing certain address boundaries |
US6018777A (en) * | 1992-04-13 | 2000-01-25 | Hyundai Electronics America | Intelligent SCSI-2/DMA processor |
US6038607A (en) * | 1994-03-24 | 2000-03-14 | Hitachi, Ltd. | Method and apparatus in a computer system having plural computers which cause the initiation of functions in each other using information contained in packets transferred between the computers |
US6081852A (en) * | 1996-04-26 | 2000-06-27 | Texas Instruments Incorporated | Packet data transferring system for autonomously operating a DMA by autonomous boot mode select signal wherein the DMA is enabled to at least one program control list |
US6092116A (en) * | 1996-12-11 | 2000-07-18 | Lsi Logic Corporation | DMA controller with response message and receive frame action tables |
US6185620B1 (en) * | 1998-04-03 | 2001-02-06 | Lsi Logic Corporation | Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion |
US20020027985A1 (en) * | 2000-06-12 | 2002-03-07 | Farrokh Rashid-Farrokhi | Parallel processing for multiple-input, multiple-output, DSL systems |
US20020169900A1 (en) * | 2001-05-11 | 2002-11-14 | Fujitsu Limited | Direct memory access controller, and direct memory access control method |
EP1271330A2 (en) | 2001-06-28 | 2003-01-02 | Sharp Kabushiki Kaisha | Data transfer control device, semiconductor memory device and electronic information apparatus |
US20030079118A1 (en) * | 2001-10-19 | 2003-04-24 | Felix Chow | Bit synchronous engine and method |
US20040015617A1 (en) * | 2001-01-25 | 2004-01-22 | Sangha Onkar S. | Flexible network interfaces and flexible data clocking |
US6775693B1 (en) * | 2000-03-30 | 2004-08-10 | Baydel Limited | Network DMA method |
US6826354B2 (en) * | 1998-10-15 | 2004-11-30 | Fujitsu Limited | Buffer control method and buffer control device |
US20050154801A1 (en) * | 2003-12-29 | 2005-07-14 | Darren Neuman | Programming system and method for a video network |
US20060206634A1 (en) * | 2005-02-24 | 2006-09-14 | Yuishi Torisaki | DMA controller |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10334037A (en) * | 1997-05-30 | 1998-12-18 | Sanyo Electric Co Ltd | Communication dma device |
JP2000099452A (en) * | 1998-09-21 | 2000-04-07 | Seiko Epson Corp | Dma control device |
KR20050045201A (en) * | 2003-11-10 | 2005-05-17 | 삼성전자주식회사 | Ending method and apparatus for transmitting direct memory access |
-
2006
- 2006-08-24 US US11/466,915 patent/US7721018B2/en active Active
-
2007
- 2007-08-16 WO PCT/US2007/076103 patent/WO2008024670A2/en active Application Filing
- 2007-08-16 KR KR1020097005408A patent/KR101158780B1/en active IP Right Grant
- 2007-08-16 CN CN2007800313803A patent/CN101506785B/en active Active
- 2007-08-16 EP EP07841006.5A patent/EP2095245B1/en active Active
Patent Citations (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4161719A (en) * | 1977-10-04 | 1979-07-17 | Ncr Corporation | System for controlling synchronization in a digital communication system |
JPS5999525A (en) * | 1982-11-30 | 1984-06-08 | Toshiba Corp | Dma transfer control system |
US4989135A (en) * | 1987-02-16 | 1991-01-29 | Hitachi, Ltd. | Communication control microcomputer |
US5175818A (en) * | 1988-02-23 | 1992-12-29 | Hitachi, Ltd. | Communication interface for independently generating frame information that is subsequently stored in host memory and sent out to transmitting fifo by dma |
EP0422776A2 (en) * | 1989-10-11 | 1991-04-17 | International Business Machines Corporation | Serial communication apparatus for receiving serial communication status data with a DMA controller |
EP0470030A2 (en) | 1990-08-02 | 1992-02-05 | International Business Machines Corporation | Fast memory power-on diagnostics using direct memory addressing |
EP0470624A2 (en) | 1990-08-08 | 1992-02-12 | Nec Corporation | DMA controller having jump function |
US6018777A (en) * | 1992-04-13 | 2000-01-25 | Hyundai Electronics America | Intelligent SCSI-2/DMA processor |
US5463762A (en) * | 1993-12-30 | 1995-10-31 | Unisys Corporation | I/O subsystem with header and error detection code generation and checking |
US6038607A (en) * | 1994-03-24 | 2000-03-14 | Hitachi, Ltd. | Method and apparatus in a computer system having plural computers which cause the initiation of functions in each other using information contained in packets transferred between the computers |
US6081852A (en) * | 1996-04-26 | 2000-06-27 | Texas Instruments Incorporated | Packet data transferring system for autonomously operating a DMA by autonomous boot mode select signal wherein the DMA is enabled to at least one program control list |
US5983289A (en) | 1996-09-11 | 1999-11-09 | Oki Data Corporation | Data transfer methods and controller for transferring data in blocks without crossing certain address boundaries |
US5974480A (en) * | 1996-10-18 | 1999-10-26 | Samsung Electronics Co., Ltd. | DMA controller which receives size data for each DMA channel |
US6092116A (en) * | 1996-12-11 | 2000-07-18 | Lsi Logic Corporation | DMA controller with response message and receive frame action tables |
US6185620B1 (en) * | 1998-04-03 | 2001-02-06 | Lsi Logic Corporation | Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion |
US6826354B2 (en) * | 1998-10-15 | 2004-11-30 | Fujitsu Limited | Buffer control method and buffer control device |
US6775693B1 (en) * | 2000-03-30 | 2004-08-10 | Baydel Limited | Network DMA method |
US20020027985A1 (en) * | 2000-06-12 | 2002-03-07 | Farrokh Rashid-Farrokhi | Parallel processing for multiple-input, multiple-output, DSL systems |
US20040015617A1 (en) * | 2001-01-25 | 2004-01-22 | Sangha Onkar S. | Flexible network interfaces and flexible data clocking |
US20020169900A1 (en) * | 2001-05-11 | 2002-11-14 | Fujitsu Limited | Direct memory access controller, and direct memory access control method |
EP1271330A2 (en) | 2001-06-28 | 2003-01-02 | Sharp Kabushiki Kaisha | Data transfer control device, semiconductor memory device and electronic information apparatus |
US20030079118A1 (en) * | 2001-10-19 | 2003-04-24 | Felix Chow | Bit synchronous engine and method |
US20050154801A1 (en) * | 2003-12-29 | 2005-07-14 | Darren Neuman | Programming system and method for a video network |
US20060206634A1 (en) * | 2005-02-24 | 2006-09-14 | Yuishi Torisaki | DMA controller |
Non-Patent Citations (2)
Title |
---|
International Search Report and Written Opinion for PCT/US2007/076103 mailed Apr. 4, 2008. |
TriMedia Product Group, "TriMedia TM1000 Preliminary Data Book", Philips Electronics North America Corporation, 1997, p. A-161. * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150039803A1 (en) * | 2012-02-29 | 2015-02-05 | Mitsubishi Electric Corporation | Data transfer apparatus, data transfer method, and data transfer program |
US9727504B2 (en) * | 2012-02-29 | 2017-08-08 | Mitsubishi Electric Corporation | Data transfer apparatus, data transfer method, and data transfer program |
US20140281098A1 (en) * | 2013-03-14 | 2014-09-18 | Infineon Technologies Ag | Conditional links for direct memory access controllers |
US9569384B2 (en) * | 2013-03-14 | 2017-02-14 | Infineon Technologies Ag | Conditional links for direct memory access controllers |
Also Published As
Publication number | Publication date |
---|---|
US20080126662A1 (en) | 2008-05-29 |
WO2008024670A2 (en) | 2008-02-28 |
WO2008024670A3 (en) | 2008-05-29 |
CN101506785A (en) | 2009-08-12 |
EP2095245B1 (en) | 2016-12-21 |
CN101506785B (en) | 2012-04-25 |
KR20090042969A (en) | 2009-05-04 |
EP2095245A2 (en) | 2009-09-02 |
KR101158780B1 (en) | 2012-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7721018B2 (en) | Direct memory access controller with flow control | |
US5812881A (en) | Handshake minimizing serial to parallel bus interface in a data processing system | |
KR100227419B1 (en) | External storage device and memory access control method for the same | |
EP0412666B1 (en) | A read/write memory | |
US5752076A (en) | Dynamic programming of bus master channels by intelligent peripheral devices using communication packets | |
US4371924A (en) | Computer system apparatus for prefetching data requested by a peripheral device from memory | |
GB2265481A (en) | Memory processor that permits aggressive execution of load instructions | |
US5465340A (en) | Direct memory access controller handling exceptions during transferring multiple bytes in parallel | |
EP1026597B1 (en) | Data alignment between buses | |
US5119487A (en) | Dma controller having programmable logic array for outputting control information required during a next transfer cycle during one transfer cycle | |
US7934043B2 (en) | Data processing apparatus for controlling access to a memory based upon detection of completion of a DMA bus cycle | |
US20080147908A1 (en) | Direct Memory Access Controller with Error Check | |
US20050038924A1 (en) | Operation mode control circuit, microcomputer including the same, and control system using the microcomputer | |
US7587533B2 (en) | Digital programming interface between a baseband processor and an integrated radio-frequency module | |
CN116560902A (en) | Processing system, related integrated circuit and method | |
US20090235010A1 (en) | Data processing circuit, cache system, and data transfer apparatus | |
EP0383891B1 (en) | Pipelined address check bit stack controller | |
US6762973B2 (en) | Data coherent logic for an SRAM device | |
CA1252577A (en) | Shared main memory and disk controller memory address register | |
US5461634A (en) | Memory storage verification system for use in an integrated circuit for performing power signal measurements | |
US6339800B1 (en) | Method for transmitting data between a microprocessor and an external memory module by using combined serial/parallel process | |
US7882322B2 (en) | Early directory access of a double data rate elastic interface | |
US6175518B1 (en) | Remote register hierarchy accessible using a serial data line | |
US7209252B2 (en) | Memory module, printer assembly, and method for storing printer code | |
US5687341A (en) | Device for speeding up the reading of a memory by a processor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAJBHARTI, NILESH;REEL/FRAME:018266/0970 Effective date: 20060818 Owner name: MICROCHIP TECHNOLOGY INCORPORATED,ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAJBHARTI, NILESH;REEL/FRAME:018266/0970 Effective date: 20060818 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:MICROCHIP TECHNOLOGY INCORPORATED;REEL/FRAME:041675/0617 Effective date: 20170208 Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT Free format text: SECURITY INTEREST;ASSIGNOR:MICROCHIP TECHNOLOGY INCORPORATED;REEL/FRAME:041675/0617 Effective date: 20170208 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:046426/0001 Effective date: 20180529 Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:046426/0001 Effective date: 20180529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:047103/0206 Effective date: 20180914 Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES C Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:047103/0206 Effective date: 20180914 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT, DELAWARE Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053311/0305 Effective date: 20200327 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROCHIP TECHNOLOGY INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 Owner name: MICROSEMI CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT;REEL/FRAME:053466/0011 Effective date: 20200529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INC.;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:053468/0705 Effective date: 20200529 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:055671/0612 Effective date: 20201217 |
|
AS | Assignment |
Owner name: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT, MINNESOTA Free format text: SECURITY INTEREST;ASSIGNORS:MICROCHIP TECHNOLOGY INCORPORATED;SILICON STORAGE TECHNOLOGY, INC.;ATMEL CORPORATION;AND OTHERS;REEL/FRAME:057935/0474 Effective date: 20210528 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059333/0222 Effective date: 20220218 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059333/0222 Effective date: 20220218 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059333/0222 Effective date: 20220218 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059333/0222 Effective date: 20220218 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059333/0222 Effective date: 20220218 |
|
AS | Assignment |
Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:059666/0545 Effective date: 20220218 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0001 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0001 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0001 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0001 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059358/0001 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059863/0400 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:059363/0001 Effective date: 20220228 |
|
AS | Assignment |
Owner name: MICROSEMI STORAGE SOLUTIONS, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROSEMI CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: ATMEL CORPORATION, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: SILICON STORAGE TECHNOLOGY, INC., ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 Owner name: MICROCHIP TECHNOLOGY INCORPORATED, ARIZONA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT;REEL/FRAME:060894/0437 Effective date: 20220228 |