US7547917B2 - Inverted multilayer semiconductor device assembly - Google Patents

Inverted multilayer semiconductor device assembly Download PDF

Info

Publication number
US7547917B2
US7547917B2 US10/907,566 US90756605A US7547917B2 US 7547917 B2 US7547917 B2 US 7547917B2 US 90756605 A US90756605 A US 90756605A US 7547917 B2 US7547917 B2 US 7547917B2
Authority
US
United States
Prior art keywords
layer
crystal orientation
gate
substrate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US10/907,566
Other versions
US20060226491A1 (en
Inventor
Robert J. Gauthier, Jr.
Mahmoud A. Mousa
Christopher S. Putnam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US10/907,566 priority Critical patent/US7547917B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MOUSA, MAHMOUD A., GAUTHIER, JR., ROBERT J., PUTNAM, CHRISTOPHER S.
Publication of US20060226491A1 publication Critical patent/US20060226491A1/en
Application granted granted Critical
Publication of US7547917B2 publication Critical patent/US7547917B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Definitions

  • the invention relates to stacked circuits, and more particularly to a stacked circuit having an inverted device and to a stacked circuit having an inverted device with a different crystal orientation.
  • SOI Silicon On Insulator
  • SOI technology reduces or eliminates bulk CMOS latch-up problems. Additionally, SOI technology reduces junction capacitance and allows circuits to operate at higher speeds. Accordingly, SOI technology allows a higher circuit density to be achieved on a silicon wafer.
  • a multiple layer device structure can be created using SOI technology.
  • Each level of a multilevel structure created using SOI may be interconnected using vertical plugs.
  • Metal connections can be used at any level.
  • NMOS and PMOS devices may each be restricted to a separate level, or NMOS and PMOS devices may be intermixed on a single level.
  • having multiple levels where each level requires a set of separate metal connections may result in a large number of metal connections, increasing the complexity and costs of the chip.
  • a layer of a multilevel device may inhibit cooling of adjacent layers by limiting heat transfer therefrom.
  • each layer has a crystal orientation different from the adjoining layers.
  • multi-layer devices When multi-layer devices are formed from a common semiconductor layer they will have the same crystal orientation from one level to the next. This limitation on the crystal orientation across multiple levels of an integrated circuit results from constraints imposed by the fabrication process.
  • semiconductor material is traditionally grown from a pre-existing layer of semiconductor material.
  • the atoms of the newly formed layer have a strong tendency to orient themselves to the pre-existing substrate's crystal structure as they are laid down.
  • a method of forming a semiconductor device assembly includes forming a first semiconductor device having a first crystal region and a second semiconductor device having a second crystal region. The first semiconductor device is placed in contact with the second semiconductor device.
  • the method includes forming a first semiconductor device having a first crystal orientation in a substrate and forming a second semiconductor device having a second crystal orientation in a substrate.
  • the first semiconductor device is placed in contact with the second semiconductor device.
  • the semiconductor device assembly includes an NMOS device having a first crystal orientation and a PMOS device having a second crystal orientation inverted on a surface of the NMOS device.
  • FIGS. 1 and 2 illustrate devices for forming an inverted multilayer semiconductor device in accordance with the invention.
  • FIG. 3 illustrates an inverted multilayer semiconductor device in accordance with the invention.
  • a first CMOS device such as a pFET
  • a second CMOS device such as an nFET
  • the second device is flipped over and bonded to the first device with a bonding layer such as SiO 2 forming an inverted stacked or an inverted multi-layered arrangement.
  • a bonding layer such as SiO 2
  • At lease one of the contacts of the first device is aligned with the corresponding contact of the second device, and the two contacts are brought into electrical contact with one another during bonding. Because the two devices are bonded in an inverted stacked arrangement, the devices are easily interconnected along the boundary between the two devices.
  • it is possible to form stacked layers of CMOS devices where each layer has either the same or a different crystal orientation in the active region as a layer below it and/or a layer above it, and the combination of devices has a reduced number of connections.
  • a first device 100 has silicon (Si) substrate 105 with a crystal orientation of [110] and a first SiO 2 layer 107 formed on top of the first Si substrate 105 .
  • a first Si layer 120 also having a crystal orientation of [110] is formed on the SiO 2 layer 107 .
  • Trenches are etched and filled with an insulating material such as an oxide to form shallow trench isolations 110 on either side of the active region of the first Si layer 120 .
  • Source/drain regions 115 are formed next to shallow trench isolations 110 in the first Si layer 120 .
  • the source/drain regions 115 are formed by any of the methods well known in the art for forming source/drain regions.
  • the upper surface of the first Si layer 120 is planarized after the source/drain regions 115 are formed using any of the methods well known in the art to planarize a Si layer.
  • a second SiO 2 layer 125 is formed over a surface of the first Si layer 120 .
  • a polysilicon gate 130 is formed on top of the second SiO 2 layer 125 such that a portion of the second SiO 2 layer 125 forms a gate oxide for the first gate 130 of the first device 100 .
  • a CA gate contact 140 is formed on the gate 130 and a metal (M 1 ) contact 155 is formed on the gate contact 140 .
  • Source/drain CA contacts 135 and 145 are formed on the source/drains 115 .
  • Source/drain MI 160 and 150 and gate metal 155 are formed thereon, respectively.
  • a dielectric 165 is formed over the top of the first device 100 , and the top of the dielectric 165 is planarized. Additionally, the dielectric 165 may be etched so that the gate metal 155 and the source/drain metal 150 are slightly higher than the surrounding dielectric 165 to facilitate making positive contact thereon during a later bonding process. Such an etching process may include etching the top surface of the dielectric 165 with an etchant which selectively removes dielectric material, but does not remove the material of the gate metal 155 and source/drain metals 150 . Alternatively, the gate metal 155 and drain/source metal 150 may be protected by a mask while the top surface of the dielectric 165 is etched.
  • Another method to raise the gate metal 155 and source/drain metal 150 above the top surface of the dielectric 165 may include planarizing the dielectric 165 , a gate metal 155 and source/drain metal 150 , and building up the gate metal 155 and source/drain metal 150 to stand slightly above the top surface of the dielectric 165 .
  • Such a build-up process may include masking the surrounding dielectric 165 to leave the gate metal 155 and source/drain metal 150 exposed, and depositing or growing a suitable conductive material on the exposed gate metal 155 and source/drain metal 150 .
  • a second device 200 is also formed using similar Fabrication methods appropriate for producing the second device 200 .
  • the second device 200 may have a crystal orientation in its active region different from the first device 100 . This is possible due to the separate fabrication processes of each of the devices, prior to inverting the second device 200 bonding.
  • a second Si substrate 205 having a crystal orientation of [100] has a second SiO 2 layer 207 formed thereon.
  • the second SiO 2 layer 207 has a second Si layer 220 formed on top.
  • the second Si layer 220 is formed to include an active region of the second device 200 and is arranged over the second Si layer 207 .
  • Trenches are etched into the second Si layer 207 and filled with an insulator such as an oxide using any of the methods well known in the art for forming and filling a trench to create shallow trench isolations 210 .
  • Source/drain regions 215 are formed on each side of an active region 225 .
  • the source/drain regions 215 of the second device 200 are formed by any of the methods well known in the art for forming source/drain regions 215 .
  • a portion of the N-well 212 lies between the shallow trench isolation 210 and the source/drain regions 215 .
  • a gate oxide 225 is formed on top of the active region of the second Si layer 220 .
  • the gate oxide 225 may be formed by any of the techniques well known in the art for forming a gate oxide.
  • a polysilicon gate 230 is formed over the gate oxide 225 .
  • a CA contact 240 is formed on the poly gate 230 and a metal (M 1 ) 255 is formed on the CA contact 240 .
  • Source/drain M 1 contacts 235 and 245 are formed on the source/drains 215 .
  • Source/drain metals 260 and 250 are formed thereon, respectively.
  • a dielectric 265 is formed over the top of the first device.
  • the second device is formed so that the gate metal 255 and source/drain metal 250 protrude slightly above the dielectric 265 surface.
  • the top of the dielectric is planarized and then etched to leave the tops of the gate metal 255 and a source/drain metal 250 slightly protruding above the surrounding surface, depending on the connection.
  • the second device 200 is inverted and bonded to the top of the first device 100 with a bonding layer 305 .
  • the bonding layer 305 attaches a top of the first device 100 to the top of the second device 200 .
  • the first and second devices, 100 and 200 are aligned with one another so that the first source/drain metal of each device 150 and 250 align with one another to make electrical contact there between. Also, the gate metal, 155 and 255 , of each device is also aligned and put in electrical contact with one another.
  • the first and second devices, 100 and 200 may be fabricated and bonded in virtually any appropriate manner to align virtually any metal contact of the first device 100 with a metal contact of the second device 200 as desired.
  • the bonding layer 305 bonds the second device 200 to the first device 100 using methods and materials well known in the art for bonding one device to another.
  • the bonding layer 305 may include any insulating substance capable of bonding a first semiconductor device to a second semiconductor device, such as, for example, a nanocleave method.
  • Other examples of bonding layers include contact adhesive and expoxies. Further examples of bonding layers include certain oxides used for bonding purposes well know in the art.
  • the bonding layer 305 should be applied so as not to interfere with the electrical connection or gate interconnect 310 between the two gate metals 155 and 255 and the electrical connection or source/drain interconnect 315 between the two source/drain metals 150 and 250 . This may include applying the bonding layer 305 so it is clear of the gate metals 155 and 255 and the source/drain metals 150 and 250 . Where appropriate, the bonding layer may also be applied in a viscous state so that it flows from the gate metal, 155 and 255 , and source/drain metal, 150 and 250 , surfaces when the surfaces make contact with one another.
  • the first device 100 may be clamped to the second device 200 with an external clamping force.
  • the external clamping force may obviate the need to use a bonding layer between the two devices (also represented as reference numeral 305 ).
  • metal plugs may be formed to the interconnections, 310 and 315 , the first and second devices, 100 and 200 .
  • the source/drain interconnection 315 may be connected to a metal plug.
  • the source/drain of the lower device may be connected to a voltage source V ss .
  • the gate interconnection 310 may be connected to a metal plug to receive a voltage input V in .
  • the separate source/drain metals, 160 and 260 may be separately connected to respective wire or plugs.
  • the inverted multilayer device 300 of FIG. 3 where the first device 100 is a pFET and the second device 200 is an nFET, is configured to function as a CMOS inverter.
  • the CMOS inverter is configured to occupy half the surface area on an IC chip due to its inverted multilayer structure.
  • the first and second devices, 100 and 200 , of the CMOS device 300 are internally connected to one another with a minimum number of metal wires due to the inverted position of the second device, thereby simplifying the input and output leads to the CMOS device 300 .
  • the second device 200 is inverted or flipped over, the respective substrates, 105 and 205 , of each device are exposed thereby enhancing the heat dissipation from each device. Also, in this manner, since the first and second devices 100 and 200 are formed separately, and then combined, it is possible to obtain a stacked structure with an inverted layer or device having a different crystal orientation in its active region relative to the other layer or device.
  • FIG. 3 shows an embodiment of an inverted multilayer device in accordance with the invention, and may equally represent a fabrication process or an apparatus or device.
  • the multilayer device 300 includes a first device 100 , for example, a pFET, onto which a second device 200 , for example, an nFET, is bonded in an inverted position.
  • the first device 100 and the second device 200 each have a different crystal orientation from one another in the active region of the multilayer device 300 .
  • the method and apparatus includes forming an integrated circuit having two semiconductor layers bonded together, where a semiconductor layer is rotated 180 degrees with respect to the other semiconductor layer, and each semiconductor layer has a crystal orientation different from the other. Rotating and bonding the semiconductor layers improves the connectability and heat transfer properties of the final structure.
  • inverted multilayer SOI device advantages include a reduction of about 50% of the area needed to create a circuit and using different crystal orientations for different devices. Additionally, where inverted multilayer devices are symmetrical, photolithography masks may be shared.

Abstract

An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.

Description

FIELD OF THE INVENTION
The invention relates to stacked circuits, and more particularly to a stacked circuit having an inverted device and to a stacked circuit having an inverted device with a different crystal orientation.
BACKGROUND DESCRIPTION
SOI (Silicon On Insulator) technology reduces or eliminates bulk CMOS latch-up problems. Additionally, SOI technology reduces junction capacitance and allows circuits to operate at higher speeds. Accordingly, SOI technology allows a higher circuit density to be achieved on a silicon wafer.
A multiple layer device structure can be created using SOI technology. Each level of a multilevel structure created using SOI may be interconnected using vertical plugs. Metal connections can be used at any level. In a multilevel device, NMOS and PMOS devices may each be restricted to a separate level, or NMOS and PMOS devices may be intermixed on a single level. However, having multiple levels where each level requires a set of separate metal connections may result in a large number of metal connections, increasing the complexity and costs of the chip. Furthermore, a layer of a multilevel device may inhibit cooling of adjacent layers by limiting heat transfer therefrom.
For some types of semiconductor devices, it is advantageous to have multiple layers of similar semiconductor material, where each layer has a crystal orientation different from the adjoining layers. When multi-layer devices are formed from a common semiconductor layer they will have the same crystal orientation from one level to the next. This limitation on the crystal orientation across multiple levels of an integrated circuit results from constraints imposed by the fabrication process.
In particular, semiconductor material is traditionally grown from a pre-existing layer of semiconductor material. During the material growth process, the atoms of the newly formed layer have a strong tendency to orient themselves to the pre-existing substrate's crystal structure as they are laid down. Thus, it becomes very difficult to create a new layer of similar semiconductor material having a crystal orientation which is different from the underlying layer.
SUMMARY OF THE INVENTION
In a first aspect of the invention, a method of forming a semiconductor device assembly includes forming a first semiconductor device having a first crystal region and a second semiconductor device having a second crystal region. The first semiconductor device is placed in contact with the second semiconductor device.
In another aspect of the invention, the method includes forming a first semiconductor device having a first crystal orientation in a substrate and forming a second semiconductor device having a second crystal orientation in a substrate. The first semiconductor device is placed in contact with the second semiconductor device.
In yet another aspect of the invention, the semiconductor device assembly includes an NMOS device having a first crystal orientation and a PMOS device having a second crystal orientation inverted on a surface of the NMOS device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 and 2 illustrate devices for forming an inverted multilayer semiconductor device in accordance with the invention; and
FIG. 3 illustrates an inverted multilayer semiconductor device in accordance with the invention.
 DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
In embodiments of the invention, a first CMOS device, such as a pFET, is formed having a first crystal orientation in the active region of the device, and a second CMOS device, such as an nFET, is formed having a second crystal orientation in the active region of the second device. After both devices are formed, the second device is flipped over and bonded to the first device with a bonding layer such as SiO2 forming an inverted stacked or an inverted multi-layered arrangement. At lease one of the contacts of the first device is aligned with the corresponding contact of the second device, and the two contacts are brought into electrical contact with one another during bonding. Because the two devices are bonded in an inverted stacked arrangement, the devices are easily interconnected along the boundary between the two devices. Thus, it is possible to form stacked layers of CMOS devices where each layer has either the same or a different crystal orientation in the active region as a layer below it and/or a layer above it, and the combination of devices has a reduced number of connections.
Referring to FIG. 1, a first device 100 has silicon (Si) substrate 105 with a crystal orientation of [110] and a first SiO2 layer 107 formed on top of the first Si substrate 105. A first Si layer 120 also having a crystal orientation of [110] is formed on the SiO2 layer 107. Trenches are etched and filled with an insulating material such as an oxide to form shallow trench isolations 110 on either side of the active region of the first Si layer 120. Source/drain regions 115 are formed next to shallow trench isolations 110 in the first Si layer 120. The source/drain regions 115 are formed by any of the methods well known in the art for forming source/drain regions.
The upper surface of the first Si layer 120 is planarized after the source/drain regions 115 are formed using any of the methods well known in the art to planarize a Si layer. A second SiO2layer 125 is formed over a surface of the first Si layer 120. A polysilicon gate 130 is formed on top of the second SiO2 layer 125 such that a portion of the second SiO2 layer 125 forms a gate oxide for the first gate 130 of the first device 100.
A CA gate contact 140 is formed on the gate 130 and a metal (M1) contact 155 is formed on the gate contact 140. Source/drain CA contacts 135 and 145 are formed on the source/drains 115. Source/ drain MI 160 and 150 and gate metal 155 are formed thereon, respectively.
A dielectric 165 is formed over the top of the first device 100, and the top of the dielectric 165 is planarized. Additionally, the dielectric 165 may be etched so that the gate metal 155 and the source/drain metal 150 are slightly higher than the surrounding dielectric 165 to facilitate making positive contact thereon during a later bonding process. Such an etching process may include etching the top surface of the dielectric 165 with an etchant which selectively removes dielectric material, but does not remove the material of the gate metal 155 and source/drain metals 150. Alternatively, the gate metal 155 and drain/source metal 150 may be protected by a mask while the top surface of the dielectric 165 is etched.
Another method to raise the gate metal 155 and source/drain metal 150 above the top surface of the dielectric 165 may include planarizing the dielectric 165, a gate metal 155 and source/drain metal 150, and building up the gate metal 155 and source/drain metal 150 to stand slightly above the top surface of the dielectric 165. Such a build-up process may include masking the surrounding dielectric 165 to leave the gate metal 155 and source/drain metal 150 exposed, and depositing or growing a suitable conductive material on the exposed gate metal 155 and source/drain metal 150.
Referring to FIG. 2, a second device 200 is also formed using similar Fabrication methods appropriate for producing the second device 200. However, the second device 200 may have a crystal orientation in its active region different from the first device 100. This is possible due to the separate fabrication processes of each of the devices, prior to inverting the second device 200 bonding. Accordingly, a second Si substrate 205 having a crystal orientation of [100] has a second SiO2 layer 207 formed thereon. The second SiO2 layer 207 has a second Si layer 220 formed on top. The second Si layer 220 is formed to include an active region of the second device 200 and is arranged over the second Si layer 207.
Trenches are etched into the second Si layer 207 and filled with an insulator such as an oxide using any of the methods well known in the art for forming and filling a trench to create shallow trench isolations 210. Source/drain regions 215 are formed on each side of an active region 225. The source/drain regions 215 of the second device 200 are formed by any of the methods well known in the art for forming source/drain regions 215. A portion of the N-well 212 lies between the shallow trench isolation 210 and the source/drain regions 215.
After the source/drain regions 215 are formed in the second device 200, a gate oxide 225 is formed on top of the active region of the second Si layer 220. The gate oxide 225 may be formed by any of the techniques well known in the art for forming a gate oxide. After the gate oxide 225 is formed, a polysilicon gate 230 is formed over the gate oxide 225. A CA contact 240 is formed on the poly gate 230 and a metal (M1) 255 is formed on the CA contact 240. Source/drain M1 contacts 235 and 245 are formed on the source/drains 215. Source/ drain metals 260 and 250 are formed thereon, respectively.
A dielectric 265 is formed over the top of the first device. As discussed with the first device, 100, the second device is formed so that the gate metal 255 and source/drain metal 250 protrude slightly above the dielectric 265 surface. For example, the top of the dielectric is planarized and then etched to leave the tops of the gate metal 255 and a source/drain metal 250 slightly protruding above the surrounding surface, depending on the connection.
Referring to FIG. 3, once the first device 100 and the second device 200 are formed, the second device 200 is inverted and bonded to the top of the first device 100 with a bonding layer 305. The bonding layer 305 attaches a top of the first device 100 to the top of the second device 200. The first and second devices, 100 and 200, are aligned with one another so that the first source/drain metal of each device 150 and 250 align with one another to make electrical contact there between. Also, the gate metal, 155 and 255, of each device is also aligned and put in electrical contact with one another. The first and second devices, 100 and 200, may be fabricated and bonded in virtually any appropriate manner to align virtually any metal contact of the first device 100 with a metal contact of the second device 200 as desired.
The bonding layer 305 bonds the second device 200 to the first device 100 using methods and materials well known in the art for bonding one device to another. The bonding layer 305 may include any insulating substance capable of bonding a first semiconductor device to a second semiconductor device, such as, for example, a nanocleave method. Other examples of bonding layers include contact adhesive and expoxies. Further examples of bonding layers include certain oxides used for bonding purposes well know in the art.
The bonding layer 305 should be applied so as not to interfere with the electrical connection or gate interconnect 310 between the two gate metals 155 and 255 and the electrical connection or source/drain interconnect 315 between the two source/ drain metals 150 and 250. This may include applying the bonding layer 305 so it is clear of the gate metals 155 and 255 and the source/ drain metals 150 and 250. Where appropriate, the bonding layer may also be applied in a viscous state so that it flows from the gate metal, 155 and 255, and source/drain metal, 150 and 250, surfaces when the surfaces make contact with one another.
As an alternative to a bonding layer, the first device 100 may be clamped to the second device 200 with an external clamping force. The external clamping force may obviate the need to use a bonding layer between the two devices (also represented as reference numeral 305).
After the first device 100 and the second device 200 are bonded to one another, metal plugs may be formed to the interconnections, 310 and 315, the first and second devices, 100 and 200. For example, the source/drain interconnection 315 may be connected to a metal plug. Similarly the source/drain of the lower device may be connected to a voltage source Vss. The gate interconnection 310 may be connected to a metal plug to receive a voltage input Vin. The separate source/drain metals, 160 and 260 may be separately connected to respective wire or plugs.
In operation, the inverted multilayer device 300 of FIG. 3, where the first device 100 is a pFET and the second device 200 is an nFET, is configured to function as a CMOS inverter. The CMOS inverter is configured to occupy half the surface area on an IC chip due to its inverted multilayer structure. The first and second devices, 100 and 200, of the CMOS device 300 are internally connected to one another with a minimum number of metal wires due to the inverted position of the second device, thereby simplifying the input and output leads to the CMOS device 300. Additionally, because the second device 200 is inverted or flipped over, the respective substrates, 105 and 205, of each device are exposed thereby enhancing the heat dissipation from each device. Also, in this manner, since the first and second devices 100 and 200 are formed separately, and then combined, it is possible to obtain a stacked structure with an inverted layer or device having a different crystal orientation in its active region relative to the other layer or device.
In other words, FIG. 3 shows an embodiment of an inverted multilayer device in accordance with the invention, and may equally represent a fabrication process or an apparatus or device. The multilayer device 300 includes a first device 100, for example, a pFET, onto which a second device 200, for example, an nFET, is bonded in an inverted position. The first device 100 and the second device 200 each have a different crystal orientation from one another in the active region of the multilayer device 300. Thus, the method and apparatus includes forming an integrated circuit having two semiconductor layers bonded together, where a semiconductor layer is rotated 180 degrees with respect to the other semiconductor layer, and each semiconductor layer has a crystal orientation different from the other. Rotating and bonding the semiconductor layers improves the connectability and heat transfer properties of the final structure.
Other advantages of the inverted multilayer SOI device include a reduction of about 50% of the area needed to create a circuit and using different crystal orientations for different devices. Additionally, where inverted multilayer devices are symmetrical, photolithography masks may be shared.
While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

Claims (9)

1. A semiconductor device assembly comprising:
a pFET device comprising a first substrate having a first crystal orientation;
an nFET device comprising a second substrate having a second crystal orientation different from the first crystal orientation,
wherein the nFET device is inverted on a surface of the pFET device such that a first dielectric layer of the pFET device is bonded to a second dielectric layer of the nFET device between the first substrate and the second substrate,
a first gate contact of a first gate of the pFET device is aligned with and in direct contact with a second gate contact of a second gate of the nFET device, and
a first metal source/drain contact of the pFET device is aligned with and in direct contact with a second metal source/drain contact of the nFET device.
2. The semiconductor device assembly of claim 1, wherein the first crystal orientation is [110] and the second crystal orientation is [100].
3. The semiconductor device assembly of claim 1, wherein the first substrate and the second substrate are exposed for enhancing heat dissipation.
4. The semiconductor device assembly of claim 1, wherein the first substrate and the second substrate are exposed.
5. The device of claim 1, wherein the pFET and nFET devices are separately formed.
6. A semiconductor device assembly, comprising:
a first device having a first crystal orientation;
a separately formed second device having a second crystal orientation different from the first crystal orientation inverted on a surface of the first device;
a source/drain metal of the first device being aligned with and in direct contact with a source/drain metal of the second device;
a gate metal of the first device being aligned with and in direct contact with a gate metal of the second device; and
a bonding layer bonding the first device to the second device, wherein the bonding layer is clear of the gate metal of the first device and the gate metal of the second device.
7. The device of claim 6, wherein the first device is a pFET and the second device is an nFET.
8. A semiconductor device assembly, comprising:
an NMOS device having a first crystal orientation; and
a PMOS device having a second crystal orientation different from the first crystal orientation inverted on a surface of the NMOS device,
wherein a first substrate of the NMOS device and a second substrate of the PMOS device are exposed for enhancing heat dissipation from each device,
the NMOS device comprises:
a first SiO2 layer arranged on the first substrate, and
a first Si layer, first shallow trench isolation regions, and first source/drain regions formed on the first SiO2 layer, and
the PMOS device comprises:
a second SiO2 layer arranged on the second substrate,
a second Si layer, second shallow trench isolation regions, second source/drain regions, and N-wells formed on the second SiO2 layer
a first gate contact of a first gate of the PMOS device is aligned with and in direct contact with a second gate contact of a second gate of the NMOS device, and
a first metal source/drain contact of the PMOS device is aligned with and in direct contact with a second metal source/drain contact of the NMOS device.
9. The semiconductor device of claim 8, further comprising a bonding layer bonding the PMOS device to the NMOS device, wherein the bonding layer is clear of the first gate contact of the PMOS device and the second gate contact of the NMOS device, and the bonding layer comprises insulating epoxy.
US10/907,566 2005-04-06 2005-04-06 Inverted multilayer semiconductor device assembly Expired - Fee Related US7547917B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/907,566 US7547917B2 (en) 2005-04-06 2005-04-06 Inverted multilayer semiconductor device assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/907,566 US7547917B2 (en) 2005-04-06 2005-04-06 Inverted multilayer semiconductor device assembly

Publications (2)

Publication Number Publication Date
US20060226491A1 US20060226491A1 (en) 2006-10-12
US7547917B2 true US7547917B2 (en) 2009-06-16

Family

ID=37082397

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/907,566 Expired - Fee Related US7547917B2 (en) 2005-04-06 2005-04-06 Inverted multilayer semiconductor device assembly

Country Status (1)

Country Link
US (1) US7547917B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032274A1 (en) * 2010-08-09 2012-02-09 International Business Machines Corporation Vertically Stacked FETs With Series Bipolar Junction Transistor
US9275911B2 (en) 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US20170338216A1 (en) * 2016-05-17 2017-11-23 X-Celeprint Limited Compound micro-transfer-printed power transistor device
US11152395B1 (en) 2020-11-12 2021-10-19 X-Celeprint Limited Monolithic multi-FETs

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7348658B2 (en) * 2004-08-30 2008-03-25 International Business Machines Corporation Multilayer silicon over insulator device
US20070145367A1 (en) * 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
US7670927B2 (en) * 2006-05-16 2010-03-02 International Business Machines Corporation Double-sided integrated circuit chips
US8013342B2 (en) * 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
US8101996B2 (en) 2008-04-15 2012-01-24 Fairchild Semiconductor Corporation Three-dimensional semiconductor device structures and methods
US8445320B2 (en) * 2010-05-20 2013-05-21 International Business Machines Corporation Graphene channel-based devices and methods for fabrication thereof
TW201238024A (en) * 2011-03-11 2012-09-16 Univ Nat Chiao Tung Three-dimensional complementary metal oxide semiconductor device
US8618647B2 (en) * 2011-08-01 2013-12-31 Tessera, Inc. Packaged microelectronic elements having blind vias for heat dissipation

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612083A (en) * 1984-07-20 1986-09-16 Nec Corporation Process of fabricating three-dimensional semiconductor device
US5057898A (en) 1989-11-24 1991-10-15 Sharp Kabushiki Kaisha Double-gated semiconductor memory device
US5426072A (en) 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5889302A (en) 1997-04-21 1999-03-30 Advanced Micro Devices, Inc. Multilayer floating gate field effect transistor structure for use in integrated circuit devices
US6075268A (en) * 1996-11-07 2000-06-13 Advanced Micro Devices, Inc. Ultra high density inverter using a stacked transistor arrangement
US6124615A (en) 1998-05-04 2000-09-26 United Microelectronics Corp. Stacked semiconductor structure for high integration of an integrated circuit with junction devices
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US20030094674A1 (en) 2000-10-25 2003-05-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor wafer
US6590258B2 (en) 2000-03-17 2003-07-08 International Business Machines Corporation SIO stacked DRAM logic
US6670677B2 (en) 2001-05-22 2003-12-30 Samsung Electronics Co., Ltd. SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon
US20040144979A1 (en) 2002-10-03 2004-07-29 Arup Bhattacharyya High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
US20040146701A1 (en) 2002-11-28 2004-07-29 Kazuo Taguchi Semiconductor substrate having SOI structure and manufacturing method and semiconductor device thereof
US6815278B1 (en) 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US20050277260A1 (en) 2004-06-14 2005-12-15 Cohen Guy M Mixed orientation and mixed material semiconductor-on-insulator wafer
US20060003554A1 (en) 2004-06-30 2006-01-05 International Business Machines Corporation Structure and method for manufacturing planar soi substrate with multiple orientations
US20060049460A1 (en) * 2004-05-28 2006-03-09 Hung-Wei Chen CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612083A (en) * 1984-07-20 1986-09-16 Nec Corporation Process of fabricating three-dimensional semiconductor device
US5057898A (en) 1989-11-24 1991-10-15 Sharp Kabushiki Kaisha Double-gated semiconductor memory device
US5426072A (en) 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US6075268A (en) * 1996-11-07 2000-06-13 Advanced Micro Devices, Inc. Ultra high density inverter using a stacked transistor arrangement
US5889302A (en) 1997-04-21 1999-03-30 Advanced Micro Devices, Inc. Multilayer floating gate field effect transistor structure for use in integrated circuit devices
US6124615A (en) 1998-05-04 2000-09-26 United Microelectronics Corp. Stacked semiconductor structure for high integration of an integrated circuit with junction devices
US6590258B2 (en) 2000-03-17 2003-07-08 International Business Machines Corporation SIO stacked DRAM logic
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US20030094674A1 (en) 2000-10-25 2003-05-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor wafer
US6670677B2 (en) 2001-05-22 2003-12-30 Samsung Electronics Co., Ltd. SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon
US20040144979A1 (en) 2002-10-03 2004-07-29 Arup Bhattacharyya High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters
US20040146701A1 (en) 2002-11-28 2004-07-29 Kazuo Taguchi Semiconductor substrate having SOI structure and manufacturing method and semiconductor device thereof
US6815278B1 (en) 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050045995A1 (en) 2003-08-25 2005-03-03 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US20060049460A1 (en) * 2004-05-28 2006-03-09 Hung-Wei Chen CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
US20050277260A1 (en) 2004-06-14 2005-12-15 Cohen Guy M Mixed orientation and mixed material semiconductor-on-insulator wafer
US7125785B2 (en) 2004-06-14 2006-10-24 International Business Machines Corporation Mixed orientation and mixed material semiconductor-on-insulator wafer
US20070015346A1 (en) 2004-06-14 2007-01-18 International Business Machines Corporation Mixed orientation and mixed material semiconductor-on-insulator wafer
US20060003554A1 (en) 2004-06-30 2006-01-05 International Business Machines Corporation Structure and method for manufacturing planar soi substrate with multiple orientations
US20060237790A1 (en) 2004-06-30 2006-10-26 International Business Machines Corporation Structure and method for manufacturing planar SOI substrate with multiple orientations

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, "Stacked Technology for Random-Access Memory Construction", vol. 29, No. 8, Jan. 1987, pp. 3428-3429.
S. J. Abou-Samra et al., "3D CMOS SOI for High Performance Computing", International Symposium on Low Power Electronics and Design, 1998 Proceedings, Aug. 10-12, 1998.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032274A1 (en) * 2010-08-09 2012-02-09 International Business Machines Corporation Vertically Stacked FETs With Series Bipolar Junction Transistor
US8492220B2 (en) * 2010-08-09 2013-07-23 International Business Machines Corporation Vertically stacked FETs with series bipolar junction transistor
US9275911B2 (en) 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US20170338216A1 (en) * 2016-05-17 2017-11-23 X-Celeprint Limited Compound micro-transfer-printed power transistor device
US10037985B2 (en) * 2016-05-17 2018-07-31 X-Celeprint Limited Compound micro-transfer-printed power transistor device
US11152395B1 (en) 2020-11-12 2021-10-19 X-Celeprint Limited Monolithic multi-FETs
US11705457B2 (en) 2020-11-12 2023-07-18 X-Celeprint Limited Monolithic multi-FETS

Also Published As

Publication number Publication date
US20060226491A1 (en) 2006-10-12

Similar Documents

Publication Publication Date Title
US7547917B2 (en) Inverted multilayer semiconductor device assembly
US10756056B2 (en) Methods and structures for wafer-level system in package
US7326642B2 (en) Method of fabricating semiconductor device using low dielectric constant material film
US6544837B1 (en) SOI stacked DRAM logic
JP5246831B2 (en) Electronic device and method of forming the same
US7790608B2 (en) Buried via technology for three dimensional integrated circuits
DE112007000267B4 (en) Method for producing a semiconductor device
US7863117B2 (en) Multilayer silicon over insulator device
KR101120805B1 (en) Metal filled through via structure for providing vertical wafer-to-wafer interconnection
TWI512896B (en) Metal pad structure over tsv to reduce shorting of upper metal layer
US10930619B2 (en) Multi-wafer bonding structure and bonding method
CN106935543A (en) Semiconductor structure and forming method thereof
US20070145367A1 (en) Three-dimensional integrated circuit structure
US20120280357A1 (en) Method of Forming an Isolation Structure
US10315915B2 (en) Electronic systems with through-substrate interconnects and MEMS device
US11189538B2 (en) Semiconductor structure with polyimide packaging and manufacturing method
TW202143426A (en) Semiconductor package with air gap and manufacturing method thereof
TW201841311A (en) Segmented guard-ring and chip edge seals
US9461017B1 (en) Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement
CN100483721C (en) Semiconductor device and method of fabricating the same
KR101064288B1 (en) Methode of forming a contact hole in semiconductor device
US7153756B1 (en) Bonded SOI with buried interconnect to handle or device wafer
US20240021470A1 (en) Semiconductor device and manufacturing method therefor
US20230253322A1 (en) Nano-tsv landing over buried power rail
US7880261B2 (en) Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GAUTHIER, JR., ROBERT J.;MOUSA, MAHMOUD A.;PUTNAM, CHRISTOPHER S.;REEL/FRAME:015864/0872;SIGNING DATES FROM 20050311 TO 20050315

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20130616