|Publication number||US7538371 B2|
|Application number||US 11/162,228|
|Publication date||26 May 2009|
|Filing date||1 Sep 2005|
|Priority date||1 Sep 2005|
|Also published as||US7491596, US20070045763, US20070184571|
|Publication number||11162228, 162228, US 7538371 B2, US 7538371B2, US-B2-7538371, US7538371 B2, US7538371B2|
|Original Assignee||United Microelectronics Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (1), Referenced by (3), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a CMOS image sensor integrated with a static random access memory (SRAM), and more particularly, to a CMOS image sensor integrated with a one-transistor static random access memory (1T-SRAM) of ultra-density.
2. Description of the Prior Art
Complementary metal-oxide semiconductor (CMOS) image sensors are produced by using conventional semiconductor techniques, which can fabricate the image sensor and the related peripheral circuit simultaneously. When compared with a charge-coupled device (CCD), which requires 30 to 40 mask processes during manufacture, the CMOS image sensor only requires approximately 20 mask processes. CMOS sensors not only simplify the manufacturing process, but also reduce cost. In addition, CMOS image sensors have advantages of small size, high quantum efficiency, and low read-out noise.
However, since memory, such as dynamic random access memory (DRAM) and image sensor devices are manufactured on different chips, miniaturization of the image system is difficult. U.S. Pat. No. 6,563,187 teaches a CMOS image sensor, and particularly, a CMOS image sensor integrated with image sensor devices, a related signal processing circuit, and memory, such as DRAM or SRAM to reduce the cost and the power consumption.
However, a typical DRAM has to check a voltage on its capacitor periodically, and needs to charge or discharge in order to refresh the capacitor. In addition, if the image sensor is integrated with an SRAM comprising 4 to 6 transistors, it will have an area of more than 4 times the area of an image sensor integrated with a DRAM. The result is a reduced integrity, and a less than compact size. Additionally, the method disclosed in the '187 patent is to integrate the memory after all the logic devices have been formed. Such a process is overly complicated.
Therefore, a primary object of the present invention is to provide a CMOS image sensor integrated with 1T-SRAM of ultra-high density and a fabrication method thereof.
According to one of the preferred embodiments of the invention, a semiconductor substrate is provided. The substrate has a pixel array part, a logic circuit part, and a memory part defined therein. The pixel array part, the logic circuit part, and the memory part are isolated from each other by a plurality of shallow trench isolation (STI) regions. There are a plurality of CMOS image sensor devices in the pixel array part, a logic circuit in the logic circuit part, and a plurality of 1T-SRAM cells in the memory part. An 1T-SRAM cell includes a capacitor structure and a transistor. The capacitor structure includes a well region formed by implanting ions in the substrate as a bottom capacitor plate, a capacitor dielectric layer formed above the well region, and a top capacitor plate formed above the dielectric layer. The transistor includes a gate dielectric layer, a gate, a drain, and a source continuous with the well region beneath the top capacitor plate and electrically connecting to it. The capacitor dielectric layer of the capacitor structure and the gate dielectric layer of the transistor are the same layer.
The capacitor dielectric layer of the capacitor structure provided by the present invention can be the same layer as the gate dielectric layer of the transistor, which means that the capacitor dielectric layer of the capacitor structure and the gate dielectric layer of the transistor are formed simultaneously. Similarly, the top capacitor plate of the capacitor structure and the gate of the transistor are also formed simultaneously. Therefore the present invention provides a CMOS image sensor integrating ultra-high density 1T-SRAM with logic devices by adding only one photomask process to the whole logic process.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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In addition, to satisfy the demand of high integrity and high capacitor area, the present invention also provides a second preferred embodiment. As described above, the second embodiment also provides a substrate 100, such as a wafer, on which a pixel array part 40, a logic circuit part 60, and a memory part 80 are defined in specific areas. A P well 102 is formed in the pixel array part 40, an N well 104 is formed in the logic circuit part 60, and another P well 106 is formed in the memory part 80. There are plurality of STI regions 108 formed in the substrate 100 to isolate the pixel array part 40, the logic circuit 60, and the memory part 80.
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Furthermore, the present invention provides a third preferred embodiment which relates to a CMOS image sensor integrated with 1T-SRAM having a deep-trenched capacitor. Please refer to
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According to the present invention, a CMOS image sensor integrated with the image sensor devices, the logic circuit, and the 1T-SRAM is provided. Compared with the conventional technique, the claimed invention is a CMOS image sensor integrated with ultra-density 1T-SRAM by only adding one photo mask process to the logic process.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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|TW264775B||Title not available|
|TWI230370B||Title not available|
|1||Wingyu Leung et al., "The Ideal SoC Memory: 1T-SRAM", ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International Volume, Issue, 2000 pp. 32-36.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9106858||1 Oct 2013||11 Aug 2015||Samsung Electronics Co., Ltd.||Image sensor, method of operating the same, and image processing system including the same|
|US9773922||28 Oct 2016||26 Sep 2017||United Microelectronics Corp.||Memory device|
|US9800814||3 Aug 2015||24 Oct 2017||Samsung Electronics Co., Ltd.||Image sensor, method of operating the same, and image processing system including the same|
|U.S. Classification||257/290, 257/303, 257/306, 257/532|
|Cooperative Classification||H01L27/14689, H01L27/14643, H01L27/11, H01L27/14609|
|European Classification||H01L27/146A4, H01L27/146V6, H01L27/11|
|1 Sep 2005||AS||Assignment|
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YANG, JINSHENG;REEL/FRAME:016485/0755
Effective date: 20050828
|4 Oct 2012||FPAY||Fee payment|
Year of fee payment: 4
|16 Oct 2016||FPAY||Fee payment|
Year of fee payment: 8