US7468325B2 - Method of cleaning silicon nitride layer - Google Patents

Method of cleaning silicon nitride layer Download PDF

Info

Publication number
US7468325B2
US7468325B2 US11/319,617 US31961705A US7468325B2 US 7468325 B2 US7468325 B2 US 7468325B2 US 31961705 A US31961705 A US 31961705A US 7468325 B2 US7468325 B2 US 7468325B2
Authority
US
United States
Prior art keywords
silicon nitride
nitride layer
solution
cleaning
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/319,617
Other versions
US20060141803A1 (en
Inventor
Dae Heok Kwon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Assigned to DONGBUANAM SEMICONDUCTOR, INC. reassignment DONGBUANAM SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KWON, DAE HEOK
Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU-ANAM SEMICONDUCTOR, INC.
Publication of US20060141803A1 publication Critical patent/US20060141803A1/en
Application granted granted Critical
Publication of US7468325B2 publication Critical patent/US7468325B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

Definitions

  • the present invention relates generally to a wafer cleaning technique in semiconductor fabrication and, more particularly, to a method of cleaning a silicon nitride layer so as to effectively remove impurities such as polymer and particle from the silicon nitride layer.
  • a silicon nitride layer has a denser and tighter structure in comparison with a silicon oxide layer, so the silicon nitride layer has excellent ability to prevent infiltration of moisture or alkali ions, and thus is typically used as a passivation layer. Furthermore, the silicon nitride layer is not oxidized and prevents oxidation of underlying silicon layer, so the silicon nitride layer is often used as a masking layer for selective oxidation. The silicon nitride layer is also used as an ion implant mask for suppressing diffusion of oxygen or other elements during the ion implantation process.
  • the silicon nitride layer has positive zeta potential and strongly attracts negatively-charged impurities such as polymer and particle, so such impurities can be hardly removed from the silicon nitride layer.
  • the potential at the solid surface 11 is referred to as the surface potential ( ⁇ 0 ).
  • a degree of diffusion of reversely charged ions is represented by the Debye parameter ( ⁇ ), and its inverse ( ⁇ ⁇ 1 ) represents the thickness of the electrical double layer 13 .
  • the silicon nitride layer has the force of strongly attracting negatively-charged impurities such as polymer and particle. So, although a cleaning process is performed, such impurities can be hardly removed from the silicon nitride layer.
  • Conventional techniques of removing impurities from the silicon nitride layer include a spin scrubber cleaning method, a chloric/ozone mix cleaning method using a mixed solution of hydrochloric acid (HCl) and ozone (O 3 ), and a SC-1 (standard cleaning-1) method using a mixed solution of ammonium hydroxide, hydrogen peroxide, and water.
  • Exemplary, non-limiting embodiments of the present invention provide a method of cleaning a silicon nitride layer on a substrate so as to effectively remove negatively-charged impurities such as polymers and particles from the silicon nitride layer by changing the zeta potential of the silicon nitride layer from positive to negative.
  • the method can further comprise, before the changing of the zeta potential, treating the substrate with spin scrubber or quick dump rinse. Also, the method can further comprise, before the cleaning of the silicon nitride layer, treating the substrate with spin scrubber or quick dump rinse.
  • the changing of the zeta potential can include dipping the substrate into a second solution selected from the group consisting of an SC-1 solution, an NC-2 solution, and an alkali solution.
  • the second solution can further have surfactant.
  • the alkali solution can be an ammonium hydroxide solution or a tri-methyl ammonium hydroxide solution and can maintain the normal temperature.
  • the changing of the zeta potential can be performed without using vibrators.
  • the cleaning of the silicon nitride layer can be performed with a vibrator used.
  • the cleaning of the silicon nitride layer with the NC-2 solution can have a mixing ratio of 1:2 ⁇ 5:30 ⁇ 50 in TMH:H 2 O 2 :H 2 O and can be performed at a temperature of about 50° C. to about 80° C.
  • FIG. 1 is a diagrammatic view illustrating zeta potential.
  • FIG. 2 is a graph showing the zeta potentials of a silicon nitride layer, an HDP-CVD oxide layer, and a silicon substrate.
  • an initial step (S 101 ) is to treat a substrate having the silicon nitride layer with spin scrubber or quick dump rinse (QDR) so as to remove relatively greater impurities from the silicon nitride layer.
  • QDR quick dump rinse
  • the next step (S 102 ) is to change the zeta potential of the silicon nitride layer from positive to negative.
  • the substrate is dipped into an adequate solution, such as an SC-1 solution, an NC-2 (new cleaning-2) solution, and/or an alkali solution.
  • an adequate solution such as an SC-1 solution, an NC-2 (new cleaning-2) solution, and/or an alkali solution.
  • the next step (S 103 ) is to treat again the substrate with a spin scrubber or QDR so as to remove impurities from the silicon nitride layer. Since the zeta potential of the silicon nitride layer is changed to negative, impurities sticking onto the silicon nitride layer can be easily removed due to a repulsion force. This step, however, can be skipped if the subsequent cleaning step has a sufficient cleaning effect.
  • the final step (S 104 ) is to clean the silicon nitride layer with an alkali solution or an NC-2 solution so as to completely remove impurities from the silicon nitride layer.
  • an NC-2 solution can have a mixing ratio of about 1:2 ⁇ 5:30 ⁇ 50 in TMH:H 2 O 2 :H 2 O and can maintain a temperature of about 50° C. to about 80° C. It is also desirable that a suitable vibrator is used to improve cleaning efficiency.
  • FIG. 4 is a cross-sectional view for illustrating the method shown in FIG. 3 .
  • a semiconductor device has typically a silicon substrate 200 , an isolation oxide layer 202 , a gate oxide layer 204 , a polysilicon gate 206 , source/drain (not shown), a sidewall spacer 208 , and a silicide layer 210 . Furthermore, a silicon nitride (SiN) layer 212 is formed thereon with a thickness of about 35 nm, for example. The silicon nitride layer 212 is used as a liner of a pre-metal dielectric (PMD) layer.
  • PMD pre-metal dielectric
  • the silicon nitride layer 212 has positive zeta potential, and silicon series impurities 220 charged with negative are stuck onto the silicon nitride layer 212 .
  • the zeta potential of the silicon nitride layer 212 is changed to negative, such impurities 220 can be easily removed due to a repulsion force.

Abstract

A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride layer is cleaned with a first solution selected from an alkali solution and an NC-2 solution. So the negatively-charged impurities can be easily removed due to a repulsion force. The substrate can be treated with spin scrubber or quick dump rinse before and/or after the changing of the zeta potential. To change the zeta potential, the substrate can be dipped into a second solution such as an SC-1 solution, an NC-2 solution, and an alkali solution.

Description

This U.S. non-provisional application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 2004-115806, which was filed in the Korean Intellectual Property Office on Dec. 29, 2004, the contents of which are incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a wafer cleaning technique in semiconductor fabrication and, more particularly, to a method of cleaning a silicon nitride layer so as to effectively remove impurities such as polymer and particle from the silicon nitride layer.
2. Description of the Related Art
As is well known in the art, a silicon nitride layer has a denser and tighter structure in comparison with a silicon oxide layer, so the silicon nitride layer has excellent ability to prevent infiltration of moisture or alkali ions, and thus is typically used as a passivation layer. Furthermore, the silicon nitride layer is not oxidized and prevents oxidation of underlying silicon layer, so the silicon nitride layer is often used as a masking layer for selective oxidation. The silicon nitride layer is also used as an ion implant mask for suppressing diffusion of oxygen or other elements during the ion implantation process.
Additionally, the silicon nitride layer has positive zeta potential and strongly attracts negatively-charged impurities such as polymer and particle, so such impurities can be hardly removed from the silicon nitride layer.
FIG. 1 is a diagrammatic view illustrating zeta potential. As shown in FIG. 1, a solid 10 has electric charges in general at its surface 11 that adjoins an aqueous solution 12. Such charges near the solid surface 11 attract reversely charged ions existing in the aqueous solution 12, so an electrical double layer 13 is formed near the solid surface 11.
Here, the potential at the solid surface 11 is referred to as the surface potential (Ψ0). Further, a degree of diffusion of reversely charged ions is represented by the Debye parameter (κ), and its inverse (κ−1) represents the thickness of the electrical double layer 13.
The zeta potential (ζ) means the potential at the outermost of the electrical double layer 13. In most cases, the zeta potential (ζ) is similar with the Stem potential (ΨS) that means the potential at the Stem plane.
FIG. 2 is a graph showing the zeta potentials of a silicon nitride layer, an HDP-CVD oxide layer, and a silicon substrate. As is appreciated from FIG. 2, the silicon nitride layer exhibits positive zeta potential regardless of pH.
Therefore, as discussed above, the silicon nitride layer has the force of strongly attracting negatively-charged impurities such as polymer and particle. So, although a cleaning process is performed, such impurities can be hardly removed from the silicon nitride layer.
Conventional techniques of removing impurities from the silicon nitride layer include a spin scrubber cleaning method, a chloric/ozone mix cleaning method using a mixed solution of hydrochloric acid (HCl) and ozone (O3), and a SC-1 (standard cleaning-1) method using a mixed solution of ammonium hydroxide, hydrogen peroxide, and water.
However, these techniques are separately employed in general and do not use electrochemical surface properties of the silicon nitride layer. So these conventional techniques may fail to provide effective cleaning for the silicon nitride layer.
SUMMARY OF THE INVENTION
Exemplary, non-limiting embodiments of the present invention provide a method of cleaning a silicon nitride layer on a substrate so as to effectively remove negatively-charged impurities such as polymers and particles from the silicon nitride layer by changing the zeta potential of the silicon nitride layer from positive to negative.
According to one exemplary embodiment of the present invention, the method comprises changing the zeta potential of the silicon nitride layer from positive to negative, and cleaning the silicon nitride layer with a first solution selected from an alkali solution and an NC-2 solution, whereby removing impurities from the silicon nitride layer.
The method can further comprise, before the changing of the zeta potential, treating the substrate with spin scrubber or quick dump rinse. Also, the method can further comprise, before the cleaning of the silicon nitride layer, treating the substrate with spin scrubber or quick dump rinse.
In the method, the changing of the zeta potential can include dipping the substrate into a second solution selected from the group consisting of an SC-1 solution, an NC-2 solution, and an alkali solution. In this case, the second solution can further have surfactant. The alkali solution can be an ammonium hydroxide solution or a tri-methyl ammonium hydroxide solution and can maintain the normal temperature.
In the method, the changing of the zeta potential can be performed without using vibrators. On the other hand, the cleaning of the silicon nitride layer can be performed with a vibrator used.
In the method, the cleaning of the silicon nitride layer with the NC-2 solution can have a mixing ratio of 1:2˜5:30˜50 in TMH:H2O2:H2O and can be performed at a temperature of about 50° C. to about 80° C.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagrammatic view illustrating zeta potential.
FIG. 2 is a graph showing the zeta potentials of a silicon nitride layer, an HDP-CVD oxide layer, and a silicon substrate.
FIG. 3 is a flow chart showing a cleaning method of a silicon nitride layer in accordance with an exemplary embodiment of the present invention.
FIG. 4 is a cross-sectional view for illustrating the method shown in FIG. 3.
 DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION
An exemplary, non-limiting embodiment of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiment set forth herein. Rather, the disclosed embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The principles and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention.
In is noted that well-known structures and processes are not described or illustrated in detail to avoid obscuring the essence of the present invention. It is also noted that the figures are not drawn to scale.
FIG. 3 is a flow chart showing a cleaning method of a silicon nitride layer in accordance with an exemplary embodiment of the present invention.
Referring to FIG. 3, an initial step (S101) is to treat a substrate having the silicon nitride layer with spin scrubber or quick dump rinse (QDR) so as to remove relatively greater impurities from the silicon nitride layer.
The next step (S102) is to change the zeta potential of the silicon nitride layer from positive to negative. For this, the substrate is dipped into an adequate solution, such as an SC-1 solution, an NC-2 (new cleaning-2) solution, and/or an alkali solution. Here, it is desirable that traditionally used vibrators do not operate because such vibrators can cause impurities to move again toward the silicon nitride layer.
An alkali solution had better maintain the normal (predetermined) temperature and can use ammonium hydroxide or TMH (tri-methyl ammonium hydroxide). For more reliable change of the zeta potential of the silicon nitride layer, surfactant (preferably, anion surfactant) can be added to an SC-1 solution, an NC-2 solution, or an alkali solution.
The next step (S103) is to treat again the substrate with a spin scrubber or QDR so as to remove impurities from the silicon nitride layer. Since the zeta potential of the silicon nitride layer is changed to negative, impurities sticking onto the silicon nitride layer can be easily removed due to a repulsion force. This step, however, can be skipped if the subsequent cleaning step has a sufficient cleaning effect.
The final step (S104) is to clean the silicon nitride layer with an alkali solution or an NC-2 solution so as to completely remove impurities from the silicon nitride layer. Desirably, an NC-2 solution can have a mixing ratio of about 1:2˜5:30˜50 in TMH:H2O2:H2O and can maintain a temperature of about 50° C. to about 80° C. It is also desirable that a suitable vibrator is used to improve cleaning efficiency.
FIG. 4 is a cross-sectional view for illustrating the method shown in FIG. 3.
Referring to FIG. 4, a semiconductor device has typically a silicon substrate 200, an isolation oxide layer 202, a gate oxide layer 204, a polysilicon gate 206, source/drain (not shown), a sidewall spacer 208, and a silicide layer 210. Furthermore, a silicon nitride (SiN) layer 212 is formed thereon with a thickness of about 35 nm, for example. The silicon nitride layer 212 is used as a liner of a pre-metal dielectric (PMD) layer.
As discussed hereinbefore, the silicon nitride layer 212 has positive zeta potential, and silicon series impurities 220 charged with negative are stuck onto the silicon nitride layer 212. However, as the zeta potential of the silicon nitride layer 212 is changed to negative, such impurities 220 can be easily removed due to a repulsion force.
While this invention has been particularly shown and described with reference to an exemplary embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A method of cleaning a silicon nitride layer on a substrate, the method comprising:
treating the substrate with a spin scrubber or a quick dump rinse;
dipping the substrate into a second solution selected from the group consisting of an SC-1 solution, an NC-2 solution, an alkali solution and anion surfactant thereby changing a zeta potential of the silicon nitride layer-from positive to negative; and
cleaning the silicon nitride layer with a first solution selected from an alkali solution and an NC-2 solution, whereby impurities are removed from the silicon nitride layer.
2. The method of claim 1, further comprising: before the cleaning of the silicon nitride layer, treating the substrate with a spin scrubber or a quick dump rinse.
3. The method of claim 1, wherein the alkali solution is an ammonium hydroxide solution or a tri-methyl ammonium hydroxide solution.
4. The method of claim 1, wherein the alkali solution maintains a predetermined temperature.
5. The method of claim 1, wherein the changing of the zeta potential is performed without using vibrators.
6. The method of claim 1, wherein the cleaning of the silicon nitride layer is performed with a vibrator used.
7. The method of claim 1, wherein the cleaning of the silicon nitride layer with the NC-2 solution has a mixing ratio of 1:2.about.5:30.about.50 in TMH:H.sub.2O.sub.2:H.sub.2O.
8. The method of claim 1, wherein the cleaning of the silicon nitride layer with the NC-2 solution is performed at a temperature of about 50.degree. C. to about 80.degree. C.
US11/319,617 2004-12-29 2005-12-29 Method of cleaning silicon nitride layer Expired - Fee Related US7468325B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2004-0115806 2004-12-29
KR1020040115806A KR100644073B1 (en) 2004-12-29 2004-12-29 Method for cleaning silicon nitride layer

Publications (2)

Publication Number Publication Date
US20060141803A1 US20060141803A1 (en) 2006-06-29
US7468325B2 true US7468325B2 (en) 2008-12-23

Family

ID=36612313

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/319,617 Expired - Fee Related US7468325B2 (en) 2004-12-29 2005-12-29 Method of cleaning silicon nitride layer

Country Status (2)

Country Link
US (1) US7468325B2 (en)
KR (1) KR100644073B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210265181A1 (en) * 2016-04-22 2021-08-26 Toshiba Memory Corporation Substrate treatment apparatus and substrate treatment method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101033347B1 (en) * 2008-10-14 2011-05-09 주식회사 동부하이텍 Method for Manufacturing Image Sensor
KR101524930B1 (en) * 2013-09-12 2015-06-01 한양대학교 에리카산학협력단 CLEANING SOLUTION FOR NITROGEN SURFACE OF GaN SUBSTRATE AND METHOD OF CLEANING NITROGEN SURFACE OF GaN SUBSTRATE USING THE SAME
CN105702724B (en) * 2014-11-27 2019-01-22 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7216656B2 (en) * 2000-12-28 2007-05-15 Yoshiharu Yamamoto Semiconductor substrate cleansing apparatus
US7235516B2 (en) * 2001-11-16 2007-06-26 Mitsubishi Chemical Corporation Semiconductor cleaning composition comprising an ethoxylated surfactant
US7338905B2 (en) * 2004-01-21 2008-03-04 Fujitsu Limited Semiconductor device manufacture method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0684866A (en) * 1992-09-04 1994-03-25 Hitachi Ltd Prevention of adhesion of foreign matters
JPH09186116A (en) * 1995-12-27 1997-07-15 Toshiba Corp Manufacture of semiconductor device and semiconductor manufacture device
KR100672933B1 (en) 2003-06-04 2007-01-23 삼성전자주식회사 Cleaning solution and cleaning method in a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7216656B2 (en) * 2000-12-28 2007-05-15 Yoshiharu Yamamoto Semiconductor substrate cleansing apparatus
US7235516B2 (en) * 2001-11-16 2007-06-26 Mitsubishi Chemical Corporation Semiconductor cleaning composition comprising an ethoxylated surfactant
US7338905B2 (en) * 2004-01-21 2008-03-04 Fujitsu Limited Semiconductor device manufacture method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210265181A1 (en) * 2016-04-22 2021-08-26 Toshiba Memory Corporation Substrate treatment apparatus and substrate treatment method

Also Published As

Publication number Publication date
KR100644073B1 (en) 2006-11-10
KR20060076110A (en) 2006-07-04
US20060141803A1 (en) 2006-06-29

Similar Documents

Publication Publication Date Title
US6475927B1 (en) Method of forming a semiconductor device
US7303951B2 (en) Method of manufacturing a trench isolation region in a semiconductor device
Heyns et al. Cost-effective cleaning and high-quality thin gate oxides
US20050239672A1 (en) Cleaning solution of silicon germanium layer and cleaning method using the same
US7468325B2 (en) Method of cleaning silicon nitride layer
US6764967B2 (en) Method for forming low thermal budget sacrificial oxides
JP5233277B2 (en) Semiconductor substrate processing method and semiconductor device manufacturing method
US7271066B2 (en) Semiconductor device and a method of manufacturing the same
US6211045B1 (en) Incorporation of nitrogen-based gas in polysilicon gate re-oxidation to improve hot carrier performance
US6825128B2 (en) Method for manufacturing semiconductor device
US20070026582A1 (en) Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device
JP4007864B2 (en) Manufacturing method of semiconductor device
JP4108445B2 (en) Manufacturing method of semiconductor device
KR100611008B1 (en) Wafer cleaning method in the semiconductor processing
US20160276165A1 (en) Method of interfacial oxide layer formation in semiconductor device
JP2005223289A (en) Method of manufacturing semiconductor device
JP2003045894A (en) Manufacturing method for semiconductor device
KR100526046B1 (en) A fabrication method of SOI wafer
JP2010056189A (en) Method for manufacturing semiconductor device
KR20060115411A (en) Method for fabricating bit-line contact in semiconductor device
CN102270559A (en) Method for cleaning by-products in grooved power transistor
KR19990016940A (en) Gate oxide film formation method
JP2006060155A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: DONGBUANAM SEMICONDUCTOR, INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KWON, DAE HEOK;REEL/FRAME:017430/0059

Effective date: 20051223

AS Assignment

Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:DONGBU-ANAM SEMICONDUCTOR, INC.;REEL/FRAME:017663/0468

Effective date: 20060324

Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:DONGBU-ANAM SEMICONDUCTOR, INC.;REEL/FRAME:017663/0468

Effective date: 20060324

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20121223