US7414917B2 - Re-driving CAwD and rD signal lines - Google Patents
Re-driving CAwD and rD signal lines Download PDFInfo
- Publication number
- US7414917B2 US7414917B2 US11/192,335 US19233505A US7414917B2 US 7414917 B2 US7414917 B2 US 7414917B2 US 19233505 A US19233505 A US 19233505A US 7414917 B2 US7414917 B2 US 7414917B2
- Authority
- US
- United States
- Prior art keywords
- memory
- signal
- substrate
- lines
- cawd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
Landscapes
- Dram (AREA)
Abstract
Description
Claims (9)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/192,335 US7414917B2 (en) | 2005-07-29 | 2005-07-29 | Re-driving CAwD and rD signal lines |
DE102006032327A DE102006032327B4 (en) | 2005-07-29 | 2006-07-12 | Semiconductor memory module and system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/192,335 US7414917B2 (en) | 2005-07-29 | 2005-07-29 | Re-driving CAwD and rD signal lines |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070025131A1 US20070025131A1 (en) | 2007-02-01 |
US7414917B2 true US7414917B2 (en) | 2008-08-19 |
Family
ID=37650521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/192,335 Expired - Fee Related US7414917B2 (en) | 2005-07-29 | 2005-07-29 | Re-driving CAwD and rD signal lines |
Country Status (2)
Country | Link |
---|---|
US (1) | US7414917B2 (en) |
DE (1) | DE102006032327B4 (en) |
Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070109833A1 (en) * | 2005-09-30 | 2007-05-17 | Pyeon Hong B | Daisy chain cascading devices |
US20080080123A1 (en) * | 2006-09-30 | 2008-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
US20080106950A1 (en) * | 2006-11-08 | 2008-05-08 | Samsung Electronics Co., Ltd. | High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof |
US20090216939A1 (en) * | 2008-02-21 | 2009-08-27 | Smith Michael J S | Emulation of abstracted DIMMs using abstracted DRAMs |
US20100020585A1 (en) * | 2005-09-02 | 2010-01-28 | Rajan Suresh N | Methods and apparatus of stacking drams |
US20100281280A1 (en) * | 2006-07-31 | 2010-11-04 | Google Inc. | Interface Circuit System And Method For Performing Power Management Operations In Conjunction With Only A Portion Of A Memory Circuit |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8122207B2 (en) | 2006-07-31 | 2012-02-21 | Google Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8130560B1 (en) * | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8154935B2 (en) | 2006-07-31 | 2012-04-10 | Google Inc. | Delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8280714B2 (en) | 2006-07-31 | 2012-10-02 | Google Inc. | Memory circuit simulation system and method with refresh capabilities |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8566516B2 (en) | 2006-07-31 | 2013-10-22 | Google Inc. | Refresh management of memory modules |
US8654601B2 (en) | 2005-09-30 | 2014-02-18 | Mosaid Technologies Incorporated | Memory with output control |
US8705240B1 (en) | 2007-12-18 | 2014-04-22 | Google Inc. | Embossed heat spreader |
US8743610B2 (en) | 2005-09-30 | 2014-06-03 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US8773937B2 (en) | 2005-06-24 | 2014-07-08 | Google Inc. | Memory refresh apparatus and method |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8949519B2 (en) | 2005-06-24 | 2015-02-03 | Google Inc. | Simulating a memory circuit |
US8977806B1 (en) | 2006-10-05 | 2015-03-10 | Google Inc. | Hybrid memory module |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
DE102005033710B3 (en) * | 2005-07-19 | 2007-01-25 | Infineon Technologies Ag | Semiconductor memory module, has control bus connected with control chip at end and with contact holes of module plate at another end, and memory chip connected to control bus by conductor of upper surface of plate and by contact holes |
US7870459B2 (en) * | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
TW200939242A (en) * | 2008-03-11 | 2009-09-16 | Nanya Technology Corp | Memory module and method for accessing memory module |
US20090296444A1 (en) * | 2008-05-29 | 2009-12-03 | Chih-Hui Yeh | Memory module and method for accessing memory module |
US8233304B2 (en) * | 2008-07-28 | 2012-07-31 | Inphi Corporation | High speed memory module |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8345441B1 (en) | 2011-10-03 | 2013-01-01 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8513813B2 (en) | 2011-10-03 | 2013-08-20 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
US8659140B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
JP5947904B2 (en) | 2011-10-03 | 2016-07-06 | インヴェンサス・コーポレイション | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
KR101894823B1 (en) | 2011-10-03 | 2018-09-04 | 인벤사스 코포레이션 | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
KR20140069343A (en) | 2011-10-03 | 2014-06-09 | 인벤사스 코포레이션 | Stub minimization with terminal grids offset from center of package |
US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5157635A (en) * | 1989-12-27 | 1992-10-20 | International Business Machines Corporation | Input signal redriver for semiconductor modules |
US6125419A (en) * | 1996-06-13 | 2000-09-26 | Hitachi, Ltd. | Bus system, printed circuit board, signal transmission line, series circuit and memory module |
US20020023191A1 (en) * | 2000-08-21 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and memory system using the same |
US6477614B1 (en) * | 1998-09-30 | 2002-11-05 | Intel Corporation | Method for implementing multiple memory buses on a memory module |
US20040151038A1 (en) * | 2002-11-29 | 2004-08-05 | Hermann Ruckerbauer | Memory module and method for operating a memory module in a data memory system |
US20040225853A1 (en) | 2003-05-08 | 2004-11-11 | Lee Terry R. | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
US6847617B2 (en) * | 2001-03-26 | 2005-01-25 | Intel Corporation | Systems for interchip communication |
US20050142950A1 (en) | 2000-05-10 | 2005-06-30 | Rambus Inc. | Multiple channel modules and bus systems using same |
US7130958B2 (en) * | 2003-12-02 | 2006-10-31 | Super Talent Electronics, Inc. | Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes |
US7133962B2 (en) * | 2003-09-09 | 2006-11-07 | Intel Corporation | Circulator chain memory command and address bus topology |
US20060265543A1 (en) * | 2005-05-17 | 2006-11-23 | Peter Oeschay | Method for setting an address of a rank in a memory module |
US20060262632A1 (en) * | 2005-05-17 | 2006-11-23 | Intel Corporation | Identical chips with different operations in a system |
US20060285424A1 (en) * | 2005-06-15 | 2006-12-21 | Peter Gregorius | High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips |
US20060291263A1 (en) * | 2005-05-13 | 2006-12-28 | Paul Wallner | Memory system and method of accessing memory chips of a memory system |
US20070005831A1 (en) * | 2005-06-30 | 2007-01-04 | Peter Gregorius | Semiconductor memory system |
US7200693B2 (en) * | 2004-08-27 | 2007-04-03 | Micron Technology, Inc. | Memory system and method having unidirectional data buses |
-
2005
- 2005-07-29 US US11/192,335 patent/US7414917B2/en not_active Expired - Fee Related
-
2006
- 2006-07-12 DE DE102006032327A patent/DE102006032327B4/en not_active Expired - Fee Related
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5157635A (en) * | 1989-12-27 | 1992-10-20 | International Business Machines Corporation | Input signal redriver for semiconductor modules |
US6125419A (en) * | 1996-06-13 | 2000-09-26 | Hitachi, Ltd. | Bus system, printed circuit board, signal transmission line, series circuit and memory module |
US6477614B1 (en) * | 1998-09-30 | 2002-11-05 | Intel Corporation | Method for implementing multiple memory buses on a memory module |
US20050142950A1 (en) | 2000-05-10 | 2005-06-30 | Rambus Inc. | Multiple channel modules and bus systems using same |
US20020023191A1 (en) * | 2000-08-21 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and memory system using the same |
US6847617B2 (en) * | 2001-03-26 | 2005-01-25 | Intel Corporation | Systems for interchip communication |
US20040151038A1 (en) * | 2002-11-29 | 2004-08-05 | Hermann Ruckerbauer | Memory module and method for operating a memory module in a data memory system |
US20040225853A1 (en) | 2003-05-08 | 2004-11-11 | Lee Terry R. | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules |
US7133962B2 (en) * | 2003-09-09 | 2006-11-07 | Intel Corporation | Circulator chain memory command and address bus topology |
US7130958B2 (en) * | 2003-12-02 | 2006-10-31 | Super Talent Electronics, Inc. | Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes |
US7200693B2 (en) * | 2004-08-27 | 2007-04-03 | Micron Technology, Inc. | Memory system and method having unidirectional data buses |
US20060291263A1 (en) * | 2005-05-13 | 2006-12-28 | Paul Wallner | Memory system and method of accessing memory chips of a memory system |
US20060265543A1 (en) * | 2005-05-17 | 2006-11-23 | Peter Oeschay | Method for setting an address of a rank in a memory module |
US20060262632A1 (en) * | 2005-05-17 | 2006-11-23 | Intel Corporation | Identical chips with different operations in a system |
US20060285424A1 (en) * | 2005-06-15 | 2006-12-21 | Peter Gregorius | High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips |
US20070005831A1 (en) * | 2005-06-30 | 2007-01-04 | Peter Gregorius | Semiconductor memory system |
Cited By (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8386833B2 (en) | 2005-06-24 | 2013-02-26 | Google Inc. | Memory systems and memory modules |
US8615679B2 (en) | 2005-06-24 | 2013-12-24 | Google Inc. | Memory modules with reliability and serviceability functions |
US8773937B2 (en) | 2005-06-24 | 2014-07-08 | Google Inc. | Memory refresh apparatus and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8949519B2 (en) | 2005-06-24 | 2015-02-03 | Google Inc. | Simulating a memory circuit |
US8811065B2 (en) | 2005-09-02 | 2014-08-19 | Google Inc. | Performing error detection on DRAMs |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US8213205B2 (en) | 2005-09-02 | 2012-07-03 | Google Inc. | Memory system including multiple memory stacks |
US20100020585A1 (en) * | 2005-09-02 | 2010-01-28 | Rajan Suresh N | Methods and apparatus of stacking drams |
US8582339B2 (en) | 2005-09-02 | 2013-11-12 | Google Inc. | System including memory stacks |
US20070109833A1 (en) * | 2005-09-30 | 2007-05-17 | Pyeon Hong B | Daisy chain cascading devices |
US8743610B2 (en) | 2005-09-30 | 2014-06-03 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US8654601B2 (en) | 2005-09-30 | 2014-02-18 | Mosaid Technologies Incorporated | Memory with output control |
US9230654B2 (en) | 2005-09-30 | 2016-01-05 | Conversant Intellectual Property Management Inc. | Method and system for accessing a flash memory device |
US9240227B2 (en) * | 2005-09-30 | 2016-01-19 | Conversant Intellectual Property Management Inc. | Daisy chain cascading devices |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US8797779B2 (en) | 2006-02-09 | 2014-08-05 | Google Inc. | Memory module with memory stack and interface with enhanced capabilites |
US8566556B2 (en) | 2006-02-09 | 2013-10-22 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US9727458B2 (en) | 2006-02-09 | 2017-08-08 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US8154935B2 (en) | 2006-07-31 | 2012-04-10 | Google Inc. | Delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8112266B2 (en) | 2006-07-31 | 2012-02-07 | Google Inc. | Apparatus for simulating an aspect of a memory circuit |
US20100281280A1 (en) * | 2006-07-31 | 2010-11-04 | Google Inc. | Interface Circuit System And Method For Performing Power Management Operations In Conjunction With Only A Portion Of A Memory Circuit |
US8340953B2 (en) | 2006-07-31 | 2012-12-25 | Google, Inc. | Memory circuit simulation with power saving capabilities |
US8280714B2 (en) | 2006-07-31 | 2012-10-02 | Google Inc. | Memory circuit simulation system and method with refresh capabilities |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US9047976B2 (en) | 2006-07-31 | 2015-06-02 | Google Inc. | Combined signal delay and power saving for use with a plurality of memory circuits |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8407412B2 (en) | 2006-07-31 | 2013-03-26 | Google Inc. | Power management of memory circuits by virtual memory simulation |
US8972673B2 (en) | 2006-07-31 | 2015-03-03 | Google Inc. | Power management of memory circuits by virtual memory simulation |
US8868829B2 (en) | 2006-07-31 | 2014-10-21 | Google Inc. | Memory circuit system and method |
US8566516B2 (en) | 2006-07-31 | 2013-10-22 | Google Inc. | Refresh management of memory modules |
US8181048B2 (en) | 2006-07-31 | 2012-05-15 | Google Inc. | Performing power management operations |
US8595419B2 (en) | 2006-07-31 | 2013-11-26 | Google Inc. | Memory apparatus operable to perform a power-saving operation |
US8601204B2 (en) | 2006-07-31 | 2013-12-03 | Google Inc. | Simulating a refresh operation latency |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8745321B2 (en) | 2006-07-31 | 2014-06-03 | Google Inc. | Simulating a memory standard |
US8631220B2 (en) | 2006-07-31 | 2014-01-14 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8122207B2 (en) | 2006-07-31 | 2012-02-21 | Google Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8667312B2 (en) | 2006-07-31 | 2014-03-04 | Google Inc. | Performing power management operations |
US8671244B2 (en) | 2006-07-31 | 2014-03-11 | Google Inc. | Simulating a memory standard |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8766324B2 (en) | 2006-09-30 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power line layout techniques for integrated circuits having modular cells |
US7750375B2 (en) * | 2006-09-30 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
US20080080123A1 (en) * | 2006-09-30 | 2008-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
US20100230726A1 (en) * | 2006-09-30 | 2010-09-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
US8217430B2 (en) * | 2006-09-30 | 2012-07-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8751732B2 (en) | 2006-10-05 | 2014-06-10 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8370566B2 (en) | 2006-10-05 | 2013-02-05 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8977806B1 (en) | 2006-10-05 | 2015-03-10 | Google Inc. | Hybrid memory module |
US7512024B2 (en) * | 2006-11-08 | 2009-03-31 | Samsung Electronics Co., Ltd. | High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof |
US20080106950A1 (en) * | 2006-11-08 | 2008-05-08 | Samsung Electronics Co., Ltd. | High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof |
US8760936B1 (en) | 2006-11-13 | 2014-06-24 | Google Inc. | Multi-rank partial width memory modules |
US8130560B1 (en) * | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8675429B1 (en) | 2007-11-16 | 2014-03-18 | Google Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8705240B1 (en) | 2007-12-18 | 2014-04-22 | Google Inc. | Embossed heat spreader |
US8631193B2 (en) | 2008-02-21 | 2014-01-14 | Google Inc. | Emulation of abstracted DIMMS using abstracted DRAMS |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20090216939A1 (en) * | 2008-02-21 | 2009-08-27 | Smith Michael J S | Emulation of abstracted DIMMs using abstracted DRAMs |
US8762675B2 (en) | 2008-06-23 | 2014-06-24 | Google Inc. | Memory system for synchronous data transmission |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8819356B2 (en) | 2008-07-25 | 2014-08-26 | Google Inc. | Configurable multirank memory system with interface circuit |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US8710862B2 (en) | 2009-06-09 | 2014-04-29 | Google Inc. | Programming of DIMM termination resistance values |
Also Published As
Publication number | Publication date |
---|---|
DE102006032327B4 (en) | 2008-10-23 |
DE102006032327A1 (en) | 2007-02-01 |
US20070025131A1 (en) | 2007-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7414917B2 (en) | Re-driving CAwD and rD signal lines | |
US11942182B2 (en) | Memory and system supporting parallel and serial access modes | |
US7529112B2 (en) | 276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment | |
US11106542B2 (en) | Memory mirroring | |
US7640386B2 (en) | Systems and methods for providing memory modules with multiple hub devices | |
US7411843B2 (en) | Semiconductor memory arrangement with branched control and address bus | |
US7865674B2 (en) | System for enhancing the memory bandwidth available through a memory module | |
US7840748B2 (en) | Buffered memory module with multiple memory device data interface ports supporting double the memory capacity | |
US7818497B2 (en) | Buffered memory module supporting two independent memory channels | |
US7899983B2 (en) | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module | |
US10109324B2 (en) | Extended capacity memory module with dynamic data buffers | |
US7397684B2 (en) | Semiconductor memory array with serial control/address bus | |
US11947474B2 (en) | Multi-mode memory module and memory component | |
JP2004327474A (en) | Memory module and memory system | |
US10956349B2 (en) | Support for multiple widths of DRAM in double data rate controllers or data buffers | |
US8279652B2 (en) | Reconfigurable input/output in hierarchical memory link | |
JP2006269054A (en) | Memory module and method | |
US20080155149A1 (en) | Multi-path redundant architecture for fault tolerant fully buffered dimms | |
US20060112239A1 (en) | Memory device for use in a memory module | |
US20100299486A1 (en) | Electronic Devices and Methods for Storing Data in a Memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RUCKERBAUER, HERMANN;MUFF, SIMON;WEISS, CHRISTIAN;AND OTHERS;REEL/FRAME:016592/0837;SIGNING DATES FROM 20050812 TO 20050823 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023773/0001 Effective date: 20060425 Owner name: QIMONDA AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023773/0001 Effective date: 20060425 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
|
AS | Assignment |
Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036701/0926 Effective date: 20150708 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160819 |