US7407834B2 - Manufacturing method of a semiconductor device - Google Patents
Manufacturing method of a semiconductor device Download PDFInfo
- Publication number
- US7407834B2 US7407834B2 US10/902,785 US90278504A US7407834B2 US 7407834 B2 US7407834 B2 US 7407834B2 US 90278504 A US90278504 A US 90278504A US 7407834 B2 US7407834 B2 US 7407834B2
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- Prior art keywords
- semiconductor device
- substrate
- external electrode
- electrode terminals
- partition
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Definitions
- first connection piece and second connection piece are arranged in a staggered footprint shape, in the third and higher rows, as they occur in a part which is coaxial with the cutting location, it is difficult to use this part (in particular the fourth corner) as an external terminal.
- the substrate is cut transversely and longitudinally to electrically isolate the partition parts. Most of the isolated partition parts are used as external electrode terminals for mounting the non-leaded semiconductor device.
- the resin layer is cut transversely and longitudinally so that the unit substrate regions are mutually independent.
- plural non-leaded semiconductor devices are manufactured by peeling the tape off. The effective removal (isolation) of the substrate and resin layer is performed for example by check pattern cutting with a dicing blade.
- the method of manufacturing the non-leaded semiconductor device using this substrate is as follows.
- Semiconductor elements are fixed to the unit substrate parts on the surface where grooves are present and the surface where grooves are not present.
- a semiconductor element is fixed to the center of a unit substrate part.
- the substrate is formed so that plural (two or more) rows of partition parts are situated outside the semiconductor element.
- the electrodes of the semiconductor element and a predetermined partition part situated outside the semiconductor element or the rear surface of the predetermined partition part are connected by wires.
- a resin layer is formed to a uniform thickness in a one-side mold by transfer molding so as to cover the semiconductor element and wires.
- a tape is affixed over the whole of the front surface of the resin layer.
- the groove bases are cut by moving a dicing blade relatively along the extension direction of the groove so as to isolate the substrate, i.e., isolate the partition regions.
- the resin layer is cut transversely and longitudinally so that the unit substrate parts are mutually independent.
- the independent unit substrate parts are supported by tape.
- plural non-leaded semiconductor devices are manufactured by peeling off the tape.
- FIG. 1 is a schematic cross-sectional view of a non-leaded resin sealing package type semiconductor device according to a first embodiment (Embodiment 1) of this invention.
- FIG. 2 is a plan view showing the semiconductor device with part of the resin sealing package removed leaving a thin sealing resin in the removed part.
- FIG. 3 is a perspective view showing the planar arrangement of the semiconductor device.
- FIG. 5 is an enlarged cross-sectional view of part of the semiconductor device.
- FIGS. 7A to 7G are cross-sectional views of steps involved in the method of manufacturing the non-leaded semiconductor device.
- FIG. 10 is a perspective view showing the planar arrangement of the semiconductor device having a three-row terminal construction.
- FIG. 11 is an enlarged cross-sectional view of part of the semiconductor device having a three-row terminal construction.
- FIGS. 12A and 12B are diagrams showing the shape of external electrode terminals according to a modification of the method of manufacturing the semiconductor device of Embodiment 1.
- FIG. 15 is a plan view showing the state where, in the manufacture of the non-leaded semiconductor device, a semiconductor element is fixed to a substrate and wires are attached thereto.
- FIG. 18 is a base plan view of the semiconductor device manufactured by Modification 1 of Embodiment 3.
- FIGS. 24A and 24B are diagrams showing the shape of external electrode terminals in a Modification 4 of Embodiment 3.
- FIGS. 30A to 30D are cross-sectional views of some of the steps in the method of manufacturing the semiconductor device according to a Modification 2 of Embodiment 4.
- FIG. 31 is a cross-sectional view of a non-leaded semiconductor device manufactured by a semiconductor device manufacturing method according to another embodiment (Embodiment 5) of this invention.
- FIG. 34 is a base plan view of the semiconductor device of Embodiment 6.
- FIG. 38 is an enlarged cross-sectional view of part of the semiconductor device of Embodiment 7.
- FIG. 42 is a schematic plan view of the substrate used in the method of manufacturing a semiconductor device according to another embodiment (Embodiment 9) of this invention.
- FIG. 43 is a cross-sectional view along a line A-A in FIG. 42 .
- FIG. 45 is a cross-sectional view of a non-leaded semiconductor device manufactured by a semiconductor device manufacturing method according to another embodiment (Embodiment 10) of this invention.
- FIG. 49 is a cross-sectional view of a non-leaded semiconductor device manufactured by a semiconductor device manufacturing method according to another embodiment (Embodiment 11) of this invention.
- FIGS. 53A to 53C are cross-sectional views of some of the steps in the method of manufacturing a semiconductor device according to Embodiment 12.
- FIG. 56 is a cross-sectional view of a non-leaded semiconductor device manufactured by a semiconductor device manufacturing method according to another embodiment (Embodiment 15) of this invention.
- FIG. 57 is a plan view showing an external outline of the resin sealing package without the resin sealing package of the semiconductor device of Embodiment 15.
- FIG. 58 is a base plan view of the semiconductor device of Embodiment 15.
- FIG. 59 is an enlarged cross-sectional view of part of the semiconductor device of Embodiment 15.
- FIG. 62 is a schematic view showing the arrangement of vacuum pads which apply vacuum suction to the lead frame during transfer molding in the semiconductor device manufacturing method according to Embodiment 15.
- FIG. 64 is a cross-sectional view of a non-leaded semiconductor device manufactured by the semiconductor device manufacturing method according to another embodiment (Embodiment 16) of this invention.
- FIG. 65 is a perspective view showing the planar arrangement of the semiconductor device of Embodiment 16.
- FIG. 66 is a base plan view of the semiconductor device of Embodiment 16.
- FIG. 67 is an enlarged cross-sectional view of part of the semiconductor device of Embodiment 16.
- FIG. 69 is an enlarged cross-sectional view showing part of the lead frame used in Embodiment 16.
- FIG. 71 is a perspective view showing the planar arrangement of the semiconductor device of Embodiment 17.
- FIG. 72 is a base plan view of the semiconductor device of Embodiment 16.
- FIG. 74 is a perspective view showing the planar arrangement of the semiconductor device of Embodiment 18.
- FIG. 75 is a base plan view of the semiconductor device of Embodiment 18.
- FIG. 76 is a cross-sectional view of a non-leaded semiconductor device manufactured by the semiconductor device manufacturing method according to another embodiment (Embodiment 19) of this invention.
- FIG. 78 is a base plan view of the semiconductor device of Embodiment 19.
- FIG. 79 is a schematic cross-sectional view of a non-leaded semiconductor device according to another embodiment (Embodiment 20) of this invention.
- FIG. 80 is a perspective view showing the planar arrangement of the semiconductor device of Embodiment 20.
- FIG. 81 is a base plan view of the semiconductor device of Embodiment 20.
- FIG. 82 is an enlarged cross-sectional view of part of the semiconductor device of Embodiment 20.
- FIG. 83 is a schematic cross-sectional view of a non-leaded semiconductor device according to another embodiment (Embodiment 21) of this invention.
- FIG. 84 is a schematic cross-sectional view of a non-leaded semiconductor device according to another embodiment (Embodiment 22) of this invention.
- FIG. 87 is an enlarged cross-sectional view of part of the non-leaded semiconductor device of Embodiment 22.
- FIGS. 88A to 88G are cross-sectional views of the steps in the method of manufacturing the non-leaded semiconductor device of Embodiment 22.
- FIG. 89 is a schematic plan view of a substrate used in the method of manufacturing the non-leaded semiconductor device of Embodiment 22.
- FIG. 90 is a schematic enlarged cross-sectional view showing a unit substrate region of the substrate used in the method of manufacturing the semiconductor device of Embodiment 22.
- FIG. 96 is a perspective view showing the planar arrangement of external electrode terminals in the semiconductor device of the modification.
- FIG. 102 is a base plan view of the non-leaded semiconductor device of Embodiment 24.
- FIG. 103 is an enlarged cross-sectional view of part of the non-leaded semiconductor device of Embodiment 24.
- FIGS. 104A to 104G are schematic cross-sectional views of the steps in the method of manufacturing the non-leaded semiconductor device of Embodiment 24.
- FIGS. 105A and 105B are schematic enlarged views showing a unit substrate region in a substrate used to manufacture the non-leaded semiconductor device of Embodiment 24.
- FIG. 108 is a base plan view of the non-leaded semiconductor device of Embodiment 5.
- FIG. 109 is an enlarged cross-sectional view of part of the non-leaded semiconductor device of Embodiment 25.
- FIG. 110 is a descriptive diagram showing the relation between the interconnections on the mounting board and the external electrode terminals of the non-leaded semiconductor device during the mounting of the non-leaded semiconductor device of Embodiment 25.
- Embodiment 1 as shown in FIG. 1 and FIG. 2 , electrically isolated partition parts 4 (partition regions) 2 are provided in a grid pattern on the rear surface (mounting surface side) of a sealing package 3 comprising a rectangle of predetermined thickness.
- a semiconductor device will be described wherein two rows of the partition parts 4 are provided as the external electrode terminals 2 along each side of the square resin sealing package.
- the partition parts (partition regions) 4 are squares wherein for example the horizontal and vertical sides are both 0.5 mm.
- the interval between the partition region 4 and partition region 4 may for example be approximately 0.15 mm.
- the pitch of the external electrode terminals is 0.5 mm
- the horizontal and vertical dimensions of the partition regions 4 are respectively 0.35 mm.
- a semiconductor element (semiconductor chip) 5 is situated inside the resin sealing package 3 , and electrodes 6 of the semiconductor element 5 ( FIG. 3 ) are electrically connected by means of conductive wires 7 to both sides of the predetermined partition parts 4 covered by the resin sealing package 3 .
- the wires 7 are also covered by the resin sealing package 3 .
- the semiconductor element 5 is fixed to the plural partition parts 4 by an adhesive 9 .
- the adhesive 9 may be conductive or insulating.
- a conductive adhesive is used, for example silver (Ag) paste. Therefore, if the substrate parts in contact with the partition parts 4 of the semiconductor chip are layers which are not used electrically, the partition parts 4 which are connected to the semiconductor element 5 via the conductive adhesive 9 , are not used as external electrode terminals. However, in this case also they may be used as mounting terminals.
- the partition parts 4 situated underneath the semiconductor element 5 may also be used as the external electrode terminals 2 .
- the partition parts 4 connected to the semiconductor element 5 via the adhesive 9 are all electrically isolated.
- the partition parts 4 not used as the external electrode terminals 2 are also fixed to the interconnection board by a bonding material such as solder or the like during installation of the semiconductor device 1 .
- the mounting strength can be increased. Further, heat dissipation is also improved.
- the partition parts 4 situated underneath the semiconductor element 5 may also be used as the external electrode terminals 2 , as described above.
- a plating film 11 as shown in FIG. 5 is provided on the surface (inner surface 10 ) to which the wires 7 of the partition members 4 are connected. This plating film 11 is provided to make good contact with the wires 7 .
- the wires 7 may be Au wires
- the plating film 11 may be an Ag plating film, Au plating film or Pd plating film.
- An external mounting plating film 13 used for mounting is provided on the rear surfaces (mounting surfaces 12 ) of the partition parts 4 .
- This external mounting plating film 13 is provided to make good contact (leak properties) with a bonding material when the semiconductor device 1 is mounted on an interconnection board such as a modular substrate or the like.
- the external mounting plating film 13 is preferably a PbSn solder plating film, and in Embodiment 1, a PbSn solder plating film is used.
- FIG. 6 is a cross-sectional view showing a state where the semiconductor device 1 of Embodiment 1 is incorporated in an electronic device, i.e., where it is mounted on an interconnection board 15 such as a motherboard or modular board of the electronic device.
- Lands 17 corresponding to the external electrode terminals 2 of the semiconductor device 1 are provided by some of interconnections 16 on the principal surface of the interconnection board 15 having a multilayer interconnection structure.
- the external electrode terminals 2 of the semiconductor device 1 are electrically connected to these lands 17 via solder (PbSn solder) 18 .
- the semiconductor device is manufactured by first fixing the semiconductor element to one surface of the substrate leaving a predetermined gap.
- the electrodes of the semiconductor element are connected to predetermined substrate regions outside the semiconductor element by conductive wires, a resin layer of fixed thickness is formed by a one-side mold by transfer molding so as to cover the semiconductor element and wires, and fragmentation is then performed by cutting the resin layer transversely and longitudinally.
- the wire connecting parts can be connected to any of the partition parts.
- the fragmentation is a division into one semiconductor element, and each of the rectangular regions comprising the plural partition parts situated around this semiconductor element.
- a semiconductor substrate 20 is first provided as shown in FIG. 7( a ).
- This substrate 20 comprises a metal plate such as a copper alloy plate, copper plate or iron-nickel alloy plate usually used for the manufacture of semiconductor devices.
- a flat copper plate is used.
- this substrate 20 is a rectangular flat plate (rectangular plate) of a size such that plural semiconductor devices can be manufactured in one operation, for example 3 columns and 8 rows of 24 semiconductor devices can be manufactured.
- the plating film 11 ( FIG. 5) comprising Ag is provided on one surface of the substrate 20 , i.e., on the principal surface to which the semiconductor element is fixed.
- the thickness of the substrate 20 may for example be 0.125-0.2 mm.
- the semiconductor element 5 is fixed to the principal surface of the substrate 20 using the usual chip bonding device, not shown.
- the semiconductor element 5 is fixed by the adhesive 9 comprising Ag paste.
- the thickness of the adhesive 9 is set as thick as, for example, approximately 30-100 um so that the tip of the dicing blade stops at the middle layer of the adhesive 9 .
- the semiconductor elements 5 are aligned (in a matrix pattern) leaving a predetermined gap horizontally and vertically from the principal surface of the substrate 20 .
- the external mounting plating film 13 is formed on the rear surface of the substrate 20 .
- the external mounting plating film 13 is shown in FIG. 5 .
- the external mounting plating film 13 may also be formed by PbSn solder, for example by electroplating.
- the external mounting plating film 13 is formed to a thickness of approximately 5-20 um.
- the boundary between a unit substrate region and a unit substrate region is cut by the dicing blade 22 , and the resin layer 3 a is cut simultaneously. Due to the cutting of the resin layer 3 a , fragmentation is achieved, and plural semiconductor devices 1 are manufactured although they are still attached to the tape 21 .
- the resin layer 3 a covering the semiconductor elements 5 and wires 7 form a sealing package 3 due to this cutting.
- the dicing blade 22 may have only one blade, or it may have plural blades which perform cutting of plural devices simultaneously in parallel directions.
- Embodiment 1 has the following advantages.
- partition parts When the partition parts are formed by etching, partition parts having any desired shape can be formed by the pattern of the etching mask. Therefore, a large partition part effectively corresponding to the semiconductor element fixing region can also be formed, and the semiconductor element can be fixed to a single partition part. In this case, there is the advantage that the heat generated by the semiconductor element 5 can be dissipated by dispersing it uniformly underneath the semiconductor element.
- a matrix type substrate was used as the substrate, but a fragmented type substrate may also be used.
- FIG. 14 and FIG. 15 are diagrams relating to the method of manufacturing the non-leaded semiconductor device according to another embodiment (Embodiment 2) of this invention.
- FIG. 14 is a cross-sectional view of the steps showing the method of manufacturing the semiconductor device
- FIG. 15 is a plan view of the substrate to which semiconductor elements are fixed and wires are attached.
- grooves 25 are formed along the lines which cut the substrate 20 in Embodiment 1.
- the grooves 25 may be formed by a dicing blade or by etching, but are formed by etching in Embodiment 1.
- a photoresist film is provided over the whole surface of the substrate 20 , and exposed to a predetermined pattern. Subsequently, the photoresist film is developed to form a checkered pattern of grooves, and the checkered pattern of grooves 25 is then provided on one surface of the substrate 20 by etching.
- a copper plate of thickness 0.125-0.2 mm is for example used as the substrate 20 as in Embodiment 1.
- the thickness of the groove bases of the grooves 25 may for example be approximately 50 ⁇ m.
- the cutting depth of the dicing blade 22 is only the groove bases of the grooves 25 , and due to the decrease in the amount of cutting, the time required for forming the external electrode terminals and fragmentation is shortened.
- the dicing blade 22 has less wear, and the life of the dicing blade 22 is extended.
- This Embodiment 2 is an example wherein the non-leaded semiconductor device 1 is manufactured by providing the grooves 25 on the rear surface of the substrate 20 .
- the method of manufacturing the semiconductor device will be described referring to the cross-sectional views of the steps in FIGS. 14A to 14G .
- the conductive substrate 20 is first provided as in Embodiment 1.
- the grooves 25 are formed transversely and longitudinally by etching as described above on the rear surface of this substrate 20 .
- a matrix of the partition parts 4 is formed by the checkered pattern of the grooves 25 .
- each transverse and longitudinal side is 0.5 mm as in the case of Embodiment 1.
- FIG. 15 is a plan view of the substrate 20 when the semiconductor elements 5 are fixed to the surface where the grooves are not present, i.e., to the principal surface of the substrate 20 , and the connections of the wires 7 have been completed.
- the grooves 25 and partition parts 4 are shown by broken lines.
- the plating film 11 not shown, for obtaining satisfactory fixing (connections) of the semiconductor elements 5 and wires 7 is also formed before or after forming the grooves 25 .
- the semiconductor elements 5 are fixed as in Embodiment 1 to the surface where grooves are not present, i.e., to the principal surface of the substrate 20 , and as shown in FIG. 14C , the electrodes of the semiconductor elements 5 are connected to the principal surface of the substrate, i.e., the rear surfaces of the partition parts 4 separated from the semiconductor elements 5 , by the conductive wires 7 ( FIG. 15 ).
- the resin layer 3 a of an insulating resin is formed on the principle surface of the substrate 20 by transfer molding so as to cover the semiconductor elements 5 and wires 7 .
- the resin layer 3 a is formed to a uniform thickness.
- the semiconductor elements 5 and wires 7 are covered by the resin so as to leave no gaps.
- the external mounting plating film 13 is formed on the rear surface of the substrate (front surfaces of the partition parts 4 ) as in Embodiment 1.
- the tape 21 is affixed as a supporting member over the whole of the front surface of the resin layer 3 a , and the substrate 20 is then cut transversely and longitudinally by the dicing blade 22 with the substrate 20 facing upwards.
- the groove bases of the grooves 25 are cut and removed while the dicing blade 22 moves relatively along the extension direction of the grooves 25 . In this case also, care is taken not to cut the rear surfaces of the semiconductor elements 5 by the dicing blade.
- plural non-leaded semiconductor devices 1 are manufactured by peeling the tape 21 off the resin sealing package 3 .
- the shape and dimensions of the partition parts may also be varied between adjacent partition parts.
- Embodiment 2 various modifications can be applied as in the case of Embodiment 1, and in this case, an identical effect to that of Embodiment 1 is obtained.
- the method of manufacturing the non-leaded semiconductor device of Embodiment 3 will be described referring to the cross-sectional views of the steps of FIGS. 16A to 16G .
- the semiconductor elements 5 are fixed to the surface where the grooves 25 are present as in Embodiment 1 and Embodiment 2.
- the electrodes of the semiconductor elements 5 are connected to the principal surface side of the substrate, i.e., the rear surfaces of the partition parts 4 separated from the semiconductor elements 5 , by the conductive wires 7 .
- the substrate 20 and the resin layer 3 a attached to the substrate 20 are cut by the dicing blade 22 between the unit substrate regions so as to perform fragmentation. Due to the cutting of the substrate 20 , the partition parts 4 become electrically isolated partition parts 4 . Further, by cutting the resin layer 3 a , the resin sealing package 3 is formed.
- plural non-leaded semiconductor devices 1 are manufactured by peeling the tape 21 off the resin sealing package 3 .
- Embodiment 3 has identical advantages to those of Embodiment 2. Also, in Embodiment 3, various modifications may be made as in Embodiment 1, in which case identical advantages to those of Embodiment 1 are obtained.
- FIG. 20 and FIG. 21 are diagrams relating to the manufacture of a semiconductor device according to a Modification 2 of Embodiment 3.
- FIG. 20 is a cross-sectional view of the manufactured semiconductor device
- FIG. 21 is an enlarged cross-sectional view of part of the semiconductor device.
- the dicing blade which cuts the partition parts 4 is narrower (thinner) than the groove width of the grooves 25 .
- FIG. 22 and FIG. 23 are diagrams relating to the manufacture of a semiconductor device according to a Modification 3 of Embodiment 3.
- FIG. 22 is a schematic cross-sectional view showing the formation of the external electrode terminals by polishing in the manufacture of the semiconductor device
- FIG. 23 is a schematic plan view showing the polishing of the front surface of the substrate.
- a rotating grinder 30 is moved in contact from one edge to the other edge of the substrate 20 , and the groove bases of the grooves 25 are removed by polishing.
- the grinder 30 supported by a rotating shaft 30 a is shown smaller.
- Modification 3 Prior to this polishing, in Modification 3, after forming the resin layer 3 a by transfer molding, the tape 21 is not affixed. Also, fragmentation is performed by dicing or laser beam irradiation.
- the fragmentation of the terminals can be performed in a short time.
- FIG. 25 is a diagram showing the shape of the external electrode terminals in the manufacture of a semiconductor device according to a Modification 5 of Embodiment 3.
- Modification 5 plural depressions 32 are provided in the surface facing the resin layer 3 a of the partition parts 4 .
- the insulating resin which forms the resin sealing package 3 is introduced into these depressions 32 , so the bonding strength with the partition parts 4 (external electrode terminals 2 ) is improved, the partition parts 4 (external electrode terminals 2 ) do not fall out so easily from the semiconductor device 1 , and product reliability increases.
- the substrate 20 and the resin layer 3 a attached to the substrate 20 are cut by the dicing blade 22 between the unit substrate parts so as to perform fragmentation.
- the partition parts 4 become electrically isolated partition parts 4 .
- the resin sealing package 3 is formed.
- Embodiment 4 it is a characteristic feature of Embodiment 4 that, as the outline portion on the mounting surface of the partition parts 4 (external electrode terminals 2 ) is determined to be a minimum by the grooves 25 , the partition parts 4 (external electrode terminals 2 ) can be formed in a precise shape.
- FIGS. 27 to 29 are diagrams relating to the manufacture of a semiconductor device according to a Modification 1 of Embodiment 4.
- FIG. 27 is a cross-sectional view showing a dicing state
- FIG. 28 is a cross-sectional view of the manufactured semiconductor device
- FIG. 29 is an enlarged cross-sectional view of part of the semiconductor device.
- FIGS. 30A to 30D are cross-sectional views of steps of one part of the method of manufacturing the semiconductor device according to a Modification 2 of Embodiment 4.
- FIGS. 30A to 30D only provision of the substrate 20 ( FIG. 30A ), filling of the grooves 25 on the surface where the semiconductor elements are attached by the filling material 33 ( FIG. 30B ), fixing of the semiconductor elements ( FIG. 30C ) and wire bonding ( FIG. 30D ) are shown.
- the grooves 25 may for example be filled by an insulating epoxy resin by the screen printing method.
- the front surface of the filling material 33 approximately coincides with the front surface of the substrate 20 so as not to interfere with the fixing of the semiconductor elements.
- FIG. 31 is a cross-sectional view of a non-leaded semiconductor device manufactured by a method according to another embodiment (Embodiment 5) of this invention
- FIG. 32 is a base plan view of the semiconductor device.
- Embodiment 5 has a stand-off construction wherein a predetermined gap is left between the rear surfaces of the semiconductor elements 5 and the interconnection board during mounting, by removing the partition parts 4 inside the three rows of the external electrode terminals 2 arranged along the sides of the semiconductor device 1 .
- the semiconductor device 1 having the structure shown in FIG. 31 can be manufactured by providing a rectangular hole which is a stand-off in the center part of the unit substrate parts of the substrate 20 , and then performing chip bonding, wire bonding, transfer molding, dicing and fragmentation.
- FIG. 32 is a base plan view of the semiconductor device 1 , there being no partition parts 4 (external electrode terminals 2 ) in the center part.
- FIG. 33 is a cross-sectional view of a non-leaded semiconductor device manufactured by a method according to another embodiment (Embodiment 6) of this invention
- FIG. 34 is a base plan view of the semiconductor device.
- Embodiment 6 is a stand-off construction as in the case of Embodiment 5.
- the substrate region surface requiring stand-off in the substrate 20 is made thinner by half-etching.
- this construction also, during mounting as in the case of Embodiment 5, if a foreign body comes to be facing the half-etched partition parts 4 , the foreign body does not easily interfere.
- FIG. 35 to FIG. 38 are diagrams relating to a method of manufacturing a non-leaded semiconductor device according to another embodiment (Embodiment 7) of this invention.
- FIG. 35 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 36 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 37 is a base plan view of the semiconductor device
- FIG. 38 is an enlarged cross-sectional view of part of the semiconductor device.
- the external electrode terminals 2 are formed by removing the bases of the grooves 25 at intervals of several grooves apart.
- the groove bases of the grooves 25 one groove apart are removed. This technique has the advantage that the size and pitch of the external electrode terminals 2 can be freely selected.
- FIG. 39 to FIG. 41 are diagrams relating to a method of manufacturing a non-leaded semiconductor device according to another embodiment (Embodiment 8) of this invention.
- FIG. 39 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 40 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 41 is a base plan view of the semiconductor device.
- Embodiment 8 is an example wherein three rows of the partition parts 4 adjacent each other including the outermost row along the sides of the semiconductor device 1 are used as the external electrode terminals 2 , and the fourth row of predetermined partition parts 4 from the outside to inside are used as the external electrode terminals 2 .
- a part A electrically connects the third row of predetermined partition parts 4 and fourth row of predetermined partition parts 4 .
- This may for example be manufactured by a construction wherein the part A adjoins parts of adjacent partition parts 4 without etching.
- one of the partition parts 4 underneath the semiconductor element 5 is electrically connected to one of the partition parts 4 outside the semiconductor element 5 , but the partition parts 4 underneath the semiconductor element 5 may be further electrically connected, or other partition parts 4 outside the semiconductor element 5 may also be electrically connected to the partition parts 4 underneath the semiconductor element 5 .
- FIG. 42 to FIG. 44 are diagrams relating to a method of manufacturing a non-leaded semiconductor device according to another embodiment (Embodiment 9) of this invention.
- FIG. 42 is a schematic cross-sectional view of the substrate used in the method of manufacturing the semiconductor device
- FIG. 43 is a cross-sectional view along a line A-A in FIG. 42
- FIG. 44 is a cross-sectional view along a line B-B in FIG. 42 .
- FIG. 45 to FIG. 48 are diagrams relating to a method of manufacturing a non-leaded semiconductor device according to another embodiment (Embodiment 10) of this invention.
- FIG. 45 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 46 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 47 is a base plan view of the semiconductor device
- FIG. 48 is a cross-sectional view of some of the steps in the method of manufacturing the semiconductor device.
- the partition parts 4 to which the semiconductor element 5 are fixed are integrated to form a chip fixing partition part 42 of a size such that the semiconductor element 5 can easily be fixed to it. This improves the mechanical strength of the part supporting the semiconductor element 5 , and improves heat dissipation properties by effectively transmitting the heat produced by the semiconductor element 5 .
- FIGS. 48A to 48C are cross-sectional views of some of the steps in the method of manufacturing the semiconductor device according to Embodiment 10. As shown in FIGS. 48A to 48C , only provision of the substrate 20 ( FIG. 48A ), fixing of the semiconductor element ( FIG. 48B ) and wire bonding ( FIG. 48C ) are shown. As shown in FIG. 48A , a structure (chip fixing partition part 42 ) is formed wherein parts of adjacent partition parts 4 are joined without etching between the parts it is desired to connect even after dicing the partition parts 4 .
- FIG. 49 to FIG. 51 are diagrams relating to a method of manufacturing a non-leaded semiconductor device according to another embodiment (Embodiment 11) of this invention.
- FIG. 49 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 50 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 51 is a cross-sectional view of some of the steps in the method of manufacturing the semiconductor device.
- Embodiment 11 is a technical concept identical to that of Embodiment 8 wherein the partition parts 4 directly underneath the semiconductor element 5 are also used as the external electrode terminals 2 .
- FIGS. 51A to 51D only provision of the substrate ( FIG. 51A ), wire bonding which electrically connects the partition parts 4 ( FIG. 51B ), fixing of the semiconductor element ( FIG. 51C ) and wire bonding ( FIG. 51D ) are shown.
- Embodiment 11 as shown in FIG. 51A , after providing the substrate 20 which has the grooves 25 on both surfaces, on the surface (principal surface) of the substrate 20 to which the semiconductor elements 5 are fixed, as shown in FIG. 51B , regions which function as the external electrode terminals 2 separate from the regions where the semiconductor elements 5 are fixed, are electrically connected by conductive wires 43 to predetermined partition parts 4 to which the semiconductor elements 5 are fixed.
- the external electrode terminals 2 may be formed underneath the semiconductor elements 5 as in Embodiment 8. As result, the degree of freedom of design of the interconnection pattern of the mounting substrate is increased.
- FIG. 52 is a cross-sectional view of a non-leaded semiconductor device manufactured by a method according to another embodiment (Embodiment 12) of this invention
- FIGS. 53A to 53C is a cross-sectional view of some of the steps showing the method of manufacturing the semiconductor device.
- FIGS. 53A to 53C only provision of the substrate ( FIG. 53A ), fixing of the semiconductor elements ( FIG. 53B ) and wire bonding ( FIG. 53C ) are shown.
- Embodiment 12 as shown in FIG. 53A , in the substrate 20 which has the grooves 25 provided on both surfaces, the grooves 25 in the regions where the semiconductor elements 5 are fixed, are filled with a filling material 44 prior to fixing the semiconductor elements, as shown in FIG. 53B , the semiconductor elements 5 are fixed to predetermined positions, and as shown in FIG. 53C , the electrodes of the semiconductor elements 5 are connected to the partition parts 4 by the conductive wires 7 . Subsequently, the steps in the manufacturing method of Embodiment 11 are followed in sequence to manufacture the semiconductor device 1 shown in FIG. 52 .
- the substrate 20 there is no particular limitation on the substrate 20 , but an example will be described where the semiconductor device is manufactured using the substrate 20 having the grooves 25 on both surfaces. As shown in FIG. 55A , the substrate 20 having the grooves 25 facing each other in corresponding positions in a checkered pattern on both surfaces is first provided, and the semiconductor elements 5 are then fixed to one surface of the substrate 20 as in Embodiment 4 ( FIG. 55B ).
- the insulating resin liquid 46 is baked under predetermined conditions so as to form the resin layer 3 a covering the semiconductor elements 5 and wires 7 .
- the semiconductor elements 5 and wires 7 are present so the surface is undulating, but the semiconductor elements 5 and wires 7 are covered by the resin without leaving any gaps.
- the insulating resin liquid 46 may be a UV curing resin.
- the tape 21 is affixed as a supporting member to the resin layer 3 a , and the substrate 20 is cut transversely and longitudinally by two dicing blades with the substrate 20 facing upwards.
- the independent partition parts 4 are formed by cutting the groove bases of the grooves 25 by the dicing blade 22 b which is narrower (thinner) than the grooves 25 , and the areas between unit substrate regions are cut by the dicing blade 22 which has approximately the same thickness as the groove width of the grooves 25 (fragmentation). The cutting between these unit substrate regions is also in part of the grooves 25 . Due to the cutting of the resin layer 3 a , the resin sealing package 3 is formed.
- unit substrate parts are formed by rectangular tabs fixed to the semiconductor element, and leads extending parallel from predetermined sides of the tabs and extending from adjacent tabs, or plural leads connected to the substrate frame.
- the leads have wire connection regions in two or more positions along their length.
- the substrate 20 is provided.
- the substrate 20 has the pattern shown in FIG. 61 .
- the materials and thickness of this substrate 20 are effectively identical to those of the aforesaid embodiments.
- the pattern may be manufactured by selectively etching or stamping the substrate 20 .
- the substrate 20 comprises a rectangular (lengthwise) substrate frame 50 , and unit substrate parts arranged transversely and longitudinally inside this substrate frame 50 .
- the rectangular regions including the unit substrate parts are referred to as unit substrate regions.
- the unit substrate regions comprise a rectangular tab 51 which fixes the semiconductor element 5 , and leads 52 extending parallel from predetermined sides of this tab 51 and extending from adjacent tabs 51 , or plural leads connected to the substrate frame 50 . Therefore, all of the leads 52 are parallel to the substrate frame 50 .
- a plating film 11 is formed in at least a part of the principal surface of the substrate 20 to which semiconductor elements and wires are connected ( FIG. 59 ).
- the substrate 20 shown in FIG. 61 There is no particular limitation on the substrate 20 shown in FIG. 61 , but a total of 21 unit substrate parts may be aligned in 3 columns and 7 rows so that 21 semiconductor devices can be manufactured from one of the substrates 20 .
- the semiconductor element 5 is already fixed, and the electrodes 6 of the semiconductor element 5 are connected to predetermined positions (wire bonding positions) of the leads 52 by the wires 7 .
- the semiconductor element 5 is fixed to the tabs on one surface (the principal surface) of the substrate 20 via the adhesive 9 ( FIG. 59 ).
- the adhesive 9 may be an insulating adhesive or a conductive adhesive.
- the tabs 51 are larger than the semiconductor element 5 .
- the electrodes of the semiconductor element 5 are connected to predetermined wire bonding positions on the leads 52 by the conductive wires 7 ( FIG. 56 and FIG. 57 ).
- the conductive wires 7 FIG. 56 and FIG. 57 .
- two regions for fixing the wires are provided in the length direction of the leads 52 . These two positions are marked by dotted lines in FIG. 61 for clarity.
- the semiconductor elements 5 and wires 7 are covered by an insulating resin (resin layer 3 a ) by transfer molding to seal the package.
- an insulating resin resin layer 3 a
- the tab parts 51 of the substrate 20 are made to adhere to the surface of the lower die of a molding die by vacuum suction nozzles 53 .
- FIG. 63 the nozzles 53 are shown schematically.
- the substrate 20 is die clamped between a lower die 55 and upper die 56 of a molding die 54 .
- the region inside the substrate frame 50 of the substrate 20 is situated inside a cavity 57 , which is a rectangular depression provided on the parting surface of the upper die 56 , and the semiconductor elements 5 and wires 7 are situated inside the cavity 57 .
- resin is pressure-injected from a gate and the cavity 57 is filled with resin, but there is a risk that resin will flow onto the lower surface of the tabs 51 , i.e., the surface of the tabs 51 in contact with the lower die 55 .
- the resin layer 3 a of constant thickness specified by the shape of the cavity 57 is formed on the principal surface side of the substrate 20 without resin adhering to the lower surface of the tabs 51 and leads 52 (See FIG. 60D ).
- the tape 21 is affixed as a supporting member to the resin layer 3 a , and the substrate 20 is cut transversely and longitudinally by a dicing blade with the substrate 20 facing upwards.
- the cutting by the dicing blade 22 is performed transversely in a direction perpendicular to the leads 52 . Cutting is performed at the parts of the leads 52 attached to the tabs 51 , the boundaries of the wire bonding positions, the boundaries between unit substrate parts (unit substrate regions) and unit substrate parts (unit substrate regions), and the boundaries between the unit substrate parts (unit substrate regions) and the frame body 50 .
- the resin layer 3 a is cut simultaneously. Due to cutting of the resin layer 3 a , the semiconductor device 1 is manufactured, and the resin layer 3 a covering the semiconductor elements 5 and wires 7 becomes the resin sealing package 3 . In the cutting of the resin layer 3 a , care is taken not to completely cut the tape 21 . As this cutting takes place in the two directions XY, it is preferred that after cutting in one direction, the parts are still held by the tape 21 .
- FIG. 56 to FIG. 59 are diagrams relating to the semiconductor devices 1 manufactured in this way.
- FIG. 56 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 57 is a plan view of the non-leaded semiconductor device showing the external outline of the resin sealing without the resin sealing
- FIG. 58 is a base plan view of the semiconductor device
- FIG. 59 is an enlarged cross-sectional view of part of the semiconductor device.
- the square tab 51 is situated in the middle, and the external electrode terminals 2 are aligned in two rows along each side of the tab 51 .
- the external electrode terminals 2 may be fixed, or the external electrode terminals 2 and tabs 51 may be fixed, to the interconnection board.
- both ends of the leads 52 formed on the external electrode terminals 2 are supported, and as it is not a cantilever construction, it does not float up during molding. Therefore, resin also does not adhere to the mounting surfaces of the external electrode terminals 2 .
- the leads 52 had two wire bonding positions, but there may be plural positions. Specifically, if further division into plural pieces is possible by the dicing blade, plural external electrode terminals 2 can also be formed from one of the leads 52 .
- FIG. 64 to FIG. 69 are diagrams relating to the method of manufacturing the semiconductor device according to another embodiment (Embodiment 16) of this invention.
- the unit substrate parts of Embodiment 15 are formed by the tabs 51 and leads 52 , so the four corners of the rectangular unit substrate regions are not used efficiently.
- This embodiment therefore provides a means of also using the four corners efficiently.
- FIG. 68 shows a partial enlargement.
- FIG. 68 and FIG. 69 are plan views showing the state where chip bonding and wire bonding have been completed.
- the semiconductor device 1 is manufactured by identical steps to those of Embodiment 15 using the substrate 20 shown in FIG. 68 .
- cutting of the corner leads 61 takes place by moving the dicing blade in a straight line to form the external electrode terminals 2 .
- the supporting pieces 60 are narrower than the width of the dicing blade, and as they are aligned in the travel direction of the dicing blade, they are cut and removed by the dicing blade.
- FIG. 64 is a cross-sectional view of the semiconductor device
- FIG. 65 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 66 is a base plan view of the semiconductor device
- FIG. 67 is an enlarged cross-sectional view of part of the semiconductor device.
- the external electrode terminals 2 are formed also at the four corners of the unit substrate regions.
- both ends of the leads 52 and corner leads 61 formed on the external electrode terminals 2 are supported, and as it is not a cantilever construction, it does not float up during molding. Therefore, resin does not adhere to the mounting surfaces of the external electrode terminals 2 .
- Embodiment 16 has some of the advantages of the preceding embodiments.
- FIG. 70 to FIG. 72 are diagrams relating to the method of manufacturing the semiconductor device according to another embodiment (Embodiment 17) of this invention.
- FIG. 70 is a cross-sectional view of the semiconductor device
- FIG. 71 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 72 is a base plan view of the semiconductor device.
- FIG. 73 to FIG. 75 are diagrams relating to the method of manufacturing a semiconductor device according to another embodiment (Embodiment 18) of this invention.
- FIG. 73 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 74 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 75 is a base plan view of the semiconductor device.
- Embodiment 18 is an example of application to the manufacture of a semiconductor device having a small tab construction as in Embodiment 17.
- the external electrode terminals 2 are arranged in three rows along the sides of the resin sealing package 3 .
- the number of the external electrode terminals 2 can be further increased.
- FIG. 76 to FIG. 78 are diagrams relating to the method of manufacturing the semiconductor device according to another embodiment (Embodiment 19) of this invention.
- FIG. 76 is a cross-sectional view of the manufactured non-leaded semiconductor device
- FIG. 77 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 78 is a base plan view of the semiconductor device.
- Embodiment 19 is an example wherein the tab surface (rear surface) to which the semiconductor element 5 is not fixed, is formed thinner than the leads 52 on the periphery by etching to a predetermined thickness, and a resin layer 3 b is also formed on the tab surface to which the semiconductor element 5 is not fixed when the resin layer 3 a is formed by transfer molding.
- the resin layer 3 b is interposed between the tab 51 and interconnection board, so the tab 51 can be electrically insulated.
- FIG. 79 to FIG. 82 are diagrams relating to the method of manufacturing the semiconductor device according to another embodiment (Embodiment 20) of this invention.
- FIG. 79 is a cross-sectional view of the semiconductor device
- FIG. 80 is a perspective view showing the planar arrangement of the semiconductor device
- FIG. 81 is a base plan view of the semiconductor device
- FIG. 82 is an enlarged cross-sectional view of part of the semiconductor device Embodiment 20, which is a Modification 3 of Embodiment 3, may be applied to the method of forming the partition parts 4 by polishing the undersurface of the substrate 20 .
- the substrate 20 is patterned, the grooves 25 are not provided in the region to which the semiconductor element 5 is fixed. In this way, the bonding surface area of the semiconductor element 5 increases, the bonding strength increases, and heat which is generated from the semiconductor element 5 can be rapidly dissipated to the outside from the partition parts 4 which have a large surface area.
- the partition parts 4 may be formed by etching.
- FIG. 83 is a schematic plan view of a semiconductor device manufactured by a method according to another embodiment (Embodiment 21) of this invention.
- FIG. 84 to FIG. 97 are diagrams relating to the non-leaded semiconductor device according to another embodiment (Embodiment 22) of this invention.
- a chip fixing partition part 42 which is slightly larger than the semiconductor element 5 is provided as in Embodiment 10, and the substrate 20 has the grooves 25 provided on the chip fixing surface side.
- the front surfaces of the external electrode terminals 2 project beyond the front surface of the resin layer forming the resin sealing package 3 (stand-off construction).
- FIG. 84 to FIG. 87 are diagrams relating to the construction of the semiconductor device
- FIG. 88 to FIG. 94 are diagrams relating to the method of manufacturing the non-leaded semiconductor device.
- the lower surface of the chip fixing partition part 42 is exposed on the lower surface of the resin sealing body 3 , and as shown in FIG. 86 , the external electrode terminals 2 are arranged in three rows on the outer periphery of the square chip fixing partition part 42 .
- a notch 26 is provided on one side of the chip fixing partition part 42 .
- the chip fixing partition part 42 is a partition part (partition region) 4 of large surface area wherein the partition part (partition region) 4 forming the external electrode terminals 2 partly does not have the grooves 25 .
- the chip fixing partition part 42 to which the semiconductor element 5 is fixed by the adhesive 9 ( FIG. 87 ) is slightly larger than the semiconductor element 5 .
- the electrodes on the front surface of the semiconductor element 5 and the external electrode terminals 2 are electrically connected by the conductive wires 7 in the resin sealing package 3 ( FIG. 85 , FIG. 87 ).
- a particular feature of this invention is that the external electrode terminals 2 and chip fixing partition part 42 project slightly from the lower face (mounting surface) of the resin sealing package. This projection is due to a plating film 27 formed on the front surfaces of the external electrode terminals 2 and chip fixing partition part 42 after etching the groove bases of the grooves 25 in the manufacture of the semiconductor device.
- a projection length z may for example be from several 10-several 100 ⁇ m. Due to this projection of the external electrode terminals 2 (stand-off construction), the external electrode terminals 2 groove can be connected to the interconnections (lands) of the mounting board without fail when the semiconductor device 1 is mounted on the mounting board.
- the plating film 27 is formed by plating on the front surfaces of the external electrode terminals 2 and chip fixing partition part 42 exposed on the lower surface of the resin sealing package 3 .
- the plating may for example be PbSn plating, and the thickness of the plating film 27 is of the order of several 10 to several 100 ⁇ m.
- the base surface of the plated external electrode terminals 2 and chip fixing partition part 42 project further than the lower surface of the resin sealing package 3 exposed by etching (stand-off construction).
- the tape 21 is affixed to the surface of the resin sealing package 3 which is the rear surface relative to the surface on which the chip fixing partition part 42 and the external electrode terminals 2 are present, and the resin sealing package 3 is cut transversely and longitudinally by the dicing blade 22 to fragment the unit substrate parts.
- the dot-and-dash line parts in FIG. 93C and FIG. 94 are the parts where the resin sealing package 3 is cut. As can be seen from these diagrams, metal is not present in the cut parts, and there is only the resin layer part forming the resin sealing package 3 . Therefore, the life of the dicing blade used for cutting is extended.
- the chip fixing surface of the partition parts 4 which is the chip fixing partition part 42 is flat, and as it has no grooves, an adhesive used for fixing the semiconductor element does not flow into these grooves, so the amount of adhesive used is less, and the cost of manufacturing the semiconductor device is reduced. Also, as it is flat, chip bonding is more stable.
- the partition parts 4 are formed as the external electrode terminals 2 or chip fixing partition part 42 by removing the groove bases of the grooves 25 , a method is used wherein the rear surface of the substrate 20 is removed to a certain thickness by polishing or etching.
- the separation of the partition parts 4 is effected by etching ( FIG. 88D ).
- the plating in FIG. 88E e.g., external plating by PbSn, etc.
- the stand-off height can be precisely controlled.
- a stand-off construction can be formed also by etching, by forming an etching mask on the rear surface of the part of the substrate 20 corresponding to the chip fixing partition part or external electrode terminals.
- FIG. 95 to FIG. 97 are diagrams relating to a non-leaded semiconductor device in a modification of Embodiment 22.
- FIG. 95 is a schematic cross-sectional view of the non-leaded semiconductor device
- FIG. 96 is a perspective view showing the planar arrangement of the external electrode terminals
- FIG. 97 is a base plan view of the semiconductor device.
- the chip fixing partition part 42 is smaller than the semiconductor element 5 .
- the substrate used for manufacturing the semiconductor device can also be used to manufacture semiconductor elements of different sizes, and therefore the universality of the substrate is increased.
- Embodiment 23 is an example wherein, in Embodiment 22, the semiconductor device 1 is manufactured using the substrate 20 which has the grooves 25 and grooves 25 a , not shown, in corresponding positions on the front and rear surfaces.
- FIGS. 98A to 98G in the manufacturing process are identical to FIGS. 88A to 88G .
- the semiconductor device of this invention can be manufactured even when grooves are not provided on only one surface.
- Embodiment 24 as shown in FIG. 105 , in the unit substrate part 37 of the substrate 20 , there is a depression 71 without an edge on the rear surface (mounting surface) of the chip fixing partition part 42 .
- the manufacture of the semiconductor device according to this example shown in FIGS. 104 A to 104 G is identical to that of Embodiment 22 shown in FIGS. 88A to 88G , except that the separation of the partition parts 4 is achieved by polishing using a grinder 30 ( FIG. 104D ) instead of etching.
- FIG. 106 to FIG. 110 are diagrams relating to a non-leaded semiconductor device according to another embodiment (Embodiment 25) of this invention.
- FIG. 106-FIG . 109 are diagrams relating to the manufacture of the non-leaded semiconductor device
- FIG. 106 is a schematic cross-sectional view of the semiconductor device
- FIG. 107 is a perspective view showing the planar arrangement of external electrode terminals
- FIG. 108 is a base plan view of the semiconductor device
- FIG. 109 is an enlarged cross-sectional view of part of the semiconductor device.
- FIG. 110 is a descriptive diagram describing the relation between the interconnections of the mounting board of the non-leaded semiconductor device and the external electrode terminals of the non-leaded semiconductor device of Embodiment 25.
- the shape of the external electrode terminals 2 is not necessarily circular, and can be any shape which allows a wider pitch between diagonally adjacent external electrode terminals.
- the external electrode terminals 2 shown in FIG. 87 have a part of narrower width (part of width B) than the width of their upper surface, and as the part of width B is supported by the resin sealing package 3 , the external electrode terminals 2 are definitively prevented from falling out of the resin sealing package 3 .
- the external electrode terminals 2 having the part of narrower width can be formed by controlling the etching rate on the upper surface of the substrate 20 to be slower than the etching rate in the part of width B. To control the etching rate, wet etching is effective.
- the refresh rate of etching solution in the vicinity of the substrate upper surface can be made slower than the refresh rate of the etching solution in the vicinity of the part of width B, and by using the difference in etching rates due to the difference in the refresh rates of the etching solution, the electrode shapes shown in FIG. 87 can easily be formed.
Abstract
Description
- (a) Two or more rows of external electrode terminals are arranged along one side of the non-leaded semiconductor device, so the number of external electrode terminals can be increased.
- (b) As two or more rows of external electrode terminals are arranged along one side of the non-leaded semiconductor device, the semiconductor device can be made compact.
- (c) The external electrode terminals are formed by cutting a metal plate transversely and longitudinally by a dicing blade, so the shape and dimensions of the external electrode terminals can be made very precise.
- (d) As the external electrode terminals are formed by cutting a metal plate transversely and longitudinally by a dicing blade, long projections (manufacturing burrs) due to cutting do not easily occur on the periphery of the external electrode terminals, and the electrode flatness improves. As a result, when the non-leaded semiconductor device is mounted on a mounting board using solder or the like, faulty contacts of the external electrode terminals with the lands (interconnections) of the mounting board due to projections do not easily occur, so mounting strength is improved and mounting reliability is improved.
- (e) In a structure wherein partition parts in a region enclosed by the semiconductor element are connected, by means of wires, to partition parts to which wires are connected outside the semiconductor element, external electrode terminals may also be formed in a region underneath the semiconductor element, so not only is there more flexibility in forming the interconnection pattern on the mounting board, but the mounting board can be made more compact by modifying the interconnection pattern.
- (f) The partition parts (external electrode terminals) can easily be formed by cutting one metal plate, so the cost of manufacturing the semiconductor device can be reduced.
- (a) At least two rows of external electrode terminals are disposed along one side of the non-leaded semiconductor device, so the number of external electrode terminals can be increased.
- (b) As two or more rows of external electrode terminals are arranged along one side of the non-leaded semiconductor device, the semiconductor device can be made compact.
- (c) The external electrode terminals are formed by cutting a metal plate transversely and longitudinally by a dicing blade, so the shape and dimensions of the external electrode terminals can be made very precise.
- (d) As the external electrode terminals are formed by cutting a metal plate transversely and longitudinally by a dicing blade, long projections (manufacturing burrs) due to cutting do not easily occur on the periphery of the external electrode terminals, and the electrode flatness improves. As a result, when the non-leaded semiconductor device is mounted on a mounting board using solder or the like, faulty contacts of the external electrode terminals with the lands (interconnections) of the mounting board due to projections do not easily occur, so mounting strength is improved and mounting reliability is improved.
- (e) As external electrode terminals can be formed for plural semiconductor devices simply by dicing with a dicing blade in the transverse and longitudinal directions of one metal plate, the cost of manufacturing semiconductor devices can be reduced.
- (f) By providing grooves in the substrate and forming electrically isolated partition regions by removing the groove bases after forming the resin layer, the partition part isolation time is shorter and the time required to manufacture the semiconductor device is shortened. Due to this shortening of the cutting time, there is less wear of the dicing blade and the life of the blade is extended. Hence, the cost of manufacturing the semiconductor device is reduced.
- (g) As the grooves are formed by etching, manufacturing burrs do not occur on the edges of the grooves. Therefore, in the manufacturing method where the semiconductor element is fixed to the surface where grooves are not present, the electrode flatness of the external electrode terminals formed by the partition parts is satisfactory, and the reliability of mounting the semiconductor device is increased.
- (h) By adopting a stand-off construction, problems do not occur even if there are foreign bodies on the mounting board during mounting of devices.
- (i) When the semiconductor element is fixed to the surface where grooves are present, isolation by removing the groove bases of the partition parts may be performed by removing the substrate by polishing or etching to a fixed thickness. In this case, the electrode flatness of the external electrode terminals can be made satisfactory.
- (j) By providing through holes at intersection points which divide the substrate transversely and longitudinally, the cutting time by the dicing blade can be shortened and the life of the blade can be extended.
- (k) When the semiconductor element is fixed to a surface where grooves are present, gaps between the semiconductor element and the substrate are prevented from occurring by filling the grooves in the region where the semiconductor element is fixed with a filling material, water does not collect on the fixing surfaces of the semiconductor element and substrate, and when the semiconductor device is mounted by solder reflow, mounting defects due to swelling of this water do not easily occur.
- (a) grooves are provided facing each other on the front and rear surfaces of the substrate, and when the partition regions of the substrate are isolated, the groove bases of the grooves on the front and rear surfaces can be cut simply by moving the dicing blade relatively in the extension direction of the grooves, therefore the isolation time of the partition parts is shorter and the time required to manufacture the semiconductor device is shortened. Also, due to the shortening of cutting time, there is less wear on the dicing blade and the life of the blade is extended. Hence, the cost of manufacturing the semiconductor device is reduced. According to the above means (4), two or more rows of external electrode terminals are disposed along one side of the non-leaded semiconductor device, so the number of external electrode terminals can be increased.
- (b) As two or more rows of external electrode terminals are arranged along one side of the non-leaded semiconductor device, the semiconductor device can be made compact.
- (c) The external electrode terminals are formed by cutting a metal plate (leads) at plural points by a dicing blade, so the shape and dimensions of the external electrode terminals can be made very precise.
- (d) As the external electrode terminals are formed by cutting a metal plate (leads) at plural points by the dicing blade, long projections (manufacturing burrs) due to cutting do not easily occur on the periphery of the external electrode terminals, and the electrode flatness improves. As a result, when the non-leaded semiconductor device is mounted on a mounting board using solder or the like, faulty contacts of the external electrode terminals with the lands (interconnections) of the mounting board due to projections do not easily occur, so mounting strength is improved and mounting reliability is improved.
- (e) As external electrode terminals can be formed for plural semiconductor devices simply by dicing with a dicing blade in the transverse and longitudinal directions of one metal plate, the cost of manufacturing semiconductor devices can be reduced.
- (f) The external electrode terminals can be formed by cutting the leads in their width direction with the dicing blade, so the cutting time can be shortened, and as the cutting time is short, there is less wear on the dicing blade and the life of the blade is extended. Hence, the cost of manufacturing the semiconductor device is reduced.
- (g) When the resin layer is formed by transfer molding, the substrate is in adhesive contact with the mounting surface of the mold by vacuum suction, and as the lead surfaces are also in adhesive contact with the mounting surface, resin no longer seeps onto the rear surface of the tabs and the rear surface of the leads. Consequently, soiling of the mounting surface of the semiconductor element by the resin can be prevented, and a non-leaded semiconductor device having a high mounting reliability can be manufactured.
- (1) The
external electrode terminals 2 are formed in two rows along the periphery (sides) of the non-leaded semiconductor device, so the number ofexternal electrode terminals 2 can be increased. - (2) In a non-leaded semiconductor device which requires a large number of external electrode terminals, the external electrode terminals have to be aligned in one row along one side of the sealing package, so the length of one side of the package has to be increased, the sealing package becomes larger and the semiconductor device becomes large, but in the case of
Embodiment 1, theexternal electrode terminals 2 are disposed in two rows along the sides of the semiconductor device, so a sealingpackage 33 can be made smaller, and thesemiconductor device 1 can be made compact. - (3) Due to the aforesaid (1) and (2), the number of
external electrode terminals 2 can be increased even in a small resin sealing package, so large numbers of terminals are possible. This is desirable in a multi-function semiconductor device. - (4) As the
external electrode terminals 2 are formed by cutting transversely and longitudinally by the dicing blade, the shape and dimensions of theexternal electrode terminals 2 can be controlled to a high precision. - (5) As the
external electrode terminals 2 are formed by cutting a metal plate transversely and longitudinally by the dicing blade, long projections (manufacturing burrs) due to cutting do not easily occur on the periphery of the external electrode terminals, and the electrode flatness improves. As a result, when the non-leaded semiconductor device is mounted on theinterconnection board 15 such as a motherboard, modular board or mounting board using solder or the like, faulty contacts of theexternal electrode terminals 2 with the lands (interconnections) 17 of the mounting board due to projections do not easily occur, so mounting strength is improved and mounting reliability is improved. - (6) As the partition parts (external electrode terminals) can easily be formed by cutting one metal plate, the cost of manufacturing the semiconductor device is reduced.
- (7) According to the aforesaid (1)-(6), a non-leaded semiconductor device which has a high mounting reliability, is compact and has large numbers of external electrode terminals, can be manufactured economically.
- (1) The
external electrode terminals 2 are formed in two rows along the periphery (sides) of the non-leaded semiconductor device, so the number of theexternal electrode terminals 2 can be increased. - (2) In a non-leaded semiconductor device which requires a large number of external electrode terminals, the external electrode terminals have to be aligned in one row along one side of the sealing package, so the length of one side of the package has to be increased, the sealing package becomes larger and the semiconductor device becomes large, but in the case of
Embodiment 2, theexternal electrode terminals 2 are disposed in two rows along the sides of the semiconductor device, so the sealingpackage 3 can be made smaller, and thesemiconductor device 1 can be made compact. - (3) Due to the aforesaid (1) and (2), the number of
external electrode terminals 2 can be increased even in a small resin sealing package, so large numbers of terminals are possible. This is desirable in a multi-function semiconductor device. - (4) As the
external electrode terminals 2 are formed by cutting transversely and longitudinally by the dicing blade, the shape and dimensions of theexternal electrode terminals 2 can be controlled to a high precision. - (5) As the
external electrode terminals 2 are formed by cutting a metal plate transversely and longitudinally by the dicing blade, long projections (manufacturing burrs) due to cutting do not easily occur on the periphery of the external electrode terminals, and the electrode flatness improves. As a result, when the non-leaded semiconductor device is mounted on theinterconnection board 15 such as a motherboard, modular board or mounting board using solder or the like, faulty contacts of theexternal electrode terminals 2 with the lands (interconnections) 17 of the mounting board due to projections do not easily occur, so mounting strength is improved and mounting reliability is improved. - (6) As the partition parts (external electrode terminals) can easily be formed by cutting one metal plate, the cost of manufacturing the semiconductor device is reduced.
- (7) In the cutting of the
substrate 20, the cutting depth of thedicing blade 22 is only the groove bases of thegrooves 25, and due to the decrease in the amount of cutting, the time required for forming the external electrode terminals and fragmentation is shortened. - (8) From the above (7), due to the decrease in the amount of cutting, the
dicing blade 22 has less wear, the life of thedicing blade 22 is extended and the cost of manufacturing thesemiconductor device 1 is reduced. - (9) According to the aforesaid (1)-(8), a non-leaded semiconductor device which has a high mounting reliability, is compact and has large numbers of external electrode terminals, can be manufactured economically.
- (1) A compact non-leaded semiconductor device can be provided.
- (2) A non-leaded semiconductor device having plural external electrode terminals can be provided.
- (3) A method of manufacturing a non-leaded semiconductor device having at least two rows of external electrode terminals along the sides of the semiconductor device, can be provided.
- (4) A method of manufacturing a non-leaded semiconductor device wherein the external electrode terminals are formed to a high precision of shape and dimensions, can be provided.
- (5) A non-leaded semiconductor device having a high mounting reliability, can be provided.
Claims (4)
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Also Published As
Publication number | Publication date |
---|---|
KR100868608B1 (en) | 2008-11-13 |
US20050003586A1 (en) | 2005-01-06 |
JP2003031730A (en) | 2003-01-31 |
TW544883B (en) | 2003-08-01 |
US20080268578A1 (en) | 2008-10-30 |
KR20020086219A (en) | 2002-11-18 |
US7459347B2 (en) | 2008-12-02 |
JP4034073B2 (en) | 2008-01-16 |
KR20080065960A (en) | 2008-07-15 |
US20020168796A1 (en) | 2002-11-14 |
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