US7351994B2 - Noble high-k device - Google Patents

Noble high-k device Download PDF

Info

Publication number
US7351994B2
US7351994B2 US10/762,164 US76216404A US7351994B2 US 7351994 B2 US7351994 B2 US 7351994B2 US 76216404 A US76216404 A US 76216404A US 7351994 B2 US7351994 B2 US 7351994B2
Authority
US
United States
Prior art keywords
layer
strained
thickness
gate oxide
epi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US10/762,164
Other versions
US20050156255A1 (en
Inventor
Liang-Gi Yao
Tien-Chih Chang
Ming-Fang Wang
Shih-Chang Chen
Mong-Song Liang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US10/762,164 priority Critical patent/US7351994B2/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, TIEN-CHIH, CHEN, SHIH-CHANG, LIANG, MONG-SONG, WANG, MING-FANG, YAO, LIANG-GI
Publication of US20050156255A1 publication Critical patent/US20050156255A1/en
Application granted granted Critical
Publication of US7351994B2 publication Critical patent/US7351994B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Definitions

  • the present invention relates generally to semiconductor fabrication and more specifically to formation of devices incorporating high-k dielectric gate oxide layers.
  • High-k dielectric materials have been investigated to replace conventional gate oxide layers due to excellent current-leakage reduction seen when using the high-k dielectric materials at the same equivalent-oxide-thickness (EOT).
  • EOT equivalent-oxide-thickness
  • high-k dielectric materials also suffer poor mobility and high threshold voltage issues in the electric performance of devices.
  • U.S. Pat. No. 6,310,367 B1 to Yagishita et al. describes a strained Si and high-k gate dielectric Tx process wherein the concentration of Ge in the channel layer of the NMOSFET is lower that the concentration of Ge in the channel layer of the PMOSFET.
  • the gate electrodes of the NMOSFET and the PMOSFET are made of metallic materials.
  • U.S. Pat. No. 6,271,094 B1 to Chooi et al. and U.S. Pat. No. 6,335,238 B1 to Hanttangady et al. are related SiGe substrate and high-k dielectric Tx patents.
  • a structure having a strained substrate formed thereover comprising at least an uppermost strained-Si epi layer.
  • At least one dielectric gate oxide portion over the strained substrate.
  • the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0.
  • the at least one dielectric gate oxide portion being comprised of HfO 2 , HfSiO 4 , N-doped hafnium silicate (N-doped HfSiO x ), ZrO 2 or ZrSiO x .
  • the invention also includes a method of forming the at least one high-k device.
  • FIG. 1 schematically illustrate a preferred embodiment of the present invention employing a first preferred embodiment strained-Si substrate.
  • FIG. 2 schematically illustrates a second preferred embodiment of the strained-Si substrate of the present invention.
  • FIG. 3 schematically illustrates a third preferred embodiment of the strained-Si substrate of the present invention.
  • FIG. 4 schematically illustrates a fourth preferred embodiment of the strained-Si substrate of the present invention.
  • FIG. 5 schematically illustrates a fifth preferred embodiment of the strained-Si substrate of the present invention.
  • all strained-Si epi layers/substrates have a dislocation density of strained-Si epi of less than about 1E6/cm 2 and a high-k dielectric material has a dielectric constant (k) of greater than about 4.0.
  • FIG. 1 (First Embodiment)
  • the preferred structure of the present embodiment includes a semiconductor structure 10 having a strained substrate 12 formed thereover to a thickness of preferably from about 3000 to 100,000 ⁇ and more preferably from about 4000 to 50,000 ⁇ .
  • strained substrate 12 is comprised of entirely of strained-silicon epitaxial (strained-Si epi). As noted above, strained-Si epi substrate 12 has a dislocation density of strained-Si epi of less than about 1E6/cm 2 .
  • Structure 10 is preferably a silicon substrate or a germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.
  • Structure 10 may include: one or more NMOS areas 14 within which one or more NMOSFETs 18 (N-type metal-oxide semiconductor field effect transistors) are formed; and may include one or more PMOS areas 16 within which one or more PMOSFETs 28 (P-type metal-oxide semiconductor field effect transistors) are formed. It is noted that a single, unitary strained-Si epi substrate layer 12 is formed under the NMOSFET's 18 and PMOSFET's 28 as this allows for enhanced mobility for both NMOS and PMOS devices 18 , 28 and allows for a simpler process in forming the underlying strained substrate layer 12 .
  • NMOSFET 18 and PMOSFET 28 each include respective high-k dielectric gate oxide portions 20 , 30 that each have a thickness of preferably from about 10 to 200 ⁇ and more preferably from about 10 to 100 ⁇ .
  • the respective high-k dielectric gate oxide portions 20 , 30 each are preferably comprised of HfO 2 , HfSiO 4 , N-doped hafnium, HfSiO x , ZrO 2 , ZrSiO x or N-doped zirconium silicate (N-doped ZrSiO x ) and more preferably HfO 2 and HfSiO 4 .
  • respective high-k dielectric gate oxide portions 20 , 30 are not formed of Ta 2 O 5 , TiO 2 or Al 2 O 3 as they have been found to have poor mobility, difficult process control and poor thermal stability. As noted above, high-k dielectric gate oxide portions 20 , 30 have a dielectric constant (k) of greater than about 4.0.
  • Respective high-k dielectric gate oxide portions 20 , 30 may be formed by depositing a layer of high-k dielectric gate oxide and then patterning it.
  • the high-k dielectric gate oxide portions 20 , 30 have respective gate electrode portions 22 , 32 having a thickness of preferably from about 500 to 2000 ⁇ and more preferably from about 700 to 1500 ⁇ and being preferably formed of polysilicon (poly Si), TaN, WSi x or tungsten (W) and more preferably polysilicon (poly Si) which is compatible with the current technology.
  • gate electrode portions 22 , 32 are not metal gates, for example not TiN metal gates which, although having a lower work function, is hard to control even when employing dummy gates and has difficult integration issues.
  • Respective sidewall spacers 24 , 34 are formed over NMOS and PMOS gate electrode portions 22 , 32 to a maximum thickness of preferably from about 200 to 800 ⁇ and more preferably from about 250 to 600.
  • Respective source/drains 26 , 36 are also formed adjacent NMOS and PMOS gate electrode portions 22 , 32 within strained-Si epi substrate 12 to a maximum depth of preferably from about 300 to 1500 ⁇ and more preferably from about 400 to 1200 ⁇ .
  • an isolation structure 40 may be formed within strained-Si epi substrate 12 /structure 10 between NMOS/PMOS devices 18 , 28 to electrically isolate them from each other for example.
  • Isolation structure 40 may be a shallow trench isolation (STI) structure, for example.
  • STI shallow trench isolation
  • NMOS devices 18 only PMOS devices 28 or other devices or a combination thereof may be formed over structure 10 and strained-Si epi substrate 12 .
  • strained substrate 12 is comprised of an upper strained-Si epi layer 54 over a relaxed Si 1-x Ge x layer 52 (where x is greater than 0 and less than about 0.50) which is in turn over a graded Si 1-y Ge y layer 50 (where y is 0 or about 0 proximate the interface between graded Si 1-y Ge y layer 50 which is in turn over a seed layer 41 and structure 10 and gradually increases (therefore graded) to about X at the interface between graded Si 1-y Ge y layer 50 and relaxed Si 1-x Ge x layer 52 ).
  • Upper strained-Si epi layer 54 has a thickness of preferably from about 100 to 500 ⁇ , more preferably from about 150 to 400 ⁇ and most preferably from about 200 to 300 ⁇ .
  • Relaxed Si 1-x Ge x layer 52 has a thickness of preferably from about 1000 to 50,000 ⁇ .
  • Graded Si 1-y Ge y layer 50 has a thickness of preferably from about 2000 to 50,000 ⁇ .
  • Seed layer 41 has a thickness of preferably from about 10 to 200 nm.
  • strained-Si epi layer 54 has a dislocation density of strained-Si epi of less than about 1E6/cm 2 .
  • strained substrate 12 is comprised of an upper strained-Si epi layer 62 over a Si 1-x Ge x layer 61 which in turn is over a silicon oxide (SiO 2 ) layer 60 thus forming a silicon-on-insulator (SOI).
  • Upper strained-Si epi layer 62 is bonded to SiO 2 layer 60 .
  • Strained-Si epi layer 62 has a thickness of preferably from about 100 to 500 ⁇ , more preferably from about 150 to 400 ⁇ and most preferably from about 200 to 300 ⁇ .
  • Si 1-x Ge x layer 61 has a thickness of preferably from about 700 to 1200 ⁇ .
  • SiO 2 layer 60 has a thickness of preferably from about 800 to 2000 ⁇ .
  • strained-Si epi layer 62 has a dislocation density of strained-Si epi of less than about 1E6/cm 2 .
  • strained substrate 12 is comprised of an upper strained-Si epi layer 78 over an upper relaxed Si 1-x Ge x layer 76 (where x is greater than 0 and less than about 0.50 which is in turn over a graded Si 1-y Ge y layer 74 (where y is about z proximate the interface between graded Si 1-y Ge y layer 74 and epi layer 72 and gradually increases (therefore graded) to about x at the interface between graded Si 1-y Ge y layer 74 and upper relaxed Si 1-x Ge x layer 77 ) which is in turn over a thin epi silicon layer 72 which is in turn over a lower relaxed Si 1-z Ge z layer 70 (where z is greater than 0 and less than about y where x ⁇ y ⁇ z.
  • Upper strained-Si epi layer 78 has a thickness of preferably from about 100 to 500 ⁇ , more preferably from about 150 to 400 ⁇ and most preferably from about 200 to 300 ⁇ .
  • Upper relaxed Si 1-x Ge x layer 76 has a thickness of preferably from about 1000 to 50,000 ⁇ and more preferably from about 2000 to 40,000 ⁇ .
  • Graded Si 1-y Ge y layer 74 has a thickness of preferably from about 200 to 50,000 ⁇ and more preferably from about 500 to 25,000 ⁇ .
  • Thin epi silicon layer 72 has a thickness of preferably from about 20 to 500 ⁇ and more preferably from about 50 to 200 ⁇ .
  • Lower relaxed Si 1-z Ge z layer 70 has a thickness of preferably from about 200 to 50,000 ⁇ and more preferably from about 500 to 25,000 ⁇ .
  • strained-Si epi layer 78 has a dislocation density of strained-Si epi of less than about 1E6/cm 2 .
  • strained substrate 12 is comprised of an upper strained-Si epi layer 88 over an upper relaxed epi Si 1-x Ge x layer 86 (where x may be constant or graded) over constant (i.e. non-graded with a constant Ge concentration Si 1-y Ge y layer 84 which is in turn over Si epi layer 82 which is in turn over constant Si 1-z Ge z layer 80 (i.e. non-graded with a constant Ge concentration); where x ⁇ y ⁇ z.
  • Upper strained-epi Si layer 88 has a thickness of preferably from about 20 to 500 ⁇ and more preferably from about 50 to 300 ⁇ .
  • Upper relaxed Si 1-x Ge x layer 86 (constant or graded) has a thickness of preferably from about 200 to 30,000 ⁇ and more preferably from about 300 to 5000 ⁇ .
  • Constant Si 1-y Ge y layer 84 has a thickness of preferably from about 200 to 20,000 ⁇ and more preferably from about 300 to 5000 ⁇ .
  • Si Epi Layer 82 has a thickness of preferably from about 20 to 500 ⁇ and more preferably from about 50 to 300 ⁇ .
  • Constant Si 1-z Ge z layer 80 has a thickness of preferably from about 200 to 20,000 ⁇ and more preferably from about 300 to 5000 ⁇ .
  • Layers 80 , 82 , 84 , 88 are strained layers.
  • NMOSFET(s) 18 , PMOSFET(s) 28 and other devices formed over the high-k dielectric gate oxide portions 20 , 30 /strained substrate 12 may also be referred to as high-k devices as they incorporate high-k dielectric gate oxide portions.

Abstract

At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

Description

FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to formation of devices incorporating high-k dielectric gate oxide layers.
BACKGROUND OF THE INVENTION
High-k dielectric materials have been investigated to replace conventional gate oxide layers due to excellent current-leakage reduction seen when using the high-k dielectric materials at the same equivalent-oxide-thickness (EOT). However, high-k dielectric materials also suffer poor mobility and high threshold voltage issues in the electric performance of devices.
U.S. Pat. No. 6,310,367 B1 to Yagishita et al. describes a strained Si and high-k gate dielectric Tx process wherein the concentration of Ge in the channel layer of the NMOSFET is lower that the concentration of Ge in the channel layer of the PMOSFET. The gate electrodes of the NMOSFET and the PMOSFET are made of metallic materials.
U.S. Pat. No. 5,357,119 to Wang et al. describes an SiGe and gate oxide process.
U.S. Pat. No. 6,353,249 B1 to Boyd et al. describes an SiGe substrate and high-k gate dielectric.
U.S. Pat. No. 6,271,094 B1 to Chooi et al. and U.S. Pat. No. 6,335,238 B1 to Hanttangady et al. are related SiGe substrate and high-k dielectric Tx patents.
U.S. Pat. No. 6,287,903 B1 to Okuno et al. describes a structure and method for a large-permittivity dielectric using a germanium layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide improved substrate/high-k dielectric gate oxide material structures and methods of forming same.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a strained substrate formed thereover is provided. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. The at least one dielectric gate oxide portion being comprised of HfO2, HfSiO4, N-doped hafnium silicate (N-doped HfSiOx), ZrO2 or ZrSiOx. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. The invention also includes a method of forming the at least one high-k device.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
FIG. 1 schematically illustrate a preferred embodiment of the present invention employing a first preferred embodiment strained-Si substrate.
FIG. 2 schematically illustrates a second preferred embodiment of the strained-Si substrate of the present invention.
FIG. 3 schematically illustrates a third preferred embodiment of the strained-Si substrate of the present invention.
FIG. 4 schematically illustrates a fourth preferred embodiment of the strained-Si substrate of the present invention.
FIG. 5 schematically illustrates a fifth preferred embodiment of the strained-Si substrate of the present invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
For the purposes of this invention, all strained-Si epi layers/substrates have a dislocation density of strained-Si epi of less than about 1E6/cm2 and a high-k dielectric material has a dielectric constant (k) of greater than about 4.0.
Strained-Si Epi Layer 12—FIG. 1 (First Embodiment)
As shown in FIG. 1, the preferred structure of the present embodiment includes a semiconductor structure 10 having a strained substrate 12 formed thereover to a thickness of preferably from about 3000 to 100,000 Å and more preferably from about 4000 to 50,000 Å.
In the first embodiment, strained substrate 12 is comprised of entirely of strained-silicon epitaxial (strained-Si epi). As noted above, strained-Si epi substrate 12 has a dislocation density of strained-Si epi of less than about 1E6/cm2.
Structure 10 is preferably a silicon substrate or a germanium substrate, is more preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.
Structure 10 may include: one or more NMOS areas 14 within which one or more NMOSFETs 18 (N-type metal-oxide semiconductor field effect transistors) are formed; and may include one or more PMOS areas 16 within which one or more PMOSFETs 28 (P-type metal-oxide semiconductor field effect transistors) are formed. It is noted that a single, unitary strained-Si epi substrate layer 12 is formed under the NMOSFET's 18 and PMOSFET's 28 as this allows for enhanced mobility for both NMOS and PMOS devices 18, 28 and allows for a simpler process in forming the underlying strained substrate layer 12.
NMOSFET 18 and PMOSFET 28 each include respective high-k dielectric gate oxide portions 20, 30 that each have a thickness of preferably from about 10 to 200 Å and more preferably from about 10 to 100 Å. The respective high-k dielectric gate oxide portions 20, 30 each are preferably comprised of HfO2, HfSiO4, N-doped hafnium, HfSiOx, ZrO2, ZrSiOx or N-doped zirconium silicate (N-doped ZrSiOx) and more preferably HfO2 and HfSiO4. It is noted that respective high-k dielectric gate oxide portions 20, 30 are not formed of Ta2O5, TiO2 or Al2O3 as they have been found to have poor mobility, difficult process control and poor thermal stability. As noted above, high-k dielectric gate oxide portions 20, 30 have a dielectric constant (k) of greater than about 4.0.
Respective high-k dielectric gate oxide portions 20, 30 may be formed by depositing a layer of high-k dielectric gate oxide and then patterning it.
The high-k dielectric gate oxide portions 20, 30 have respective gate electrode portions 22, 32 having a thickness of preferably from about 500 to 2000 Å and more preferably from about 700 to 1500 Å and being preferably formed of polysilicon (poly Si), TaN, WSix or tungsten (W) and more preferably polysilicon (poly Si) which is compatible with the current technology. It is noted that gate electrode portions 22, 32 are not metal gates, for example not TiN metal gates which, although having a lower work function, is hard to control even when employing dummy gates and has difficult integration issues.
Respective sidewall spacers 24, 34 are formed over NMOS and PMOS gate electrode portions 22, 32 to a maximum thickness of preferably from about 200 to 800 Å and more preferably from about 250 to 600.
Respective source/drains 26, 36 are also formed adjacent NMOS and PMOS gate electrode portions 22, 32 within strained-Si epi substrate 12 to a maximum depth of preferably from about 300 to 1500 Å and more preferably from about 400 to 1200 Å.
As shown in FIG. 1, an isolation structure 40 may be formed within strained-Si epi substrate 12/structure 10 between NMOS/PMOS devices 18, 28 to electrically isolate them from each other for example. Isolation structure 40 may be a shallow trench isolation (STI) structure, for example.
It is noted that only NMOS devices 18, only PMOS devices 28 or other devices or a combination thereof may be formed over structure 10 and strained-Si epi substrate 12.
Strained-Si Epi Layer 54/Relaxed Si1-xGex Layer 52/Graded Si1-yGey Layer Substrate 12—FIG. 2 (Second Embodiment)
As shown in FIG. 2 and in the second embodiment, strained substrate 12 is comprised of an upper strained-Si epi layer 54 over a relaxed Si1-xGex layer 52 (where x is greater than 0 and less than about 0.50) which is in turn over a graded Si1-yGey layer 50 (where y is 0 or about 0 proximate the interface between graded Si1-yGey layer 50 which is in turn over a seed layer 41 and structure 10 and gradually increases (therefore graded) to about X at the interface between graded Si1-yGey layer 50 and relaxed Si1-xGex layer 52).
Upper strained-Si epi layer 54 has a thickness of preferably from about 100 to 500 Å, more preferably from about 150 to 400 Å and most preferably from about 200 to 300 Å. Relaxed Si1-xGex layer 52 has a thickness of preferably from about 1000 to 50,000 Å. Graded Si1-yGey layer 50 has a thickness of preferably from about 2000 to 50,000 Å. Seed layer 41 has a thickness of preferably from about 10 to 200 nm.
As noted above, strained-Si epi layer 54 has a dislocation density of strained-Si epi of less than about 1E6/cm2.
Strained-Si Epi Layer 62/SiO2 Layer 60 (SOI Layer 12)—FIG. 3 (Third Embodiment)
As shown in FIG. 3 and in the third embodiment, strained substrate 12 is comprised of an upper strained-Si epi layer 62 over a Si1-xGex layer 61 which in turn is over a silicon oxide (SiO2) layer 60 thus forming a silicon-on-insulator (SOI). Upper strained-Si epi layer 62 is bonded to SiO2 layer 60.
Strained-Si epi layer 62 has a thickness of preferably from about 100 to 500 Å, more preferably from about 150 to 400 Å and most preferably from about 200 to 300 Å. Si1-xGex layer 61 has a thickness of preferably from about 700 to 1200 Å. SiO2 layer 60 has a thickness of preferably from about 800 to 2000 Å.
As noted above, strained-Si epi layer 62 has a dislocation density of strained-Si epi of less than about 1E6/cm2.
Strained-Si Epi Layer 78/Upper Relaxed Si1-xGex Layer 76/Graded Si1-yGey Layer 74/Thin Epi Layer 72/Lower Relaxed Si1-zGez Layer 70—FIG. 4 (Fourth Embodiment)
As shown in FIG. 4 and in the fourth embodiment, strained substrate 12 is comprised of an upper strained-Si epi layer 78 over an upper relaxed Si1-xGex layer 76 (where x is greater than 0 and less than about 0.50 which is in turn over a graded Si1-yGey layer 74 (where y is about z proximate the interface between graded Si1-yGey layer 74 and epi layer 72 and gradually increases (therefore graded) to about x at the interface between graded Si1-yGey layer 74 and upper relaxed Si1-xGex layer 77) which is in turn over a thin epi silicon layer 72 which is in turn over a lower relaxed Si1-zGez layer 70 (where z is greater than 0 and less than about y where x≧y≧z.
Upper strained-Si epi layer 78 has a thickness of preferably from about 100 to 500 Å, more preferably from about 150 to 400 Å and most preferably from about 200 to 300 Å. Upper relaxed Si1-xGex layer 76 has a thickness of preferably from about 1000 to 50,000 Å and more preferably from about 2000 to 40,000 Å. Graded Si1-yGey layer 74 has a thickness of preferably from about 200 to 50,000 Å and more preferably from about 500 to 25,000 Å. Thin epi silicon layer 72 has a thickness of preferably from about 20 to 500 Å and more preferably from about 50 to 200 Å. Lower relaxed Si1-zGez layer 70 has a thickness of preferably from about 200 to 50,000 Å and more preferably from about 500 to 25,000 Å.
As noted above, strained-Si epi layer 78 has a dislocation density of strained-Si epi of less than about 1E6/cm2.
Upper Strained-Si epi layer 88/Relaxed-Si1-xGex Layer 86/Constant Si1-yGey Layer 84/Si Epi Layer 82/Constant Si1-zGez Layer 80—FIG. 5 (Fifth Embodiment)
As shown in FIG. 5 and in the fifth embodiment, strained substrate 12 is comprised of an upper strained-Si epi layer 88 over an upper relaxed epi Si1-xGex layer 86 (where x may be constant or graded) over constant (i.e. non-graded with a constant Ge concentration Si1-yGey layer 84 which is in turn over Si epi layer 82 which is in turn over constant Si1-zGez layer 80 (i.e. non-graded with a constant Ge concentration); where x≧y≧z.
Upper strained-epi Si layer 88 has a thickness of preferably from about 20 to 500 Å and more preferably from about 50 to 300 Å. Upper relaxed Si1-xGex layer 86 (constant or graded) has a thickness of preferably from about 200 to 30,000 Å and more preferably from about 300 to 5000 Å. Constant Si1-yGey layer 84 has a thickness of preferably from about 200 to 20,000 Å and more preferably from about 300 to 5000 Å. Si Epi Layer 82 has a thickness of preferably from about 20 to 500 Å and more preferably from about 50 to 300 Å. Constant Si1-zGez layer 80 has a thickness of preferably from about 200 to 20,000 Å and more preferably from about 300 to 5000 Å.
Layers 80, 82, 84, 88 are strained layers.
NMOSFET(s) 18, PMOSFET(s) 28 and other devices formed over the high-k dielectric gate oxide portions 20, 30/strained substrate 12 may also be referred to as high-k devices as they incorporate high-k dielectric gate oxide portions.
Advantages of the Present Invention
The advantages of one or more embodiments of the present invention include:
    • 1. higher mobility of high-k devices is achieved; and
    • 3. reduced threshold voltage of high-k devices is achieved.
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Claims (21)

1. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising an uppermost strained-Si epi layer, a middle relaxed Si1-xGex layer and a lowermost graded Si1-yGey layer, the uppermost strained-Si epi layer being disposed directly on the middle relaxed Si1-xGex layer;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
2. The device of claim 1, the uppermost strained-Si epi layer having a thickness of from about 100 to 500 Å; the middle relaxed Si1-xGex layer having a thickness of from about 1000 to 50,000 Å; and the lowermost graded Si1-yGey layer having a thickness of from about 200 to 50,000 Å.
3. The device of claim 1, where x is greater than 0 and less than about 0.50 and where y is 0 or about 0 proximate the structure and increases to about x proximate the middle relaxed Si1-xGex layer, wherein x≧y.
4. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising an uppermost strained-Si epi layer, a middle Si1-xGex layer and a lower silicon oxide layer;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
5. The device of claim 4, wherein the uppermost strained-Si epi layer has a thickness of from about 100 to 500 Å, the middle Si1-xGex layer has a thickness of from about 700 to 1200 Å and the lower silicon oxide layer has a thickness of from about 800 to 2000 Å.
6. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising an uppermost strained-Si epi layer over an upper relaxed Si1-xGex layer over a graded Si1-yGey layer over an epi layer over a lowermost relaxed Si1-zGez layer, wherein x≧y≧z;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
7. The device of claim 6, the uppermost strained-Si epi layer having a thickness of from about 100 to 500 Å; the upper relaxed Si1-xGex layer having a thickness of from about 1000 to 50,000 Å; the graded Si1-yGey layer having a thickness of from about 2000 to 50,000 Å; the epi layer having a thickness of from about 20 to 500 Å; and the lowermost relaxed Si1-zGez layer having a thickness of from about 200 to 50,000 Å.
8. The device of claim 6, the uppermost strained-Si epi layer having a thickness of from about 150 to 300 Å; the upper relaxed Si1-xGex layer having a thickness of from about 2000 to 40,000 Å; the graded Si1-yGey layer having a thickness of from about 500 to 25,000 Å; the epi layer having a thickness of from about 50 to 200 Å; and the lowermost relaxed Si1-zGez layer having a thickness of from about 500 to 25,000 Å.
9. The device of claim 6, where x is no less than y and less than about 0.50, where y is no less than z proximate the epi layer and increases to about x proximate the upper relaxed Si1-xGex layer, and where z is greater than 0 and less than about 0.50.
10. The device of claim 6, wherein the at least one dielectric gate oxide portion being comprised of HfO2 or HfSiO4.
11. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising an uppermost strained-Si epi layer, a relaxed Si1-yGey layer under the uppermost strained-Si epi layer, a constant Si1-yGey layer under the relaxed SiyGey layer, a silicon epi layer under the constant Si1-yGey layer, and a constant Si1-zGez layer under the silicon epi layer, wherein the uppermost relaxed-Si epi layer is comprised of Si1-xGex wherein x is constant or graded;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
12. The device of claim 11, wherein the relaxed Si1-yGey layer has a thickness of from about 200 to 30,000 Å, the constant Si1-yGey layer has a thickness of from about 200 to 20,000 Å, the silicon epi layer has a thickness of from about 20 to 500 Å, the constant Si1-zGez layer has a thickness of from about 200 to 20,000 Å, and the uppermost strained-Si epi layer has a thickness of from about 20 to 500 Å.
13. The device of claim 11, wherein the relaxed Si1-yGey layer has a thickness of from about 300 to 5000 Å, the constant Si1-yGey layer has a thickness of from about 300 to 5000 Å, the silicon epi layer has a thickness of from about 50 to 300 Å, the constant Si1-zGez layer has a thickness of from about 300 to 5000 Å, and the uppermost strained-Si epi layer has a thickness of from about 50 to 300 Å.
14. The device of claim 11, wherein the at least one dielectric gate oxide portion is comprised of HfO2 or HfSiO4.
15. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising at least an uppermost strained-Si epi layer having a dislocation density of strained-Si epi of less than about 1E6/cm2;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
16. The structure of claim 15, wherein the at least one dielectric gate oxide portion is comprised of HfO2, HfSiO4, N-doped hafnium, HfSiOX, ZrO2, ZrSiOX or N-doped zirconium silicate.
17. The device of claim 15, wherein the structure is a silicon substrate or a germanium substrate.
18. The device of claim 15, wherein the strained substrate is comprised of only the uppermost strained-Si epi layer.
19. At least one high-k device, comprising:
a structure having a strained substrate formed thereover, the strained substrate comprising only an uppermost strained-Si epi layer having a thickness of from about 100 to 500 Å;
at least one dielectric gate oxide portion over the strained substrate, the at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0; and
a device over each of the at least one dielectric gate oxide portion to complete the at least one high-k device.
20. The device of claim 19, the uppermost strained-Si epi layer having a thickness of from about 150 to 300 Å.
21. The device of claim 19, the uppermost strained-Si epi layer having a thickness of from about 200 to 300 Å.
US10/762,164 2004-01-21 2004-01-21 Noble high-k device Active 2024-12-26 US7351994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/762,164 US7351994B2 (en) 2004-01-21 2004-01-21 Noble high-k device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/762,164 US7351994B2 (en) 2004-01-21 2004-01-21 Noble high-k device

Publications (2)

Publication Number Publication Date
US20050156255A1 US20050156255A1 (en) 2005-07-21
US7351994B2 true US7351994B2 (en) 2008-04-01

Family

ID=34750338

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/762,164 Active 2024-12-26 US7351994B2 (en) 2004-01-21 2004-01-21 Noble high-k device

Country Status (1)

Country Link
US (1) US7351994B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052066A1 (en) * 2008-08-26 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. structure and method for a cmos device with doped conducting metal oxide as the gate electrode

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361961B2 (en) * 2005-04-25 2008-04-22 Altera Corporation Method and apparatus with varying gate oxide thickness
US7964910B2 (en) 2007-10-17 2011-06-21 International Business Machines Corporation Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US6271094B1 (en) 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6287903B1 (en) 1997-12-24 2001-09-11 Texas Instruments Incorporated Structure and method for a large-permittivity dielectric using a germanium layer
US6310367B1 (en) 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US6335238B1 (en) 1997-05-08 2002-01-01 Texas Instruments Incorporated Integrated dielectric and method
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6407406B1 (en) 1998-06-30 2002-06-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20020125497A1 (en) * 2001-03-02 2002-09-12 Fitzgerald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6784101B1 (en) * 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
US6805962B2 (en) * 2002-01-23 2004-10-19 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US20060057749A1 (en) * 2002-12-11 2006-03-16 Robert Dwilinski Template type substrate and a method of preparing the same
US20060197126A1 (en) * 2002-06-07 2006-09-07 Amberwave Systems Corporation Methods for forming structures including strained-semiconductor-on-insulator devices
US7217603B2 (en) * 2002-06-25 2007-05-15 Amberwave Systems Corporation Methods of forming reacted conductive gate electrodes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387903B1 (en) * 1997-08-27 2002-05-14 Merck & Co., Inc. Inhibitors of prenyl-protein transferase

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US6335238B1 (en) 1997-05-08 2002-01-01 Texas Instruments Incorporated Integrated dielectric and method
US6287903B1 (en) 1997-12-24 2001-09-11 Texas Instruments Incorporated Structure and method for a large-permittivity dielectric using a germanium layer
US6407406B1 (en) 1998-06-30 2002-06-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6310367B1 (en) 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US7084431B2 (en) * 1999-03-12 2006-08-01 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6271094B1 (en) 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US6353249B1 (en) 2000-02-14 2002-03-05 International Businsess Machines Corporation MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US20020125497A1 (en) * 2001-03-02 2002-09-12 Fitzgerald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6805962B2 (en) * 2002-01-23 2004-10-19 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US6784101B1 (en) * 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
US20060197126A1 (en) * 2002-06-07 2006-09-07 Amberwave Systems Corporation Methods for forming structures including strained-semiconductor-on-insulator devices
US7217603B2 (en) * 2002-06-25 2007-05-15 Amberwave Systems Corporation Methods of forming reacted conductive gate electrodes
US20060057749A1 (en) * 2002-12-11 2006-03-16 Robert Dwilinski Template type substrate and a method of preparing the same
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100052066A1 (en) * 2008-08-26 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. structure and method for a cmos device with doped conducting metal oxide as the gate electrode
US7947588B2 (en) 2008-08-26 2011-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a CMOS device with doped conducting metal oxide as the gate electrode

Also Published As

Publication number Publication date
US20050156255A1 (en) 2005-07-21

Similar Documents

Publication Publication Date Title
US6921913B2 (en) Strained-channel transistor structure with lattice-mismatched zone
US7138310B2 (en) Semiconductor devices having strained dual channel layers
CN101364600B (en) Circuit structure and method for processing circuit structure
US8125032B2 (en) Modified hybrid orientation technology
US6620664B2 (en) Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
TWI473271B (en) Dual metal gate corner
CN101304031B (en) Ciucuit structure and manufacturing method thereof
US20170040449A1 (en) Reduced Local Threshold Voltage Variation MOSFET Using Multiple Layers of Epi for Improved Device Operation
US20090149010A1 (en) STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C
US7531398B2 (en) Methods and devices employing metal layers in gates to introduce channel strain
WO2006007394A2 (en) Strained tri-channel layer for semiconductor-based electronic devices
CN103311247A (en) Semiconductor device and manufacturing method thereof
US20090174003A1 (en) Dual work function device with stressor layer and method for manufacturing the same
EP1976017A1 (en) Semiconductor device
CN101000928A (en) Thin silicon single diffusion field effect transistor and forming method thereof
JP2000031491A (en) Semiconductor device, its manufacture, semiconductor substrate and its manufacture
US20070132011A1 (en) Semiconductor device and method of fabricating the same background
JP2010118500A (en) Semiconductor device and its production process
US7994037B2 (en) Gate dielectrics of different thickness in PMOS and NMOS transistors
CN101364599B (en) CMOS structure, method for processing cmos structure and processer containing at least cmos circuit
JP2011003717A (en) Semiconductor apparatus and method of manufacturing the same
US8502325B2 (en) Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance
JP2006278376A (en) Semiconductor device and manufacturing method thereof
US7351994B2 (en) Noble high-k device
JP2004247341A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAO, LIANG-GI;CHANG, TIEN-CHIH;WANG, MING-FANG;AND OTHERS;REEL/FRAME:014915/0980

Effective date: 20031030

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12