US7316980B2 - Method for forming ferrocapacitors and FeRAM devices - Google Patents

Method for forming ferrocapacitors and FeRAM devices Download PDF

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US7316980B2
US7316980B2 US10/678,758 US67875803A US7316980B2 US 7316980 B2 US7316980 B2 US 7316980B2 US 67875803 A US67875803 A US 67875803A US 7316980 B2 US7316980 B2 US 7316980B2
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ferroelectric material
openings
depositing
electrode layer
etching
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US20050074979A1 (en
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Haoren Zhuang
Ulrich Egger
Rainer Bruchhaus
Karl Hornik
Jenny Lian
Stefan Gernhardt
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Qimonda AG
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Infineon Technologies AG
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Priority to JP2006532251A priority patent/JP2007507882A/en
Priority to EP04775590A priority patent/EP1668675A1/en
Priority to PCT/SG2004/000268 priority patent/WO2005031816A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present invention relates to methods for forming ferrocapacitors of the kind used in FeRAM devices, and to methods for forming FeRAM devices themselves.
  • the invention further relates to FeRAM devices including ferrocapacitors formed by the method.
  • a vertical capacitor includes a ferroelectric element sandwiched between electrodes to either side, all at substantially the same level in the FeRAM device.
  • FIGS. 1 to 5 The process steps of a conventional technique for forming a vertical capacitor structure are illustrated in FIGS. 1 to 5 .
  • the vertical capacitors are typically formed over a substructure, which may for example be of the form shown in FIG. 1 in which various electronic components 1 are connected to conductive plugs 3 which extend upwards through a matrix 5 (e.g. of TEOS (tetraethylorthosilicate)).
  • a matrix 5 e.g. of TEOS (tetraethylorthosilicate)
  • TiN/Ir barrier elements 7 having a top surface flush with the surface of the matrix 5 .
  • an insulating layer 9 of Al 2 O 3 is formed over the surface of the matrix 5 , and a layer of ferroelectric material 11 such as PZT (PbZrTiO 3 ) is formed over that.
  • hardmask elements 13 are deposited in selected areas of the PZT layer 11 , and the portions of the PZT and Al 2 O 3 which are not protected by the hardmask elements 13 are etched all the way through, forming openings 17 .
  • Al 2 O 3 fences 15 are often formed on the sides of the remaining PZT.
  • the openings 17 are then filled with conductive material 19 such as IrO 2 , by depositing IrO 2 over the entire structure, as shown in FIG. 4 , and chemical-mechanical planarization (CMP) polishing is performed to form a flat upper surface 21 which is partly the PZT 11 and partly the conductive material 19 . Then, as shown in FIG. 5 , an Al 2 O 3 layer 23 is formed over the surface 21 .
  • the elements 19 of IrO 2 constitute electrodes, while the remaining PZT 11 forms the dielectric.
  • the vertical capacitor structure has great potential for reducing the cell size, especially if the etching taper angle of the remaining PZT 11 (i.e. the angle between the horizontal direction and the sides of the remaining PZT) is high.
  • the taper angle becomes close to 90°, the Al 2 O 3 fences 15 are more likely to be formed.
  • These fences 15 are difficult to remove (e.g. by a wet cleaning process), and dramatically reduce the Q SW (i.e. the maximum charge which can be stored in the ferrocapacitor) because the insulating fences 15 reduce the effective area of the capacitor.
  • the present invention aims to alleviate the above problem, at least partially, and in particular to provide a new and useful method for forming ferrocapacitors and FeRAM devices with improved properties.
  • the present invention proposes that the etching of the ferroelectric material and Al 2 O 3 layer is performed in a two stage process: in a first stage only the ferroelectric material is etched to form openings in it, leaving the Al 2 O 3 layer substantially Intact (so that fences are not produced); then an electrode layer is deposited into the openings formed in the ferroelectric layer, then further etching is performed to form openings in the Al 2 O 3 layer.
  • the second etching step there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
  • the invention proposes a method for forming a ferrocapacitor which include the steps of:
  • the invention further provides the ferrocapacitor devices produced by the method, and FeRAM devices including such ferrocapacitors.
  • FIGS. 1 to 5 show the steps of a convention method of forming vertical capacitors
  • FIGS. 6 to 9 show the steps of a method which is an embodiment of the invention.
  • FIGS. 6 to 9 The method which is an embodiment of the invention will be explained with reference to FIGS. 6 to 9 .
  • the vertical capacitor structure is formed in these figures over a substructure as shown in FIG. 1 .
  • Elements shown in FIGS. 1 to 5 which exactly correspond to elements in FIGS. 6 to 9 are illustrated by the same reference numerals.
  • the first step of the method is for a layer 31 of an Insulating material such as Al 2 O 3 to be formed over the substructure, and for a thicker layer 33 of ferroelectric material (typically PZT) to be formed over the Al 2 O 3 layer 31 .
  • Hardmask elements 34 are formed over the PZT layer 33 in a formation which exposes areas of the PZT (e.g. circular, square or rectangular areas) which overlie the barrier elements 7 .
  • etching is carried out, using the hardmask elements 34 to form a plurality of openings 35 in the PZT, as shown in FIG. 6 .
  • the openings 35 do not extend through the whole of the PZT layer 33 .
  • a thin layer 37 of PZT remains at the bottom of the openings 35 , and in particular the Al 2 O 3 layer 31 is not disturbed.
  • a layer 39 of a conductive material e.g. IrO 2 is then formed over the structure of FIG. 6 , including in particular portions 41 on the sides of the openings.
  • the portions 41 will constitute electrode elements in the completed ferrocapacitor device, as explained below.
  • a possible thickness range for the layer 39 would be 15 nm to 20 nm.
  • further etching is performed.
  • This further etching thins the layer 39 of conductive material in all places, and in particular removes completely the portions of the layer 39 at the bottom of the openings 35 .
  • the thin layer 37 of PZT at the bottom of the openings 35 is removed, and the openings 35 are extended through the Al 2 O 3 layer 31 , to form gaps in it at which the tops of the barrier elements 7 are exposed.
  • fences of Al 2 O 3 will be formed on the portions 41 of the layer 39 on the sides of the openings, but nevertheless the entire sides of the remaining parts of the PZT layer 33 are in contact with the electrode elements 41 , and therefore have no influence on the Q SW .
  • the openings 35 are filled with further conductive material 43 , such as more IrO 2 .
  • CMP polishing is performed to form a flat upper surface 45 which is partly the PZT 33 and partly the conductive material 43 .
  • Al 2 O 3 layer 47 is formed over the surface 45 , to form the completed structure shown in FIG. 9 .
  • the conductive material 43 makes electrical contact with the barrier elements 7 and the electrode elements 41 remaining from the layer 39 , thereby electrically connecting the electrode elements 41 with desired electrical components of the substructure.

Abstract

Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Description

FIELD OF THE INVENTION
The present invention relates to methods for forming ferrocapacitors of the kind used in FeRAM devices, and to methods for forming FeRAM devices themselves. The invention further relates to FeRAM devices including ferrocapacitors formed by the method.
BACKGROUND OF INVENTION
Many conventional FeRAM devices include a horizontal ferrocapacitor structure, in which a stack of layers is formed including top and bottom electrodes sandwiching a ferroelectric layer. An alternative “vertical capacitor” structure was suggested in U.S. Pat. No. 6,300,652, the disclosure of which is incorporated herein by reference. A vertical capacitor includes a ferroelectric element sandwiched between electrodes to either side, all at substantially the same level in the FeRAM device.
The process steps of a conventional technique for forming a vertical capacitor structure are illustrated in FIGS. 1 to 5. The vertical capacitors are typically formed over a substructure, which may for example be of the form shown in FIG. 1 in which various electronic components 1 are connected to conductive plugs 3 which extend upwards through a matrix 5 (e.g. of TEOS (tetraethylorthosilicate)). The upper ends of the plugs 3 terminate in TiN/Ir barrier elements 7, having a top surface flush with the surface of the matrix 5.
As shown in FIG. 2, an insulating layer 9 of Al2O3 is formed over the surface of the matrix 5, and a layer of ferroelectric material 11 such as PZT (PbZrTiO3) is formed over that.
As shown in FIG. 3, hardmask elements 13 are deposited in selected areas of the PZT layer 11, and the portions of the PZT and Al2O3 which are not protected by the hardmask elements 13 are etched all the way through, forming openings 17. During this process Al2O3 fences 15 are often formed on the sides of the remaining PZT.
The openings 17 are then filled with conductive material 19 such as IrO2, by depositing IrO2 over the entire structure, as shown in FIG. 4, and chemical-mechanical planarization (CMP) polishing is performed to form a flat upper surface 21 which is partly the PZT 11 and partly the conductive material 19. Then, as shown in FIG. 5, an Al2O3 layer 23 is formed over the surface 21. The elements 19 of IrO2 constitute electrodes, while the remaining PZT 11 forms the dielectric.
The vertical capacitor structure has great potential for reducing the cell size, especially if the etching taper angle of the remaining PZT 11 (i.e. the angle between the horizontal direction and the sides of the remaining PZT) is high. However, if the taper angle becomes close to 90°, the Al2O3 fences 15 are more likely to be formed. These fences 15 are difficult to remove (e.g. by a wet cleaning process), and dramatically reduce the QSW (i.e. the maximum charge which can be stored in the ferrocapacitor) because the insulating fences 15 reduce the effective area of the capacitor.
SUMMARY OF THE INVENTION
The present invention aims to alleviate the above problem, at least partially, and in particular to provide a new and useful method for forming ferrocapacitors and FeRAM devices with improved properties.
In general terms, the present invention proposes that the etching of the ferroelectric material and Al2O3 layer is performed in a two stage process: in a first stage only the ferroelectric material is etched to form openings in it, leaving the Al2O3 layer substantially Intact (so that fences are not produced); then an electrode layer is deposited into the openings formed in the ferroelectric layer, then further etching is performed to form openings in the Al2O3 layer. Thus, by the time the second etching step is performed, there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
Specifically, in a first aspect the invention proposes a method for forming a ferrocapacitor which include the steps of:
    • depositing a ferroelectric material over an Insulating layer;
    • a first etching step of etching of the ferroelectric material to form openings in it,
    • depositing an electrode layer into the openings formed in the ferroelectric layer;
    • is a second etching step, after depositing the electrode layer, of etching the insulating layer at the bottom of the openings to form gaps in it; and
    • inserting conductive material into the gaps.
The invention further provides the ferrocapacitor devices produced by the method, and FeRAM devices including such ferrocapacitors.
BRIEF DESCRIPTION OF THE FIGURES
Preferred features of the Invention will now be described, for the sake of illustration only, with reference to the following figures in which:
FIGS. 1 to 5 show the steps of a convention method of forming vertical capacitors; and
FIGS. 6 to 9 show the steps of a method which is an embodiment of the invention.
 DETAILED DESCRIPTION OF THE EMBODIMENTS
The method which is an embodiment of the invention will be explained with reference to FIGS. 6 to 9. The vertical capacitor structure is formed in these figures over a substructure as shown in FIG. 1. Elements shown in FIGS. 1 to 5 which exactly correspond to elements in FIGS. 6 to 9 are illustrated by the same reference numerals.
The first step of the method, as in the conventional method is for a layer 31 of an Insulating material such as Al2O3 to be formed over the substructure, and for a thicker layer 33 of ferroelectric material (typically PZT) to be formed over the Al2O3 layer 31. Hardmask elements 34 are formed over the PZT layer 33 in a formation which exposes areas of the PZT (e.g. circular, square or rectangular areas) which overlie the barrier elements 7. Then, etching is carried out, using the hardmask elements 34 to form a plurality of openings 35 in the PZT, as shown in FIG. 6. However, in contrast to FIG. 3, the openings 35 do not extend through the whole of the PZT layer 33. Typically, a thin layer 37 of PZT remains at the bottom of the openings 35, and in particular the Al2O3 layer 31 is not disturbed.
As shown in FIG. 7, a layer 39 of a conductive material, e.g. IrO2 is then formed over the structure of FIG. 6, including in particular portions 41 on the sides of the openings. The portions 41 will constitute electrode elements in the completed ferrocapacitor device, as explained below. A possible thickness range for the layer 39 would be 15 nm to 20 nm.
As shown in FIG. 8, further etching is performed. This further etching thins the layer 39 of conductive material in all places, and in particular removes completely the portions of the layer 39 at the bottom of the openings 35. Furthermore, the thin layer 37 of PZT at the bottom of the openings 35 is removed, and the openings 35 are extended through the Al2O3 layer 31, to form gaps in it at which the tops of the barrier elements 7 are exposed. During this process, it is possible that fences of Al2O3 will be formed on the portions 41 of the layer 39 on the sides of the openings, but nevertheless the entire sides of the remaining parts of the PZT layer 33 are in contact with the electrode elements 41, and therefore have no influence on the QSW.
Subsequently, the openings 35 are filled with further conductive material 43, such as more IrO2. Then, as in the conventional method, CMP polishing is performed to form a flat upper surface 45 which is partly the PZT 33 and partly the conductive material 43. Then, an Al2O3 layer 47 is formed over the surface 45, to form the completed structure shown in FIG. 9, The conductive material 43 makes electrical contact with the barrier elements 7 and the electrode elements 41 remaining from the layer 39, thereby electrically connecting the electrode elements 41 with desired electrical components of the substructure.
Although only a single embodiment of the invention has been described in detail, many variations of the method are possible within the scope of the invention as will be clear to a skilled reader.

Claims (16)

1. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material on an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer on the openings in the ferroelectric material;
a second etching step, after depositing the electrode layer, of etching to form gaps in the electrode layer and the insulating layer at the bottom of the openings; and
inserting conductive material into the gaps at least on a portion of the electrode layer.
2. A method according to claim 1 in which the first etching step leaves a film of ferroelectric material remaining at the bottom of the openings, and the film of ferroelectric material is removed during the second etching step.
3. A method according to claim 1 further comprising planarizing to form a flat upper surface on the ferroelectric material and depositing an insulating layer over it, after inserting the conductive material.
4. A method according to claim 3 in which the conductive material substantially fills the openings at least up to the planarization level.
5. A method according to claim 1 wherein the electrode layer has a thickness in the range of 15 nm to 20 nm.
6. A method according to claim 1 wherein the insulating layer is Al2O3.
7. A method according to claim 1 wherein the ferroelectric material is PZT.
8. A method according to claim 1 wherein the electrode layer contains iridium.
9. A method according to claim 1 wherein the conductive material contains iridium.
10. A method for forming a ferrocapacitor includes the steps of:
depositing a ferroelectric material over an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material, but leaving a film of ferroelectric material remaining at the bottom of the openings;
depositing an electrode layer into the openings formed in the ferroelectric material;
a second etching step, after depositing the electrode layer, of etching the film of the ferroelectric material and the insulating layer at the bottom of the openings to form gaps; and
inserting conductive material into the gaps.
11. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material over an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer into the openings formed in the ferroelectric material;
a second etching step, after depositing the electrode layer, of etching to form gaps in the electrode layer and the insulating layer at the bottom of the openings;
inserting conductive material into the gaps; and
planarizing to form a flat upper surface on the ferroelectric material and depositing an insulating layer over the upper surface, after inserting the conductive material.
12. A method according to claim 11 in which the conductive material substantially fills the openings at least up to the planarization level.
13. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material over an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer into the openings formed in the ferroelectric material, the electrode layer has a thickness in the range of 15 nm to 20 nm;
a second etching step, after depositing the electrode layer, of etching to remove the electrode layer and the insulating layer at the bottom of the openings; and
inserting conductive material into the gaps.
14. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material over an insulating layer, the insulating layer is Al2O3;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer into the openings formed in the ferroelectric material;
a second etching step, after depositing the electrode layer, of etching to create gaps in the electrode layer and the insulating layer at the bottom of the openings; and
inserting conductive material into the gaps.
15. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material over an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer into the openings formed in the ferroelectric material, wherein the electrode layer contains iridium;
a second etching step, after depositing the electrode layer, of etching to create gaps in the electrode layer and the insulating layer at the bottom of the openings; and
inserting conductive material into the gaps.
16. A method for forming a vertical ferrocapacitor comprising:
depositing a ferroelectric material over an insulating layer;
a first etching step of etching of the ferroelectric material to form openings in the ferroelectric material;
depositing an electrode layer into the openings formed in the ferroelectric material;
a second etching step, after depositing the electrode layer, of etching to create gaps in the electrode layer and the insulating layer at the bottom of the openings; and
inserting conductive material into the gaps, wherein the conductive material contains iridium.
US10/678,758 2003-10-02 2003-10-02 Method for forming ferrocapacitors and FeRAM devices Expired - Fee Related US7316980B2 (en)

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JP2006532251A JP2007507882A (en) 2003-10-02 2004-08-31 Method for forming vertical ferroelectric capacitor
EP04775590A EP1668675A1 (en) 2003-10-02 2004-08-31 Method for forming vertical ferroelectric capacitors
PCT/SG2004/000268 WO2005031816A1 (en) 2003-10-02 2004-08-31 Method for forming vertical ferroelectric capacitors

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342436B2 (en) 2019-06-24 2022-05-24 Samsung Electronics Co., Ltd. Semiconductor devices

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4336001A1 (en) 1993-10-21 1995-04-27 Siemens Ag Capacitor arrangement and production method therefor
US6033919A (en) 1996-10-25 2000-03-07 Texas Instruments Incorporated Method of forming sidewall capacitance structure
US6259125B1 (en) * 1995-09-21 2001-07-10 Micron Technology, Inc. Scalable high dielectric constant capacitor
US6300652B1 (en) 1995-11-22 2001-10-09 Infineon Technologies Ag Memory cell configuration and method for its production
US20010031529A1 (en) 1998-07-31 2001-10-18 Franz Hofmann Method for fabricating a memory cell
US20010055869A1 (en) * 1998-09-03 2001-12-27 Micron Technology, Inc. Method for producing low carbon/oxygen conductive layers
US6351005B1 (en) 1998-09-17 2002-02-26 Micron Technology, Inc. Integrated capacitor incorporating high K dielectric
US20020154265A1 (en) * 2001-04-20 2002-10-24 Hubby Laurence M. Fiber faceplate suspended particle display
US20030155595A1 (en) * 2002-02-15 2003-08-21 Fujitsu Limited Semiconductor device and method of manufacturing the same
US6642564B2 (en) * 2001-07-18 2003-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and method for fabricating the same
US20030227799A1 (en) * 2002-01-23 2003-12-11 Yutaka Higo Tunnel magnetoresistive effect element, method of manufacturing tunnel magnetoresistive effect element and magnetic memory device
US6753437B1 (en) * 2003-01-22 2004-06-22 Tanaka Kikinzoku Kogyo K.K. CVD material compound and method for manufacturing the same, and CVD method of iridium or iridium compound thin film

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4336001A1 (en) 1993-10-21 1995-04-27 Siemens Ag Capacitor arrangement and production method therefor
US6259125B1 (en) * 1995-09-21 2001-07-10 Micron Technology, Inc. Scalable high dielectric constant capacitor
US6300652B1 (en) 1995-11-22 2001-10-09 Infineon Technologies Ag Memory cell configuration and method for its production
US6033919A (en) 1996-10-25 2000-03-07 Texas Instruments Incorporated Method of forming sidewall capacitance structure
US20010031529A1 (en) 1998-07-31 2001-10-18 Franz Hofmann Method for fabricating a memory cell
US20010055869A1 (en) * 1998-09-03 2001-12-27 Micron Technology, Inc. Method for producing low carbon/oxygen conductive layers
US6351005B1 (en) 1998-09-17 2002-02-26 Micron Technology, Inc. Integrated capacitor incorporating high K dielectric
US20020154265A1 (en) * 2001-04-20 2002-10-24 Hubby Laurence M. Fiber faceplate suspended particle display
US6642564B2 (en) * 2001-07-18 2003-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and method for fabricating the same
US20030227799A1 (en) * 2002-01-23 2003-12-11 Yutaka Higo Tunnel magnetoresistive effect element, method of manufacturing tunnel magnetoresistive effect element and magnetic memory device
US20030155595A1 (en) * 2002-02-15 2003-08-21 Fujitsu Limited Semiconductor device and method of manufacturing the same
US6753437B1 (en) * 2003-01-22 2004-06-22 Tanaka Kikinzoku Kogyo K.K. CVD material compound and method for manufacturing the same, and CVD method of iridium or iridium compound thin film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342436B2 (en) 2019-06-24 2022-05-24 Samsung Electronics Co., Ltd. Semiconductor devices

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