US7254690B2 - Pipelined semiconductor memories and systems - Google Patents
Pipelined semiconductor memories and systems Download PDFInfo
- Publication number
- US7254690B2 US7254690B2 US10/850,719 US85071904A US7254690B2 US 7254690 B2 US7254690 B2 US 7254690B2 US 85071904 A US85071904 A US 85071904A US 7254690 B2 US7254690 B2 US 7254690B2
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- United States
- Prior art keywords
- row
- address
- independently addressable
- particular bank
- bank
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
Definitions
- RLDRAM reduced latency DRAM
- the banks are cycled in sequence and the PAGE in the previously accessed bank is closed in each bank as the cycling starts to a new bank access.
Abstract
Description
- a) Addresses are received, appropriately level shifted/converted after detection (on chip)
- b) Bank selection is made
- c) Row address is streered to the selected bank
- d) Row address is decoded (to select 1 of n rows) in the specific bank (assumes proper subarray is selected, if necessary)
- e) Word line is activated
- f) Signal from all storage cells (memory cells) in the related row, are detected and amplified by the sense amplifier (for a read operation in a dynamic cell, appropriate digital level is written instead of RESTORE)
- g) Column start address is selected, data prefetched in the ‘burst order’ defined (activation of column address select can be posted earlier; ‘posted CAS’ as is well known in the industry)
- h) If the command is READ, appropriate data is sent to output buffers (depending on data fetch schemes, DDR or QDR is employed
- i) If the command is WRITE, appropriate data is received from the input buffers (level shifted and amplified as needed) is coupled to appropriate lines of columns at the sense amplifiers
- j) RESTORE is performed if a memory core requires that function, automatically, as a part of the READ
- k) Page is left open for further READ/WRITE operations into the same PAGE (usually one Page is equal to one row of data). As is well known in the industry, nonvolatile memory IC's also used PAGE driven architecture, by employing an SRAM buffer.
- 1) it steers the address to the designated bank (if a DRAM or SRAM) or block/sector (if Flash memory) or similar memory array unit as used by memory IC's.
- 2) it has the ability to map, if required, addresses, or sequence the addresses appropriately, to avoid bank/block/sector/subarray/row conflicts
- 3) if a BANK is busy, it has the ability to hold the addresses in a STAGING area temporarily, and release that address to that bank at the appropriate time without causing device malfunction. This increases bus utilization time.
Claims (8)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/850,719 US7254690B2 (en) | 2003-06-02 | 2004-05-20 | Pipelined semiconductor memories and systems |
US11/771,689 US20080010429A1 (en) | 2003-06-02 | 2007-06-29 | Pipelined semiconductor memories and systems |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US47522403P | 2003-06-02 | 2003-06-02 | |
US10/850,719 US7254690B2 (en) | 2003-06-02 | 2004-05-20 | Pipelined semiconductor memories and systems |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/771,689 Continuation US20080010429A1 (en) | 2003-06-02 | 2007-06-29 | Pipelined semiconductor memories and systems |
Publications (2)
Publication Number | Publication Date |
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US20040243781A1 US20040243781A1 (en) | 2004-12-02 |
US7254690B2 true US7254690B2 (en) | 2007-08-07 |
Family
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/850,719 Active 2025-05-13 US7254690B2 (en) | 2003-06-02 | 2004-05-20 | Pipelined semiconductor memories and systems |
US11/771,689 Abandoned US20080010429A1 (en) | 2003-06-02 | 2007-06-29 | Pipelined semiconductor memories and systems |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US11/771,689 Abandoned US20080010429A1 (en) | 2003-06-02 | 2007-06-29 | Pipelined semiconductor memories and systems |
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