US7231009B2 - Data synchronization across an asynchronous boundary using, for example, multi-phase clocks - Google Patents
Data synchronization across an asynchronous boundary using, for example, multi-phase clocks Download PDFInfo
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- US7231009B2 US7231009B2 US10/371,220 US37122003A US7231009B2 US 7231009 B2 US7231009 B2 US 7231009B2 US 37122003 A US37122003 A US 37122003A US 7231009 B2 US7231009 B2 US 7231009B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Definitions
- Embodiments of the invention relate to systems and methods for transferring synchronous digital signals across an asynchronous boundary.
- Metastability generally refers to a circuit or system that has an unstable and transient, but relatively long-lived state. The problem of metastability is well known in the art, and can be illustrated, for example, by operation of a bistable latch.
- a bistable latch requires the coincident occurrence of two pulses, e.g., a data pulse and a clock pulse, to change the state of the latch.
- a bistable latch a “metastable” state can occur when the two actuating pulses do not overlap sufficiently in time to permit the bistable latch to completely switch from one stable state to the other.
- setup time violation or hold time violation can occur when a clock pulse is poorly synchronized with a data pulse
- the bistable latch output can move from one stable level to the other and then back again.
- the metastable latch problem occurs when a clock pulse from one domain overlaps insufficiently with a data pulse synchronized to a clock pulse from another domain.
- a clocked bistable latch can malfunction if the data input changes during the setup-time interval preceding a clock pulse. As long as the clocked bistable latch makes some decision upon receipt of the active edge of the clock pulse, the circuit incorporating the latch will operate properly. An incoming transition edge of a data signal should occur before a transition edge of a clock signal to the latch. However, if the input changes at a particularly bad time within the setup-time, the clocked bistable latch can hover at the logic threshold or the clocked bistable latch can go into one state and then switch back to the other state. Stated yet another way, a clocked bistable latch can malfunction if the data input changes during the hold-time interval following a clock pulse.
- One method of determining whether a problem in data synchronization across asynchronous boundaries will occur is to employ a higher frequency clock.
- the higher frequency clock may then determine the relationship between clocks in each of two asynchronous domains.
- a higher frequency clock requires circuitry to have less margin of error, thereby making associated circuitry more difficult to design.
- FIG. 1 is a circuit diagram of a retiming circuit according to one embodiment of the invention.
- FIG. 2 illustrates the waveforms of external and internal clocks and of incoming data used as inputs by the retiming circuit of FIG. 1 .
- FIG. 3 is a flow chart of one embodiment of a method according to the invention.
- FIG. 4 is a flow chart of another embodiment of a method according to the invention.
- FIG. 5 is a block diagram of a system for providing data synchronization under an embodiment of the invention.
- This invention relates to systems and methods for transferring synchronous digital signals, such as across an asynchronous boundary.
- Data transfer over a boundary separating an external clock domain and an internal clock domain can cause elements of the receiving circuit to enter a metastable state.
- One embodiment of the invention provides a method of data synchronization across an asynchronous boundary with two non-synchronous clocks of the same frequency, using a system having multi-phase clock signals.
- the method uses multi-phase clock signals to determine if the phase difference between an active edge of an external clock signal and the active edge of the 0 th phase of an internal sampling clock signal is less than a pre-selected value. If this phase difference is too small, the subsystem receiving data across the asynchronous boundary can experience metastability problems.
- the method samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal. For example, if the system determines that the rising edge of the external clock signal is near to that of a first internal clock signal, then the system effectively latches data based on a falling edge of the external clock signal (based on a second clock signal 180° out of phase with the first internal clock signal). By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the system provides a sufficient setup/hold margin to avoid a metastability or other problem in the subsystem receiving data across an asynchronous boundary.
- an embodiment according to the invention can avoid this metastability problem.
- This embodiment uses two phases of multi-phase clock signals to obtain information about the phase of an external clock, and thereby determine whether a first 0 th clock signal, or a 180° out of phase second phase clock signal is to be used.
- FIG. 1 Details regarding a specific circuit for implementing an aspect of the invention are first described with respect to FIG. 1 . Examples of signals employed by the circuit of FIG. 1 are then discussed. Thereafter, a block diagram illustrating a broad implementation of another aspect of the invention is described. Finally, two methods of performing data synchronization are discussed.
- FIG. 1 shows a schematic diagram for a synchronization or retiming circuit 10 for transferring synchronous digital data over an asynchronous boundary.
- FIG. 2 illustrates the waveforms of an external clock signal (“rckin”), of an incoming data signal (“rdi”) and of four internal clock signals each having a distinct phase (“p ⁇ 0 >” through “p ⁇ 3 >”).
- the retiming circuit of FIG. 1 receives all six signals illustrated in FIG. 2 as inputs.
- the illustrated scheme uses four internal clock signals each having a distinct phase, p ⁇ 0 >–p ⁇ 4 >, where the 1 st , 2 nd and 3 rd phase internal clock signals p ⁇ 1 >, p ⁇ 2 >, and p ⁇ 3 > are 90, 180 and 270 degrees, respectively, out of phase with the 0 th clock signal p ⁇ 0 >, but all clock signals have the same frequency.
- the retiming circuit 10 may be placed at a boundary between two asynchronous clocks, such as at the boundary between one subsystem operating under an external clock signal, and a second subsystem operating under an internal clock signal.
- the retiming circuit shown in FIG. 1 receives an external clock signal on a line “rckin.”
- the external clock signal rckin cannot be used to latch data out of the retiming circuit 10 because a metastability condition could arise if the rising edge of this clock signal coincides with data transition and with the 0 th phase of the internal clock.
- the line rckin couples to inputs of D flip-flops 12 and 13 .
- the D flip-flop 12 receives the 1 st phase of the internal clock signal p ⁇ 1 > and samples the external clock signal rckin at the rising edge of the 1 st clock signal p ⁇ 1 >.
- the D flip-flop 13 receives the 3 rd phase of the internal clock signal p ⁇ 3 > and samples the external clock signal rckin at the rising edge of the 3 rd clock signal p ⁇ 3 >.
- the output of the D flip-flop 12 passes through an inverter 14 before coupling to a first input of a two input NAND gate 15 , while the output of the D flip-flop 13 couples directly to the other input of the NAND gate.
- the D flip-flops 12 and 13 together with the first and third internal clock signals p ⁇ 1 > and p ⁇ 3 > sample the external clock signal, while the inverter 14 and NAND gate 15 determine where the rising edge of the external clock signal rckin occurs.
- the output of the NAND gate 15 couples to the control input of a multiplexer (MUX) 16 , which has two data inputs and one output.
- MUX multiplexer
- the retiming circuit 10 receives an incoming data signal on a line “rdi.”
- the line rdi couples to a first data input of the MUX 16 and to the input of a D flip-flop 17 .
- the D flip-flop 17 receives the 2 nd phase of the internal clock signal p ⁇ 2 > and samples the incoming data signal at the rising edge of the 2 nd clock signal p ⁇ 2 >.
- the output of the D flip-flop 17 couples to the second input of MUX 16 .
- the 0 th phase internal clock signal p ⁇ 0 > is assumed to be synchronized with the incoming data, but if a possible metastability condition or other problem could exist, a clock signal out of phase with p ⁇ 2 > is used instead.
- the D flip-flops 12 and 13 are triggered by the rising edges of the 1 st and 3 rd internal clock signals, p ⁇ 1 > and p ⁇ 3 >, respectively, of the multiple-phase clocks. Together with the inverter 14 and NAND gate 15 , the D flip-flops 12 and 13 effectively operate to detect the phase of the external clock signal rckin.
- the MUX 16 selects the output of the D flip-flop 17 using the 2 nd internal clock signal p ⁇ 2 > for latching data. Alternatively, if the output of the NAND gate 15 is low, the MUX 16 selects the first input coupled directly to the rdi line. Finally, a D flip-flop 18 , triggered by the 0 th internal clock signal p ⁇ 0 > samples the output of the MUX 16 .
- the rising edge of rckin and the rising edge of 0 th internal clock signal p ⁇ 0 > are close to each other.
- the phase difference between the active edges of rckin and p ⁇ 0 > are less than a pre-selected value, as shown as a time difference tdiff between time t 0 and time t 1 .
- the active edges of the external clock correlate with the transitions of the incoming data.
- the retiming circuit uses the 2 nd internal clock signal p ⁇ 2 > (approximately 180° out of phase with p ⁇ 0 >) for latching the incoming data. If the phase difference between the active edges of the external clock and p ⁇ 0 >, tdiff in FIG.
- the retiming circuit uses the 0 th internal clock signal p ⁇ 0 > for latching the incoming data rdi.
- This embodiment gives setup/hold margin proportional to clock period, which is neither process nor technology dependent, and also more tolerant to relative jitter between two non-synchronous clocks, because the absolute amount of relative jitter is likely to increase at lower clock frequency.
- retiming circuit As will be obvious to those of skill in the art, other embodiments of the retiming circuit are possible. For example, an alternative circuit could use or receive more than four phases of internal multi-phase clock signals, and have accompanying changes in circuitry. Also the NAND gate 15 could be replaced by more complicated logic to deal with the case where the phase difference between two non-synchronous clocks varies dynamically.
- the retiming circuit 10 of FIG. 1 is only one example of an implementation of a broader retiming system 200 shown in FIG. 5 .
- the retiming system 200 includes a clock signal comparator 202 that receives internal clock signals 1 through N, and compares them with an external clock signal.
- a clock signal sample component 203 may form an input to the clock signal comparator 202 to periodically sample the external clock signal based on one or more of the internal clock signals.
- the clock signal comparator may compare various features of the external clock signal with one or more internal clock signals, such as phase differences, timing between active/inactive clock edges, etc.
- At least two of the internal clock signals 1 -N are input to a clock signal selector 204 .
- the clock signal comparator 202 Based on a comparison between the external clock signal and one or more of the internal clock signals 1 -N, the clock signal comparator 202 generates an output signal on a line 205 , which is used to control the clock signal selector 204 and output or select one of the internal clock signals 1 -N as a selected clock signal on line 207 .
- a sample and hold component 206 receives the inputting data, and samples and holds it based on the selected clock signal to provide synchronized output data. Examples of specific implementations of the various blocks and components in the retiming system 200 are shown with corresponding broken line boxes in FIG. 1 (where the sample and hold component 206 may be implemented by the D flip-flops 17 and 18 ).
- aspects of the invention may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs).
- PLDs programmable logic devices
- FPGAs field programmable gate arrays
- PAL programmable array logic
- ASICs application specific integrated circuits
- microcontrollers with memory such as electronically erasable programmable read only memory (EEPROM)
- EEPROM electronically erasable programmable read only memory
- embedded microprocessors firmware, software, etc.
- the software may be carried by any computer readable medium, such as magnetically- or optically-readable disks (fixed or floppy), modulated on a carrier signal or otherwise transmitted, etc.
- aspects of the invention may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types.
- MOSFET metal-oxide semiconductor field-effect transistor
- CMOS complementary metal-oxide semiconductor
- ECL emitter-coupled logic
- polymer technologies e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures
- mixed analog and digital etc.
- one embodiment of a method 101 for transferring data across an asynchronous boundary includes sampling an external clock according to first and third phases of internal multi-phase clock signals under blocks 100 and 102 , respectively. The method then determines in block 104 if the active edge of the external clock occurs between the active edge of the first and third phases of the internal multi-phase clocks. If it does, then the method samples in block 110 an incoming data signal according to the 0 th phase of the multi-phase clock signals. If it does not, then the method first samples in block 106 the incoming data signal according to the second phase of the multi-phase clock signals. Thereafter, the method samples the previously sampled data signal according to the 0 th phase of the internal multi-phase clock signals in block 108 . The method continues then with each new input data pulse or other data signal.
- FIG. 4 another embodiment employs a method 121 for transferring synchronous digital signals across an asynchronous boundary separating an external clock domain and an internal clock domain includes determining in block 120 whether the phase difference between the active edges of an external clock and the 0 th phase of the internal multi-phase clock signals is below a pre-selected value.
- the method 121 includes sampling in block 110 an incoming data signal according to the 0 th phase of the internal multi-phase clock signal. If the phase difference is below the pre-selected value, then the incoming data signal is sampled in block 122 according to a delayed phase of the internal multi-phase clock signal. After sampling the incoming data signal according to the delayed phase, the method can include sampling in block 108 the incoming data signal according to the 0 th phase of the internal multi-phase clock signals.
- the multi-phase clock signals are typically synchronized.
- the clock signals need not be synchronized, but additional circuitry, such as buffering circuits, are provided to so compensate.
- additional circuitry such as buffering circuits, are provided to so compensate.
- the external clock signal may be substituted in certain environments. While the four phases of the multi-phase clock signals are described above as being 90° out of phase, different phase differences may be employed.
- an alternative embodiment could sample a clock of the destination domain and delay the data signal in the source domain before exporting it to the destination domain.
- the destination domain receives a data signal that has already been synchronized with the clock of the destination domain.
- Embodiments of the invention may be employed in not only systems, but subsystems and even chips. Complicated semiconductor chips having multiple subsystems operating under several different clocks may often be required to transmit data across such chip subsystems. Embodiments of the invention permit data to be transferred across such asynchronous subsystem boundaries without loss in data, thereby reducing bit error rates in the chip. Embodiments of the invention allow one system to receive a data stream synchronized to an external clock and recover and synchronize to the incoming data based on a new or “recovery” clock signal in a quick manner, without losing data in the data stream.
Abstract
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- that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. When the claims use the word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.
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US20080304599A1 (en) * | 2004-12-23 | 2008-12-11 | Nxp B.V. | Interface Circuit As Well As Method For Receiving And/Or For Decoding Data Signals |
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US20050254569A1 (en) * | 2004-05-14 | 2005-11-17 | Afshin Momtaz | System and method for generating equalization coefficients |
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