US7167481B2 - Technique for computing pathways in a multi-stage switch fabric through exploitation of symmetrical links - Google Patents
Technique for computing pathways in a multi-stage switch fabric through exploitation of symmetrical links Download PDFInfo
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- US7167481B2 US7167481B2 US10/119,765 US11976502A US7167481B2 US 7167481 B2 US7167481 B2 US 7167481B2 US 11976502 A US11976502 A US 11976502A US 7167481 B2 US7167481 B2 US 7167481B2
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- 239000004744 fabric Substances 0.000 title claims abstract description 114
- 230000037361 pathway Effects 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims description 38
- 230000008569 process Effects 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 239000000543 intermediate Substances 0.000 description 28
- 230000000903 blocking effect Effects 0.000 description 10
- 230000008707 rearrangement Effects 0.000 description 9
- 230000011664 signaling Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
- H04L49/254—Centralised controller, i.e. arbitration or scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/256—Routing or path finding in ATM switching fabrics
Definitions
- the invention relates to devices and methods for switching data traffic, and more particularly to devices and methods to establish internal pathways in a switch fabric needed to realize a plurality of links between external ports.
- a switch fabric provides pathways for conveying data traffic between external input and output ports.
- a switch fabric may include an input and an output stage, each stage including a plurality of switching elements. The input and output stages respectively provide a plurality of external input and output ports connected to external connections.
- the switch fabric also includes one or more intermediate stages including a plurality of switching elements. Internal pathways are selectively established in the switch fabric between the external input ports and the external output ports to provide the switching capability. When the number of external input and output ports is large, it is usually not cost-effective, or technically feasible, to directly connect each external input port to all the external output ports.
- switch fabric may become blocked.
- the switch fabric is said to be blocked when no pathway between an external input port and an external output port can be established. Therefore, data traffic between these external ports cannot be passed.
- the invention provides a switch fabric for switching data traffic according to a plurality of links.
- the data traffic may convey audio information, video information, or any other type of information.
- the switch fabric includes input, output and at least one intermediate stages, each stage including a plurality of switching elements.
- the switching elements of the input and output stages respectively have external input and output ports.
- the switch fabric further includes a switch fabric controller.
- the switch fabric controller includes a link database including information about the plurality of links.
- the switch fabric controller is operative to search the link database to identify symmetrical links and to establish internal pathways between the input stage and the output stage through the at least one intermediate stage, wherein at least two symmetrical links identified by the searching are realized using a common switching element of the at least one intermediate stage.
- the invention provides a more efficient utilization of the switch fabric. Consequently, a smaller, less complicated, and less expensive switch fabric can be employed.
- Two links are symmetrical at the first level if:
- An internal pathway realizing a unicast link provides connectivity between a single external input port and a single external output port.
- An internal pathway realizing a multicast link provides connectivity between any other number of ports of the input and output stages.
- the link from the external input port # 1 to the external output ports # 2 and # 3 is symmetrical at the first level with the link from external input ports # 2 and # 3 to the external output port # 1 .
- two links can be symmetrical at the first level even when they use different ones or different combinations of the intermediate stage switching elements.
- Two links are symmetrical at the second level if in addition to being symmetrical at the first level they share a common switching element at the input stage. Also, two links are symmetrical at the third level if in addition to being symmetrical at the second level, they share a common switching element at the output stage.
- symmetrical link or equivalent used in this specification without the qualifier “first level”, “second level” or “third level” implies symmetry at least at the first level without excluding symmetry at the second level or at the third level.
- Bi-directional links between network elements are a specific example of the notion of symmetrical links.
- a first network element (network element 1 ) sending data over a first link to three other network elements (network elements 2 , 3 and 4 ).
- the network elements 2 , 3 and 4 send data to network element 1 over a second link. Therefore, the first and the second would be symmetrical.
- the switch fabric controller considers links to be realized before passing any traffic. Typically, this situation occurs when the switch fabric is switched from an inactive state to an active state. Symmetrical links are searched for in the link database and instructions are sent to the switching elements such that symmetrical link pairs are realized by using a common switching element(s) of the intermediate stage(s) between the input and the output stages. The number of symmetrical link pairs that can be bundled into one common intermediate stage switching element is practically limited by the bandwidth capacity of the switching elements and the number of available connections between the switching elements.
- the switch fabric controller computes a revised internal pathway map while the switch fabric is in operation and re-arranges the connections between switching elements to implement the revised internal pathway map. This situation occurs when a new link is to be realized while the switch fabric is in operation.
- the computation of the revised internal pathway map involves searching at least one existing link (for which an internal pathway has already been set) that is symmetrical to the new link. If one or more such prior symmetrical links are found, the data traffic associated with the new link is passed through an intermediate stage switching element that is used by one of the prior symmetrical link(s). If no symmetrical links are found, then a new internal pathway is created using an available intermediate stage switching element.
- the invention provides a switch fabric controller for use with a switch fabric.
- the invention provides a computer readable storage medium including a program element for execution by a CPU to compute an internal pathway map for a switch fabric.
- the invention provides a method for switching data traffic.
- FIG. 1 is a block diagram of a Clos switch fabric
- FIG. 2 is a flow chart of an internal pathway map creation algorithm.
- FIG. 1 shows a multi-stage switch fabric 100 .
- the switch fabric 199 comprises a three-stage Clos network 100 and a switch fabric controller 105 .
- the Clos network 100 comprises an input stage 110 , an output stage 120 and an intermediate stage 130 .
- Data traffic enters and exits the switch fabric 199 respectively at the input and output stages 110 and 120 .
- the intermediate stage 130 is used to convey data traffic internally between the input and the output stages 110 and 120 .
- a switch fabric 199 comprising a Clos network 100 is illustrated on FIG. 1 to give a concrete example of implementation.
- the present invention is applicable to other types of multi-stage switch fabrics, in particular to switch fabrics comprising more than one intermediate stage.
- Each of the input, output and intermediate stages 110 , 120 and 130 comprises a plurality of switching elements 140 a,b referred to generally by the reference numeral 140 .
- the input stage 110 comprises the switching elements 140 1,b
- the output stage 120 comprises the switching elements 140 2,b
- the intermediate stage 130 comprises the switching elements 140 3,b .
- the input and output stages 110 and 120 each comprise r switching elements 140 a,b while the intermediate stage 130 comprises m switching elements 140 3,b .
- all the stages 110 , 120 and 130 have an identical number of switching elements 140 . This is not an essential requirement and the number of switching elements 140 can vary from one stage ( 110 , 120 or 130 ) to another without departing from the spirit of the invention.
- Each switching element 140 a,b comprises a plurality of input and output ports, each port being either an internal or an external port.
- External input and output ports are respectively used to convey data traffic from and to a plurality of external input and output connections 150 b,c and 152 b,c and are only present at the input and output stages 110 and 120 .
- the external input and output connections are globally referred to respectively by the reference numerals 150 and 152 .
- Internal input and output ports are used to convey data traffic from and to connection matrices 160 and 162 .
- the connection matrices 160 and 162 respectively connect the intermediate stage 130 to the input stage 110 and the output stage 120 by conveying data traffic between internal input and output ports of switching elements of the input output and intermediate stages 110 , 120 and 130 through permanent or temporary internal connections.
- data traffic flows through the switch in only one direction, namely from the right to the left of the switch fabric 199 .
- data traffic always passes through the Clos network 100 in the following sequence; data enters through the input stage 110 , passes through the intermediate stage 130 and leaves the switch fabric through the output stage 120 .
- the external input connections 150 and the external output connections 152 connect the input stage 110 and the output stage 120 to external network elements that send data traffic to the switch fabric 199 or receive data traffic from the switch fabric 199 .
- N can be different or equal to m.
- each switching element 140 direct data traffic between the internal and external input and output ports.
- each switching element is an Application Specific Integrated Circuit (ASIC).
- ASIC Application Specific Integrated Circuit
- connection matrices 160 and 162 are known in the art and their structure and operation will not be described in more detail.
- the basic function of the switch fabric controller 105 is to compute an internal pathway map that represents all the internal pathways in the switch fabric 199 .
- Another function of the switch fabric controller 105 is to send control signals to the switching elements 140 and connection matrices 160 and 162 , the control signals comprising instructions for establishing the internal pathways according to the pathway map.
- the switch fabric controller 105 includes a Central Processing Unit (CPU) 190 connected to a storage medium 192 over a data bus 194 .
- the storage medium 192 is shown as a single block, it may include a plurality of separate components, such as a fixed disk and a Random Access Memory (RAM), among others.
- the data bus 194 is connected to a signaling link 170 that communicates with the network elements connected to the external connections 150 and 152 .
- the data bus 194 is connected to the Clos network 100 through a control path 180 .
- the control path 180 conveys control signals between the data bus 194 and the switching elements 140 and connection matrices 160 and 162 .
- a link is defined by the external input ports of the switching elements 140 of the input stage 110 and the external output ports of the switching elements 140 of the output stage 120 through which data traffic is exchanged.
- a link could be realized between the external input port connected to the external input connection 150 1,1 and the external output ports connected to the external output connections 152 2,3 and 152 4,2 .
- a link is defined solely by the point(s) of entry of data in the switch fabric 199 and the point(s) of release of data from the switch fabric 199 .
- An internal connection is a permanent or temporary data channel between two of the switching elements 140 .
- An internal pathway realizes a link by setting internal connections between switching elements 140 of the input, output and intermediates stages 110 , 120 and 130 .
- Many different internal pathways may realize a given link. For example, to realize the particular link given in the example above, all the data traffic may go through the switching element 140 3,1 of the intermediate stage 130 .
- the data traffic between the external input and output ports connected to the external input and output connections 150 1,1 and 152 2,3 may go through the switching element 140 3,1 and the data traffic between the external input and output ports connected to the external input and output connections 150 1,1 and 152 4,2 may go through the switching element 140 3,4 .
- the switch fabric controller 105 is adapted to receive information signals through the signaling link 170 from the network elements with which the switch fabric 199 exchanges data traffic, the information signals providing information concerning links to be realized by the switch fabric 199 .
- a link database which resides in the storage medium 192 , stores the information concerning the links to be realized.
- FIG. 2 is a flowchart of an example of implementation of a process for computing an internal pathway map implemented by the switch fabric controller 105 .
- This process is implemented by software residing in the storage medium 192 and executed by the CPU 190 .
- the software is a program element comprising a searching module for searching the link database to identify pairs of symmetrical links (symmetrical links at the first level, the second level and the third level, as the case may be) and a processing module for computing internal pathways between the input stage and the output stage.
- the process illustrated on FIG. 2 may be run every time when a new internal pathway needs to be added to an already existing internal pathway map. This happens when the switch fabric 199 is in operation and a new link needs to be realized. It will be plain to the reader skilled in the art that the process can also be used, with some minor modifications, to compute a new internal pathway map, which may be the case if the switch fabric 199 is reset.
- the process begins at step 205 .
- the switch fabric controller 105 examines if it is possible to allocate an internal pathway to realize a new link by using free internal connections. If there is no blocking, an internal pathway allocation is made at step 212 , thereby producing a modified internal pathway map, which is stored in the storage medium 192 at step 297 . Then, at step 298 , the CPU 190 sends control signals to the switching elements 140 and connection matrices 160 and 162 such that the switch fabric implements the internal pathway map including the internal pathway for the new link.
- step 215 the switch fabric controller 105 examines if the link to realize is a unicast link or not. If it is a unicast link, a rearrangement algorithm is used at step 217 to resolve the blocking.
- a rearrangement algorithm is described in Ohta et al., “A Rearrangement Algorithm for Three-Stage Switching”, Electronics and communications in Japan, Part 1, Vol. 70, No. 9, 1987. The contents of this document are incorporated herein by reference. Other rearrangement algorithms can also be used without departing from the spirit of the invention.
- the step 217 yields a revised internal pathway map, which includes an internal pathway for the new link.
- the revised internal pathway map is stored at step 297 in the storage medium 192 .
- the CPU 190 sends control signals to the switching elements 140 and connection matrices 160 and 162 for implementing the revised pathway map.
- step 220 the method continues to step 220 , wherein all the links in the link database are examined and a weight is assigned to each link.
- Methods of assigning weights to links are well known in the art. In a non-limiting example of implementation weights are assigned according to the complexity of the link, the complexity being determined by the number of external input and output ports involved in realizing the link. The higher the complexity, the higher the weight.
- the links are sorted by the program element according to the weight assigned to them.
- the links are sorted in decreasing order of weight (complexity).
- the searching module of the program element searches the sorted links to identify pairs of symmetrical links, in particular pairs of multicast links that are symmetrical at the third level..
- internal pathways are assigned to the pairs of third level symmetrical links by the processing module of the program element, such that the internal pathways for both links in the pair are routed through a common switching element 140 of the intermediate stage 130 . In the case of multiple intermediate stages, the internal pathways for both links in the pair are routed through the same switching element in each intermediate stage.
- the unicast links are allocated using the remaining free connections at step 240 . If there is blocking in the allocation of unicast links, a rearrangement algorithm, which may be the rearrangement algorithm referred to above, can be used.
- control signals are sent over the control path 180 to configure the switching elements 140 and the connection matrices 160 and 162 in order to set internal connections according to the internal pathway map, thereby realizing the links.
- step 299 The process terminates at step 299 .
- signaling information can be sent through the signaling link 170 to the network elements to notify those network elements that the switch fabric 199 is ready to pass data traffic.
- the method described in FIG. 2 has partitioned the switch fabric ( 100 ) into two parts: one part that has non-rearrangeable multicast links as realized at step 235 , and the second part having rearrangeable unicast links.
- the switch fabric 100 is non-blocking because the rearrangeable part retains the non-blocking characteristics.
- the invention provides a method allowing realizing a class of multicast internal pathways as rearrangeable links.
- This class includes bi-directional links whereby there are protection constraints among the external input ports ( 150 ) and external output ports ( 152 ).
- the allocation of internal pathways that are constrained to pass through a common switching element 140 is particularly advantageous in the context of protection switching, wherein protection pathways have to be set within a small delay subsequent to a failure of a working link, such that the data traffic on a working link is redirected over a protection link.
- the switch controller 105 is adapted to receive signals from network elements comprising instructions regarding the protection switching to effect. In general, this method allows the protection switching activity to be achieved quickly without having to perform link rearrangements throughout the switch fabric 100 .
- the links to be established are separated in first and second groups of links.
- the separation in groups is effected in the following fashion.
- Each link in the link database is considered separately.
- the first link is placed arbitrarily in one of the two groups, say group # 1 .
- the switch fabric controller 105 searches the remaining links in the links database for a link that is symmetrical to the first link. In this example symmetry at the third level is considered. If such third level symmetrical link is found, then the third level symmetrical link is automatically placed in the other group, say group # 2 .
- the process continues until all the links have been assigned to group # 1 or to group # 2 .
- two groups of links are produced, where links that are symmetrical at the third level to one another are placed in different groups.
- half of the interconnectivity 160 between each input 110 and intermediate stage 130 switching element is allocated for group # 1 links. The same is done for the interconnectivity between the intermediate stage 130 and the output stage 120 switching elements. The remaining interconnectivity is allocated for group # 2 links. Essentially, this leaves half of the possible internal pathways allocated for the group # 1 links and the other half for the group # 2 links.
- 150 1,1 and 150 1,2 are protecting and working inputs respectively, and 152 1,1 and 152 1,2 are the corresponding outputs wherein 150 1,1 protects 150 1,2 and 152 1,1 protects 152 1,2 .
- 150 r,1 and 150 r,2 are low and high priority inputs, and 152 r,1 and 152 r,2 are the corresponding outputs.
- switch fabric controller 105 requests the following connections:
- the link 150 r,1 to 152 1,1 is realized using the pathway from 140 1,r via the first interconnect to 140 3,2 , and from 140 3,2 via the first interconnect to 140 2,1 . Then, the link 150 1,1 to 152 r,1 is automatically realized by using the interconnects allocated to group # 2 . That is, the pathway from 140 1,1 via the second interconnect to 140 3,2 is used, and the pathway from 140 3,2 via the second interconnect to 140 2,r is used. Note the group # 2 pathway was obtained from the group # 1 pathway by using symmetrical links.
- the switch fabric controller 105 makes a change at switching element 140 1,1 to alter the internal connections such that the working link selects the traffic from the protection input port 150 1,1 . Similar protection switch behaviour would occur if the external output port 152 1,1 were to fail, whereby only one switching element is affected. If there was either an upstream or a downstream failure whereby the network element was required to passthrough protected traffic from 150 1,1 to 152 1,1 this is achieved by the switch fabric controller 105 making a change at switching element 140 3,2 to alter the internal connections such that the traffic from 150 1,1 is redirected toward external output port 152 1,1 .
- the lower priority traffic is negated.
- the low priority traffic at external output port 152 r,1 and the low priority traffic at external input port 150 1,1 is negated.
- this method provides, assume that two links are realized through the switch fabric 100 .
- the first link is a working link, in other words it is the link that carries data traffic during normal operation of the switch fabric 100 .
- This link enters the switch fabric 100 at the external input connection 150 1,1 and leaves at the external output connection 152 r,n , passing through the switching element 140 3,2 .
- the working link is protected by a protection link that enters at the external input connection 150 r,n , leaves at the external output connection 152 1,1 and passes through the switching element 140 3,2 .
- low priority data traffic is passed over at least a portion of the protection link.
- This low priority data traffic enters at the external input connection 150 r,2 , leaves at the external output connection 152 1,1 and passes through the switching element 140 3,2 . If the working link fails, say because of a failure downstream the external output connection 152 r,n , a protection switching procedure is implemented by the switch fabric controller 105 such that the data traffic is now redirected toward the external output connection 152 1,1 . This is effected simply by making a change at the switching element 140 3,2 to alter the internal connections between the switching element 140 3,2 and the output stage 120 . This operation can be done very rapidly since only a single switching event at the switching element 140 3,2 is necessary and no link rearrangement is required. As a result data traffic entering at the external input connection 150 1,1 will now leave at the external output connection 152 1,1 and still pass internally through the switching element 140 3,2 .
- the lower priority data traffic is dropped and the link entering at the external input connection 150 r,2 , leaving at the external output connection 152 1,1 and passing through the switching element 140 3,2 is negated.
- symmetrical links are constrained to pass through a common switching element 140 of the intermediate stage 130 . Accordingly, there is an advantage to use one of the links in a symmetrical pair of links to provide protection switching for the other link that constitutes the working link.
- This approach makes the designation of protection links and pathways simple once the symmetrical links in the links database have been identified.
- the invention is not limited to this feature and protection pathways can be assigned or created without any regard to symmetry between links.
Abstract
Description
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- I. the number of external input ports of the first link is equal to the number of external output ports of the second link; and
- II. the number of external output ports of the first link is equal to the number of external input ports of the second link.
-
- low priority
bi-directional links 150 r,1 to 152 1,1 and - high priority
bi-directional links 150 1,2 to 152 r,2.
- low priority
Claims (21)
Priority Applications (2)
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EP20020258927 EP1326384B1 (en) | 2001-12-20 | 2002-12-20 | Technique for computing pathways in a multi-stage switch fabric through exploitation of symmetrical links |
DE2002611111 DE60211111T2 (en) | 2001-12-20 | 2002-12-20 | Method for calculating the paths in a multilevel exchange by utilizing the symmetrical connections |
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CA002365963A CA2365963A1 (en) | 2001-12-20 | 2001-12-20 | Technique for computing pathways in a multi-stage switch fabric through exploitation of symmetrical links |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20040088469A1 (en) * | 2002-10-30 | 2004-05-06 | Levy Paul S. | Links having flexible lane allocation |
US20120170575A1 (en) * | 2010-12-29 | 2012-07-05 | Juniper Networks, Inc. | Methods and apparatus for validation of equal cost multi path (ecmp) paths in a switch fabric system |
US8798077B2 (en) | 2010-12-29 | 2014-08-05 | Juniper Networks, Inc. | Methods and apparatus for standard protocol validation mechanisms deployed over a switch fabric system |
US20140307579A1 (en) * | 2013-04-12 | 2014-10-16 | International Business Machines Corporation | Software implementation of network switch/router |
US20200076744A1 (en) * | 2011-09-07 | 2020-03-05 | Konda Technologies Inc. | Fast scheduling and optmization of multi-stage hierarchical networks |
US11405332B1 (en) * | 2011-09-07 | 2022-08-02 | Konda Technologies Inc. | Fast scheduling and optimization of multi-stage hierarchical networks |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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US7027404B2 (en) * | 2001-08-20 | 2006-04-11 | Samsung Electronics Co., Ltd. | Mechanism for cell routing in a multi-stage fabric with input queuing |
US7383330B2 (en) * | 2002-05-24 | 2008-06-03 | Emc Corporation | Method for mapping a network fabric |
JP2007532037A (en) * | 2003-09-06 | 2007-11-08 | チーク テクノロジーズ,インク. | Strictly non-blocking multicast linear time multistage network |
US20060159078A1 (en) * | 2003-09-06 | 2006-07-20 | Teak Technologies, Inc. | Strictly nonblocking multicast linear-time multi-stage networks |
CN100452886C (en) * | 2003-09-27 | 2009-01-14 | 华为技术有限公司 | Method and device of realizing synchronous switchover of CLDS crosslink matrix |
US20050111433A1 (en) * | 2003-11-25 | 2005-05-26 | Stewart Mark A.W. | Method of operating a Clos network |
US8175021B2 (en) * | 2005-11-04 | 2012-05-08 | Texas Instruments Incorporated | Method for transmission of unicast control in broadcast/multicast transmission time intervals |
US8265070B2 (en) * | 2008-12-15 | 2012-09-11 | Oracle America, Inc. | System and method for implementing a multistage network using a two-dimensional array of tiles |
US20110041002A1 (en) * | 2009-08-12 | 2011-02-17 | Patricio Saavedra | System, method, computer program for multidirectional pathway selection |
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US9973265B2 (en) * | 2014-04-30 | 2018-05-15 | The Boeing Company | Hitless rearrangement of a satellite-hosted switch via propagated synchronization |
US9980021B2 (en) | 2015-10-07 | 2018-05-22 | Ciena Corporation | Scalable switch fabric using optical interconnects |
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FR3071120B1 (en) * | 2017-09-11 | 2019-09-13 | Thales | COMMUNICATION NETWORK, MEASUREMENT SYSTEM, TRANSPORT MEANS AND METHOD FOR CONSTRUCTING AN ASSOCIATED COMMUNICATION NETWORK |
US11658888B2 (en) | 2021-05-19 | 2023-05-23 | Ciena Corporation | Network timing trail visualization and method of troubleshooting |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247513A (en) | 1990-05-22 | 1993-09-21 | Alcatel N.V. | Multiple path self-routing switching network for switching asynchronous time-division multiplex packets with availability signalling |
US5550815A (en) * | 1994-12-30 | 1996-08-27 | Lucent Technologies Inc. | Apparatus and method for reducing data losses in a growable packet switch |
US5754120A (en) | 1995-12-21 | 1998-05-19 | Lucent Technologies | Network congestion measurement method and apparatus |
US5781546A (en) | 1996-06-25 | 1998-07-14 | International Business Machines Corporation | Route restrictions for deadlock free routing with increased bandwidth in a multi-stage cross point packet switch |
WO2000077986A1 (en) | 1999-06-15 | 2000-12-21 | Ironbridge Networks, Inc. | Apparatus and method for scaling a switching fabric in a network switching node |
US6661788B2 (en) * | 1999-05-14 | 2003-12-09 | Nortel Networks Limited | Multicast scheduling for a network device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6504786B1 (en) * | 2000-11-07 | 2003-01-07 | Gautam Nag Kavipurapu | High speed, scalable, dynamic integrated programmable switch (DIPS) device |
US6885669B2 (en) * | 2001-09-27 | 2005-04-26 | Teak Networks, Inc. | Rearrangeably nonblocking multicast multi-stage networks |
US6868084B2 (en) * | 2001-09-27 | 2005-03-15 | Teak Networks, Inc | Strictly nonblocking multicast multi-stage networks |
-
2001
- 2001-12-20 CA CA002365963A patent/CA2365963A1/en not_active Abandoned
-
2002
- 2002-04-11 US US10/119,765 patent/US7167481B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247513A (en) | 1990-05-22 | 1993-09-21 | Alcatel N.V. | Multiple path self-routing switching network for switching asynchronous time-division multiplex packets with availability signalling |
US5550815A (en) * | 1994-12-30 | 1996-08-27 | Lucent Technologies Inc. | Apparatus and method for reducing data losses in a growable packet switch |
US5754120A (en) | 1995-12-21 | 1998-05-19 | Lucent Technologies | Network congestion measurement method and apparatus |
US5781546A (en) | 1996-06-25 | 1998-07-14 | International Business Machines Corporation | Route restrictions for deadlock free routing with increased bandwidth in a multi-stage cross point packet switch |
US6661788B2 (en) * | 1999-05-14 | 2003-12-09 | Nortel Networks Limited | Multicast scheduling for a network device |
WO2000077986A1 (en) | 1999-06-15 | 2000-12-21 | Ironbridge Networks, Inc. | Apparatus and method for scaling a switching fabric in a network switching node |
Non-Patent Citations (2)
Title |
---|
A Rearrangement Algorithm for Three-Stage Switching Networks, Satoru Ohta and Hiromi Ueda, NIT Electrical Communications Laboratories, Yokosuka, Japan 238, Electronics and Communications in Japan, Part 1, vol. 70. No. 9, 1987 Translated from Denshi Tsushin Oakkai Ronbunsh. vol. 69-B. No 2, Feb. 1986. pp. 139-140. |
European Search Report EP 02 25 8927, Sep. 19, 2003. |
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