US7161122B2 - Assembly packaging using induction heating - Google Patents

Assembly packaging using induction heating Download PDF

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Publication number
US7161122B2
US7161122B2 US10/876,512 US87651204A US7161122B2 US 7161122 B2 US7161122 B2 US 7161122B2 US 87651204 A US87651204 A US 87651204A US 7161122 B2 US7161122 B2 US 7161122B2
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Prior art keywords
die
ihs
package substrate
tim
bumps
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US20050284863A1 (en
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Thomas Joseph DeBonis
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Intel Corp
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Intel Corp
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Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DEBONIS, THOMAS JOSEPH
Publication of US20050284863A1 publication Critical patent/US20050284863A1/en
Priority to US11/599,529 priority patent/US7880124B2/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B6/00—Heating by electric, magnetic or electromagnetic fields
    • H05B6/02—Induction heating
    • H05B6/10—Induction heating apparatus, other than furnaces, for specific applications
    • H05B6/105—Induction heating apparatus, other than furnaces, for specific applications using a susceptor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75264—Means for applying energy, e.g. heating means by induction heating, i.e. coils
    • H01L2224/75266—Means for applying energy, e.g. heating means by induction heating, i.e. coils in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81222—Induction heating, i.e. eddy currents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Definitions

  • Embodiments of the invention relate to the field of semiconductors, and more specifically, to device packaging.
  • IHS integrated heat spreader
  • FIG. 1 is a diagram illustrating a packaging system in which one embodiment of the invention can be practiced.
  • FIG. 2A is a diagram illustrating baking a package substrate according to one embodiment of the invention.
  • FIG. 2B is a diagram illustrating placing die on the package substrate according to one embodiment of the invention.
  • FIG. 2C is a diagram illustrating localizing heat on the die according to one embodiment of the invention.
  • FIG. 2D is a diagram illustrating dispensing thermal interface material and sealant according to one embodiment of the invention.
  • FIG. 2E is a diagram illustrating placing an integrated heat spreader (IHS) on the die according to one embodiment of the invention.
  • IHS integrated heat spreader
  • FIG. 2F is a diagram illustrating localizing heat on the IHS according to one embodiment of the invention.
  • FIG. 2G is a diagram illustrating curing the thermal interface material and sealant according to one embodiment of the invention.
  • FIG. 3 is a flowchart illustrating a process to package a device using induction heating according to one embodiment of the invention.
  • FIG. 4 is a flowchart illustrating a process to localize heating on the die according to one embodiment of the invention.
  • FIG. 5 is a flowchart illustrating a process to localize heating on the IHS according to one embodiment of the invention.
  • An embodiment of the present invention is a technique to package a device.
  • Heat is localized on a die having bumps on a package substrate using a first induction heater operating at a first frequency.
  • Heat is localized on at least an integrated heat spreader (IHS), a thermal interface material (TIM), an underfill, and a sealant on the die using a second induction heater operating at a second frequency.
  • IHS integrated heat spreader
  • TIM thermal interface material
  • underfill an underfill
  • sealant on the die using a second induction heater operating at a second frequency.
  • One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, a method of manufacturing or fabrication, etc.
  • One embodiment of the invention addresses the problems caused by the differences or mismatches between the coefficients of thermal expansion (CTEs) of the silicon die and the package substrate. These problems include stress, poor co-planarity, and warping of the component. Additionally, one embodiment of the invention reduces the time-temperature exposure of the die and the package; thereby reducing undesired reactions, particularly with the Controlled Collapse Chip Connection (C4) joints. Reducing these undesired reactions leads to increased reliability of the C4 joints and other interfaces in the die and package.
  • CTEs coefficients of thermal expansion
  • the advantages of one embodiment of the invention include at least: (1) improved process control and reduction of tooling costs because the entire assembly process can be performed on individual packages with single-unit handling capability, (2) improved throughput time (TPT), (3) significant reduction of CTE mismatches between die and package substrate, (4) reduction of tool footprint thanks to small induction heating coils, (5) efficient heating due to induction heating leading to reduction of total thermal budget that the device and package is exposed to.
  • TPT throughput time
  • FIG. 1 is a diagram illustrating a packaging system 100 in which one embodiment of the invention can be practiced.
  • the packaging system 100 represents an assembly flow or process to package semiconductor devices. It includes an oven 110 , a package tool assembly 120 , and a burn-in or cure oven 180 . As is known by one skilled in the art, the packaging system may include more or less than these components.
  • the oven 110 bakes a package substrate 115 to prepare it for the assembly process.
  • the package substrate 115 may be moisture absorbent and therefore may be dried to eliminate the absorbed moisture.
  • the baking temperature and time depend on the type of material and the condition of the substrate. In one embodiment, the bake time is 24 hours and the baking temperature is 125° C.
  • the package tool assembly 120 includes a number of tools to place various components onto the package substrate 115 . These tools include various dispensers or pumps to dispense or deposit flux, epoxy, or sealant, pick and place tool, etc.
  • the package tool assembly 120 includes a dispenser 122 , a TIM dispenser 125 A, a sealant dispenser 125 B, an epoxy underfill dispenser 125 C, a die induction heater 124 , a lever arm assembly 126 , and an IHS induction heater 128 .
  • These tools are used to place and process components such as a die 140 , an integrated heat spreader (IHS) 150 , a flux 160 , a sealant 170 , and an epoxy underfill 175 .
  • IHS integrated heat spreader
  • the oven 180 is used mainly to cure the glue or polymer-type TIM, sealant, epoxy underfill and other interface materials in the package. It may also be used to burn in the packaged device for early failures.
  • the entire assembly process can be performed using the packaging system 100 through several phases or stages.
  • the package tool assembly 120 may be used in one single unit station or several stations. These phases or stages are illustrated in FIGS. 2A through 2G .
  • FIG. 2A is a diagram illustrating baking a package substrate according to one embodiment of the invention.
  • the package substrate 115 is any suitable substrate for packaging. It may be a ceramic substrate or an organic substrate.
  • the package substrate 115 has interconnecting elements to attach the device to a printed circuit board (PCB). Any suitable device packaging technique may be used including Ball Grid Array (BGA), Pin Grid Array (PGA), flip chip technology, etc.
  • BGA Ball Grid Array
  • PGA Pin Grid Array
  • flip chip technology etc.
  • the package substrate 115 is placed in the oven 110 ( FIG. 1 ) at an elevated temperature (e.g., 125° C.) over an extended period of time (e.g., 24 hours) to remove any moisture.
  • FIG. 2B is a diagram illustrating placing die on the package substrate according to one embodiment of the invention.
  • the die 140 ( FIG. 1 ) has a number of bumps 145 deposited on the lower surface.
  • the bumps 145 are Controlled Collapse Chip Connection (C4) bumps.
  • the dispenser 122 may be used to dispense flux onto the bump locations.
  • a place and alignment tool 210 is used to pick the die 140 , position it above the package substrate 115 , align it at a proper location, and place it on the package substrate 115 . Typically, the location is at the center of the package substrate 115 .
  • FIG. 2C is a diagram illustrating localizing heat on the die according to one embodiment of the invention.
  • the die induction heater 124 is placed above and near the upper surface of the die 140 .
  • the die induction heater 124 is a device that provides fast and efficient heating using induction. It typically includes an alternating current (AC) power supply and an induction coil. When it is energized by the AC power supply, the alternating current is sent through the induction coil, generating a magnetic field. When it is placed above the die 140 and the bumps 145 , the magnetic field induces eddy currents in the die 140 and the bumps 145 and generates a localized heat.
  • AC alternating current
  • the heat penetration into the die 140 and the bumps 145 provided by the die induction heater 124 is a function of the operating frequency.
  • an operating frequency between 1 KHz to 10 KHz may be sufficient to achieve satisfactory penetration depth. It is contemplated that the operating frequency may be higher for smaller sizes, and may be between 100 KHz to 400 KHz.
  • the heating time may be within a few seconds to less than a minute. This time exposure is much faster than traditional heating techniques and therefore provides very efficient and cost effective assembly process.
  • the size of the induction coil typically is approximately the same as the size of the die 140 ; therefore the assembly tool requires small footprint or space, leading to reduced costs. More importantly, the heating is carried out locally within the die 140 and the bumps 145 .
  • the package substrate 115 remains essentially thermally isolated from the die 140 and the bumps 145 . It remains cool throughout the local induction heating of the die 140 and the bumps 145 . Stress and other problems caused by CTE mismatch may be reduced or eliminated resulting in high reliability of the C4 solder joints. After induction heating, the C4 solder joints are formed and the die 140 is attached to the package substrate 115 .
  • FIG. 2D is a diagram illustrating dispensing thermal interface material and sealant according to one embodiment of the invention.
  • the TIM dispenser 125 A dispenses the flux 160 ( FIG. 1 ) as the thermal interface material on the upper surface of the die 140 .
  • the TIM 160 may be any suitable material such as grease or grease-like material filled with conductive particles, adhesive, phase change material, gel, or solders. When a solder-type TIM is used, it reflows during the IHS local heating as explained in FIG. 2F .
  • the sealant dispenser 125 B dispenses the sealant 170 on the package substrate 115 , typically at its edge or periphery.
  • the underfill dispenser 125 C dispenses the epoxy underfill 175 .
  • FIG. 2E is a diagram illustrating placing an integrated heat spreader (IHS) on the die according to one embodiment of the invention.
  • the IHS 150 may be made by a thermally conductive material such as aluminum, plated copper, copper alloy, ceramic, or carbon composites.
  • the IHS 150 is positioned to align with the package substrate 115 and placed on the package substrate at the periphery and the TIM 160 on the die 140 .
  • the lever arm assembly 126 applies a force on the IHS 150 to maintain a desired bond line thickness (BLT) between the lower IHS surface and the die upper surface.
  • BLT bond line thickness
  • FIG. 2F is a diagram illustrating localizing heat on the IHS according to one embodiment of the invention.
  • the IHS induction heater 128 ( FIG. 1 ) is placed above the IHS 150 to localize the heat on the IHS, the TIM 160 and the sealant 170 .
  • the IHS induction heater 128 operates in the same manner as the die induction heater 124 . It may be the same as the die induction heater 124 . In other words, the same induction heater can be used as the die induction heater 124 and the IHS induction heater 128 with same or different operating frequencies. It may be a different induction heater than the die induction heater 124 , having different induction coil, and operating at a different frequency.
  • the heating time is a function of the type of induction heater used and the operating frequency. Typically, the heating time is approximately equal to one minute and the operating frequency ranges from 1 KHz to 10 KHz.
  • the local heating may also cure the TIM 160 if a solder-type TIM is used because it does not require a long cure time. The solder-type TIM may be melted and alloyed during this second induction heating.
  • FIG. 2G is a diagram illustrating curing the thermal interface material and sealant according to one embodiment of the invention.
  • the packaged device including the IHS 150 sealed to the substrate 115 and encasing the die 140 is placed in the burn-in oven 180 ( FIG. 1 ) to cure the TIM 160 (other than solder-type TIM) and the sealant 170 .
  • the TIM 160 is a solder-type TIM
  • the oven curing is not needed.
  • the die 140 and the package substrate 115 are held relative rigid because the IHS 150 and burn-in socket are in place. This reduces the package warping and improves co-planarity and pin true position. In addition, this permits the epoxy to cure at approximately the device operating temperature for minimum stress.
  • FIG. 3 is a flowchart illustrating a process 300 to package a device using induction heating according to one embodiment of the invention.
  • the process 300 localizes heat on a die having bumps on a package substrate using a die induction heater operating at a first frequency (Block 310 ). Then, the process 300 localizes heat on at least an IHS, TIM on the die, an underfill, and a sealant using an IHS induction heater operating at a second frequency (Block 320 ). Next, the process 300 cures the TIM (other than solder-type TIM) and sealant in an oven (Block 330 ) The curing of the TIM and sealant can be done in a burn-in oven while the devices are being burned in. The process 300 is then terminated.
  • FIG. 4 is a flowchart illustrating the process 310 to localize heating on the die according to one embodiment of the invention.
  • the process 310 prepares the package substrate to remove any absorbed moisture (Block 410 ). This can be done by baking the package substrate in an oven at an elevated temperature (e.g., 125° C.) for an extended period of time (e.g., 24 hours). Next, the process 310 applies flux to the bumps on the die (Block 420 ). Then, the process 310 aligns the die above the package substrate (Block 430 ) and places the die on the package substrate (Block 440 ).
  • an elevated temperature e.g., 125° C.
  • the process 310 places the die induction heater above the die (Block 450 ). Then, the process 310 heats the die and bumps locally through the generated magnetic field (Block 460 ). The bumps then form bump joints between the die and the package substrate. The process 310 is then terminated.
  • FIG. 5 is a flowchart illustrating the process 320 to localize heating on the IHS according to one embodiment of the invention.
  • the process 320 dispenses the TIM on the die (Block 510 ). Then, the process 320 dispenses the sealant on the package substrate and underfill under the die (Block 520 ). Next, the process 320 places the IHS on the TIM and the sealant (Block 530 ). Then, the process 320 activates a lever arm mechanism to apply force on the IHS to maintain the desired BLT (Block 540 ).
  • the process 320 places an IHS induction heater above the IHS (Block 550 ). Then, the process 320 heats the IHS, the TIM, the underfill, and the sealant locally (Block 560 ). As noted earlier, if the TIM is a solder-type TIM, this local heating also cures the TIM. The process 320 is then terminated.

Abstract

An embodiment of the present invention is a technique to package a device. Heat is localized on a die having bumps on a package substrate using a first induction heater operating at a first frequency. Heat is localized on at least an integrated heat spreader (IHS), a thermal interface material (TIM), an underfill, and a sealant on the die using a second induction heater operating at a second frequency.

Description

BACKGROUND
1. Field of the Invention
Embodiments of the invention relate to the field of semiconductors, and more specifically, to device packaging.
2. Description of Related Art
Thermal design is critical during device packaging. As operating frequencies and power dissipation increase, device packaging focuses more and more on efficient ways to transfer heat from the semiconductor junctions to the environment. One of the common methods to provide heat transfer is the use of an integrated heat spreader (IHS) as part of the device package.
Existing techniques to address the problem of thermal design during device packaging have a number of disadvantages. Typically, the die and package substrate are heated at an elevated temperature in an oven and then cooled. Due to mismatch in coefficients of thermal expansion (CTEs) between the die and the substrate, warping may occur resulting in a reduction in co-planarity. During IHS attachment, spring clip tension is applied to the IHS in a convection oven to maintain control of bond line thickness (BLT). The repeated thermal cycling of the clips and the number of spring clips required in a high volume manufacturing (HVM) factory with many hours of work in process (WIP) leads to inefficient and costly packaging assembly.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
FIG. 1 is a diagram illustrating a packaging system in which one embodiment of the invention can be practiced.
FIG. 2A is a diagram illustrating baking a package substrate according to one embodiment of the invention.
FIG. 2B is a diagram illustrating placing die on the package substrate according to one embodiment of the invention.
FIG. 2C is a diagram illustrating localizing heat on the die according to one embodiment of the invention.
FIG. 2D is a diagram illustrating dispensing thermal interface material and sealant according to one embodiment of the invention.
FIG. 2E is a diagram illustrating placing an integrated heat spreader (IHS) on the die according to one embodiment of the invention.
FIG. 2F is a diagram illustrating localizing heat on the IHS according to one embodiment of the invention.
FIG. 2G is a diagram illustrating curing the thermal interface material and sealant according to one embodiment of the invention.
FIG. 3 is a flowchart illustrating a process to package a device using induction heating according to one embodiment of the invention.
FIG. 4 is a flowchart illustrating a process to localize heating on the die according to one embodiment of the invention.
FIG. 5 is a flowchart illustrating a process to localize heating on the IHS according to one embodiment of the invention.
 DESCRIPTION
An embodiment of the present invention is a technique to package a device. Heat is localized on a die having bumps on a package substrate using a first induction heater operating at a first frequency. Heat is localized on at least an integrated heat spreader (IHS), a thermal interface material (TIM), an underfill, and a sealant on the die using a second induction heater operating at a second frequency.
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in order not to obscure the understanding of this description.
One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, a method of manufacturing or fabrication, etc.
One embodiment of the invention addresses the problems caused by the differences or mismatches between the coefficients of thermal expansion (CTEs) of the silicon die and the package substrate. These problems include stress, poor co-planarity, and warping of the component. Additionally, one embodiment of the invention reduces the time-temperature exposure of the die and the package; thereby reducing undesired reactions, particularly with the Controlled Collapse Chip Connection (C4) joints. Reducing these undesired reactions leads to increased reliability of the C4 joints and other interfaces in the die and package.
The advantages of one embodiment of the invention include at least: (1) improved process control and reduction of tooling costs because the entire assembly process can be performed on individual packages with single-unit handling capability, (2) improved throughput time (TPT), (3) significant reduction of CTE mismatches between die and package substrate, (4) reduction of tool footprint thanks to small induction heating coils, (5) efficient heating due to induction heating leading to reduction of total thermal budget that the device and package is exposed to.
FIG. 1 is a diagram illustrating a packaging system 100 in which one embodiment of the invention can be practiced. The packaging system 100 represents an assembly flow or process to package semiconductor devices. It includes an oven 110, a package tool assembly 120, and a burn-in or cure oven 180. As is known by one skilled in the art, the packaging system may include more or less than these components.
The oven 110 bakes a package substrate 115 to prepare it for the assembly process. The package substrate 115 may be moisture absorbent and therefore may be dried to eliminate the absorbed moisture. The baking temperature and time depend on the type of material and the condition of the substrate. In one embodiment, the bake time is 24 hours and the baking temperature is 125° C.
The package tool assembly 120 includes a number of tools to place various components onto the package substrate 115. These tools include various dispensers or pumps to dispense or deposit flux, epoxy, or sealant, pick and place tool, etc. In one embodiment, the package tool assembly 120 includes a dispenser 122, a TIM dispenser 125A, a sealant dispenser 125B, an epoxy underfill dispenser 125C, a die induction heater 124, a lever arm assembly 126, and an IHS induction heater 128. These tools are used to place and process components such as a die 140, an integrated heat spreader (IHS) 150, a flux 160, a sealant 170, and an epoxy underfill 175.
The oven 180 is used mainly to cure the glue or polymer-type TIM, sealant, epoxy underfill and other interface materials in the package. It may also be used to burn in the packaged device for early failures.
The entire assembly process can be performed using the packaging system 100 through several phases or stages. The package tool assembly 120 may be used in one single unit station or several stations. These phases or stages are illustrated in FIGS. 2A through 2G.
FIG. 2A is a diagram illustrating baking a package substrate according to one embodiment of the invention. The package substrate 115 is any suitable substrate for packaging. It may be a ceramic substrate or an organic substrate. The package substrate 115 has interconnecting elements to attach the device to a printed circuit board (PCB). Any suitable device packaging technique may be used including Ball Grid Array (BGA), Pin Grid Array (PGA), flip chip technology, etc. The package substrate 115 is placed in the oven 110 (FIG. 1) at an elevated temperature (e.g., 125° C.) over an extended period of time (e.g., 24 hours) to remove any moisture.
FIG. 2B is a diagram illustrating placing die on the package substrate according to one embodiment of the invention. The die 140 (FIG. 1) has a number of bumps 145 deposited on the lower surface. In one embodiment, the bumps 145 are Controlled Collapse Chip Connection (C4) bumps. The dispenser 122 may be used to dispense flux onto the bump locations. A place and alignment tool 210 is used to pick the die 140, position it above the package substrate 115, align it at a proper location, and place it on the package substrate 115. Typically, the location is at the center of the package substrate 115.
FIG. 2C is a diagram illustrating localizing heat on the die according to one embodiment of the invention. The die induction heater 124 is placed above and near the upper surface of the die 140. The die induction heater 124 is a device that provides fast and efficient heating using induction. It typically includes an alternating current (AC) power supply and an induction coil. When it is energized by the AC power supply, the alternating current is sent through the induction coil, generating a magnetic field. When it is placed above the die 140 and the bumps 145, the magnetic field induces eddy currents in the die 140 and the bumps 145 and generates a localized heat.
The heat penetration into the die 140 and the bumps 145 provided by the die induction heater 124 is a function of the operating frequency. For a die size of approximately 10 mm or 1 cm, an operating frequency between 1 KHz to 10 KHz may be sufficient to achieve satisfactory penetration depth. It is contemplated that the operating frequency may be higher for smaller sizes, and may be between 100 KHz to 400 KHz. The heating time may be within a few seconds to less than a minute. This time exposure is much faster than traditional heating techniques and therefore provides very efficient and cost effective assembly process. In addition, the size of the induction coil typically is approximately the same as the size of the die 140; therefore the assembly tool requires small footprint or space, leading to reduced costs. More importantly, the heating is carried out locally within the die 140 and the bumps 145. The package substrate 115 remains essentially thermally isolated from the die 140 and the bumps 145. It remains cool throughout the local induction heating of the die 140 and the bumps 145. Stress and other problems caused by CTE mismatch may be reduced or eliminated resulting in high reliability of the C4 solder joints. After induction heating, the C4 solder joints are formed and the die 140 is attached to the package substrate 115.
FIG. 2D is a diagram illustrating dispensing thermal interface material and sealant according to one embodiment of the invention. The TIM dispenser 125A dispenses the flux 160 (FIG. 1) as the thermal interface material on the upper surface of the die 140. The TIM 160 may be any suitable material such as grease or grease-like material filled with conductive particles, adhesive, phase change material, gel, or solders. When a solder-type TIM is used, it reflows during the IHS local heating as explained in FIG. 2F. The sealant dispenser 125B dispenses the sealant 170 on the package substrate 115, typically at its edge or periphery. The underfill dispenser 125C dispenses the epoxy underfill 175.
FIG. 2E is a diagram illustrating placing an integrated heat spreader (IHS) on the die according to one embodiment of the invention. The IHS 150 may be made by a thermally conductive material such as aluminum, plated copper, copper alloy, ceramic, or carbon composites. The IHS 150 is positioned to align with the package substrate 115 and placed on the package substrate at the periphery and the TIM 160 on the die 140. The lever arm assembly 126 applies a force on the IHS 150 to maintain a desired bond line thickness (BLT) between the lower IHS surface and the die upper surface.
FIG. 2F is a diagram illustrating localizing heat on the IHS according to one embodiment of the invention. The IHS induction heater 128 (FIG. 1) is placed above the IHS 150 to localize the heat on the IHS, the TIM 160 and the sealant 170. The IHS induction heater 128 operates in the same manner as the die induction heater 124. It may be the same as the die induction heater 124. In other words, the same induction heater can be used as the die induction heater 124 and the IHS induction heater 128 with same or different operating frequencies. It may be a different induction heater than the die induction heater 124, having different induction coil, and operating at a different frequency. As with the die induction heater 124, the heating time is a function of the type of induction heater used and the operating frequency. Typically, the heating time is approximately equal to one minute and the operating frequency ranges from 1 KHz to 10 KHz. The local heating may also cure the TIM 160 if a solder-type TIM is used because it does not require a long cure time. The solder-type TIM may be melted and alloyed during this second induction heating.
Since the heating is carried out locally within the IHS 150, the TIM 160, and the sealant 170, the package substrate 115 and the die 140 remain cool or thermally isolated. Therefore, problems caused by CTE mismatches between the package substrate 115 and the die 140 are avoided or reduced. For example, if the CTE of the die is 3 ppm/° C., the CTE of the IHS is 6 ppm/° C., and the CTE of the substrate is 16 ppm/° C., the CTE mismatch is 6 ppm/° C.−3 ppm/° C.=3 ppm/° C. instead of close to 16 ppm/° C.−6 ppm/° C.=10 ppm/° C. if both the substrate 115 and the IHS 150 are heated together.
FIG. 2G is a diagram illustrating curing the thermal interface material and sealant according to one embodiment of the invention. The packaged device including the IHS 150 sealed to the substrate 115 and encasing the die 140 is placed in the burn-in oven 180 (FIG. 1) to cure the TIM 160 (other than solder-type TIM) and the sealant 170. As discussed earlier, if the TIM 160 is a solder-type TIM, the oven curing is not needed. The die 140 and the package substrate 115 are held relative rigid because the IHS 150 and burn-in socket are in place. This reduces the package warping and improves co-planarity and pin true position. In addition, this permits the epoxy to cure at approximately the device operating temperature for minimum stress.
FIG. 3 is a flowchart illustrating a process 300 to package a device using induction heating according to one embodiment of the invention.
Upon START, the process 300 localizes heat on a die having bumps on a package substrate using a die induction heater operating at a first frequency (Block 310). Then, the process 300 localizes heat on at least an IHS, TIM on the die, an underfill, and a sealant using an IHS induction heater operating at a second frequency (Block 320). Next, the process 300 cures the TIM (other than solder-type TIM) and sealant in an oven (Block 330) The curing of the TIM and sealant can be done in a burn-in oven while the devices are being burned in. The process 300 is then terminated.
FIG. 4 is a flowchart illustrating the process 310 to localize heating on the die according to one embodiment of the invention.
Upon START, the process 310 prepares the package substrate to remove any absorbed moisture (Block 410). This can be done by baking the package substrate in an oven at an elevated temperature (e.g., 125° C.) for an extended period of time (e.g., 24 hours). Next, the process 310 applies flux to the bumps on the die (Block 420). Then, the process 310 aligns the die above the package substrate (Block 430) and places the die on the package substrate (Block 440).
Next, the process 310 places the die induction heater above the die (Block 450). Then, the process 310 heats the die and bumps locally through the generated magnetic field (Block 460). The bumps then form bump joints between the die and the package substrate. The process 310 is then terminated.
FIG. 5 is a flowchart illustrating the process 320 to localize heating on the IHS according to one embodiment of the invention.
Upon START, the process 320 dispenses the TIM on the die (Block 510). Then, the process 320 dispenses the sealant on the package substrate and underfill under the die (Block 520). Next, the process 320 places the IHS on the TIM and the sealant (Block 530). Then, the process 320 activates a lever arm mechanism to apply force on the IHS to maintain the desired BLT (Block 540).
Next, the process 320 places an IHS induction heater above the IHS (Block 550). Then, the process 320 heats the IHS, the TIM, the underfill, and the sealant locally (Block 560). As noted earlier, if the TIM is a solder-type TIM, this local heating also cures the TIM. The process 320 is then terminated.
While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims (11)

1. A method comprising:
localizing heat on a die having bumps on a package substrate using a first induction heater operating at a first frequency, the package substrate being substantially thermally isolated from the die and the bumps; and
localizing heat on at least one of an integrated heat spreader (IHS), a thermal interface material (TIM) on the die, an underfill, and a sealant on the package substrate using a second induction heater operating at a second frequency.
2. The method of claim 1 wherein localizing heat on the die and the bumps comprises:
preparing the package substrate to remove absorbed moisture;
applying flux to the bumps;
aligning the die above the package substrate; and
placing the die on the package substrate.
3. The method of claim 2 wherein localizing heat on the die and the bumps further comprises:
placing the first induction heater above the die; and
heating the die and the bumps locally at the first frequency of the first induction heater, the bumps forming bump joints between the die and the package substrate.
4. The method or claim 1 wherein localizing heat on the THS and the TIM comprises:
dispensing the TIM on the die;
dispensing the sealant on the package substrate;
placing the IHS on the TIM and the sealant;
applying force on the IHS to maintain desired bond line thickness (BLT).
5. The method of claim 4 wherein localizing heat on the IHS and the TIM further comprises:
placing the second induction heater above the IHS; and
heating the IHS, the TIM, and the sealant locally at the second frequency of the second induction heater.
6. The method of claim 4 wherein applying force on the IHS comprises:
activating a lever arm assembly on the IHS.
7. The method of claim 1 further comprising:
curing at least one of the TIM and the sealant in an oven.
8. The method of claim 5 wherein localizing heat on the HIS comprises:
dispensing the underfill under the die.
9. The method of claim 1 wherein the First and second induction heaters are same.
10. The method of claim 1 wherein the first and second frequencies are approximately equal.
11. The method of claim 1 wherein at least one of the first and second frequencies is between 1 KHz to 10 KHz.
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US20070084856A1 (en) 2007-04-19

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