US7085336B2 - Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same - Google Patents
Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same Download PDFInfo
- Publication number
- US7085336B2 US7085336B2 US09/875,364 US87536401A US7085336B2 US 7085336 B2 US7085336 B2 US 7085336B2 US 87536401 A US87536401 A US 87536401A US 7085336 B2 US7085336 B2 US 7085336B2
- Authority
- US
- United States
- Prior art keywords
- signal
- delay
- delay time
- receiving
- transmission path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Abstract
Description
CON_CODE=C1*DT [Equation 1]
DELT=C2*CON_CODE [Equation 2]
C1*C2=1 [Equation 3]
Claims (29)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000035335A KR100335503B1 (en) | 2000-06-26 | 2000-06-26 | Signal transmission circuit, signal transmission method for synchronizing different delay characteristics, and data latch circuit of semiconductor device having the same |
KR2000-35335 | 2000-06-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010055344A1 US20010055344A1 (en) | 2001-12-27 |
US7085336B2 true US7085336B2 (en) | 2006-08-01 |
Family
ID=19673917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/875,364 Expired - Fee Related US7085336B2 (en) | 2000-06-26 | 2001-06-05 | Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same |
Country Status (6)
Country | Link |
---|---|
US (1) | US7085336B2 (en) |
JP (1) | JP2002057559A (en) |
KR (1) | KR100335503B1 (en) |
DE (1) | DE10130732B4 (en) |
IT (1) | ITMI20011235A1 (en) |
TW (1) | TW563315B (en) |
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Also Published As
Publication number | Publication date |
---|---|
DE10130732B4 (en) | 2007-01-04 |
US20010055344A1 (en) | 2001-12-27 |
JP2002057559A (en) | 2002-02-22 |
TW563315B (en) | 2003-11-21 |
KR100335503B1 (en) | 2002-05-08 |
DE10130732A1 (en) | 2002-01-10 |
KR20020000459A (en) | 2002-01-05 |
ITMI20011235A1 (en) | 2002-12-12 |
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